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DATA CTRL ENCODE DATA GA9101 TRANSMITTE GA9103 OPTICS COAX T


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DATA CTRL ENCODE DATA GA9101 TRANSMITTE
GA9103
OPTICS COAX TLX, MEDIA
GA9103 ENDEC
LOOP
REMOTE
Mbaud Fibre Channel ENDEC
DATA STATUS DECODE DATA GA9102 RECEIVER RLX, MEDIA OPTICS COAX
Features
Fibre Channel, point-to-point, network, SCSI applications With fiber optics, FC-265 chip provides complete FC-0, FC-1 solution 8b/10b Encode/Decode data, ordered sets, line states TTL-compatible 10-bit-wide Transmitter/Receiver interface with 26.5625 byte clock Parity Generate/Check
DATACOM PRODUCTS
TriQuint's GA9103 three devices FC-265 chip designed support requirements Fibre Channel Standard X3T9.3. GA9103 encoder/decoder (ENDEC) integrated circuit which implements 8b/10b encoding/decoding scheme data, ordered sets line states associated with Fibre Channel Physical Level Standard (FC-PH). addition, CMOS ENDEC chip performs 32-bit parity generate/check functions. interfaces TriQuint's GA9101 GA9102 Transmitter Receiver, respectively, either fabric device link protocol controller. FC-265 (GA9101, GA9102 GA9103) provides comprehensive electrical physical interface Fibre Channel. These chips designed operate 265.625 Megabaud, operating speeds specified standard. Fibre Channel provides transport vehicle upper-layer Intelligent Peripheral Interface (IPI) Small Computer System Interface (SCSI) command sets, High-Performance Parallel Interface (HIPPI) data link layer, other user-defined command sets. Fibre Channel capable replacing SCSI, IPI, HIPPI physical interfaces with protocol-efficient alternative that provides performance improvements distance and/or speed. SCSI commands HIPPI data link operations intermixed Fibre Channel. Proprietary other command sets also share Fibre Channel. Figure
Common chip fabric device adapters Multiplexed data/control 8-bit system interface 68-pin PLCC
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GA9103
Fibre Channel optimized predictable transfers large blocks data such those used file transfers between processors (supercomputer, mainframe, super-mini, etc.), storage systems (disk tape), communications, output-only devices such laser printers raster-scan graphics terminals. Transmitter/Receiver chips, designed with TriQuint's proprietary micron One-UpGaAs process, interface either directly electrical medium fiber-optic interface. chips implement parallel-to-serial conversion, clock generation, receive clock/data recovery, serialto-parallel conversion.
Fibre Channel protocol simple economical enhances system throughput. transmission medium isolated from control protocol that implementation point-to-point links, multi-drop buses, rings, crosspoint switches, other special implementations made technology best suited usage environment. Fibre channel organized into five layers shown Figure With this standard, user communi-cate over distances baud rates 132.8125 Megabaud 1.0625 Gigabaud. This standard will support links over coaxial fiber-optic cables. Along with fiber-optic module, this chipset will provide complete FC-0 FC-1 solutions Fibre Channel data link.
Figure GA9103 ENDEC Block Diagram
TERR RAWTx CTXD0.7 CTXP PERR CTXC1 CTXC0 RESETN WSYNC CRXS2 RWSTART ERROR CRXS1 CRXD0.7 RAWRx CRXS0, CRXP PARITY GENERATE 10b/8b DECODER 32-BIT CHECK LINE STATE DECODE ORDERED DECODE PARITY CHECK 32-BIT GENERATE/ CHECK 8b/10b ORDERED ENCODER
REGISTE
BTXD0.9
ENCODE
TXCLK
DECODE
SYNC RXCLK
REGISTE
BRXD0.9
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GA9103
Figure Layers Fibre Channel
(Mapping) 802.2
HIPP
Others
End-of-Frame (EOF). corresponds ones complement remainder obtained dividing frame sequence polynomial H(x) following generator polynomial: G(x)
FC-265
Striping Multicast Huntgroup (common services)
Signalling Protocol, including
Encoding Decoding
Media
Functional Description
GA9103 8-bit inter-face host side 10-bit interface Transmitter (Tx) Receiver (Rx). device major independent functional blocks, ENCODE DECODE. ENCODE block interfaces with DECODE with Below details functional blocks.
frame sequence polynomial formed follows: bits frame treated coefficient polynomial D(x) order where degree less than total number bits. polynomial H(x) formed multiplying D(x) inverting terms resulting polynomial starting X(k+32) term. order computation within byte made starting with least-significant (CTXD0) continuing through most-significant (CTXD7). appended incoming data, starting with most significant coefficient (X31) continuing through least-significant coefficient. check performed checking remainder incoming frame against expected value. incoming correct, remainder should "C704DD7B" (Hex), order reception. error occurs, flagged TERR pin. pass-through mode, function disabled. Generate function enabled device interface Check function enabled fabric interface means CTXC1 input signal. logic HIGH CTXC1 indicates Generate function selected, while logic indicates that Check selected. When initiated, Generate/Check commences after Start-ofFrame signal, ends prior End-of-Frame signal. (See Figures start computation 32-bit Generate mode ENCODE block, following conditions must met: CTXC1 HIGH, previous encoded
Encode
PARITY CHECK block compares input parity with that incoming data, CTXD0.7 CTXCO. number ones input even number, CTXP will HIGH. number ones input data odd, CTXP will LOW. there parity error, flagged through PERR signal. passthrough mode (RAWTx=1), PERR forced zero. 32-bit Generate/Check block either generates checks 32-bit incoming 8-bit bus, CTXD0.7. methodology, polynomials, equations 32-bit same FDDI's Frame Check Sequence, adopted Fibre Channel. 32-bit computed every frame computation begins after receipt Start-ofFrame (SOF) ordered finishes byte before
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DATACOM PRODUCTS
GA9103
word Start-of-Frame (SOF), CTXC0 signal goes from HIGH LOW. computation complete when CTXC0 signal goes back HIGH. CTXC0 signal must HIGH least four byte clocks order append transmitted data. Generate mode, signal TERR (CRC Error) LOW. timing Generate mode shown Figure While internal logic does check parity during Append cycle, four input bytes CTXD0.7 ignored. initiate 32-bit Check mode ENCODE block, following state required: CTXC0 signal goes from HIGH LOW, previous encoded ordered SOF, CTXC1 LOW. When CTXC0 signal goes back HIGH, computation complete. computed value compared "C704DD7B" (Hex) error occurred. there error, flagged through TERR going HIGH byte time End-of-Frame. timing Check mode shown Figure 8b/10b Ordered ENCODER encodes data Fibre Channel rules encoding. encoding valid data special characters shown Tables tables have columns encoded output based current Running Disparity (RD). current Running Disparity positive negative power RESETN being activated, always negative. Running Disparity calculated from transmitted character. forced negative CTXC0 Ordered encode primitive, such R-Rdy, etc., when link exits diagnostic (RAW) mode. ordered sets then encoded according Table Each ordered four bytes wide. ordered encoding procedure follows: ENCODER looks CXTD0.7 signal inputs while Ordered Set, CXTC0, signal HIGH encodes four
bytes, based contents CTXD0.7. contents CTXD0.7 next three bytes ignored. fields within first byte, CTXD0.7, word Ordered Encoding shown Figure CTXD7 corresponds Cntl signal. Cntl signal,
Figure Data Fields Fibre Channel Ordered Encoding
CTXD CTXD CTXD CTXD CTXD CTXD CTXD CTXD Cntl Type
when LOW, indicates Fibre Channel-defined ordered sets being transmitted. When Cntl signal HIGH, undefined ordered sets being transmitted. signal (CTXD6), when HIGH, indicates Line State ordered being transmitted, and, when LOW, indicates ordered other than Line State being transmitted. (CTXD5), when HIGH, indicates Start-of-Frame ordered being transmitted, (CTXD4), when HIGH, indicates End-of-Frame ordered being transmitted. Type (CTXD3.0) indicates type ordered sets within SOF, EOF, Line States Undefined categories that being transmitted. PERR TERR HIGH within frame, EOFn EOFt that particular frame transmitted EOFni (see Table Similarly, PERR TERR HIGH while EOFdt being transmitted, encoded EOFdti, indicate invalid condition node. selects between 8b/10b ENCODER output data inputs, CTXD0.7. When RAWTx input signal HIGH, inputs CTXD0.7, CTXP, CTXC0 selected, TERR When RAWTx input LOW, ENCODER output selected. output bits wide clocked into REGISTER using transmit byte clock, TXCLK, from
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GA9103
Transmitter chip, GA9101. output REGISTER interface goes directly GA9101, Transmitter I.C. FC-265. asynchronous RESETN input, when LOW, used clear inter-nal state machine registers. will take
five byte clocks clear internal state machines after RESETN input goes back HIGH. ordering transmission mode CTXD0.7, CTXP1 CTXC0. corresponds mapping these signals BTXD9.0, respectively.
Figure Error Timing
TXCLK
CTXC0
IDLE CTXD0.7 IDLE Bytes
Bytes
Computation Dn-3 Dn-2 Dn-1
Bytes IDLE
CTXC1
CTXC0
Byte
Bytes
Byte
Byte
Bytes
Append (internal signal)
Bytes
BTXD0.9
IDLE
Dn-3
Dn-2
Dn-1
Bytes data packet size. divisible "don't care," parity checked.
Bytes
Bytes
Bytes
Bytes
Figure Check Mode Timing
IDLE CTXD0.7 IDLE Bytes Bytes Computation Dn-3 Dn-2 Dn-1 Bytes Bytes IDLE
CTXC1
CTXC0
Check (internal signal)
BTXD0.9
IDLE
Dn-3
Dn-2
Dn-1
Bytes
Bytes
Bytes
Bytes
Bytes
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DATACOM PRODUCTS
Figure Generate Mode Timing
GA9103
Table Valid Data Characters Encoding
Data Byte Name D0.0 D1.0 D2.0 D3.0 D4.0 D5.0 D6.0 D7.0 D8.0 D9.0 D10.0 D11.0 D12.0 D13.0 D14.0 D15.0 D16.0 D17.0 D18.0 D19.0 D20.0 D21.0 D22.0 D23.0 D24.0 D25.0 D26.0 D27.0 D28.0 D29.0 D30.0 D31.0 D0.1 D1.1 D2.1 D3.1 D4.1 D5.1 D6.1 D7.1 D8.1 D9.1 D10.1 D11.1 D12.1 D13.1 D14.1 D15.1 D16.1 D17.1 D18.1 D19.1 D20.1 D21.1 D22.1 D23.1 D24.1 D25.1 D26.1 D27.1 D28.1 D29.1 D30.1 D31.1 D0.2 D1.2 D2.2 D3.2 D4.2 D5.2 D6.2 D7.2 D8.2 Current Bits EDCBA 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 abcdei 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 fghj 0100 0100 0100 1011 0100 1011 1011 1011 0100 1011 1011 1011 1011 1011 1011 0100 0100 1011 1011 1011 1011 1011 1011 0100 0100 1011 1011 0100 1011 0100 0100 0100 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 0101 0101 0101 0101 0101 0101 0101 0101 0101
Current abcdei 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110
fghj 1011 1011 1011 0100 1011 0100 0100 0100 1011 0100 0100 0100 0100 0100 0100 1011 1011 0100 0100 0100 0100 0100 0100 1011 1011 0100 0100 1011 0100 1011 1011 1011 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 0101 0101 0101 0101 0101 0101 0101 0101 0101
Data Byte Name D9.2 D10.2 D11.2 D12.2 D13.2 D14.2 D15.2 D16.2 D17.2 D18.2 D19.2 D20.2 D21.2 D22.2 D23.2 D24.2 D25.2 D26.2 D27.2 D28.2 D29.2 D30.2 D31.2 D0.3 D1.3 D2.3 D3.3 D4.3 D5.3 D6.3 D7.3 D8.3 D9.3 D10.3 D11.3 D12.3 D13.3 D14.3 D15.3 D16.3 D17.3 D18.3 D19.3 D20.3 D21.3 D22.3 D23.3 D24.3 D25.3 D26.3 D27.3 D28.3 D29.3 D30.3 D31.3 D0.4 D1.4 D2.4 D3.4 D4.4 D5.4 D6.4 D7.4 D8.4 D9.4 D10.4 D11.4 D12.4 D13.4 D14.4 D15.4 D16.4 D17.4
Current Bits EDCBA 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 abcdei 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011
fghj 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0011 0011 0011 1100 0011 1100 1100 1100 0011 1100 1100 1100 1100 1100 1100 0011 0011 1100 1100 1100 1100 1100 1100 0011 0011 1100 1100 0011 1100 0011 0011 0011 0010 0010 0010 1101 0010 1101 1101 1101 0010 1101 1101 1101 1101 1101 1101 0010 0010 1101
Current abcdei 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011
fghj 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 1100 1100 1100 0011 1100 0011 0011 0011 1100 0011 0011 0011 0011 0011 0011 1100 1100 0011 0011 0011 0011 0011 0011 1100 1100 0011 0011 1100 0011 1100 1100 1100 1101 1101 1101 0010 1101 0010 0010 0010 1101 0010 0010 0010 0010 0010 0010 1101 1101 0010
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GA9103
Table Valid Data Characters Encoding (cont.)
Data Byte Name
D18.4 D19.4 D20.4 D21.4 D22.4 D23.4 D24.4 D25.4 D26.4 D27.4 D28.4 D29.4 D30.4 D31.4 D0.5 D1.5 D2.5 D3.5 D4.5 D5.5 D6.5 D7.5 D8.5 D9.5 D10.5 D11.5 D12.5 D13.5 D14.5 D15.5 D16.5 D17.5 D18.5 D19.5 D20.5 D21.5 D22.5 D23.5 D24.5 D25.5 D26.5 D27.5 D28.5 D29.5 D30.5 D31.5 D0.6 D1.6 D2.6 D3.6 D4.6 D5.6 D6.6 D7.6 D8.6 D9.6 D10.6 D11.6 D12.6 D13.6 D14.6 D15.6 D16.6 D17.6 D18.6 D19.6 D20.6 D21.6 D22.6 D23.6 D24.6 D25.6 D26.6
Current
fghj
1101 1101 1101 1101 1101 0010 0010 1101 1101 0010 1101 0010 0010 0010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110
Current abcdei
010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110
fghj
0010 0010 0010 0010 0010 1101 1101 0010 0010 1101 0010 1101 1101 1101 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110
Bits EDCBA
10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010
abcdei
010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110
Data Byte Name
D27.6 D28.6 D29.6 D30.6 D31.6 D0.7 D1.7 D2.7 D3.7 D4.7 D5.7 D6.7 D7.7 D8.7 D9.7 D10.7 D11.7 D12.7 D13.7 D14.7 D15.7 D16.7 D17.7 D18.7 D19.7 D20.7 D21.7 D22.7 D23.7 D24.7 D25.7 D26.7 D27.7 D28.7 D29.7 D30.7 D31.7
Current
fghj
Current abcdei
001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100
fghj
0110 0110 0110 0110 0110 1110 1110 1110 0001 1110 0001 0001 0001 1110 0001 0001 1000 0001 1000 1000 1110 1110 0001 0001 0001 0001 0001 0001 1110 1110 0001 0001 1110 0001 1110 1110 1110
Bits EDCBA
11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
abcdei
110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011
0110 0110 0110 0110 0110 0001 0001 0001 1110 0001 1110 1110 1110 0001 1110 1110 1110 1110 1110 1110 0001 0001 0111 0111 1110 0111 1110 1110 0001 0001 1110 1110 0001 1110 0001 0001 0001
Table Valid Special Characters Encoding
Special Code Name K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 K28.6 K28.7 K23.7 K27.7 K29.7 K30.7 Current abcdei 001111 001111 001111 001111 001111 001111 001111 001111 111010 110110 101110 011110 fghj 0100 1001 0101 0011 0010 1010 0110 1000 1000 1000 1000 1000 Current abcdei 110000 110000 110000 110000 110000 110000 110000 110000 000101 001001 010001 100001 fghj 1011 0110 1010 1100 1101 0101 1001 0111 0111 0111 0111 0111
Notes: "HGF EDCBA" correspond Data Inputs CTXD7.0, that order. transmitted first, followed "b", "c", "j". "abcdeifghj", that order, correspond BTXD9 BTXD0.
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DATACOM PRODUCTS
GA9103
Table Ordered Encoding Fibre Channel
C-Interface Signals (Mode: Raw) Inputs CTxD7.0 Byte Byte Byte Type 0001
0010 0011 0101 0110 0111 1101 1000 0000 0100 1100 1001 0001 1101 0000 0110 1000 1001 1010 1011 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYB)2 (XYC)2 (XYC)2 (XYC (XYC)2 (XYC)2 (XYC)2 (XYC)2 (XYC)2 (XYC)2 (XYC)2 (XYC)2 (XYC)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2 (XYD)2
Function
SOFn13 SOFn2 SOFn3 SOFi1 SOFi2 SOFi3 SOFc1 SOFf EOFn4,5 EOFt5 EOFdt6 EOFa EOFni EOFdti Idle R-Rdy Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Cntl
Byte
Begin. Output (four encoded bytes) Byte 1-Byte 2-Byte 3-Byte (K28.5-D21.5-D23.1-D23.1)
(K28.5-D21.5-D21.1-D21.1) (K28.5-D21.5-D22.1-D22.1) (K28.5-D21.5-D23.2-D23.2) (K28.5-D21.5-D21.2-D21.2) (K28.5-D21.5-D22.2-D22.2) (K28.5-D21.5-D23.0-D23.0) (K28.5-D21.5-D24.2-D24.2) (K28.5-D21.4-D21.6-D21.6) (K28.5-D21.5-D21.6-D21.6) (K28.5-D21.4-D21.3-D21.3) (K28.5-D21.5-D21.3-D21.3) (K28.5-D21.4-D21.4-D21.4) (K28.5-D21.5-D21.4-D21.4) (K28.5-D21.4-D21.7-D21.7) (K28.5-D21.5-D21.7-D21.7) (K28.5-D10.4-D21.6-D21.6) (K28.5-D10.5-D21.6-D21.6) (K28.5-D10.4-D21.4-D21.4) (K28.5-D10.5-D21.4-D21.4) (K28.5-D21.4-D21.5-D21.5) (K28.5-D21.4-D10.2-D10.2) (K28.5-D21.2-D31.5-D5.2) (K28.5-D21.1-D10.4-D21.2) (K28.5-D9.2-D31.5-D9.2) (K28.5-D21.1-D31.5-D9.2) (K28.0-DX.YB-DX.YC-DX.YD) (K28.1-DX.YB-DX.YC-DX.YD) (K28.2-DX.YB-DX.YC-DX.YD) (K28.3-DX.YB-DX.YC-DX.YD) (K28.4-DX.YB-DX.YC-DX.YD) (K28.5-DX.YB-DX.YC-DX.YD) (K28.6-DX.YB-DX.YC-DX.YD) (K28.7-DX.YB-DX.YC-DX.YD) (K23.7-DX.YB-DX.YC-DX.YD) (K27.7-DX.YB-DX.YC-DX.YD) (K29.7-DX.YB-DX.YC-DX.YD) (K30.7-DX.YB-DX.YC-DX.YD)
Notes: Don't Care (any value). Outputs data characters ordered must encoded correct data values. Start-of-frame delimiter.
End-of-frame delimiter. Encoded EOFni TERR PERR Encoded EOFdti TERR PERR
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GA9103
Decode Decode block GA9103 return path serial link from remote transmitter host. takes encoded 10-bit data from GA9102 (Rx) decodes into 8-bit data host. 10-bitwide input, BRXD0.9, first clocked into REGISTER, using Receiver byte clock, RXCLK. 10b/8b DECODER decodes data special characters according Tables Initially, current Running Disparity negative each characters decoded based received character. DECODER also checks validity received characters based Tables ERROR flag there code violations four bytes word, running disparity error. ERROR signal active entire duration word transmission, regardless which byte error. ERROR also used flag three other invalid conditions: Examples improper running disparity are: with positive running disparity, content specified positive running disparity, received with BRD-. Table Four bytes received signal must analyzed order perform ORDERED DECODE. purpose ordered decoding, SYNC signal used align four bytes information generate word. ordered sets decoded according Table (Ordered Decoding). ORDERED DECODE block generates Data/Ordered signal, CRXS0, along with 8-bit decoded ordered set. periodic signal, RWSTART, also generated from this block. SYNC signal used generate RWSTART, which HIGH first byte output, CRXD0.7, every word. RWSTART initialized RESETN, RAWRx, K28.5 followed three valid data bytes (DX.YA, DX.YB, DX.YC). relationship between ERROR, RXCLK, RWSTART shown Figure
DATACOM PRODUCTS
special character detected second, third, fourth character transmission word SYNC when BRXD0.9 K28.5 ordered received with improper beginning running disparity
Figure ERROR Signal Timing
RXCLK RWSTART ERRO
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GA9103
WSYNC signal from ORDERED DECODE block used denote whether link wordsynchronized. shown WSYNC State Diagram Figure WSYNC link loses word synchronization, reset condition, "RAW" mode. link achieves word synchronization, (WSYNC only after three valid ordered sets received without error first byte K28.5 character. Once synchronized, link could lose synchronization receives minimum four invalid words within consecutive seven words sequence shown State Diagram. During this sequence, link reacquire word synchronization (State receives consecutive valid words each States shown State Diagram. RAWRx WSYNC
ordered sets received correspond primitive sequence, LINE STATE DECODER increments counter using SYNC signal. primitive sequences, defined Fibre Channel standard, Offline State (OLS), Not-Operational State (NOS), Link Reset (LR), Link Reset Response (LRR). These transmitted indicate specific condition within port. Transmission indicates port detected link failure condition. indicates port preparing either initialize, into diagnostic mode, power down. sent after link timeout error occurred received. transmitted recognize Link Reset. three consecutive ordered sets received, corresponding information sent through CRXD0.7, according Ordered Decoding table (see Table
Figure WSYNC State Diagram
STATE WSYNC (Word Sync Acquired) Three Valid Ordered Sets with K28.5 First Byte errors RAWRx RESETN=0 STATE WSYNC First Invalid Word Invalid Word within Consecutive Words
Invalid Word
Consecutive Consecutive Valid Words Valid Words STATE STATE
WSYNC Second Invalid Word Invalid Word within Consecutive Words
WSYNC (Loss Word Sync)
Consecutive Valid Words STATE
WSYNC Third Invalid Word Invalid Word within Consecutive Words
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GA9103
CRXS2 active long four possible line state signals, (OLS, NOS, LRR), being received. Once active, CRXS2 remains active count line state ordered sets. third count, CRXS2 goes inactive CRXS0 goes active. proper line state output signals flagged CRXD0.7, Table figure below shows example timing sequence line states when RAWRx fields within first byte, CRXD0.7, word Ordered Decoding shown Figure CRXD7 corresponds Cntl signal which, when logic LOW, indicates Fibre Channel-defined ordered been received. When Cntl signal HIGH, indicates non-Fibre Channel (undefined) ordered been received.
signal (CRXD6), when HIGH, indicates Line State ordered set, IDLE R_RDY, been received, when LOW, signal indicates ordered other than Line State been received. (CRXD5), when HIGH, indicates Start-of-Frame ordered been received (CRXD4), when HIGH, indicates End-of-Frame ordered set. Type (CRXD3.0) indicates different types ordered sets within SOF, EOF, Line State Undefined categories. CHECK block performs 32-bit Cyclic Redundancy Check received data. check begins after Start-of-Frame Detect finishes prior End-of-Frame. errors flagged CRXS1 RAWRx CRXS1 mode used whenever 10-bit-wide input data receiver passed through, undecoded, receive outputs, CRXD0.7, CRXP, CRXS0. used choose between decoded data/ordered register output.
Figure Data Fields Ordered Decoding
CRXD CRXD CRXD CRXD CRXD CRXD CRXD CRXD Cntl Type
Figure Example Timing Sequence Line States
RXCLK WORD CTXD0.7 CRXS0 CRXS2 DATA WORD DATA WORD DATA DATA
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DATACOM PRODUCTS
GA9103
When RAWRx input signal active, undecoded data selected; otherwise, decoded data/ordered set/line state chosen. CRXS2 CRXS0 LOW, decoded data output selected through MUX. CRXS0 HIGH CRXS2 LOW, ordered set/line state selected. CRXS2 goes HIGH, output disabled (that output data ignored). Table PARITY GENERATE block used generate parity signal CRXP every byte data, CRXD0.7 CRXS0. number ones output, CRXD0.7
CRXS0, even number, CRXP will HIGH. number ones output, CRXD0.7 CRXS0, odd, CRXP will LOW.
Table Selection
CRXS2
CRXS0
Output
Decoded Data Ordered set/line state Decoded line state word Undecoded data*
*Note: CRXS0 part this data.
Table Ordered Decoding Fibre Channel
C-Interface Signals (Mode: Raw) Outputs (CRXD7.0) Byte Type
0001 0010 0011 0101 0110 0111 1101 1000 0000 0100 1100 1001 0001 1101 0000 0110 1000 1001 (9516) (9516) (9516) (9516) (8A16) (8A16)
Input Cntl
SOFn1 SOFn2 SOFn3 SOFi1 SOFi2 SOFi3 SOFc1 SOFf EOFn EOFt EOFdt EOFa EOFni EOFdti Idle R_Rdy
Byte
Byte
(B516) (B516) (B516) (B516) (B516) (B516) (B516) (B516) (B516) (B516) (B516) (B516) (AA16) (AA16) (9516) (9516) (5516) (3516) (3716) (3516) (3616) (5716) (5516) (5616) (1716) (5816) (D516) (7516) (9516) (F516) (D516) (9516) (B516) (4A16) (BF16) (8A16)
Byte
(3716) (3516) (3616) (5716) (5516) (5616) (1716) (5816) (D516) (7516) (9516) (F516) (D516) (9516) (B516) (4A16) (4516) (5516)
(Continued next page)
Notes: Valid unrecognized control sequence starting with 'K28.5'. valid acquiring Word Sync. Beginning Running Disparity Negative. Beginning Running Disparity Positive
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GA9103
Table Ordered Decoding Fibre Channel (continued)
C-Interface Signals (Mode: Raw) Outputs (CRXD7.0) Byte Type
1010 1011 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
Input Cntl
(K28.0-DX.YB-DX.YC-DX.YD) (K28.1-DX.YB-DX.YC-DX.YD) (K28.2-DX.YB-DX.YC-DX.YD) (K28.3-DX.YB-DX.YC-DX.YD) (K28.4-DX.YB-DX.YC-DX.YD) (K28.5-DX.YB-DX.YC-DX.YD)1 (K28.6-DX.YB-DX.YC-DX.YD) (K28.7-DX.YB-DX.YC-DX.YD) (K23.7-DX.YB-DX.YC-DX.YD) (K27.7-DX.YB-DX.YC-DX.YD) (K29.7-DX.YB-DX.YC-DX.YD) (K30.7-DX.YB-DX.YC-DX.YD)
Byte
Byte
(4916) (9516) (XYB) (XYB) (XYB) (XYB) (XYB) (XYB) (XYB) (XYB) (XYB) (XYB) (XYB) (XYB) (BF16) (BF16) (XYC) (XYC) (XYC) (XYC) (XYC) (XYC) (XYC) (XYC) (XYC) (XYC) (XYC) (XYC)
Byte
(4916) (4916) (XYD) (XYD) (XYD) (XYD) (XYD) (XYD) (XYD) (XYD) (XYD) (XYD) (XYD) (XYD)
Notes:
Valid unrecognized control sequence starting with 'K28.5'. valid acquiring Word Sync. Beginning Running Disparity Negative. Beginning Running Disparity Positive
Figure System Block Diagram
CTXD0.7 CTXP CTXC0,1 RESETN PERR RAWTx RAWRx TERR WSYNC CRXS0.2 CRXD0.7 CRXP ERROR RWSTART TXCLK BTXD0.9 GA9101 TRANSMITTER TLX, SIG, SIGN OPTICS/ COAX MEDIA REMOTE
LOOPEN GA9103 ENDEC RXCLK SYNC BRXD0.9
SIGDE
RLX, OPTICS/ COAX
GA9102 RECEIVE
RX,RY
MEDIA FROM REMOTE
SYNCEN REFCLK
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DATACOM PRODUCTS
GA9103
Table Absolute Maximum Ratings Exceeding absolute maximum ratings damage device.
Storage temperature Ambient temperature Supply voltage ground input voltage input current
-65°C +150°C -55°C +125°C -0.5 +7.0 -0.5 (VCC +0.5
Table Operating Conditions (Proper functionality guaranteed under these conditions.)
Supply voltage Ambient temperature
70°C
Figure Test Load, Outputs
1100
2200
Table Characteristics (Over operating range unless otherwise specified.)
Limits1 Typ.
0.37 -150 -400
Symbol
VIH2 VIL2
Description
Output HIGH voltage Output voltage Input HIGH level Input level Input Leakage current
Test Conditions
VIN3
Min.
Max.
Unit
Guaranteed input logical HIGH voltage inputs Guaranteed input logical voltage inputs 0.40
Notes:
Typical limits are: These absolute values with respect device ground, overshoots system tester noise included. VIN, input, HIGH LOW.
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GA9103
Table Characteristics ENCODE
Parameter
Description
TXCLK Pulse Width HIGH TXCLK Pulse Width TXCLK Period CTXD0.7; CTXP; CTXC0,1 Setup Time CTXD0.7; CTXP; CTXC0,1 Hold Time TXCLK PERR, TERR TXCLK BTXD0.9 ENCODE Latency
Min.
15.00 15.00 37.51 2.00 7.00 3.50 5.00 2*T3
Typ.
37.70
Max.
Unit
37.89
17.00 19.00 3*T3
Figure ENCODE Timing Diagram
TXCLK
CTXD0.7, CTXP, CTXC0.1, PERR, TERR BTXD0.9
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DATACOM PRODUCTS
GA9103
Table Characteristics DECODE
Parameter
Description
RXCLK Pulse Width HIGH RXCLK Pulse Width RXCLK Period BRXD0.9, SYNC Valid RXCLK BRXD0.9, SYNC Valid from RXCLK CRXD0.7, CRXP, ERROR, CRXS0.2, RWSTART Valid RXCLK CRXD0.7, CRXP, ERROR, CRXS0.2, RWSTART Valid from RXCLK CRXD0.7, CRXP, ERROR, CRXS0.2, RWSTART from RXCLK DECODE Latency
Min.
(T22/2) (T22/2) 37.51 1.00 8.00 4.70 18.25 2.50 6*T22
Typ.
Max.
Unit
37.70
37.89
11.00 7*T22
Note:
DECODE functional block clocks negative edge RXCLK.
Figure DECODE Timing Diagram
RXCLK BRXD0.9, SYNC CRXD0.7, CRXP, ERROR, CRXS0.2, RWSTART
Table Characteristics Miscellaneous
Parameter
Description
RESETN Pulse Width
Min.
Typ.
Max.
Unit
Figure RESETN Timing Diagram
RESETN
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GA9103
Figure GA9103 Pinout
CTXD7 CTXP PERR TERR RAWTx RAWRx RESETN RWSTART ERROR WSYNC CRXS2 CRXS1
BTXD5 BTXD6 BTXD7 BTXD8 BTXD9 TXCLK RXCLK BRXD0 BRXD1 BRXD2 BRXD3 BRXD4 BRXD5
CTXD6 CTXD5 CTXD4 CTXD3 CTXD2 CTXD1 CTXD0 CTXC0 CTXC1 BTXD0 BTXD1 BTXD2 BTXD3 BTXD4
GA9103-2CC
(TOP VIEW)
CRXS0 CRXD0 CRXD1 CRXD2 CRXD3 CRXD4 CRXD5 CRXD6 CRXD7 CRXP SYNC BRXD9 BRXD8 BRXD7 BRXD6
Table Definitions
Symbol
CRXD0.7 CRXS0 CRXS1 CRXS2 BRXD0.9 RXCLK SYNC TXCLK BTXD0.9 CTXD0.7 CTXC0 TERR RWSTART CTXC1 WSYNC RAWTx RESETN ERROR PERR CRXP CTXP RAWRx RESERVED
Output Output Output Output Input Input Input Input Output Input Input Output Output Input Output Input Input Output Output Output Input Input Input Input
Quantity
Logic Level
Active
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
Description
Receive Data Output Receive Control Receive Error Line State Receive Data Input Receive Byte Clock Receive Byte Sync Transmit Byte Clock Transmit Data Output Transmit Data Input Transmit Control Transmit Error Start Word Generate Word Synchronized Mode Transmit System Reset Illegal Line Code Disparity Received Parity Error Parity Output Parity Input Mode Receive Volt Supply Ground
59-57, 55-51 37-39, 41-43, 45-48 22-24, 26-28, 30-32 17-13, 11-9
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DATACOM PRODUCTS
GA9103
Figure 68-Pin Plastic Leaded Chip Carrier (PLCC)
.800 REF. .045 .003 .045 .020 MIN. .009 .001
.045 +.003
.030 .005
.990 .005
(BOTTOM VIEW)
.050 TYP.
.910 .020
.954 .002 .029 .003 .018 .003
.990 .005
.954 .002 .110 .020 (All dimensions inches)
.025 MIN. .182 .018
Ordering Information
GA9103-ENDEC MBaud Fibre Channel ENDEC
Supporting Products
GA9101-2MC GA9102-2MC
Additional Information
Transmitter Receiver
latest specifications, additional product information, worldwide sales distribution locations, information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
technical questions additional information specific applications: Email: applications@tqs.com
information provided herein believed reliable; TriQuint assumes liability inaccuracies omissions. TriQuint assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. TriQuint does authorize warrant TriQuint product life-support devices and/or systems. Copyright 1997 TriQuint Semiconductor, Inc. rights reserved. Revision 1.1.A November 1997
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