LC2MOS 8-Bit with Output Amplifiers AD7224 GENERAL DESCRIPTION

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LC2MOS 8-Bit with Output Amplifiers AD7224 GENERAL DESCRIPTION

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FEATURES 8-Bit CMOS with Output Amplifiers Operates with Single Dual Supplies Total Unadjusted Error: Less Than Over Temperature Extended Temperature Range Operation P-Compatible with Double Buffered Inputs Standard 18-Pin DIPs, 20-Terminal Surface Mount Package SOIC Package
LC2MOS 8-Bit with Output Amplifiers AD7224
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7224 precision 8-bit voltage-output, digital-toanalog converter, with output amplifier double buffered interface logic monolithic CMOS chip. external trims required achieve full specified performance part. double buffered interface logic consists 8-bit registers-an input register register. Only data held registers determines analog output converter. double buffering allows simultaneous update system containing multiple AD7224s. Both registers made transparent under control three external lines, LDAC. With both registers transparent, RESET line functions like zero override; useful function system calibration cycles. logic inputs CMOS level compatible control logic speed compatible with most 8-bit microprocessors. Specified performance guaranteed input reference voltages from +12.5 when using dual supplies. part also specified single supply operation using reference output amplifier capable developing across load. AD7224 fabricated ion-implanted high speed Linear Compatible CMOS (LC2MOS) process which been specifically developed allow high speed digital logic circuits precision analog circuits integrated same chip.
Amplifier CMOS Chip single-chip design 8-bit output amplifier inherently more reliable than multi-chip designs. CMOS fabrication means power consumption typical with single supply). Total Unadjusted Error fabrication AD7224 Analog Devices Linear Compatible CMOS (LC2MOS) process coupled with novel switch-pair arrangement, enables excellent total unadjusted error less than over full operating temperature range. Single Dual Supply Operation voltage-mode configuration AD7224 allows operation from single power supply rail. part also operated with dual supplies giving enhanced performance some parameters. Versatile Interface Logic high speed logic allows direct interfacing most microprocessors. Additionally, double buffered interface enables simultaneous update AD7224 multiple systems. part also features zero override function.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7224-SPECIFICATIONS
DUAL SUPPLY
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Temperature Coefficient Zero Code Error Zero Code Error Temperature Coefficient REFERENCE INPUT Voltage Range Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Leakage Current Input Capacitance3 Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate3 Voltage Output Settling Time3 Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough Minimum Load Resistance POWER SUPPLIES Range Range 25°C TMIN TMAX 25°C TMIN TMAX SWITCHING CHARACTERISTICS3, 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX
(VDD 11.4 16.5 10%; AGND DGND VREF (VDD unless otherwise noted. specifications TMIN TMAX unless otherwise noted.)
Versions2 (VDD Binary 11.4/16.5 4.5/5.5 Versions2 (VDD Binary 11.4/16.5 4.5/5.5 Units Bits ppm/°C µV/°C Conditions/Comments
VREF Guaranteed Monotonic 16.5 VREF
Occurs when loaded with
V/µs secs min/V min/V VREF Settling Time VREF Settling Time VREF VOUT Specified Performance Specified Performance Outputs Unloaded; VINL VINH Outputs Unloaded; VINL VINH Outputs Unloaded; VINL VINH Outputs Unloaded; VINL VINH
Chip Select/Load Pulse Width
Write/Reset Pulse Width
Chip Select/Load Write Setup Time
Chip Select/Load Write Hold Time
Data Valid Write Setup Time
Data Valid Write Hold Time
NOTES Maximum possible reference voltage. Temperature ranges follows: Versions: -40°C +85°C Versions: -40°C +85°C Versions: -55°C +125°C Sample Tested 25°C Product Assurance ensure compliance. Switching characteristics apply single dual supply operation. Specifications subject change without notice.
REV.
AD7224 SINGLE SUPPLY
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Differential Nonlinearity REFERENCE INPUT Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Leakage Current Input Capacitance3 Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough3 Minimum Load Resistance POWER SUPPLIES Range 25°C TMIN TMAX SWITCHING CHARACTERISTICS3, 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX
(VDD AGND DGND VREF unless otherwise noted. specifications TMIN TMAX unless otherwise noted.)
Versions2 Binary 14.25/15.75 Versions2 Binary 14.25/15.75 Units Bits Conditions/Comments
Guaranteed Monotonic
Occurs when loaded with
V/µs secs min/V Settling Time Settling Time VREF VOUT Specified Performance Outputs Unloaded; VINL VINH Outputs Unloaded; VINL VINH
Chip Select/Load Pulse Width
Write/Reset Pulse Width
Chip Select/Load Write Setup Time
Chip Select/Load Write Hold Time
Data Valid Write Setup Time
Data Valid Write Hold Time
NOTES Maximum possible reference voltage. Temperature ranges follows: AD7224KN, +70°C AD7224BQ, -25°C +85°C AD7224TD, -55°C +125°C Terminology. Sample tested 25°C Product Assurance ensure compliance. Specifications subject change without notice.
REV.
AD7224
ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE
AGND -0.3 DGND -0.3 -0.3 AGND DGND -0.3 Digital Input Voltage DGND -0.3 VREF AGND -0.3 VOUT AGND2 VSS, Power Dissipation (Any Package) +75°C Derates above 75°C mW/°C Operating Temperature Commercial Versions) -40°C +85°C Industrial Versions) -40°C +85°C Extended Versions) -55°C +125°C Storage Temperature -65°C +150°C Lead Temperature (Soldering, secs) +300°C
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. outputs shorted AGND provided that power dissipation package exceeded. Typically short circuit current AGND
Model1 AD7224KN AD7224LN AD7224KP AD7224LP AD7224KR-1 AD7224LR-1 AD7224KR-18 AD7224LR-18 AD7224BQ AD7224CQ AD7224TQ AD7224UQ AD7224TE AD7224UE
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C
Total Unadjusted Error (LSB)
Package Option2 N-18 N-18 P-20A P-20A R-20 R-20 R-18 R-18 Q-18 Q-18 Q-18 Q-18 E-20A E-20A
NOTES order MIL-STD-883 processed parts, /883B part number. Contact your local sales office military data sheet. Leadless Ceramic Chip Carrier; Plastic DIP; Plastic Leaded Chip Carrier; Cerdip; SOIC.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7224 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality. CONFIGURATIONS SOIC
VOUT VREF AGND DGND (MSB) RESET
VOUT VREF AGND DGND (MSB)
WARNING!
SENSITIVE DEVICE
(SOIC)
RESET
(SOIC)
VOUT VREF AGND DGND (MSB)
RESET LDAC
LDAC
LDAC
AD7224
(LSB)
AD7224
R-18
(LSB)
AD7224
R-20
VIEW (Not Scale)
VIEW (Not Scale)
VIEW (Not Scale) (LSB)
LCCC
RESET VOUT VOUT
PLCC
RESET
CONNECT
VREF AGND DGND (MSB)
LDAC
VREF AGND DGND (MSB)
LDAC
AD7224
VIEW (Not Scale)
(LSB)
AD7224
VIEW (Not Scale)
(LSB)
CONNECT
CONNECT
REV.
AD7224
TERMINOLOGY
TOTAL UNADJUSTED ERROR
VOUT VREF where fractional representation digital input code vary from 255/256.
OP-AMP SECTION
Total Unadjusted Error comprehensive specification which includes full-scale error, relative accuracy zero code error. Maximum output voltage VREF (ideal), where (ideal) VREF/256. size will vary over VREF range. Hence zero code error, relative size, will increase VREF decreases. Accordingly, total unadjusted error, which includes zero code error, will also vary terms LSBs over VREF range. result, total unadjusted error specified fixed reference voltage
RELATIVE ACCURACY
voltage-mode converter output buffered unity gain noninverting CMOS amplifier. This buffer amplifier capable developing across load drive capacitive loads 3300 AD7224 operated single dual supply resulting different performance some parameters from output amplifier. single supply operation (VSS AGND) sink capability amplifier, which normally reduced output voltage nears AGND. full sink capability maintained over full output voltage range tying This indicated Figure
Relative Accuracy endpoint nonlinearity measure maximum deviation from straight line passing through endpoints transfer function. measured after allowing zero code error full-scale error normally expressed LSBs percentage full-scale reading.
DIFFERENTIAL NONLINEARITY
ISINK
Differential Nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity over operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGH
+15V 25°C
Digital Feedthrough glitch impulse transferred output change digital input code. specified secs measured VREF
FULL-SCALE ERROR
VOUT Volts
Full-Scale Error defined Measured Value Zero Code Error Ideal Value
Figure Variation ISINK with VOUT
CIRCUIT INFORMATION
SECTION
AD7224 contains 8-bit voltage-mode digital-to-analog converter. output voltage from converter same polarity reference voltage, allowing single supply operation. novel switch pair arrangement AD7224 allows reference voltage range from +12.5 consists highly stable, thin-film, R-2R ladder eight high speed NMOS single pole, double-throw switches. simplified circuit diagram this shown Figure
VREF AGND SHOWN VOUT
Settling-time negative-going output signals approaching AGND similarly affected VSS. Negative-going settling-time single supply operation longer than dual supply operation. Positive-going settling-time affected VSS. Additionally, negative gives more headroom output amplifier which results better zero code performance improved slew-rate output, than obtained single supply mode.
DIGITAL SECTION
AD7224 digital inputs compatible with either CMOS levels. logic inputs static-protected gates with typical input currents less than Internal input protection achieved on-chip distributed diode between DGND each gate. minimize power supply currents, recommended that digital input voltages driven close supply rails (VDD DGND) practically possible.
INTERFACE LOGIC INFORMATION
Figure Simplified Circuit Diagram
input impedance VREF code dependent vary from minimum infinity. lowest input impedance occurs when loaded with digital code 01010101. Therefore, important that reference presents output impedance under changing load conditions. nodal capacitance reference terminals also code dependent typically varies from VOUT considered digitally programmable voltage source with output voltage REV.
Table shows truth table AD7224 operation. part contains registers, input register register. control loading input register while LDAC control transfer information from input register register. Only data held register will determine analog output converter. control signals level-triggered therefore either both registers made transparent; input register keeping "LOW", register keeping LDAC "LOW". Input data latched rising edge
AD7224
Table AD7224 Truth Table
RESET LDAC Function Both Registers Transparent Both Registers Latched Both Registers Latched Input Register Transparent Input Register Latched Register Transparent Register Latched Both Registers Loaded With Zeros Both Register Latched With Zeros Output Remains Zero Both Registers Transparent Output Follows Input
+2.5 bandgap reference AD584, precision reference. Note that order achieve output voltage range nominal power supply voltage required AD7224.
GROUND MANAGEMENT
transient voltages between AGND DGND cause noise analog output. This especially true microprocessor systems where digital noise prevalent. simplest method ensuring that voltages AGND DGND equal AGND DGND together AD7224. more complex systems where AGND DGND intertie backplane, recommended that diodes connected inverse parallel between AD7224 AGND DGND pins (IN914 equivalent).
High State, State, Don't Care. control inputs level triggered.
contents both registers reset level RESET line. With both registers transparent, RESET line functions like zero override with output brought duration RESET pulse. both registers latched, "LOW" pulse RESET will latch into registers output remains after RESET line returned "HIGH". RESET line used ensure power-up AD7224 output also useful, when used zero override, system calibration cycles. Figure shows input control logic AD7224.
LDAC RESET INPUT DATA INPUT REGISTER REGISTER
Applying AD7224
UNIPOLAR OUTPUT OPERATION
This basic mode operation AD7224, with output voltage having same positive polarity VREF. AD7224 operated single supply (VSS AGND) with positive/negative supplies (see op-amp section which outlines advantages having negative VSS). Connections unipolar output operation shown Figure voltage VREF must never negative with respect DGND. Failure observe this precaution cause parasitic transistor action possible device destruction. code table unipolar output operation shown Table
VREF DATA (8-BIT) LDAC VOUT
Figure Input Control Logic
AD7224
AGND DGND
RESET
LDAC
DATA
Figure Unipolar Output Circuit
Table III. Unipolar Code Table
Register Contents 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 Analog Output
DATA VALID
NOTES: INPUT SIGNAL RISE FALL TIMES MEASURED FROM 20ns OVER RANGE VINH TIMING MEASUREMENT REFERENCE LEVEL
Figure Write Cycle Timing Diagram
SPECIFICATION RANGES
maintain specified accuracy, reference voltage must least below power supply voltage. This voltage differential required correct generation bias voltages switches. With dual supply operation, AD7224 extended range from (i.e., from +11.4 +16.5 Operation also specified single power supply Performance specified over wide range reference voltages from (VDD with dual supplies. This allows range standard reference generators used such AD580,
Note:
REV.
AD7224
BIPOLAR OUTPUT OPERATION
AD7224 configured provide bipolar output operation using external amplifier resistors. Figure shows circuit used implement offset binary coding. this case
VREF
AGND VBIAS
VOUT
AD7224
DGND
With VREF where fractional representation digital word register. Mismatch between causes gain offset errors; therefore, these resistors must match track over temperature. Once again, AD7224 operated single supply from positive/negative supplies. Table shows digital code versus output voltage relationship circuit Figure with
VREF DATA (8-BIT) LDAC RESET AGND DGND VOUT +15V
Figure AGND Bias Circuit
MICROPROCESSOR INTERFACE
ADDRESS
8085A 8088
ADDRESS DECODE
LDAC
AD7224*
LATCH ADDRESS DATA *LINEAR CIRCUITRY OMITTED CLARITY
VREF
+15V VOUT
Figure AD7224 8085A/8088 Interface
ADDRESS 6809 6502 ADDRESS DECODE LDAC
AD7224
±0.1%
Figure Bipolar Output Circuit
AD7224*
DATA *LINEAR CIRCUITRY OMITTED CLARITY
Table III. Bipolar (Offset Binary) Code Table
Register Contents 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 Analog Output
Figure AD7224 6809/6502 Interface
ADDRESS
Z-80
ADDRESS DECODE LDAC
AD7224*
DATA *LINEAR CIRCUITRY OMITTED CLARITY
AGND BIAS
Figure AD7224 Z-80 Interface
ADDRESS 68008 ADDRESS DECODE LDAC
AD7224 AGND biased above system (AD7224 DGND) provide offset "zero" analog output voltage level. Figure shows circuit configuration achieve this. output voltage, VOUT, expressed VOUT VBIAS (VIN) where fractional representation digital word register vary from 255/256. given VIN, increasing AGND above system will reduce effective VDD-VREF which must least ensure specified operation. Note that AD7224 must referenced DGND. REV.
DTACK
AD7224*
DATA *LINEAR CIRCUITRY OMITTED CLARITY
Figure AD7224 68008 Interface
AD7224
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
18-Pin Plastic (Suffix
18-Pin Cerdip (Suffix
18-Pin Ceramic (Suffix
18-Lead SOIC (R-18)
0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00)
0.4625 (11.75) 0.4469 (11.35)
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
PLCC Package P-20A
0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) IDENTIFIER VIEW 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.020 (0.50) 0.356 (9.04) 0.350 (8.89) 0.395 (10.02) 0.385 (9.78) 0.110 (2.79) 0.085 (2.16)
0.180 (4.57) 0.165 (4.19) 0.025 (0.63) 0.015 (0.38)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27)
0.0192 (0.49) 0.0138 (0.35)
0.0125 (0.32) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
0.048 (1.21) 0.042 (1.07)
20-Lead SOIC (R-20)
0.050 (1.27)
0.040 (1.01) 0.025 (0.64)
0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00)
LCCC Package E-20A
0.100 (2.54) 0.064 (1.63) 0.075 (1.91) 0.200 (5.08) 0.100 (2.54) 0.015 (0.38)
0.5118 (13.00) 0.4961 (12.60)
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
0.358 (9.09) 0.342 (8.69) 0.358 (9.09)
0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) 0.075 (1.91)
BOTTOM VIEW
0.028 (0.71) 0.022 (0.56)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27)
0.0192 (0.49) 0.0138 (0.35)
0.0125 (0.32) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
0.050 (1.27)
0.088 (2.24) 0.054 (1.37)
0.055 (1.40) 0.045 (1.14)
0.150 (3.81)
REV.
PRINTED U.S.A.
C836a-10-10/84

LC2MOS 8-Bit with Output Amplifiers AD7224 GENERAL DESCRIPTION

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