3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-

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3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-

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IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP, 0.40mm pitch TVSOP packages Extended commercial range 40°C 85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µW typ. static) Rail-to-Rail output swing increased noise margin Drive Features ALVCHR16270: Balanced Output Drivers: ±12mA switching noise
IDT74ALVCHR16270
CMOS technology. ALVCHR16270 used applications which data must transferred from narrow high-speed wide lowerfrequency bus. This device provides synchronous data exchange between ports. Data stored internal registers low-to-high transition clock (CLK) input when appropriate clock-enable (CLKEN) inputs low. select (SEL) line selects data outputs. data transfer A-to-B direction, two-stage pipeline provided A-to-1B path, with single storage register A-to-2B path. Proper control these inputs allows sequential 12-bit words presented synchronously 24-bit word B-port. Data flow controlled active-low output enables (OEA OEB). control terminals registered synchronize bus-direction changes with CLK. ALVCHR16270 series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been designed drive ±12mA designated threshold levels. ALVCHR16270 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
DESCRIPTION:
This registered exchanger built using advanced dual metal
FUNCTIONAL BLOCK DIAGRAM
CLKEN1B
CLKEN2B
CLKE
1999 Integrated Device Technology, Inc.
JUNE 1999
DSC-4578/-
IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
CONFIGURATION
FUNCTION TABLES
Inputs
Outputs Active Active
1Bx,
OUTPUT ENABLE
CLKEN1B
SO56-1 SO56-2 SO56-3
CLKENA2
Active Active
A-TO-B STORAGE (OEB
Inputs CLKENA1 CLKENA2 Outputs
1BO(2) 1BO(2) 2BO(2) 2BO(2)
L(3) H(3) 1BO(2) 1BO(2) 1BO(2)
2BO(2)
B-TO-A STORAGE (OEA
Inputs CLKEN1B CLKEN2B
Outputs AO(2) AO(2)
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established. edges needed propagate data.
CLKEN2B
CLKENA1
SSOP/ TSSOP/TVSOP VIEW
IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
DESCRIPTION
Names Ax(1:12)
1Bx(1:12) 2Bx(1:12)
Description Bidirectional Data Port Usually connected CPU's Address/Data bus.(1) Bidirectional Data Port Usually connected even path even bank memory.(1) Bidirectional Data Port Usually connected path bank memory.(1) Clock Input Clock Enable Input A-1B Register. CLKENA1 during rising edge CLK, data will clocked into register A-1B (Active LOW). Clock Enable Input A-2B Register. CLKENA2 during rising edge CLK, data will clocked into register A-2B (Active LOW). Clock Enable Input 1B-A Register. CLKEN1B during rising edge CLK, data will clocked into register 1B-A (Active LOW). Clock Enable Input 2B-A Register. CLKEN2B during rising edge CLK, data will clocked into register 2B-A (Active LOW). Port Selection. When HIGH during rising edge CLK, enables data transfer from Port Port. When during rising edge CLK, enables data transfer from Port Port. Synchronous Output Enable Port (Active LOW) Synchronous Output Enable Port (Active LOW)
CLKENA1 CLKENA2 CLKEN1B CLKEN2B
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Unit
NEW16link
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NEW16link
Max. ±100
NOTE: applicable device type.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
NEW16link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
NEW16link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Propagation Delay Propagation Delay Propagation Delay Output Enable Time Output Disable Time Setup Time, data before Setup Time, data before Setup Time, CLKENA1 CLKENA2 before Setup Time, CLKEN1B CLKEN2B before Setup Time, before Hold Time, data after Hold Time, data after Hold Time, CLKENA1 CLKENA2 after Hold Time, CLKEN1B CLKEN2B after Hold Time, after Pulse Width, HIGH Output Skew(2) Parameter
2.5V 0.2V Min. Max.
2.7V Min. Max.
3.3V 0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
TEST CIRCUITS WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH LOAD/2 tPHZ tPLZ DISABLE LOAD/2
ALVC Link
LOAD Open
D.U.T.
ALVC Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM
ALVC Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
NEW16link
OUTPUT SKEW INPUT
tPHL1
tPLH1
PULSE WIDTH
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
ALVC Link
OUTPUT
OUTPUT tPLH2 tPHL2
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
ALVC Link
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCHR16270 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
ORDERING INFORMATION
ALVC Device Type Package Range Bus-Hold
Shrink Outline Package (SO56-1) Thin Shrink Outline Package (SO56-2) Thin Very Outline Package (SO56-3) 12-Bit 24-Bit Registered Exchanger 3-State Outputs Double-D ensity, ±12m Bus-Hold -40°C +85°C
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3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-

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