184-pin Unbuffered DDR-I SDRAM Modules 256MB 512MB Modules Prelim
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HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
184-pin Unbuffered DDR-I SDRAM Modules
256MB 512MB Modules Preliminary Datasheet Rev. 0.99
184-pin Unbuffered 8-Byte Dual-In-Line DDR-I SDRAM non-parity ECC-Modules Server main memory applications bank bank organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) Single power supply Built with 256Mbit DDR-I SDRAMs organisaed 32Mb 66-Lead TSOPII package Programmable Latency, Burst Length, Wrap Sequence (Sequential Interleave) Performance: Component Speed Grade Module Speed Grade
Auto Refresh (CBR) Self Refresh inputs outputs SSTL_2 compatible Serial Presence Detect with 2PROM Jedec standard MO-206a form factor: 133.35 31.75 4.00 Jedec standard reference layout Gold plated contacts
-7.5 PC2100
PC1600
Unit
DDR266A DDR266B DDR200 PC2100
Clock Frequency (max.) Clock Frequency (max.)
HYS64/72Dxx0x0GU industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized non-parity main memory applications. memory array designed with Double Data Rate Synchronous DRAMs. variety decoupling capacitors mounted board. DIMMs feature serial presence detect based serial E2PROM device using 2-pin protocol. first bytes programmed with configuration data second bytes available customer.
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HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Ordering Information Type PC2100 (CL=2): HYS64D32000GU-7 HYS72D32000GU-7 HYS64D64020GU-7 HYS72D64020GU-7 PC2100 (CL=2.5): HYS64D32000GU-7.5 HYS72D32000GU-7.5 HYS64D64020GU-7.5 HYS72D64020GU-7.5 PC1600 (CL=2): HYS64D32000GU-8 HYS72D32000GU-8 HYS64D64020GU-8 HYS72D64020GU-8 PC1600-20220-B1 PC1600-20220-B1 PC1600-20220-A1 PC1600-20220-A1
bank DIMM bank ECC-DIMM banks DIMM banks ECC-DIMM
Compliance Code
Description
SDRAM Technology
PC2100-20330-B1 PC2100-20330-B1 PC2100-20330-A1 PC2100-20330-A1 PC2100-25330-B1 PC2100-25330-B1 PC2100-25330-A1 PC2100-25330-A1
bank DIMM bank ECC-DIMM banks DIMM banks ECC-DIMM
MBit Mbit MBit MBit MBit Mbit MBit MBit MBit Mbit MBit MBit
bank DIMM bank ECC-DIMM banks DIMM banks ECC-DIMM
Note: part numbers with place code (not shown), designating silicon-die revision. Reference information available request. Example: 72D32000GU-8-A, indicating Rev.A used SDRAM components.
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2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Definitions Functions BA0, DQ63 CKE0 CKE1 DQS0 DQS8 CLK0 CLK2, CLK0 CLK2 DQS9 DQS17 Address Inputs Bank Selects Data Input/Output Chip Selects Power Ground Driver power supply Indentification flag reference supply Serial EEPROM power supply Serial clock Serial data line slave address select connect
VDDID VREF VDDSPD
Check Bits (x72 organization only) VDDQ Address Strobe Column Address Strobe Read/Write Input Clock Enable SDRAM data strobes SDRAM clock (positive lines) SDRAM clock (negative lines) SDRAM data mask/ high data strobes
Address Format Density Organization Memory SDRAMs Banks row/bank/ Refresh Period Interval SDRAMs columns bits 13/2/10 13/2/10 13/2/10 13/2/10
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2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Configuration
PIN#
Frontside Symbol
VREF DQS0 DQS1 VDDQ CLK1 CLK1 DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 DQ18 VDDQ DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 DQS8
Frontside PIN# Symbol
DQ32 VDDQ DQ33 DQS4 DQ34 DQ35 DQ40 VDDQ DQ41 DQS5 DQ42 DQ43 DQ48 DQ49 CLK2 CLK2 VDDQ DQS6 DQ50 DQ51 VDDID DQ56 DQ57 DQS7 DQS8 DQ59
Backside PIN# Symbol
VDDQ DM0/DQS9 VDDQ DQ12 DQ13 DM1/DQS10 DQ14 DQ15 CKE1 VDDQ (BA2) DQ20 DQ21 DM2/DQS11 DQ22 DQ23 DQ28 DQ29 VDDQ DM3/DQS12 DQ30 DQ31 VDDQ
Backside PIN# Symbol
DM8/DQS17 VDDQ DQ36 DQ37 DM4/DQS13 DQ38 DQ39 DQ44 DQ45 VDDQ DM5/DQS14 DQ46 DQ47 VDDQ DQ52 DQ53 (A13) DM6/DQS15 DQ54 DQ55 VDDQ DQ60 DQ61 DM7/DQS16 DQ62 DQ63 VDDQ VDDSPD
Note: Pins 134, 135, ("no-connects") organised non-ECC modules
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2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
DQS0 DM0/DQS9
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS1 DM1/DQS10
DQ10 DQ12 DQ13 DQ14 DQ15
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Clock Wiring Serial BA0, BA1: SDRAMs A12: SDRAMs VDD, VDDQ VREF VDDID SDRAMs CKE0 SDRAMs SDRAMs CKE: SDRAMs Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 SDRAMs SDRAMs SDRAMs SDRAMs
Wire Clock Loading Table/Wiring Diagrams
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/S relationships must maintained shown. DQS, DM/DQS resistors: Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP (OPEN): VDDQ
Block Diagram: Bank DDR-I SDRAM DIMM Module HYS64D32000GU using organized SDRAMs Card Version
INFINEON Technologies
2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
DQS0 DM0/DQS9
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS1 DM1/DQS10
DQ10 DQ12 DQ13 DQ14 DQ15
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Clock Wiring
BA0, VDD, VDDQ VREF VDDID
BA0, BA1: SDRAMs A12: SDRAMs
Serial
Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2
SDRAMs SDRAMs SDRAMs SDRAMs
Wire Clock Loading Table/Wiring Diagrams
CKE1 CKE0
CKE: SDRAMs SDRAMs SDRAMs CKE: SDRAMs SDRAMs
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/S relationships must maintained shown. DQS, DM/DQS resistors: Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP (OPEN): VDDQ
Block Diagram: Bank DDR-I SDRAM DIMM Modules HYS64D64020GU using Organized SDRAMs Card Version
INFINEON Technologies
2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
DQS0 DM0/DQS9
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS1 DM1/DQS10
DQ10 DQ12 DQ13 DQ14 DQ15
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS8 DM8/DQS17
BA0, VDD, VDDQ VREF VDDID Serial
BA0, BA1: SDRAMs A12: SDRAMs SDRAMs Wire Clock Loading Table/Wiring Diagrams CKE0 SDRAMs CKE: SDRAMs SDRAMs Clock Wiring Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 SDRAMs SDRAMs SDRAMs SDRAMs
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/S relationships must maintained shown. DQS, DM/DQS resistors: Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP (OPEN): VDDQ
Block Diagram: Bank DDR-I SDRAM DIMM Module HYS72D32000GU using organized SDRAMs Card Version INFINEON Technologies 2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
DQS0 DM0/DQS9
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS1 DM1/DQS10
DQ10 DQ12 DQ13 DQ14 DQ15
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS8 DM8/DQS17
Clock iring BA0, BA0, BA1: SDRAMs A12: SDRAMs VDD, VDDQ VREF VDDID Serial Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 SDRAMs SDRAMs SDRAMs SDRAMs
Wire Clock Loading Table/Wiring Diagrams
CKE1 CKE0
CKE: SDRAMs SDRAMs SDRAMs CKE: SDRAMs SDRAMs
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/S relationships must maintained shown. DQS, DM/DQS resistors: Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP (OPEN): VDDQ
Block Diagram: Bank DDR-I SDRAM DIMM Modules HYS72D64020GU using Organized SDRAMs Card Version INFINEON Technologies 2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
oads
DRAM
DRAM
Clock Wiring
INFINEON Technologies
2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Supply Voltage Levels Parameter Device Supply Voltage Output Supply Voltage Input Reference Voltage Termination Voltage
Symbol min.
Limit Values nom. 1.25 max. 1.35 1.15
Unit
Notes
VDDQ VREF
VREF 0.04 VREF
VREF 0.04
Under conditions, VDDQ must less than equal VDD. Peak peak noise VREF exceed VREF (DC). VREF also expected track noise variations VDDQ. transmitting device must track VREF receiving device.
Operating Conditions (SSTL_2 Inputs) (VDDQ Voltage Referenced VSS) Parameter Symbol min. Input Logic High Input Logic Input Leakage Current Output Leakage Current
Limit Values max.
Unit
Notes
(DC) (DC)
VREF 0.18
0.30
VDDQ VREF 0.18
relationship between VDDQ driving device VREF receiving device what determines noise margins. However, case (max) (input overdrive), VDDQ receiving device that referenced. case where device implemented such that supports SSTL_2 inputs SSTL_2 outputs (such translator), therefore VDDQ supply voltage connection, inputs must tolerate input overdrive (High corner VDDQ mV). under test input VDDQ Values shown DDR-SDRAM component-
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2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Operating, Standby Refresh Currents reference only) (values apply SDRAM component 266A&B
Symbol
Parameter/Condition Operating Current: bank; active precharge;
Unit
Notes
IDD0
MIN; inputs changing twice clock cycle; address control inputs changing once clock cycle
Operating Current: bank; active read precharge; IDD1
Burst 2.5; MIN; IOUT 0mA; address control inputs changing once clock cycle
IDD2P
Precharge Power-Down Standby Current: banks
idle; power-down mode; MAX;
Idle Standby Current: MIN; banks idle; IDD2N
MIN; MIN; address control inputs changing once clock cycle
IDD3P
Active Power-Down Standby Current: bank active;
power-down mode;
MAX;
Active Standby Current: bank; active precharge;CS IDD3N
MIN; tRAS MAX; inputs changing twice clock cycle; address control inputs changing once clock cycle
Operating Current: bank; Burst reads; continuous IDD4R
burst; address control inputs changing once clock cycle; outputs changing twice clock cycle; 2.5; MIN; IOUT
Operating Current: bank; Burst writes; continuous IDD4W
burst; address control inputs changing once clock cycle; inputs changing twice clock cycle; 2.5;
IDD5 IDD6 IDD7
Auto-Refresh Current: tRFC Self-Refresh Current: 0.2V Operating Current: four banks; ffour bank interleaving with
BL=4, address control inputs randomly changing; data changing every transfer; MIN; IOUT 0mA;
specifications tested after device properly initialized. Input slew rate 1V/ns. Enables on-chip refresh address counters.
INFINEON Technologies
2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Characteristics (for reference only) (values apply SDRAM component
Parameter Symbol DDR266A min. Output Access Time from CK/CK Output access Time from CK/CK High Level Width Level Width Clock Period Input Hold Time Input Setup Time Input Pulse Width (for each input) Data-Out High-impedance from CK/CK Data-Out Low-impedance from CK/CK Write Command First Latching Transition DQS-DQ Skew Data-Out Hold Time from input (high) pulse width (write cycle) falling edge setup time (write cycle) falling edge hold time from (write cycle) Mode register command cycle time Write Preamble Setup Time Write Postamble Write Preamble Address control input setup time Address control input hold time Read Preamble Read Postamble Active Time Cycle Time Operation Auto Refresh Delay Precharge Time Active bank Active bank command max. 0.75 0.75 0.55 0.55 0.75 0.75 1.25 120K -7.5 DDR266B min. 0.75 0.75 0.45 0.45 1.75 0.75 0.75 0.75 tHP0.75 0.35 0.25 max. 0.75 0.75 0.55 0.55 0.75 0.75 1.25 120k DDR200 min. 0.45 0.45 0.75 max. 0.55 0.55 1.25
Unit
Notes
tDQSCK tDIPW tDQSS tDQSQ tDQSL;H tDSS tDSH tMRD tWPRES tWPST tWPRE tRPRE tRPST tRAS tRFC tRCD tRRD
0.75 0.75 0.45 0.45 1.75 0.75 0.75 0.75 tHP0.75 0.35 0.25
tHP-1.0 0.35 0.25 120K
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2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Parameter
Symbol
DDR266A min. max.
-7.5 DDR266B min. max.
DDR200 min. max.
Unit
Notes
Write Recovery Time Auto Precharge Write Recovery Precharge Time Internal Write Read Command Delay Exit self-refresh non-read command Exit self-refresh read command Average Periodic Refresh Intercal Transition Time
tDAL tWTR tXSNR tXSDR tREF
(twr/tck trp/tck)
Minimum Auto Refresh cycle time greater than minimum cycle time during normal Read Write operation. lesser These parameters guarantee device timing, they necessarily tested each device they guaranteed design tester correlation =0.9ns DDR266 measured with command address input slew rate 1.0V/ns command address input slew rate 0.5V/ns 1.0V/ns 1.0ns should guaranteed design DDR200 1.2ns command address input slew rate 1.0V/ns assumed slew rate measured between VOH(AC) (AC) slew rates assumed 1.0V/ns Pulse width command address signals properly sampled rising edges clock shall minimum 2.2ns
Environmental Parameters
Symbol TOPR HOPR TSTG HSTG Parameter Operating Temperature (ambient) Operating Humidity (relative) Storage Temperature Storage Humidity (without condensation) Barometric Pressure (operating storage)
Rating +100
Units
Notes
Pascal
stresses greater than those listed cause permanent damage device. Device functional operation above these conditions implied. 3000 (9850
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2.01
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Codes PC1600 Modules "-8" Byte# Description Entry Value 256MByte bank MByte banks MBYte banks 2.01 MByte bank
Number Bytes Total Bytes Serial Memory Type Number Addresses
(without bits)
DDR-SDRAM SSTL_2.5 non-ECC Self-Refresh, tCCD latency latency Write latency unbuffered 10.0 supported supported
Number Column Addresses Number DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time SDRAM Access Time from Clock DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay Back-toBack Random Column Address Burst Length Supported Number SDRAM Banks Supported Latencies Latencies Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time Latency Max. Data Access Time from Clock Minimum Clock Cycle Time Maximum Data Access Time from Clock Minimum Precharge Time
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HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Byte#
Description
Entry Value 256MByte bank
MByte banks MBYte banks 2.01 MByte bank
Minimum Active Active Delay tRRD Minimum Delay tRCD Minimum Pulse Width tRAS Module Bank Density (per bank) Addr. Command Setup Time Addr. Command Hold Time Data Input Setup Time Data Input Hold Time 36-40 Superset Information (may used future) Minimum Core Cycle Time Min. Auto Refresh Cycle Time tRFC Maximum Clock Cycle Time Max. DQS-DQ Skew tDDSQ X-Factor tQHS 46-61 Superset Information (may used future) Revision Checksum Bytes 64-127 Manufacturers Information
256MByte Revision
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HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Codes PC2100 Modules "-7.5" Byte# Description Entry Value 256MByte bank MByte banks MBYte banks 2.01 MByte bank
Number Bytes Total Bytes Serial Memory Type Number Addresses
(without bits)
DDR-SDRAM SSTL_2.5 0.75 non-ECC Self-Refresh, tCCD latency latency Write latency unbuffered 10.0 0.75 supported supported
Number Column Addresses Number DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time SDRAM Access Time from Clock DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay Back-toBack Random Column Address Burst Length Supported Number SDRAM Banks Supported Latencies Latencies Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time Latency Max. Data Access Time from Clock Minimum Clock Cycle Time Maximum Data Access Time from Clock Minimum Precharge Time
INFINEON Technologies
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Byte#
Description
Entry Value 256MByte bank
MByte banks MBYte banks 2.01 MByte bank
Minimum Active Active Delay tRRD Minimum Delay tRCD Minimum Pulse Width tRAS Module Bank Density (per bank) Addr. Command Setup Time Addr. Command Hold Time Data Input Setup Time Data Input Hold Time 36-40 Superset Information (may used future) Minimum Core Cycle Time Min. Auto Refresh Cycle Time tRFC Maximum Clock Cycle Time Max. DQS-DQ Skew tDDSQ X-Factor tQHS 46-61 Superset Information (may used future) Revision Checksum Bytes 64-127 Manufacturers Information
256MByte 0.75 Revision
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HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Codes PC2100 Modules "-7" Byte# Description Entry Value 256MByte bank MByte banks MBYte banks 2.01 MByte bank
Number Bytes Total Bytes Serial Memory Type Number Addresses
(without bits)
DDR-SDRAM SSTL_2.5 0.75 non-ECC Self-Refresh, tCCD latency latency Write latency unbuffered 0.75 supported supported
Number Column Addresses Number DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time SDRAM Access Time from Clock DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay Back-toBack Random Column Address Burst Length Supported Number SDRAM Banks Supported Latencies Latencies Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time Latency Max. Data Access Time from Clock Minimum Clock Cycle Time Maximum Data Access Time from Clock Minimum Precharge Time
INFINEON Technologies
HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Byte#
Description
Entry Value 256MByte bank
MByte banks MBYte banks 2.01 MByte bank
Minimum Active Active Delay tRRD Minimum Delay tRCD Minimum Pulse Width tRAS Module Bank Density (per bank) Addr. Command Setup Time Addr. Command Hold Time Data Input Setup Time Data Input Hold Time 36-40 Superset Information (may used future) Minimum Core Cycle Time Min. Auto Refresh Cycle Time tRFC Maximum Clock Cycle Time Max. DQS-DQ Skew tDDSQ X-Factor tQHS 46-61 Superset Information (may used future) Revision Checksum Bytes 64-127 Manufacturers Information
256MByte 0.75 Revision
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HYS64/72D32000GU HYS64/72D64020GU Unbuffered DDR-I SDRAM-Modules
Package Outlines Simplified Mechanical Drawing
(for details JEDEC document MO-206a)
DDR-I Unbuffered DIMM Modules
133,35 128,93
31.75
19,8
64,77
49,53
Detail
6,62
Detail
2,175
INFINEON Technologies
10,0 17,8
2.01
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