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IA186ES/IA188ES 8/16-BIT Microcontrollers Copyright 2003 IA1


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IA186ES/IA188ES 8/16-BIT Microcontrollers
Copyright 2003
IA186ES/IA188ES
8/16-BIT MICROCONTROLLERS
Data Sheet Contents FEATURES Description Interface Control Peripheral Control Registers.8
Baud Rates
Clock Power Management
System Clocks.
Power-Save Mode Initialization Reset Reset Configuration Register. Chip-Selects Chip-Select Timing
Ready Wait-State Programming.57 Chip-Select Overlap Upper Memory Chip Select.58 Memory Chip Select Midrange Memory Chip Selects Peripheral Chip Selects.59
Refresh Control Interrupt Control Interrupt Types Timer Control Watchdog Timer Direct Memory Access (DMA).63 Operation
Channel Control Registers Priority
Pulse Width Demodulation Asynchronous Serial Ports Programmable (PIO) Descriptions Instruction Summary Absolute Maximum Ratings
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IA186ES/IA188ES
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Characteristics Over Commercial Operating Ranges.99 Characteristics .100
Alphabetic Waveform Parameters .100 Numeric Waveform Parameters .102 Waveforms.104
IA186ES PQFP .119 IA186ES TQFP .122 IA188ES PQFP .125 IA188ES TQFP .128 Physical Dimensions .131
PQFP .131 TQFP .133
Ordering Information .134
IA186ES-PQF100I .134 IA186ES-PTQ100I .134 IA188ES-PQF100I .134 IA188ES-PTQ100I .134
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IA186ES/IA188ES
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FEATURES
Pin-for-Pin compatible with AMD® Am186ES/188ES devices features retained, including: allowing same crystal/system clock frequency 8086/8088 instruction with additional instruction extensions Programmable interrupt controller channels Three 16-bit timers Programmable chip select logic wait-state generator Dedicated watch timer independent asynchronous serial ports (UARTs) capability Hardware flow control 9-bit data capability Pulse Width Demodulator feature programmable pins (PIO) Pseudo-static/dynamic controller Fully static CMOS design operation industrial operating conditions power supply Available packages: 100-pin Thin Quad Flat Pack (TQFP) 100-pin Plastic Quad Flat Pack (PQFP)
IA186ES/188ES form, fit, function replacement original Advanced Micro Devices® Am186ES/188ES family microcontrollers. InnovASIC produces replacement using MILESTM, Managed Lifetime Extension System, cloning technology. This technology produces replacement more complex than "emulation" while ensuring they compatible with original MILEScaptures design clone produced even silicon technology advances. MILESalso verifies clone against original that even "undocumented features" duplicated. This Data Sheet contains preliminary information IA186ES/188ES. complete data sheet which documents necessary engineering information about IA186ES/188ES including functional descriptions, electrical characteristics, applicable timing will available when device nears completion.
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IA186ES/IA188ES
8/16-BIT MICROCONTROLLERS
Description
IA186ES/188ES family microcontrollers replaces obsolete AMD® Am186ES/188ES devices, allowing customers retain existing board designs, software compilers/assemblers, emulation tools, thereby avoiding expensive redesign efforts. IA186ES/188ES microcontrollers upgrade 80C186/188 microcontroller designs, with integrated peripherals provide increased functionality reduce system costs. InnovASIC devices designed satisfy requirements embedded products designed telecommunications, office automation storage, industrial controls. block diagram IA186ES/188ES microcontroller depicted Figure
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uzi_n s6/lock_n/clkdiv2_n hold
hlda srdy den_n/ds_n ardy dt/r_n
s2_n s0_n
a[19:0] ad[15:0] bhe_n/aden_n wr_n wlb_n whb_n rd_n
Clock Power Management Interface Control
clkouta
clkoutb
drq0/int5
Direct Memory Access
res_n drq1/int6
Peripheral Control Registers
Interrupt Controller
Pulse Width Demodulator (PWD)
int4 int3/inta1_n int2/inta0_n int1/select_n int0
Timers
lcs_n/once0_n mcs3_n/rfsh_n ucs_n/once1_n pcs5_n/a1 pcs6_n/a2 mcs2_n mcs0_n pcs3_n pcs0_n
tmrin0 tmrout0 tmrin1 tmrout1
Chip Selects Control
txd0
Asynchronous Serial Port
rxd0 cts0_n/enrx0_n rts0_n/rtr0_n
pio[31:0]
Programmable
Asynchronous Serial Port
txd1 rxd1 cts1_n/enrx1_n rts1_n/rtr1_n
Instruction Decode Execution
Figure IA186EM Block Diagram Note: descriptions pins that share other functions with pins. pwd, int5, int6, rts1_n/rtr1_n, cts1_n/enrx1_n multiplexed with int2_n/inta0_n, drq0, drq0, pcs3_n, pcs2_n respectively.
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IA186ES/188ES microcontroller consists following functional blocks: Interface Control Peripheral Control Registers Chip Selects Control Programmable Clock Power Management Direct Memory Access (DMA) Interrupt Controller Timers Asynchronous Serial Ports
brief description each block follows:
Interface Control
Interface Control (BIC) manages accesses external memory external peripherals. These peripherals mapped either memory space space. supports both multiplexed non-multiplexed operations. Multiplexed address data provided [15:0] bus, while non-multiplexed address provided [19:0] bus. provides address information entire cycle (t1-t4), while provides address information only during first (t1) phase cycle. more details regarding cycles, waveforms this datasheet. provide capability dynamically alter size data bus. programming auxiliary control register (AUXCON), user easily support external peripherals memory devices both widths without specialized micro-code managing data accesses. AUXCON register contains programmable bits this purpose: LSIZ, MSIZ, IOSIZ. details regarding operation these bits, individual register descriptions under Peripheral Control Registers section this datasheet. IA186ESmicrocontroller provides signals support this functionality: write high byte (whb_n) write byte (wlb_n). Obviously, IA188ES microcontroller requires only single write byte (wb_n) signal support 8-bit data bus. also provides support Pseudo-Static (PSRAM) devices. PSRAM supported lower chip select (lcs_n) area only. order support PSRAM Chip Selects Control (CSC) must appropriately programmed. details regarding this operation Chips Selects Control Section this datasheet.
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Peripheral Control Registers
on-chip peripherals IA186ES/188ES microcontroller controlled from 256-byte block internal registers. Although these registers actually located peripherals they control, they addressed within single 256-byte block spaced therefore treated functional unit purposes this document. these registers depicted table write operations performed IA188ES should 8-bit writes, which will still result 16-bit data transfers Peripheral Control Block (PCB) register even named register 8-bit register. read performed registers should word reads. Code written with these points mind will correctly both IA186ES IA188ES. However unpredictable behavior both IA186ES IA188ES processors unaligned read write accesses performed.
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Register Name Peripheral Control Block Registers
Relocation Register Reset Configuration Register Processor Release Level Register Auxiliary Configuration Register System Configuration Register Watchdog Timer Control Register Clock Prescaler Register Memory Partition Register
Offset
Register Name Timer Registers
Timer Mode Control Register Timer Count Compare Register Timer Count Register Timer Mode Control Register Timer Count Compare Register Timer Count Compare Register Timer Count Register Timer Mode Control Register Timer Count Compare Register Timer Count Compare Register Timer Count Register
Offset
Registers
DMA1 Control Register DMA1 Transfer Count Register DMA1 Destination Address High Register DMA1 Destination Address Register DMA1 Source Address High Register DMA1 Source Address Register DMA0 Control Register DMA0 Transfer Count Register DMA0 Destination Address High Register DMA0 Destination Address Register DMA0 Source Address High Register DMA0 Source Address Register
Interrupt Registers
Serial Port Interrupt Control Register Serial Port Interrupt Control Register INT4 Interrupt Control Register INT3 Interrupt Control Register INT2 Interrupt Control Register INT1 Interrupt Control Register INT0 Interrupt Control Register DMA1/INT6 Interrupt Control Register DMA0/INT5 Interrupt Control Register Timer Interrupt Control Register Interrupt Status Register Interrupt Request Register Interrupt In-Service Register Interrupt Priority Mask Register Interrupt Mask Register Interrupt Poll Status Register Interrupt Poll Register End-of-Interrupt (EOI) Register Interrupt Vector Register
Chip-Select Registers
pcs_n mcs_n Auxiliary Register Mid-Range Memory Chip-Select Register Peripheral Chip-Select Register Low-Memory Chip-Select Register Upper-Memory Chip-Select Register
Serial Port Registers
Serial Port Baud Rate Divisor Register Serial Port Receive Register Serial Port Transmit Register Serial Port Status Register Serial Port Control Register
Registers
Data Register Direction Register Mode Register Data Register Direction Register Mode Register
Serial Port Registers
Serial Port Baud Rate Divisor Register Serial Port Receive Register Serial Port Transmit Register Serial Port Status Register Serial Port Control Register
Table Peripheral Control Registers.
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RELREG (0feh) Peripheral Control Block RELocation REGister maps entire Peripheral Control Block Register Bank either memory space. addition, RELREG contains which places Interrupt Controller either Master Slave Mode. RELREG contains 20ffh reset.
S/Mn
IO/Mn
[19:8]
(bit Reserved. S/Mn (bit this places Interrupt Controller into slave mode. When zero, Interrupt Controller master mode. (bit Reserved. IO/Mn (bit 12)- this maps Peripheral Control Block Register Bank into space. When zero, Peripheral Control Block mapped into memory space. [19:8] (bits 11-0) Sets base address (upper bits) Peripheral Control Block Register Bank. [7:0} default zero. Note that when (IO/Mn) one, [19:16] ignored.
RESCON (0f6h) RESet CONfiguration Register latches user-defined information present specified pins rising edge reset. contents this register read only remain valid until next reset. RESCON contains user-defined information reset.
[15:0]
[15:0] (bits 15-0) rising edge reset, values specified pins [15:0] IA186ES [15:8], [7:0]} IA188ES) latched into this register.
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(0f4h) Processor Release Level Register contains code corresponding latest processor production release. Read-Only Register contains 1100h. [7:0]
[7:0] (bits 15-8) latest Processor Release Level. Value Processor Release Level (bits 7-0) Reserved.
AUXCON (0f2h) AUXillary CONfiguration Register configures flow control signals asynchronous serial ports. addition AUXCON controls data width bit) lower memory, middle memory, accesses. AUXCON contains 0000h reset.
ENRX1 RTS1 ENRX0 RTS0 LSIZ MSIZ IOSIZ
(bit 15-7) Reserved. ENRX1 (bit When one, cts1_n/enrx1_n functions cts1_n. When zero, cts1_n/enrx1_n functions enrx1_n. RTS1 (bit When one, rtr1_n/rts1_n functions rts1_n. When zero, rtr1_n/rts1_n functions rtr1_n. ENRX0 (bit When one, cts0_n/enrx0_n functions cts0_n. When zero, cts0_n/enrx0_n functions enrx0_n. RTS0 (bit When one, rtr0_n/rts0_n functions rts0_n. When zero, rtr0_n/rts0_n functions rtr0_n.
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LSIZ (bit IA186ES only) When one, 8-bit data access performed lower chip-select (lcs_n) space. When zero, 16-bit data access performed.
MSIZ (bit IA186ES only) When one, 8-bit data access performed middle chipselect (mcs_n) space peripheral chip-select space (psc_n, only pcs_n mapped memory). When zero, 16-bit data access performed. IOSIZ (bit IA186ES only) When one, 8-bit data access performed space. When zero, 16-bit data access performed.
SYSCON (0f0h) SYStem CONfiguration Register controls several miscellaneous system timing functions. SYSCON contains 0000h reset.
PSEN MCSBIT DSDEN
PSEN (bit When one, enables power-save mode causing internal operating clock divided value F2-F0. External interrupts interrupts from internal interrupts automatically clear PSEN. Software interrupts exception clear PSEN. Please that value PSEN restored upon execution IRET instruction. MCSBIT (bit When one, mcs0_n active over entire range, thus freeing msc2 mcs1_n used programmable I/O. When this zero, msc0_n behaves normally. DSDEN (bit When one, ds_n/den_n functions ds_n. When this zero, ds_n/den_n functions den_n. individual descriptions details data strobe (ds_n) mode versus data enable (den_n) mode. (bit When one, pulse width demodulator enabled. When this zero, pulse width demodulator disabled. (bit When one, clkoutb output follows input crystal (PLL) frequency. When this zero, clkoutb follows internal clock frequency after clock divider. (bit When one, clkoutb output driven low. When this zero, clkoutb driven output bit. (bit When one, clkouta output follows input crystal (PLL) frequency. When this zero, clkouta follows internal clock frequency after clock divider.
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(bit When one, clkouta output driven low. When this zero, clkouta driven output bit. (bits 7-3) Reserved. bits read back zeros. F2-F0 (bits 2-0) These bits control clock divider shown below. Note, PSEN must clock divider function. Divider Factor Divide (20) Divide (21) Divide (22) Divide (23) Divide (24) Divide (25) Divide (26) Divide (27)
WDTCON (0e6h) WatchDog Timer CONtrol Register provides control status watchdog timer (WDT). WDTCON contains c080h reset. WRST
RSTFLAG NMIFLAG TEST
COUNT
(bit When one, watchdog timer enabled. When zero, watchdog timer disabled. WRST (bit When one, internal reset generated when timeout count (COUNT) reached. When this zero, will generated once timeout count reached NMIFLAG zero. NMIFLAG one, internal reset generated when timeout count reached. RSTFLAG (bit When one, timeout event occurred. This cleared software external reset. NMIFLAG (bit When one, event occurred. This cleared software external reset. this when timeout occurs, internal reset generated regardless state WRST.
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TEST (bit This reserved chip test should always zero. (bits 10-8) Reserved.
COUNT (bits 7-0) Control timeout period follows: timeout exponent/frequency Where: timeout timeout period seconds. Frequency processor frequency hertz. Exponent based upon count shown below: Exponent
EDRAM (0e4h) Enable Dynamic Refresh Control Register provides control status refresh counter. EDRAM register contains 0000h reset. [8:0]
(bit When one, refresh counter enabled msc3_n configured rfsh_n. Clearing clears refresh counter disables refresh requests. refresh address unaffected clearing (bits 14-9) Reserved. These bits read back zero.
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[8:0] (bits 8-0) These bits hold current value refresh counter. These bits readonly.
CDRAM (0e2h) Count Dynamic Refresh Control Register determines period between refresh cycles. CDRAM register undefined reset. [8:0]
(bits 15-9) Reserved. These bits read back zero. [8:0] (bits 8-0) These bits hold clock count interval between refresh cycles. power-save mode, refresh counter value should adjusted account clock divider value SYSCON.
MDRAM (0e0h) Memory Partition Dynamic Refresh Control Register holds A19A13 address bits 20-bit base refresh address. MDRAM register contains 0000h reset. [6:0]
[6:0] (bits 15-9) Upper bits corresponding address bits a19-a13 20-Bit memory refresh address. These bits available a19-a0 bus. When using PSRAM mode, M6M0 must programmed 0000000b. Reserved [8:0] (bits 8-0) Reserved. These bits read back zero.
D1CON (0dah) CONtrol Registers. D0CON (0cah) Control Registers control operation channels. D0CON D1CON registers undefined reset, except that
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DM/IOn DDEC DINC SM/IOn SDEC SINC
TDRQ
Bn/W
SYN1SYN0
DM/IOn (bit Destination Address Space Select selects memory space destination address. When DM/IO destination address memory space, while when destination address space. DDEC (bit Destination Decrement automatically decrements destination address after each transfer when address decremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). DINC (bit Destination Increment, when automatically increments destination address after each transfer. address incremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). SM/IOn (bit Source Address Space Select selects memory space source address. When SM/IOn source address memory space, while when source address space. SDEC (bit Source Decrement, when automatically decrements destination address after each transfer. address decremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). SINC (bit Source Increment, when automatically increments destination address after each transfer. address incremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). (bit Terminal Count. decrements transfer count each transfer. When source destination synchronized transfers terminate when count reaches when source destination synchronized transfers terminate when count reaches Unsynchronized transfers always when count reaches irrespective setting this bit. (bit Interrupt. channel generates interrupt request completion transfer count when this However, interrupt generated, must also
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SYN1-SYN0 (bits 7-6) Synchronization Type bits select channel synchronization shown following table. value these bits ignored TDRQ (bit processor reset causes these bits 11b. SYN1 SYN0 Sync Type Unsynchronized Source Synchronized Destination Synchronized Reserved
(bit Relative Priority. Selects high priority this channel relative other channel during simultaneous transfers when TDRQ (bit Timer Synchronization. Enables requests from timer when disables requests from timer when (bit External Interrupt Enable Bit. external interrupt controller processes requests this respective channel does respond changes pin. However, when this functions pin. (bit Change Start Bit. This must allow modification during write. During write, when changed when writing control word. result reading this always (bit Start/Stop Channel. When start channel started. must this modified only during same register write. processor reset causes this Bn/W (bit Byte/Word Select. When word transfers selected, when byte transfers selected. (The IA188ES does support word transfers furthermore they supported chip selects programmed 8-bit transfers.)
D1TC (0d8h) Transfer Count Registers. D0TC (0c8h) Transfer Count registers maintained each channel. They decremented after each cycle. state control register influence this activity. But, unsynchronized transfers programmed control word set, activity ceases when transfer count register reaches D0TC D1TC registers undefined reset.
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TC15
[15:0] (bits 15-0) Transfer Count contains transfer count respective channel. value decremented after each transfer.
D1DSTH (0d6h) DeSTination Address High Register. D0DSTH (0c6h) 20-bit destination address consists these four bits combined with 16-bits respective Destination Address Register. transfer requires that complete 16-bit registers (high registers) used both source destination addresses each channel involved. These four registers must initialized. Each address incremented decremented independently each other after each transfer. addresses incremented decremented word transfers incremented decremented byte transfers. D0DSTH D1DSTH registers undefined reset. Reserved
DDA19-DDA16
Reserved [15:4] (bits 15-4) Reserved. [19:16] (bits 3-0) Destination Address High bits driven onto A19-A16 during write phase transfer.
DIDSTL (0d4h) DeSTination Address Register. D0DSTL (0c4h) sixteen bits these registers combined with four bits respective Destination Address High Register produce 20-bit destination address. D0DSTL D1DSTL registers undefined reset.
DDA15 DDA0
[15:0] (bits 15-0) Destination Address bits driven onto A19-A16 during write phase transfer.
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D1SRCH (0d2h) SouRCe Address High Register. D0SRCH (0c2h)
20-bit source address consists these four bits combined with 16-bits respective Source Address Register. transfer requires that complete 16-bit registers peripheral control block (high registers) used both source destination addresses each channel involved. Each channel requires that four address registers initialized. Each address incremented decremented independently each other after each transfer. addresses incremented decremented word transfers incremented decremented byte transfers. D0SRCH D1SRCHL registers undefined reset. Reserved
DSA1 -DSA16
Reserved [15:4] (bits 15-4) Reserved [19:16] (bits 3-0) Source Address High bits driven onto A19-A16 during read phase transfer.
D1SRCL (0d0h) SouRCe Address Register. D0SRCL (0c0h) sixteen bits these registers combined with four bits respective Source Address High register produce 20-bit source address. D0SRCL D1SRCL registers undefined reset.
DSA15-DSA0
[15:0] (bits 15-0) Source Address bits placed onto a15-a0 during read phase transfer.
MPCS (0a8h) Auxiliary Register. This register controls more than type chip select, making different from other chip select control registers. MPCS register contains information following, mcs3_n mcs0_n well pcs6_n pcs5_n pcs3_n pcs0_n.
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MPCS register also contains that configures pcs6_n pcs5_n pins either chip selects alternate sources address bits. Either address bits pcs6_n pcs5_n selected exclusion other. When programmed address bits, these outputs used provide latched address bits pcs6_n pcs5_n high active processor reset. access MPCS register causes pins activate, when pcs6_n pcs5_n configured address pins. pcs6_n pcs5_n pins require corresponding access PACS register activated. value MPCS register undefined reset.
M6-M0
R1-R0
Reserved (bit [6:0] (bits14-8) MCS_n Block Size These bits determine total block size MCS3_n MCS0_n chip selects. total block size divided equally among four chip selects. following table shows relationship between [6:0] size memory block. Total Block Size 128K 256K 512K Individual Select Size 128K 0000001b 0000010b 0000100b 0001000b 0010000b 0100000b 1000000b
(bit7) Selector This determines whether pcs6_n pcs5_n pins configured chip selects alternate outputs When this pcs6_n pcs5_n configured peripheral chip select pins, whereas when pcs6_n pcs5_n become address address respectively. (bit Memory/ Space Selector determines whether pcs_n pins active either during memory cycles. When pcs_n outputs active memory cycles, active cycles when Reserved (bits 5:3) (bit Ready Mode This influences only pcs6_n pcs5_n chip selects. external ready required, while external ready ignored. each case, values R1-R0 bits determine number wait states inserted.
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[1:0] (bits 1-0) Wait-State Value These bits influence only pcs6_n pcs5_n chip selects. value R1-R0 determines number wait states inserted into access depending whether PCS_n memory area. three wait states inserted 11b).
MMCS (0a6h) Midrange Memory Chip Select Register. Four chip-select pins, mcs3_n mcs0_n, provided within user-locatable memory block. memory block base address located anywhere within 1-Mbyte memory address space, excluding areas associated with ucs_n lcs_n chip selects (and, mapped memory, address range Peripheral Chip Selects, pcs6_n pcs5_n pcs3_n pcs0_n). pcs_n chip selects mapped space mcs_n address range overlap pcs_n address range registers program Midrange Chip Selects. Midrange Memory Chip Select (MMCS) register determines base address, ready condition wait states memory block that accessed through mcs_n pins. pcs_n mcs_n Auxiliary (MPCS) register configures block size. reset mcs3_n mcs0_n pins active. Accessing with write both MMCS MPCS registers activates these chip selects. mcs3_n mcs0_n outputs assert with multiplexed address (ad15 ao15 ad0) rather than earlier timing unlike ucs_n lcs_n chip selects. timing delayed half cycle later than that ucs_n lcs_n used address selection. value MMCS register undefined reset.
BA19 BA13
[15:9] (bits 15-9) Base Address. value BA19 BA13 determines Base Address memory block that addressed mcs_n chip select pins. These bits correspond bits 20-bit memory address. remaining bits base address always base address integer multiple size memory clock selected MPCS register. example, midrange block Kbytes, block could located 20000h 28000h 24000h. lcs_n chip select inactive, base address midrange chip selects 00000h, because lcs_n chip select defined 00000h unused. further limitation that base address must integer multiple block size means that 512K MMCS block size only used with lcs_n chip select inactive base address midrange chip selects 00000h.
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Reserved [8:3] (bits 8-3)
(bit Ready mode. This determines mcs_n chip selects ready mode. When external ready necessary, external ready ignored. each case number wait states inserted access determined value bits. [1:0] (bits 1-0) Wait-State Value. number wait states inserted access determined value bits. three wait states inserted 11b).
PACS (0a4h) PeripherAl Chip Select Register. Peripheral Chip Selects asserted over 256-byte range with same timing address bus. There chip selects, pcs6_n pcs5_n pcs3_n pcs0_n that utilized either user-locatable memory blocks. Excluding areas utilized ucs_n, lcs_n, mcs_n chip selects, memory block located anywhere within Mbyte address space. These chip selects also configured access Kbyte space. Programming Peripheral Chip Selects uses registers, Peripheral Chip Select (PACS) register pcs_n mcs_n Auxiliary (MPCS) register. PACS register establishes base address, configures ready mode, determines number wait states pcs3_n pcs0_n outputs. MPCS register configures pcs6_n pcs5_n pins either chip selects address pins When these pins configured chip selects, MPCS register determines whether they active during memory cycles determines ready state wait states these output pins. These pins active reset activated chip selects writing registers (PACS MPCS). configure activate them address pins necessary write both PACS MPCS registers. pcs6_n pcs5_n configured wait states while pcs3_n pcs0_n programmed wait states. value PACS register undefined reset.
BA19 BA11
[19:11] (bits 15-7) Base Address bits determine base address correspond bits 20-bit programmable base address peripheral chip select block. However PCS_n chip selects mapped space, these bits must 0000b, addresses only bits wide.
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Address Ranges PCSn Line PCS0n PCS1n PCS2n PCS3n Reserved PCS5n PCS6n Range Base Address Base Address Base Address Base Address Base Address 1280 Base Address 1536
High Base Address Base Address Base Address Base Address 1023 Base Address Base Address
Reserved [6:4] (bits 6-4) (bit Wait State Value. following table. (bit Ready Mode. When external ready required. When external ready ignored, each case number wait states determined following table. [1:0] (bits Wait-State Value. following table. should noted that pcs6_n pcs5_n pcs3_n pcs0_n pins multiplexed with programmable pins them function chip selects, mode direction settings these pins must normal operation. PCS3n PCS0n Wait-State Encoding Wait States
LMCS (0a2h) Memory Chip Select Register configures Memory Chip Select that been provided facilitate access interrupt vector table located 00000h bottom memory. lcs_n active reset. width data lcs_n space should configured AUXCON register before activating lcs_n chip select pin, write access LMCS register.
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value LMCS register undefined reset except which
R1-R0
Reserved [15] (bit [2:0] (bits Upper Boundary. These bits define upper boundary memory accessed lcs_n chip select. following table gives possible configurations block size (max 512Kbytes). LMCS Block Size Programming Values Memory Block Size 128K 256K 512K Reserved [11:8] (bits 11-8) (bit Disable Address When address driven onto address (ad15 ad0) during address phase cycle, while address disabled, providing some measure power saving. This reset. BHE_n/ADEN_n held during rising edge res_n, then address always driven, independent setting (bit PSRAM Mode Enable PSRAM support lcs_n chip select memory space enabled when EDRAM, MDRAM, CDRAM refresh control unit registers must configured auto refresh before PSRAM support enabled. Setting enable (EN) enable register (EDRAM, offset e4h) configures mcs3_n/rfsh_n rfsh_n. Reserved (bits 5-3) (bit Ready Mode. When this external ready required, while when external ready ignored. either case however, value bits determine number wait states inserted. [1:0] (bits R1-R0) Wait-State Value. number wait states inserted into access memory area determined value these bits. This number ranges from 11b)
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Ending Address 0FFFFh 1FFFFh 3FFFFh 7FFFFh
000b 001b 011b 111b
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UMCS (0a0h) Upper Memory Chip Select Register configures Upper Memory Chip Select pin, which used memory. reset first fetch takes place memory location FFFF0h thus this area memory usually used instruction memory. With this mind ucs_n defaults active state reset with memory range Kbytes (F0000h FFFFFh), external ready required, three wait states automatically inserted. upper memory range always ends FFFFFh, whereas lower this upper memory range programmable. value UMCS register F03Bh reset.
R1-R0
Reserved [15] (bit [2:0] (bits 14-12) Lower Boundary. These bits determine bottom memory accessed ucs_n chip selects.
UMCS Block Size Programming Values Memory Block Size 128K 256K 512K Starting Address F0000h E0000h C0000h 80000h 111b 110b 100b 000b Comments Default
Reserved (bits (bit Disable Address. When address driven onto address (ad15 ad0) during address phase cycle when ucs_n asserted, while address disabled, address driven address when ucs_n asserted, providing some measure power saving. This reset. bhe_n/aden_n held during rising edge res_n, then address always driven independent setting Reserved (bit Reserved (bit
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(bit Ready Mode When this external ready required, while when external ready ignored. either case however, value bits determine number wait states inserted. [1:0] (bits 1-0) Wait-State Value. number wait states inserted into access lcs_n memory area determined value these bits. This number ranges from 11b).
SP0BAUD (088h) Serial Port BAUD Rate Divisor Registers. SP1BAUD (018h) There baud rate divisor registers, each port, allowing ports operate different baud rates. value these registers determines number internal processor cycles phase (half-period) serial clock. contents these registers must adjusted reflect processor clock frequency powersave mode effect. baud rate divisor calculated from: BAUDDIV (Processor Frequency baud rate)) setting BAUDDIV 0001h, maximum baud rate 1/16 internal processor frequency clock set. This provides baud rate 2500Kb 40MHz. BAUDDIV zero, transmission reception data does occur. baud rate tolerance +3.0% -2.5% with respect actual serial port baud rate, target baud rate.
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Baud Rate 1050 1200 1800 2400 4800 7200 9600 19200 28800 38400 56000 57600 76800 115200 128000 153600 4166 2083 1190 1041
Divisor Based Clock Rate 5208 2604 1488 1302 6875 3437 1964 1718 1145 8333 4166 2380 2083 1388 1041
Special 187500
value SP0BAUD SP1BAUD registers reset 0000h.
BAUDDIV BAUDDIV [15:0] (bits 15-0) Baud Rate Divisor. Defines divisor internal processor clock. Copyright 2003 ENG21 030117-00 www.innovasic.com innovASIC Customer Support: Obsolescence Page 1.888.824.4184
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SP0RD (086h) Serial Port Receive Registers. SP1RD (016h) Data received over serial ports stored these registers until read. data received initially receive shift register software access) permitting data received while previous data being read. status these registers indicated (Receive Data Ready) serial port status registers. When indicates that there valid data receive register. automatically cleared when receive register read. handshaking employed, control signals cts_n/enrx_n de-asserted while receive register valid unread data. cts_n/enrx_n signal reasserted after data receive register read. value SP0RD SP1RD registers undefined reset. Reserved RDATA
Reserved (bits 15-8) Reserved. RDATA [7:0] (bits 7-0) Holds valid data while respective status register set. SP0TD (084h) Serial Port Transmit Registers. SP1TD (014h) Data written these registers, software, with values transmitted serial port. Double buffering these transmitters allows transmission data from transmit shift registers software access), while next data written into transmit registers. TEMT THRE bits respective Serial Port Status registers indicate status these pairs registers. Invoking handshaking requires that rts_n/rtr_n inputs asserted before transmitters send data which remain held transmit shift registers without affecting transmit pin. value SPTD registers undefined reset. Reserved
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Reserved (bits 15-8) Reserved. TDATA [7:0] (bits 7-0) Holds data transmitted.
SP0STS (082h) Serial Port STatuS Register. SP1STS (012h) These registers store information concerning current status respective ports. status bits described below. value SP0STS SP1STS registers undefined reset. Reserved
BRK1 BRK0 THRE TEMT
Reserved (bits 15-11) Reserved. BRK1 (bit Long Break Detected. long break signal level period greater that times. (start number data bits parity bits stop bit). Should data reception progress when break starts, reception current word will completed then timing break with begin. This will generate framing error, stop will detected break. Detection break with time period only guaranteed break commences outside frame. NOTE: This should reset software. BRK0 (bit Short Break Detected. short break period greater than times. (start number data bits parity bits stop bit). Should data reception progress when break starts, reception current word will completed then timing break with begin. This will generate framing error, stop will detected break. Detection break with time period only guaranteed break commences outside frame. NOTE: This should reset software. (bit Received This ninth data received modes (See definition Serial Port Control Register). NOTE: This should reset software. (bit Receive Data Ready. When this indicates that respective SPRD register contains valid data. This read only only reset reading corresponding Receive register.
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THRE (bit Transmit Holding Register Empty. When this indicates that corresponding transmit holding register ready accept data. This read only bit. (bit Framing Error Detected. When receiver samples line when stop expected (line high) framing error generated setting this bit. NOTE: This should reset software. (bit Overrun Error Detected. When data overwrites valid data receive register (because hasn't been read) overrun error detected setting this bit. NOTE: This should reset software. (bit Parity Error Detected. When parity error detected either mode this set. NOTE: This should reset software. TEMT (bit Transmitter Empty. When both transmit shift register transmit register empty, this indicating software that safe disable transmitter. This read only.
(bit Handshake Signal This inverted value cts_n read only. (bit Reserved
SP0CT (080h) Serial Port ConTrol Registers. SP1CT (010h) These registers control both transmit receive parts respective serial ports. value SP0CT &SP1CT registers 0000h reset. MODE
RSIE TXIE RXIE TMODE RMODE
[15:13] (bits 15-13) Control Field. These bits respective ports with transfers following table.
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Control Bits Bits 000b 001b 010b 011b 100b 101b 110b 111b Receive DMA0 DMA1 Reserved DMA0 DMA1
Transmit DMA1 DMA0 Reserved DMA0 DMA1
transfers both serial ports destination-synchronized operations. When transmit holding register empty, transfer requested, corresponding with assertion THRE status register non-DMA mode. However when configured transfers, respective transmit interrupt disabled without regard TXIE bit. transfers from both serial ports source-synchronized operations. When receive holding register contains valid data, transfer requested, corresponding with assertion status register non-DMA mode. However when configured receives, respective receive interrupt disabled without regard RXIE bit, although RSIE still permit receive status interrupts depending setting. transfers preclude hardware handshaking. either both serial ports configured transfers request internally generated corresponding external signals, drq0 and/or drq1 play role. RSIE (bit Receive Status Interrupt Enable. When exception occurs during data reception interrupt request generated enabled this (RSIE Interrupt requests made error conditions listed (BRK0, BRK1, OER, PER, FER) serial port status register. (bit Send Break. When this driven overriding data that course being shifted transmit shift register. definitions long short break Serial Port Status register definition. (bit Transmit This ninth data transmitted when modes This cleared each transmitted word buffered. transmit data with this high following procedure recommended. TEMT serial port status register must high. writing serial port control register. Finally write transmit character serial port transmit register.
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(bit Flow Control Enable. This controls hardware handshake (flow control) enabling when vice versa. type flow control depends value ENRX0/ENRX1 RTS0/RTS1 bits AUXCON register. Serial port special case that this associated pins used flow control overriding Peripheral Chip Select signals. This reset. TXIE (bit Transmitter Ready Interrupt Enable. This enables generation interrupt requests whenever transmit holding register empty (THRE respective port does generate interrupts when this Interrupts continue generated long THRE TXIE RXIE (bit Receive Data Ready Interrupt Enable. This enables generation interrupt requests whenever receive register contains valid data (RDR respective port does generate interrupts when this Interrupts continue generated long RXIE TMODE (bit Transmit Mode. transmit section serial port enabled when this Conversely transmit section serial port disabled when this RMODE (bit Receive Mode. receive section serial port enabled when this Conversely receive section serial port disabled when this (bit Even Parity. When this even parity protocol established, conversely parity established when this This only valid when parity enabled (PE). (bit Parity Enable. Parity enabled when this disabled when this MODE [2:0] (bit 2-0) Mode Operation. These three bits establish mode operation respective serial port. following table shows valid modes their functions. Serial Port MODE Settings MODE
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Description Data Mode Data Mode Data Mode Data Mode Data Mode Data Mode Data Mode Data Mode
Data Bits
Parity Bits
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Note: these were originally reserved modes that have been implemented provide stop bits. Mode requires that ninth data state otherwise character will ignored receiver. transmit section, however operates were mode This designed facilitate multi drop communication over common serial data link. this purpose port question initially programmed mode each data received with ninth (bit compared software with unique identifier this port. identifier comparison does find match then port left mode case that comparison finds identifier match port should reprogrammed mode that ninth allowed Handshaking should only employed such multidrop system ports that exchanging data (mode prevent multiple ports from attempting drive handshake signals. Mode does support handshaking this reason should enabled. possible that more than ports configured mode same time then handshaking should implemented. Mode allows data bits parity enabled data bits parity enabled. parity used then ninth data transmit section writing serial port control register. ninth read receive port from serial port status register. Mode simply allows start bit, data bits, stop without parity, which available.
PDATA1 (07ah) DATA Registers. PDATA0 (074h), When configured output value corresponding data register driven onto pin. other configured input then value into corresponding data register. following table lists default states pins.
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Assignments Number 7(a) 8(a) 9(a) Associated Name tmrin1 tmrout1 pcs6/A2 pcs5/A1 dt/r_n den_n/ds_n srdy tmrout0 tmrin0 drq0/int5 drq1/int6 mcs0_n mcs1_n pcs0_n pcs1_n pcs2_n/cts1_n/enrx1_n pcs3_n/rts1_n/rtr1_n rts0_n/rtr0_n cts0_n/enrx0_n txd0 rxd0 mcs2_n mcs3_n/rfsh_n
Power-On Reset Status Input with pull-up Input with pull-down Input with pull-up Input with pull-up Normal operation(c) Normal operation(c) Normal operation(d) Normal operation(c) Normal operation(c) Normal operation(c) Normal operation(c) Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up
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Assignments continued Number 26(a,
Associated Name txd1 rxd1 s6/lock_n/clkdiv2_n int4 int2/inta0_n/pwd
Power-On Reset Status Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up
Notes: Emulators these pins. (s2_n-s0_n, res_n, nmi, clkouta, bhe_n, ale, ad15 ad0, used emulators also.) bhe_n/aden_n held during power-on reset these pins revert normal operation. When used pin, input with available pull-up option. When used pin, input with available pull-down option. pins initialize either shown following table. value PDATA registers undefined reset. PDATA
PDATA
PDATA
PDATA PDATA [15:0] (bits 15-0) Data Bits. This register contains values bits that either driven received from corresponding pins depending configuration each either output input. values these bits correspond those direction registers Mode registers. PDATA [31:16] (bits 15-0) Data Bits. This register contains values bits that either driven received from, corresponding pins depending configuration each Copyright 2003 ENG21 030117-00 www.innovasic.com innovASIC Customer Support: Obsolescence Page 1.888.824.4184
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either output input. values these bits correspond those direction registers Mode registers pins operated open-drain outputs Maintain data constant appropriate data register. Writing value data into respective position Direction register, that output either disabled depending value data bit.
PDIR1 (078h) DIRection Registers. PDIR0 (072h) Each configured input output corresponding direction register. Mode Direction Settings Mode Direction function Normal operation input with pullup/pulldown output input without pullup/pulldown
PDIR0 value PDIR0 register FC0Fh reset.
PDIR
PDIR1 value PDIR1 register FFFFh reset.
PDIR
PDIR [15:0] (bits 15-0) Direction Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers.
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PDIR [31:16] (bits 15-0) Direction Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers.
PMODE1 (076h) MODE Registers. PMODE0 (070h) Each configured input output corresponding direction register. number PMODE corresponds number. table Mode Direction Settings PDIR description above. PMODE0 value PDIR0 register 0000h reset.
PMODE
PMODE1 value PDIR1 register 0000h reset.
PMODE
PMODE [15:0] (bits 15-0) Mode Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers.
PMODE [31:16] (bits 15-0) Mode Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers.
T1CON (05eh) Timer Timer Mode CONtrol Registers. T0CON (056h) This registers controls operation Timer Timer respectively.
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value T0CON T1CON registers 0000h reset.
INHn
CONT
(bit Enable Bit. timer enabled when timer count inhibited when Setting this writing T2CON register requires that INHn during same write. This write only, with INHn same write operation. INHn (bit Inhibit Bit. Gates setting enable (EN) bit. This must same write operation that sets enable (EN) bit. This always reads (bit Interrupt Bit. interrupt request generated when Count register reaches maximum, setting dual maxcount mode interrupt request generated when count register reaches value maxcount maxcount interrupt requests generated this interrupt request generated then enable cleared before said interrupt serviced, interrupt request will remain. (bit Register Bit. This when maxcount register used compare timer count value. when maxcount compare register used. Reserved (bits 11-6) (bit Maximum Count. When timer reaches maximum count this regardless interrupt enable bit. This also every time maxcount compare register reached, when dual maxcount mode. This used software polling monitor timer status rather than through interrupts desired. (bit Retrigger Bit. (bit Prescaler Bit. ignored external clocking enabled (EXT Timer prescales timer when Otherwise timer incremented every fourth CLKOUT cycle. (bit External Clock Bit. This determines whether external internal clock used. external clock used internal used. (bit Alternate Compare Bit. timer will count maxcount compare register reset count register then count maxcount compare register reset count register begin again maxcount compare register timer will count maxcount compare register reset count register begin again maxcount compare register Maxcount compare register used this case.
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CONT (bit Continuous Mode Bit. timer will continuously when this timer will stop after each count will cleared CONT CONT respective timer counts maxcount compare value resets, then commences counting maxcount compare value, resets ceases counting.
T2CON (066h) Timer Mode CONtrol Registers. This register controls operation Timer value T2CON register 0000h reset. CONT
INHn
(bit Enable Bit. timer enabled when timer count inhibited when Setting this writing T2CON register requires that during same write. This write only, with INHn same write operation. (bit Inhibit Bit. Gates setting enable (EN) bit. This must same write operation that sets enable (EN) bit. This always reads (bit Interrupt Bit. interrupt request generated when Count register reaches maximum, setting Reserved (bits 12-6) (bit Maximum Count. When timer reaches maximum count this regardless interrupt enable bit. This used software polling monitor timer status rather than through interrupts desired. Reserved (bits 4-1) CONT (bit Continuous Mode Bit. timer will continuously when this timer will stop after each count will cleared this
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T2COMPA (062h), Timer Maxcount COMpare Registers. T1COMPB (05ch) T1COMPA (05ah) T0COMPB (054h) T0COMPA (052h)
These registers contain maximum count value that compared respective count register. Timer Timer have these compare registers each. Timer and/or Timer is/are configured count compare firstly register then register TMROUT0 TMROUT1 signals used generate various duty-cycle wave forms. Timer only compare register, T2COMPA. these timer maxcount compare registers 0000h, respective timer will count from 0000h FFFFh before generating interrupt request. example timer configured this manner with 40MHz clock will interrupt every 6.5536 value these registers 0000h reset.
TC15
[15:0] (bits 15-0) Timer Compare Value. timer will count value respective register before resetting count value
T2CNT (060h) Timer CouNT Registers. T1CNT (058h) T0CNT (050h), These registers incremented every four internal clock cycles relevant timer enabled. Increment Timer Timer also controlled external signals tmrin0 tmrin1 respectively, prescaled Timer Comparisons made between count registers maxcount registers action taken dependant achieving maximum count. value these registers 0000h reset.
TC15
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[15:0] (bits 15-0) Timer Count Value. This register value current count related timer that incremented every fourth processor clock internal clocked mode. Alternatively register incremented each time Timer maxcount reached using Timer prescaler. Timer Timer externally clocked tmrin0 tmrin1 signals.
SP0CON (044h) Serial Port Interrupt CONtrol Registers. SP1CON (042h) (Master Mode) These registers control operation serial ports' interrupt source value these registers 001Fh reset.
Reserved Reserved (bits 15-5) Reserved (bit
(bit Mask. This bit, when enables serial port cause interrupt. When this prevents serial port from generating interrupt. [2:0] (bits 2-0) Priority. These bits define priority serial port interrupt relation other interrupt signals. interrupt priority lowest reset. values shown following table. Priority Level Priority (High) (Low) 000b 001b 010b 011b 100b 101b 110b 111b
I4CON (040h) INT4 CONtrol Register. (Master Mode) int4 signal only intended fully nested mode available cascade mode.
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value I4CON register 000Fh reset.
Reserved
LMSK
Reserved (bits 15-5) L(bit Level-Triggered Mode. int4 interrupt edge level triggered depending value bit. int4 active high level sensitive interrupt int4 rising edge triggered interrupt. interrupt int4 must remain active (high) until serviced. (bit Mask. int4 signal cause interrupt int4 signal cannot cause interrupt [2:0] (bit 2-0) Priority. These bits define priority serial port interrupt relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
I3CON (03eh) INT2/INT3 CONtrol Register. I2CON (03ch), (Master Mode) INT2 INT3 designated interrupt type respectively. int2 int3 pins configured interrupt acknowledge pins inta0 inta1 respectively cascade mode. value these registers 000Fh reset.
Reserved
LMSK
Reserved (bits 15-5) L(bit Level-Triggered Mode. int2 int3 interrupt edge level triggered depending value this bit. int2 int3 active high level-sensitive interrupt int2 int3 rising edge triggered interrupt. interrupt int2 int3 must remain active (high) until acknowledged. (bit Mask. int2 int3 signal cause interrupt int2 int3 signal cannot cause interrupt Interrupt Mask Register duplicate this bit.
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[2:0] (bit 2-0) Priority. These bits define priority serial port interrupt int2 int3 relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
I1CON (03ah) INT0/INT1 CONtrol Register. I0CON (038h), (Master Mode) IINT0 INT1 designated interrupt type respectively. int2 int3 pins configured interrupt acknowledge pins inta0 inta1 respectively, interrupt acknowledge signals int0 int1 cascade mode. value these registers 000Fh reset.
Reserved Reserved (bits 15-7)
SFNM LMSK
SPNM (bit Special Fully Nested Mode. This enables fully nested mode int0 int1 when (bit Cascade Mode. This enables cascade mode int0 int1 when L(bit Level-Triggered Mode. int0 int1 interrupt edge level triggered depending value bit. int0 int1 active high level-sensitive interrupt int0 int1 rising edge triggered interrupt. interrupt int0 int1 must remain active (high) until acknowledged. (bit Mask. int0 int1 signal cause interrupt int0 int1 signal cannot cause interrupt Interrupt Mask Register duplicate this bit. [2:0] (bit 2-0) Priority. These bits define priority serial port interrupt int0 int1 relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
TCUCON (032h) Timer Control Unit Interrupt CONtrol Register. (Master Mode) three timers, Timer2, Timer1, Timer0, have their interrupts assigned types 08h, 12h, configured this register.
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value these registers 000Fh reset.
Reserved
Reserved (bits 15-4) (bit Mask. interrupt sources cause interrupt interrupt sources cannot cause interrupt Interrupt Mask Register duplicate this bit. [2:0] (bit 2-0) Priority. These bits define priority serial port interrupts relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level). T2INTCON (03ah) Timer INTerrupt CONtrol Register. T1INTCON (038h) T0INTCON (032h) (Slave Mode) three timers, Timer2, Timer1, Timer0, each have interrupt control register, whereas master mode three masked prioritized register (TCUCON). value these registers 000Fh reset.
Reserved
Reserved (bits 15-4) (bit Mask. interrupt sources cause interrupt interrupt sources cannot cause interrupt Interrupt Mask Register duplicate this bit. [2:0] (bit 2-0) Priority. These bits define priority serial port interrupts relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
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DMA1CON/INT6CON (036h) INTerrupt CONtrol Register. DMA0CON/INT5CON (034h) (Master Mode)
DMA0 DMA1 interrupts have interrupt type respectively. These pins configured external interrupts requests respective Control register. value these registers 000Fh reset.
Reserved
Reserved (bits 15-4) (bit Mask. interrupt sources cause interrupt interrupt sources cannot cause interrupt Interrupt Mask Register duplicate this bit. [2:0] (bits 2-0) Priority. These bits define priority serial port interrupts relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
DMA1CON/INT6 (036h) INTerrupt CONtrol Register. DMA0CON/INT5 (034h) (Slave Mode) control registers maintain their original functions addressing that they possessed Master Mode. These pins configured external interrupts requests respective Control register. value these registers 000Fh reset.
Reserved Reserved (bits 15-4)
(bit Mask. interrupt sources cause interrupt interrupt sources cannot cause interrupt Interrupt Mask Register duplicate this bit.
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[2:0] (bits 2-0) Priority. These bits define priority serial port interrupts relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
INTSTS (030h) INTerrupt STatuS Register. (Master Mode) Interrupt status register contains interrupt request status each three timers, Timer2, Timer1, Timer0. DHLT TMR2 TMR0
Reserved
DHLT (bit Halt. activity halted when this automatically when non-maskable interrupt occurs cleared when IRET instruction executed. Interrupt handlers other time critical software modify this directly disable transfers. However, DHLT should modified software timer interrupts enabled function this register interrupt request register timers would compromised. Reserved (bits 14-3) [2:0] (bit 2-0) Timer Interrupt Request. pending interrupt request indicated respective timer, when these bits (N.B. REQST register logical these timer interrupt requests) (Slave Mode) When nonmaskable interrupts occur interrupt status register controls operation interrupt request status each three timers, Timer2, Timer1, Timer0. DHLT TMR2 TMR0
Reserved
DHLT (bit Halt. activity halted when this automatically when non-maskable interrupt occurs cleared when IRET instruction executed. Interrupt handlers other time critical software modify this directly disable transfers. However, DHLT should modified software timer interrupts enabled function this register interrupt request register timers would compromised. Reserved (bits 14-3)
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[2:0] (bit 2-0) Timer Interrupt Request. pending interrupt request indicated respective timer, when these bits (N.B. REQST register logical these timer interrupt requests)
REQST (02eh) Interrupt REQueST Register. (Master Mode) This read only register, such read results status interrupt request bits presented interrupt controller. REQST register undefined reset
Reserved
D1/I6 D0/I5
Reserved (bits (bit Serial Port Interrupt Request. This serial port interrupt state when enabled logical serial port interrupt sources: THRE, RDR, BRK1, BRK0, FER, PER, OER. (bit Serial Port Interrupt Request. This serial port interrupt state when enabled logical serial port interrupt sources: THRE, RDR, BRK1, BRK0, FER, PER, OER. [4:0] (bits Interrupt Requests. When these bits indicates that relevant interrupt pending interrupt. D1/I6 (bit Channel 1/Interrupt Request. When indicates that either channel int6 pending interrupt. D0/I5 (bit Channel 0/Interrupt Request. When indicates that either channel int5 pending interrupt. Reserved (bit (bit Timer Interrupt Request. This timer interrupt state logical timer interrupt requests. When indicates that timer control unit pending interrupt.
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(Slave Mode)
This read only register, such read results status interrupt request bits presented interrupt controller. status these bits available when this register read. This register read only. When internal interrupt request (D1/I6, D0/I5, TMR2, TMR1, TMR0) occurs, respective internally generated interrupt acknowledge resets these bits. REQST register contains 0000h reset. TMR0
Reserved Reserved (bits
TMR2 TMR1 D1/I6 D0/I5
TMR2 (bit Interrupt Requests. When indicates that timer pending interrupt. TMR1 (bit Interrupt Requests. When indicates that timer pending interrupt. D1/I6 (bit Channel 1/Interrupt Request. When indicates that either channel int6 pending interrupt. D0/I5 (bit Channel 0/Interrupt Request. When indicates that either channel int5 pending interrupt. Reserved (bit TMR0 (bit Timer Interrupt Request. When indicates that timer pending interrupt.
INSERV (02ch) IN-SERVice Register. (Master Mode) interrupt controller sets bits this register when interrupt taken. INSERV register contains 0000h reset
Reserved
D1/I6 D0/I5
Reserved (bits
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(bit Serial Port Interrupt Request. This serial port interrupt state. (bit Serial Port Interrupt Request. This serial port interrupt state. [4:0] (bits Interrupt Requests. When these bits indicates that relevant interrupt pending interrupt. D1/I6 (bit Channel 1/Interrupt Request. When indicates that either channel int6 pending interrupt. D0/I5 (bit Channel 0/Interrupt Request. When indicates that either channel int5 pending interrupt. Reserved (bit (bit Timer Interrupt Request. This timer interrupt state logical timer interrupt requests. When indicates that timer control unit pending interrupt. (Slave Mode) This read only register, such read results status interrupt request bits presented interrupt controller. status these bits available when this register read. This register read only. When internal interrupt request (D1/I6, D0/I5, TMR2, TMR1, TMR0) occurs, respective internally generated interrupt acknowledge resets these bits. REQST register contains 0000h reset. TMR0
Reserved
TMR2 TMR1 D1/I6 D0/I5
Reserved (bits TMR2 (bit Timer2 Interrupt Service. Timer being serviced when this
TMR1 (bit Timer1 Interrupt Service. Timer being serviced when this D1/I6 (bit Channel Interrupt Service. channel int6 being serviced when this
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D0/I5 (bit Channel Interrupt Service. channel int5 being serviced when this Reserved (bit TMR0 (bit Timer Interrupt Service. Timer being serviced when this
PRIMSK (02ah) PRIority MaSK Register. (Master Slave Mode) This register contains value that sets minimum priority level which interrupt generated maskable interrupt. PRIMSK register contains 0007h reset
PRM2 PRM0
Reserved (bits [2:0] (bits Priority Field Mask. This three-bit field sets minimum priority necessary maskable interrupt generate interrupt. maskable interrupt, with numerically higher value than that contained these three bits, masked. Priority Level Priority (High) (Low)
unmasked interrupt generate interrupt priority level other hand priority level only unmasked interrupts with priority permitted generate interrupts.
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IMASK (028h) Interrupt MASK Register. (Master Mode)
interrupt mask register read/write. Setting this register effectively same setting corresponding interrupt control register. Setting masks interrupt. interrupt request enabled when corresponding IMASK register contains 07fdh reset
Reserved
D1/I6 D0/I5
Reserved (bits (bit Serial Port Interrupt Mask. Setting this indication that serial port interrupt masked. (bit Serial Port Interrupt Mask. Setting this indication that serial port interrupt masked. [4:0] (bits Interrupt Mask. When these bits indication that relevant interrupt masked. D1/I6 (bit Channel 1/Interrupt Mask. Setting this indication that either channel int6 interrupt masked. D0/I5 (bit Channel 0/Interrupt Mask. When indicates that either channel int5 interrupt masked. Reserved (bit (bit Timer Interrupt Mask. When indicates that timer control unit interrupt masked. (Slave Mode) interrupt mask register read/write. Setting this register effectively same setting corresponding interrupt control register. Setting masks interrupt request. interrupt request enabled when corresponding IMASK register contains 003dh reset. TMR0
Reserved
TMR2 TMR1 D1/I6 D0/I5
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Reserved (bits
TMR2 (bit Timer2 Interrupt Mask. This provides indication state mask Timer Interrupt Control register. When indicates that interrupt request masked. TMR1 (bit Timer1 Interrupt Mask. This provides indication state mask Timer Interrupt Control register. When indicates that interrupt request masked. D1/I6 (bit Channel Interrupt Mask. This provides indication state mask channel int5 Interrupt Control register. When indicates that interrupt request masked. D0/I5 (bit Channel Interrupt Mask. This provides indication state mask channel int6 Interrupt Control register. When indicates that interrupt request masked. TMR0 (bit Timer Interrupt Mask. This provides indication state mask Timer Interrupt Control register. When indicates that interrupt request masked.
POLLST (026h) POLL STatus Register. (Master Mode) This register reflects current state Poll register read without affecting contents. However when Poll Register read, causes current interrupt acknowledged replaced next interrupt. poll status register read only. IREQ
Reserved
IREQ (bit Interrupt Request. This when interrupt pending during this state, bits contain valid data. Reserved (bits 14-6) [5:0] (bit 5-0) Poll Status. These bits show interrupt type highest priority pending interrupt.
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POLL (024h) POLL Register. (Master Mode) When Poll Register read, causes current interrupt acknowledged replaced next interrupt. poll status register reflects current state Poll register read without affecting contents. POLL register read only. IREQ
Reserved
IREQ (bit Interrupt Request. This when interrupt pending during this state, bits contain valid data. Reserved (bits 14-6) [4:0] (bit 4-0) Poll Status. These bits show interrupt type highest priority pending interrupt.
(022h) End-Of-Interrupt Register. (Master Mode) Service flags In-Service register reset when write made register. interrupt service routine (ISR) should write reset bit, In-Service register, interrupt before executing IRET instruction than ends interrupt service routine. Specific reset preferred method resetting bits most secure. register write only. NSPEC
Reserved
NSPEQ (bit Non-Specific EOI. This non-specific when indicates specific EOI. Reserved (bits 14-5) [4:0] (bit 4-0) Source Interrupt Type. These bits show interrupt type highest priority pending interrupt. Copyright 2003 ENG21 030117-00 www.innovasic.com innovASIC Customer Support: Obsolescence Page 1.888.824.4184
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(022h) Specific End-Of-Interrupt Register. (Slave Mode)
Service flag specific priority, In-Service register, reset when write made register. three-bit user supplied priority-level value that points in-service that reset. Writing this value this register resets specific bit. Specific reset preferred method resetting bits most secure. register write only undefined reset.
Reserved (bits 15-3) Write [2:0] (bit 2-0) Interrupt Type. priority (interrupt service) reset encoded these three bits. Writing these bits caused issuance interrupt type. Table Interrupt Types.
INTVEC (020h) -INTerrupt VECtor Register. (Slave Mode) shifts left bits (multiplies 8-bit interrupt type, generated interrupt controller, produce offset into interrupt vector table. INTVEC register undefined reset.
Reserved (bits 15-8) Read [4:0] (bits 7-3) Interrupt Type. These five bits contain most significant bits interrupt types used internal interrupt type. least significant bits interrupt type supplied interrupt controller, priority level interrupt request. Reserved (bits 2-0) Read
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Clock Power Management
phase-lock-loop (PLL) second programmable system clock output (CLKOUTB) included clock power management unit. internal clock same frequency crystal with duty cycle worse case, generated obviating need external clock. power-on reset (POR) resets PLL. Recommended range values are: 15pF 22pF
Crystal
Am186/188ES
Figure Crystal Configuration
System Clocks.
required internal oscillator driven external clock source that should connected leaving unconnected. clock outputs clkouta clkoutb enabled disabled individually (System Configuration register bits 8)). These clock control bits allow clock output frequency other power-save frequency. Processor Internal Clock
Power-Save Divisor /128)
clkouta
Drive enable Time Delay 2.5nS Drive enable Figure Organization Clock
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Power-Save Mode
operation peripheral operate slower clock frequency when power save mode reducing power consumption thermal dissipation. Should interrupt occur, microcontroller returns normal operating frequency automatically internal clock's next rising edge clock dependant devices should reprogrammed changed frequency during power-save mode period.
Initialization Reset
res_n (Reset), highest priority interrupt, must held during power-up initialize microcontroller correctly. This operation makes device cease instruction execution local activity. microcontoller begins instruction execution physical address FFFF0h when res_n becomes inactive after internal processing interval with ucs_n asserted three wait states. Reset also sets certain registers predetermined values resets Watchdog timer.
Reset Configuration Register.
data address/data (ad15 Am186ES ao15 Am188ES) written into Reset Configuration register when reset low. This data system dependant held Reset Configuration register after Reset de-asserted. This configuration data placed address/data using weak external pull-up pull-down resistors applied external driver, processor does drive during reset. method supplying software with some initial data after reset; example, option jumper positions.
Chip-Selects
Chip-select generation programmable memories peripherals. Programming also available produce ready wait-state generation plus latched address bits memory cycles, chip-select lines active within their programmed areas, regardless whether they generated internal unit CPU. There chip-selects outputs memories further peripherals whether memory space. memory chip-selects able address three memory ranges, whereas peripheral chip-selects used address 256-byte blocks that offset from programmable base address. Writing chip-select register enables related logic even event that question another function, example case that programmed PIO.
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Chip-Select Timing
normal timing, ucs_n lcs_n outputs asserted with non-multiplexed address bus.
Ready Wait-State Programming
Each memory peripheral chip-select lines have ready signal programmed that ardy srdy signal. chip-select control registers (UMCS, LMCS, MMCS, PACS, MPCS) have single that selects external ready signal used (R2, (bits 1-0) these registers control number wait-states that inserted during each access memory peripheral location (from control registers pcs3_n pcs0_n utilize three bits, (bits provide wait-states addition original values wait states. case where external ready been selected required, internally programmed wait-states will always completed before external ready finish extend cycle. example, consider system which number wait-states inserted been three; external ready sampled processor during first wait cycle. access completed after seven cycles cycles plus wait-cycles) ready asserted; alternatively ready asserted during first wait cycle access prolonged until ready asserted more waitstates inserted followed ardy signal asynchronous ready with that active high accepts rising edge asynchronous clkouta. However, additional clock period necessary falling edge ardy synchronized clkouta.
Chip-Select Overlap
Overlapping chip-selects those configurations which more than chip-select asserted same physical address. example configured space with other chip select configured memory, address 00000h overlapping chip selects. recommended that multiple chip-select signals asserted same physical address, although inescapable certain systems. this case, then overlapping chip-selects must have same external ready configuration same number wait-states inserted into access cycles. Internal signals employed access peripheral control block (PCB) these signals serve chip selects that configured with wait-states external ready. programmed with addresses that overlap external chip-selects only these chip selects configured same manner. Care should exercised Disable Address (DA) LMCS UMCS registers when overlapping additional chip-select with either lcs_n ucs_n chip-selects. Setting prevents address from being driven onto accesses which respective chip-select active, including those accesses which multiple selects active. mcs_n pcs_n pins dual-purpose pins, either chip-selects inputs outputs, however their respective ready wait-state configurations their chip-select function will
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effect matter which function these pins actually programmed. This requires that even these pins configured enabled, writing MMCS MPCS registers mcs_n chip-selects PACS MPCS registers pcs_n chip-selects), ready wait-state settings these signals must agree with settings over-lapping chip-selects they been configured chip-selects. Even though pcs4_n available external ready wait-state logic must therefore follow rules overlapping chip-selects. pcs6_n pcs5_n other hand have ready wait-state logic that disabled when these pins configured address bits respectively. chip-select configuration rules followed processor hang with appearance waiting ready signal even system which ready (ardy srdy) always
Upper Memory Chip Select
ucs_n chip-select memory. reset micro controller begins fetching executing instructions memory location FFFF0h, upper memory usually utilized instruction memory. this ucs_n active reset memory range 64Kbytes (F0000h FFFFFh) default along with external ready required three wait-states automatically inserted. lower boundary ucs_n programmable provide ranges 64Kbytes 512Kbytes.
Memory Chip Select
lcs_n chip-select lower memory configured 8-bit 16-bit accesses AUXCON register. interrupt vector table bottom memory beginning 00000h, this usually utilized control data memory. Unlike ucs_n this inactive reset.
Midrange Memory Chip Selects
There four midrange chip-selects, mcs3_n-mcs0_n, which used user-located memory block. base address memory block located anywhere 1-Mbyte memory address space with some exceptions. memory spaces used ucs_n lcs_n chip-selects excluded, pcs6_n, pcs5_n, pcs3_n pcs0_n. pcs_n chip-selects mapped space then address range overlap address range. mcs0_n chip select programmed active over entire range leaving mcs3_n mcs1_n free pins. configured 8-bit 16-bit accesses AUXCON register. range width determined width non-UCS/non-LCS memory ranges. assertion outputs occurs with same timing multiplexed address bus.
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Peripheral Chip Selects
There peripheral chip-selects, pcs6_n, pcs5_n, pcs3_n pcs0_n, that used within user defined memory block. base address this user defined memory block located anywhere within 1-Mbyte memory address space except spaces associated with ucs_n, lcs_n, mcs_n chip selects, programmed 64Kbyte space. pcs4_n available. None pcs_n pins active reset. pcs6_n, pcs5_n programmed have waitstates, whereas pcs3_n pcs0_n programmed have these wait-states. configured 8-bit 16-bit accesses AUXCON register. range width determined width non-UCS/non-LCS memory range width space. assertion outputs occurs with same timing multiplexed address bus. Each operates over 256-byte address range.
Refresh Control
Refresh Control Unit (RCU) generates refresh cycles automatically with fixed wait-state value three PSRAM automatic refresh mode. generates memory read request after programmable period time interface unit. Enable register (EDRAM) enables refresh cycles, operating processor internal clock. processor power-save mode, must reconfigured clock rate. hlda asserted when refresh request initiated (indicating hold condition), processor disables hlda allow refresh cycle performed. external circuit master must deassert hold signal least clock period permit execution refresh cycle.
Interrupt Control
Interrupt requests originate from variety internal external sources, that arranged internal interrupt controller priority order presented processor. Eight external interrupt sources, seven maskable nonmaskable (NMI) connected processor, eight internal interrupt sources (three timers, channels, asynchronous serial ports, Watchdog Timer NMI) that brought external pins. Interrupts int6 int5 multiplexed with drq1 drq0 available respective enabled internally synchronized.
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seven external maskable interrupt request pins are, with exception int0, multifunction pins, function being that direct interrupt requests. int4 int0 level edge triggered whereas int6 int5 edge triggered. When configured cascade mode, int1 int0 interface with external interrupt controller 82C59A type. When int0 configured cascade mode, function int2 automatically switched inta0_n role similarly, int3 switched inta1_n role when int1 configured cascade mode. programming internal interrupt controller slave mode, external 82C59A compatible interrupt controller used system master, this case int6 int4 cannot used. When interrupt accepted, other interrupts disabled, re-enabled setting Interrupt Enable Flag (IF), Processor Status Flags register, during Interrupt Service Routine (ISR). Setting permits interrupts equal greater priority interrupt currently running ISR. Further interrupts from same source will blocked until corresponding In-Service register (INSERV) cleared. Special Fully Nested mode invoked int0 int1 SFNM INT0 INT1 Control register respectively, when this this mode interrupt generated these sources regardless in-service bit. following table shows priorities interrupts power-on reset.
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Interrupt Types
Interrupt Name Divide Error Exception Trace Interrupt Non-maskable Interrupt (NMI) Breakpoint Interrupt INT0 Detected Overflow Exception Array Bounds Exception Unused Opcode Exception Opcode Exception Timer Interrupt Timer Interrupt Timer Interrupt Reserved Interrupt/INT5 Interrupt/INT6 INT0 Interrupt INT1 Interrupt INT2 Interrupt INT3 Interrupt INT4 Interrupt Asynchronous Serial Port Interface Asynchronous Serial Port Interface Reserved
Interrupt Type
Vector Table Address
Type
Overall Priority
Related Instructions DIV, IDIV INT3 INT0 BOUND Undefined Opcodes Opcodes
Notes: user does changed priority levels then default priority level will used interrupt sources. Instruction execution generates interrupts. Performed same manner 8086 8088. opcode causes trap. Only generated three timers they share priority level with regard other sources. timers themselves have interrupt priority order among themselves 2C). These interrupt types programmable Slave mode. available slave mode.
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Timer Control
IA186ES IA188ES each have watchdog timer three programmable timers. Timer0 timer1 each have input output connected external pins that permit them count time events, produce variable duty-cycle waveforms non-repetitive waveforms. These same timers used measure high pulse widths Pulse Width Demodulator pin. Timer2 does have external connections confined internal functions such real-time coding, time-delay applications, prescaler timer0 timer1, synchronize transfers. Peripheral Control Block contains eleven 16-bit registers control programmable timers. present value timer located associated timer-count register, which read from written time regardless whether timer operation not. value timercount register incremented microcontroller every time timer event takes place. maximum value that each timer reach determined value stored associated maximum count register. Upon reaching this maximum count value; timer count register reset same clock cycle that this count attained, that timer count register does store this maximum value. Both timer0 timer1 have maximum count registers, primary secondary register, permitting each timer alternate between discrete maximum values. Timer0 timer1 have maximum count registers configured ways, primary only both primary secondary. only primary configured operate then reaching maximum count output will clock period. both primary secondary registers enabled then output reflects state whichever registers control time, generating required waveform that dependant values maximum count registers. timers operate quarter internal clock frequency they polled every fourth clock period. Alternatively external clock used, this case timer output take clock cycles respond input.
Watchdog Timer
Watchdog Timer (WDT) operates real fashion used prevent loss control event that software does respond expected manner. active after reset, maximum timeout count, programmed system reset mode. control register (WDTCON) written only once after reset. This accomplished writing 3333h then CCCCh followed configuration data WDTCON register. number other operations, including memory read writes, performed between these words provided they include access WDTCON register.
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Writing AAAAh then 5555h WDTCON register resets current count. This count cannot read. before number other operations, including memory read writes, performed between these words provided they include access WDTCON register. these sequences designed prevent executing code from impeding event from occurring. 40MHz system, maximum 1.67-second timeout period possible with WDT. programmed generate system reset when times-out. programmed generate NMI, NMIFLAG (bit WDTCON register will when occurs. This flag should tested interrupt service routine (ISR) establish whether interrupt generated external source. should clear this flag, set, writing 3333h CCCCh sequence followed configuration data which includes clearing NMIFLAG. system reset generated place second interrupt, NMIFLAG while second timeout occurs. RSTFLAG (bit WDTCON register reset generated, occurrence while programmed generate resets, because event occurred with NMIFLAG set. This permits system initialization code distinguish between reset hardware reset take suitable action. RSTFLAG cleared read write WDTCON register. During reset, external pins re-sampled, ensuring that clocking, reset configuration register, other features that user programmable during reset change when system reset occurs. other activities same those normal system reset.
Direct Memory Access (DMA)
Direct memory access (DMA) relieves involvement transfer data between memory peripherals over either both high-speed channels. Data transferred from memory I/O, memory, memory-to-memory, I/O-to-I/O. Furthermore channels connected asynchronous serial ports. IA186ES microcontroller supports transfer both bytes words, from, even addresses, does support word transfers memory that configured byte accesses. IA188ES does support word transfers all. Each data transfer will take cycles minimum clock cycles). There four sources requests each channel, channel request (drq1 drq0), Timer2, serial port, system software. channels programmed have different priorities facilitate resolution simultaneous requests interrupt transfer other channel.
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Operation
Peripheral Control Block contains registers each channel control specify operation channels. registers consist pair registers store 20-bit source address, pair registers store 20-bit destination address, 16-bit transfer count register, 16-bit control register. number transfers required designated Transfer Count register bytes words furthermore will automatically. channel function defined Control registers, which along with other registers changed time including during transfer implemented immediately.
Channel Control Registers
D1CON (0dah) D0CON (0cah) CONtrol Registers above. Briefly, these registers specify following: Whether data destination memory space. (Bit 15). Whether destination address incremented, decremented, unchanged after each transfer. (Bit 13). Whether data source memory space. (Bit 12). Whether source address incremented, decremented, unchanged after each transfer? (Bit 10). Whether transfers cease upon reaching designated count. (Bit Whether last transfer generates interrupt. (Bit Synchronization mode. (Bits relative priority channel with respect other. (Bit Acceptance requests from Timer2. (Bit Configuration pins INT. (Bit Byte Word transfers. (Bit
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Adder Control Logic
20-bit Adder/Subtractor Transfer Counter Destination Address Source Address Transfer Counter Destination Address Source Address
Timer Request drq1 Request Selection Logic
Control Logic
drq0 Interrupt Request
Channel Control Register Channel Control Register
Internal Address/Data
Figure Unit
Priority
transfers have higher priority than transfers with excerption word accesses memory locations between locked memory addresses. cannot access memory during transfer transfer cannot suspended interrupt request; continuous activity will thus cause interrupt latency suffer. However request halts activity, enabling respond promptly request.
Pulse Width Demodulation
should noted that there support analog digital conversion. This feature provides means measuring width pulse both high phases enabled (Bit System Configuration Register (SYSCON).
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TMRIN0, TMRIN1, INT2, INT4 internally configured support detection rising falling edges (int2/int0_n/pwd) enable either timer0 timer1 depending whether signal high respectively. tmrin0, tmrin1, int4 pins available pins this mode they used.
int2
int4 timer1 enabled
int2
Interrupts generated
timer0 enabled
Figure Typical Waveform int2/int0_n/pwd current count respective timer, timer1 INT2 timer0 INT4 should inspected Interrupt Service Routine (ISR) determine pulse width. timer count register should then reset readiness next pulse. maximum resolution timers determined timer count rate, which processor clock rate. avoid overhead servicing timer interrupt cases which pulse width short, INT2 INT4 request bits Interrupt Request register polled. other hand, cases which pulse width greater than maximum count timer, detection achieved monitoring Maximum Count (MC) respective timer enabling timer interrupt requests setting respective Timer Mode Control Register.
Asynchronous Serial Ports
There independent asynchronous serial ports that employ standard industry communication protocols their implementation full duplex, bi-directional data transfers. These ports sources destinations transfers independently each other. following features supported: Full-duplex data transfers 9-Bit data transfers Odd, even, parity stop bits. Break characters lengths Error detection provided Parity, Framing, Overrun errors Hardware handshaking achieved with following selectable control signals: Clear-to-send (cts_n) Enable receiver request (enrx_n)
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Ready send (rts_n) Ready receive (rtr_n) from ports Each port maskable interrupts 9-Bit multidrop protocol Each port independent baud rate generator Maximum baud rate 1/16 processor clock Transmit Receive lines double buffered
Programmable (PIO)
pins programmable signals. following tables list these pins with their name number, firstly numerical order, then name alphabetical order. Programming should only performed normal function required normal function disabled longer affect pin. programmed input output with without either weak pull-up pull-down, open-drain output. Following power reset pins have default status shown following tables.
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7(1) 8(1) 9(1) 26(1,2) 29(1,2)
Associated tmrin1 tmrout1 pcs6_n/a2 pcs5_n/a1 dt/r_n den_n/ds_n srdy tmrout0 tmrin0 drq0/int5 drq1/int6 mcs0_n mcs1_n pcs0_n pcs1_n pcs2_n/cts1_n/enrx1_n pcs3_n/rts1_n/rtr1_n rts0_n/rtr0_n cts0_n/enrx0_n txd0 rxd0 mcs2_n mcs3_n/rfsh_n uzi_n txd1 rxd1 s6/lock_n/clkdiv2 int4 int2/inta0_n/pwd
Power-On Reset Status Input with pullup Input with pulldown Input with pullup Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup
Associated cts0_n/enrx0_n den_n/ds_n drq0/int5 drq1/int6 dt/r_n int2/inta0_n/pwd int4 mcs0_n mcs1_n mcs2_n mcs3_n/rfsh_n pcs0_n pcs1_n pcs2_n/cts1_n/enrx1_n pcs3_n/rts1_n/rtr1_n pcs5_n/a1 pcs6_n/a2 rts0_n/rtr0_n rxd0 rxd1 s6/lock_n/clkdiv2 srdy timerin0 tmrin1 tmrout0 tmrout1 txd0 txd1 uzi_n
Power-On Reset Status Normal operation(3) Normal operation(3) Normal operation(3) Input with pullup Normal operation(3) Input with pullup Input with pullup Normal operation(3) Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Normal operation(4) Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup
NOTES: These notes apply both tables Emulators these pins also s2_n-s0_n, res_n, nmi, clkouta, bhe_n ale, ad15-ad0, a16-a0. bhe_n/aden_n (IA186ES) rfsh_n/aden_n (IA188ES) held during power-on reset then these pins will revert normal operation. Input with pullup when used PIO. Input with pulldown option available when used PIO. These default status setting changed desired. three most significant bits address (a19 a17) start with their normal function power reset, permitting processor begin fetching instructions from boot address FFFF0h. Furthermore, normal function default setting dt/r_n, den_n, srdy power reset. s6/clkdiv2_n uzi_n automatically return normal operation event that ad15-ad0 override enabled. ad15-ad0 override enabled bhe_n/aden_n IA186ES, rfsh2_n/aden_n IA188ES, held during power reset.
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IA186ES/IA188ES
8/16-BIT MICROCONTROLLERS
Descriptions
a19/pio9, a18/pio8, a17/pio7, Address (synchronous outputs with tristate)
These pins system's source non-multiplexed memory addresses occur half CLKOUTA cycle before multiplexed address/data (ad15-ad0 IA186ES ao15_ao8 ad7-ad0 AI188ES). address tristated during hold reset.
ad15 IA186ES Address/Data (level-sensitive synchronous inouts with tristate)
These pins system's source time-multiplexed memory addresses data. address function these pins disabled. (See bhe_n/aden_n description.) address function these pins enabled, address will present this during cycle data will present during same cycle. whb_n active then these pins tristated during cycle. address/data tristated during hold reset. These pins used load internal Reset Configuration register (RESCON, offset 0F6h) with configuration data during power-on reset.
ao15 IA188ES Address (level-sensitive synchronous outputs with tristate)
Address will contain valid high order address bits during cycle (t1, enabled Upper Lower Memory Chip Select registers (UMCS, offset 0a0h LMCS, offset 0a2h). These pins combined with ad7-ad0 complete multiplexed address tristated during hold reset condition.
Address/Data (level-sensitive synchronous inouts with tristate)
These pins system's source time-multiplexed order byte addresses memory 8-bit data. order address byte will present this during cycle 8-bit data will present during same cycle. address function these pins disabled. (See bhe_n/aden_n description.) wlb_n active, these pins tristated during cycle. address/data tristated during hold reset.
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IA186ES/IA188ES
8/16-BIT MICROCONTROLLERS
Address Latch Enable (synchronous output)
This signal indicates presence address address (ad15-ad0 IA186ES ao15-ao8 ad7-ad0 AI188ES), which guaranteed valid falling edge ale. ONCE mode this tristated during hold reset.
ardy Asynchronous Ready (level-sensitive asynchronous input)
This asynchronous signal provides indication microcontroller that addressed device memory space will complete data transfer. This active high signal asynchronous with respect clkouta falling edge ardy synchronized clkouta additional clock cycle added. ardy srdy must synchronized clkouta guarantee number inserted wait states. ardy should tied high maintain permanent assertion ready condition. other hand ardy signal used system should tied which passes control srdy signal.
bhe_n/aden_n IA186ES only High Enable (synchronous output with tristate) /Address Enable (input with internal pullup)
bhe_n bhe_n address inform system which bytes data (upper, lower, both) involved current memory access cycle shown following table. bhe_n Type Cycle Word Transfer High Byte Transfer (Bits 15-8) Byte Transfer (Bits 7-0) Refresh
bhe_n does require latching during hold reset tristated. asserted during remains through high byte write enable functions bhe_n performed whb_n wlb_n respectively. When using bus, DRAM refresh cycles indicated bhe_n/aden_n both being high. During refresh cycles busses have same address during address phase cycle necessitating determinant refresh cycle rather than
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IA186ES/IA188ES
8/16-BIT MICROCONTROLLERS
additional signal utilized PSRAM refreshes (see mcs3_n/rfsh_n description). aden_n There weak internal pullup bhe_n/aden_n obviating need external pullup reducing power consumption. Holding aden_n high letting float during power-on reset passes control address function (ad15-ad0) during cycles from aden_n LMCS UMCS registers. When address function selected memory address placed a19-a0 pins. Holding aden_n during power-on reset, both address data driven onto independently setting. This normally sampled rising edge res_n condition uzi_n default their normal functions.
clkouta Clock Output (synchronous output)
This internal clock output system. Bits System Configuration register control output this pin, which disabled, output frequency, output power save frequency (internal processor frequency after divisor). clkouta used full speed clock source power-save mode. A.C. timing specifications that clock related refer clkouta, which remains active during reset hold conditions.
clkoutb Clock Output (synchronous output)
This additional clock system with output delayed with respect clkouta. Bits System Configuration register control output this pin, which disabled, output frequency, output power save frequency (internal processor frequency after divisor). clkoutb used full speed clock source power-save mode, remains active during reset hold conditions.
cts0_n/enrx0_n/pio21 Clear-to-Send Enable-Receive-Request (both asynchronous inputs)
cts0_n This Clear-to-Send signal asynchronous serial port provided that (ENRX0) AUXCON register (FC) SP0CT register cts0_n controls transmission data from asynchronous serial port when asserted transmitter begins transmitting next frame data when asserted data transmitted held transmit register. This signal only checked start data frame transmission. enrx0_n This Enable-Receiver-Request asynchronous serial port case when (ENRX0) AUXCON register (FC) SP0CT register enables asynchronous serial port receiver.
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IA186ES/IA188ES
8/16-BIT MICROCONTROLLERS
den_n/ds_n/pio5 Data Enable /Data Strobe (both synchronous outputs with tristate)
den_n This signal asserted during I/O, memory, interrupt acknowledge processes deasserted when dt/r_n undergoes change state. tristated hold reset. After reset this defaults den_n. ds_n data strobe used under conditions which write cycle same timing read cycle. used with other control signals interface with 68K-type peripherals without further system interface logic. When asserted, addresses valid, during write data valid, while during read data applied bus.
drq0/int5/pio12 Request (synchronous level-sensitive input) Maskable Interrupt Request (asynchronous edge-triggered input)
drq0 external device, that ready channel carry transfer, indicates microcontroller this readiness this pin. latched must remain asserted until dealt with. int5 channel required, then used extra interrupt request sharing DMA0 interrupt type (0ah) control bits. latched must remain asserted until dealt with.
drq1/int6/pio13 Request (synchronous level-sensitive input) Maskable Interrupt Request (asynchronous edge-triggered input)
drq1 external device, that ready channel carry transfer, indicates microcontroller this readiness this pin. latched must remain asserted until dealt with. int6 channel required, then used extra interrupt request sharing DMA1 interrupt type (0bh) control bits. latched must remain asserted until dealt with.
dt/r_n/pio4 Data Transmit Receive (synchronous output with tristate)
microntroller transmits data when dt/r_n pulled high receives data when this pulled low. floats during reset hold condition.
Ground
seven pins, depending package, connect microcontroller system ground.
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IA186ES/IA188ES
8/16-BIT MICROCONTROLLERS hlda Hold Acknowledge (synchronous output)
This pulled high signal system that microntroller ceded control local bus, response high hold signal external master, after microcontroller completed current cycle. assertion hlda accompanied tristating den_n, rd_n, wr_n, s2-s0, ad15-ad0, a19-a0, bhe_n, whb_n, wlb_n, dr/r_n, followed driving high chip selects ucs_n, lcs_n, mcs3_n mcs0_n, pcs6_n pcs5_n, pcs3_n pcs0_n. external master releases control local deassertion hold that turn induces microcontroller deassert hlda. microcontroller take control necessary, execute refresh example), deasserting hlda without master first deasserting hold. This requires that external master must able deassert hold permit microcontroller access bus.
int0 Maskable Interrupt Request (asynchronous input)
int0 provides indication that interrupt request occurred, provided that int0 masked, program execution will continue location specified INT0 vector interrupt vector table. Although interrupt requests asynchronous, they synchronized internally edge level triggered. assertion interrupt request must maintained until handled, ensure that recognized.
int1/select_n Maskable Interrupt Request 1/Slave Select (both asynchronous inputs)
int1 int1 provides indication that interrupt request occurred, provided that int1 masked, program execution will continue location specified INT1 vector interrupt vector table. Although interrupt requests asynchronous, they synchronized internally edge level triggered. assertion interrupt request must maintained until handled, ensure that recognized. select_n This provides indication microcontroller that interrupt type been placed address/data when internal Interrupt Control Unit slaved external interrupt controller. Before this occurs however, int0 must have indicated interrupt request occurred.
int2/inta0_n/pwd/pio31 Maskable Interrupt Request (asynchronous input) Interrupt Acknowledge (synchronous output) Pulse Width Demodulator (Schmitt trigger input)
int2 int2 provides indication that interrupt request occurred, provided that int1 masked, program execution will continue location specified int1 vector interrupt vector table. Although interrupt requests asynchronous, they synchronized internally edge level triggered. assertion
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8/16-BIT MICROCONTROLLERS
interrupt request must maintained until handled, ensure that recognized. When int0 configured cascade mode, int2 changes function inta0_n. inta0_n this function indicates system that microcontroller requires interrupt type response interrupt request int0 when microcontroller's Interrupt Control Unit cascade mode. processes signal Schmitt trigger when pulse width demodulation enabled. drives ti

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