IA186EM/IA188EM 8/16-BIT Microcontrollers Copyright 2003 IA1
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IA186EM/IA188EM 8/16-BIT Microcontrollers
Copyright 2003
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Production Version
Data Sheet Contents FEATURES.3 Description.4 Interface Control Peripheral Control Registers Clock Power Management
System Clocks. Power-Save Mode. Initialization Reset. Reset Configuration Register. Chip-Selects Chip-Select Timing Ready Wait-State Programming Chip-Select Overlap Upper Memory Chip Select.53 Memory Chip Select Midrange Memory Chip Selects Peripheral Chip Selects Refresh Control Interrupt Control.54 Timer Control.56 Direct Memory Access (DMA) Operation.57 Asynchronous Serial Port
Synchronous Serial Port Programmable (PIO) Descriptions Instruction Summary (Key abbreviations appears table).73 Absolute Maximum Ratings Characteristics Over Commercial Operating Ranges
Characteristics Over Commercial Operating Ranges MHz) Waveforms
Physical Dimensions .124 Ordering Information .127
IA186EM-PQF100I.127 IA186EM-PTQ100I .127 IA188EM-PQF100I.127 IA188EM-PTQ100I .127 Cross Reference Part Numbers .127 Errata .128 Copyright 2003 ENG21 030617-03 www.innovasic.com innovASIC Customer Support: Obsolescence® Page 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Production Version
FEATURES
Pin- for-Pin compatible with AMD® Am186EM/188EM devices features retained, including: allowing same crystal/system clock frequency 8086/8088 instruction with additional instruction extensions Programmable interrupt controller channels Three 16-bit timers Programmable chip select logic wait-state generator Dedicated watch timer independent asynchronous serial ports (UARTs) capability Hardware flow control 9-bit data capability Pulse Width Demodulator feature programmable pins (PIO) Pseudo-static/dynamic controller Fully static CMOS design operation industrial operating conditions power supply Available packages: 100-pin Thin Quad Flat Pack (TQFP) 100-pin Plastic Quad Flat Pack (PQFP)
IA186EM/188EM form, fit, function replacement original Advanced Micro Devices® Am186EM/188EM family microcontrollers. InnovASIC produces replacement using MILES Managed Lifetime Extensio System, cloning technology. This technology produces replacement more complex than "emulation" while ensuring they compatible with original MILES captures design clone produced even silicon technology advances. MILES also verifies clone against original that even "undocumented features" duplicated. This Data Sheet contains preliminary information IA186EM/188EM. complete data sheet which documents necessary engineering information about IA186EM/188EM including functional descriptions, electrical characteristics, applicable timing will available when device nears completion.
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Production Version
Description
IA186EM/188EM family microcontrollers replaces obsolete Am186EM/188EM devices, allowing customers retain existing board designs, software compilers/assemblers, emulation tools, thereby avoiding expensive redesign efforts. IA186EM/188EM microcontrollers upgrade 80C186/188 microcontroller designs, with integrated peripherals provide increased functionality reduce system costs. InnovASIC devices designed satisfy requirements embedded products designed telecommunications, office automation storage, industrial controls. block diagram IA186EM/188EM microcontroller depicted Figure IA186EM/188EM microcontroller consists following functional blocks: Interface Control Peripheral Control Registers Chip Selects Control Programmable Clock Power Management Direct Memory Access (DMA) Interrupt Controller Timers Asynchronous Serial Ports Synchronous Serial Interface.
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Production Version
uzi_n s6/clkdiv2_n
s2_n s0_n
hlda srdy den_n/ds_n ardy
a[19:0] ad[15:0] den_n wr_n wlb_n whb_n rd_n
dt/r_n
hold
Clock Power Management Interface Control
clkouta
clkoutb
drq0
Direct Memory Access
res_n drq1
Peripheral Control Registers
int4 int3/inta1_n/irq
Interrupt Controller
int2/inta0_n int1/select_n int0
tmrin0
Timers
lcs_n/once0_n mcs3_n/rfsh_n ucs_n/once1_n pcs5_n/a1 pcs6_n/a2 mcs2_n mcs0_n pcs3_n pcs0_n
tmrout0 tmrin1 tmrout1
Chip Selects Control
txd0
Asynchronous Serial Port
rxd0 cts0_n/enrx0_n rts0_n/rtr0_n
sclk pio[31:0]
Programmable
Synchronous Serial Port
sden0 sden1 sdata
Instruction Decode Execution
Figure IA186/88EM Block Diagram Note: descriptions pins that share other functions with pins. pwd, int5, int6, rts1_n/rtr1_n, cts1_n/enrx1_n multiplexed with int2_n/inta0_n, drq0_n, drq0_n, pcs3_n, pcs2_n respectively.
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
brief description each block follows:
Production Version
Interface Control
Interface Control (BIC) manages accesses external memory external peripherals. These peripherals mapped either memory space space. supports both multiplexed non- multiplexed operations. Multiplexed address data provided [15:0] bus, while non- multiplexed address provided [19:0] bus. provides address information entire cycle (t1-t4), while provides address information only during first (t1) phase cycle. more details regarding cycles, waveforms this datasheet. IA186EM microcontroller provides signals that serve byte write enables, write high byte (whb_n) write byte (wlb_n). Obviously, IA188EM microcontroller requires only single write byte (wb_n) signal support 8-bit data bus. whb_n logical bhe_n wr_n. wlb_n logical wr_n. wlb_n logical wr_n. wb_n whenever byte written IA188EM data ad[7:0]. byte write enables driven conjunction with non- multiplexed address a[19:0] facilitate meeting timing requirements common SRAMs. also provides support Pseudo-Static (PSRAM) devices. PSRAM supported lower chip select (lcs_n) area only. order support PSRAM Chip Selects Control (CSC) must appropriately programmed. details regarding this operation Chips Selects Control Section this datasheet.
Peripheral Control Registers
on-chip peripherals IA186EM/188EM microcontroller controlled from 256-byte block internal registers. Although these registers actually located peripherals they control, they addressed within single 256-byte block spaced therefore treated functional unit purposes this document. these registers depicted table write operations performed IA188EM should 8-bit writes, which will still result 16-bit data transfers Peripheral Control Block (PCB) register even named register 8-bit register. read performed registers should word reads. Code written with these points mind will correctly both IA186EM IA188EM. However unpredictable behavior will result both IA186EM IA188EM processors unaligned read write accesses performed.
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Register Name Peripheral Control Block Registers
Relocation Register Reset Configuration Register Processor Release Level Register Power-Save Control Register Enable Register Clock Prescaler Register Memory Partition Register
Production Version
Register Name Timer Registers
Timer Mode Control Register Timer Count Compare Register Timer Count Register Timer Mode Control Register Timer Count Compare Register Timer Count Compare Register Timer Count Register Timer Mode Control Register Timer Count Compare Register Timer Count Compare Register Timer Count Register
Offset
Offset
Registers
DMA1 Control Register DMA1 Transfer Count Register DMA1 Destination Address High Register DMA1 Destination Address Register DMA1 Source Address High Register DMA1 Source Address Register DMA0 Control Register DMA0 Transfer Count Register DMA0 Destination Address High Register DMA0 Destination Address Register DMA0 Source Address High Register DMA0 Source Address Register
Interrupt Registers
Serial Port Interrupt Control Register Watchdog Timer Control Register INT4 Interrupt Control Register INT3 Interrupt Control Register INT2 Interrupt Control Register INT1 Interrupt Control Register INT0 Interrupt Control Register DMA1 Interrupt Control Register DMA0 Interrupt Control Register Timer Interrupt Control Register Interrupt Status Register Interrupt Request Register In-Service Register Priority Mask Register Interrupt Mask Register Poll Status Register Poll Register End-of-Interrupt (EOI) Register Interrupt Vector Register
Chip-Select Registers
pcs_n mcs_n Auxiliary Register Mid-Range Memory Chip -Select Register Peripheral Chip-Select Register Low-Memory Chip-Select Register Upper-Memory Chip-Select Register
Asynchronous Serial Port Register
Serial Port Baud Rate Divisor Register Serial Port Receive Register Serial Port Transmit Register Serial Port Status Register Serial Port Control Register
Synchronous Serial Port Register
Synchronous Serial Receive Register Synchronous Serial Transmit Register Synchronous Serial Transmit Register Synchronous Serial Enable Register Synchronous Serial Status Register
Registers
Data Register Direction Register Mode Register Data Register Direction Register Mode Register
Table Peripheral Control Registers.
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
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RELREG (0feh) Peripheral Control Block RELocation REGister maps entire Peripheral Control Block Register Bank either memory space. addition, RELREG contains which places Interrupt Controller either Master Slave Mode. RELREG contains 20ffh reset. S/Mn
IO/Mn
[19:8]
(bit Reserved. S/Mn (bit this places Interrupt Controller into slave mode. When zero, Interrupt Controller master mode. (bit Reserved. IO/Mn (bit 12)- this maps Peripheral Control Block Register Bank into space. When zero, Peripheral Control Block mapped into memory space. [19:8] (bits 11-0) Sets base address (upper bits) Peripheral Control Block Register Bank. [7:0} default zero. Note that when (IO/M_n) one, [19:16] ignored.
RESCON (0f6h) RESet figuration Register latches user-defined information present specified pins rising edge reset. This contents this register read only remain valid until next reset. RESCON contains user-defined information reset.
[15:0]
[15:0] (bits 15-0) rising edge reset, values specified pins [15:0] IA186Es [15:8], [7:0]} IA188EM) latched into this register.
(0f4h) Processor Release Level Register contains code corresponding latest processor production release. Read-Only Register contains 0400h. [7:0] Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page
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IA186EM/IA188EM
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[7:0] (bits 15-8) latest Processor Release Level. Value Processor Release Level (bits 7-0) Reserved.
Production Version
PDCON (0f0h) Power-save CONtrol Register controls several miscellaneous system timing functions. SYSCON contains 0000h reset. PSEN
PSEN (bit When one, enables power-save mode causing internal operating clock divided value F2-F0. External interrupts interrupts from internal interrupts automatically clear PSEN. Software interrupts exception clear PSEN. Please that value PSEN restored upon execution IRET instruction. (bit 14-12) Reserved. These bits read back zeros. (bit When one, clkoutb output follows input crystal (PLL) frequency. When this zero, clkoutb follows internal clock frequency after clock divider. (bit When one, clkoutb output pulled low. When this zero, clkoutb driven output bit. (bit When one, clkouta output follows input crystal (PLL) frequency. When this zero, clkouta follows internal clock frequency after clock divider. (bit When one, clkouta output pulled low. When this zero, clkouta driven output bit. (bits 7-3) Reserved. These bits read back zeros. F2-F0 (bits 2-0) These bits control clock divider shown below. Note, PSEN must clock divider function. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Production Version
Divider Factor Divide (20) Divide (21) Divide (22) Divide (23) Divide (24) Divide (25) Divide (26) Divide (27)
EDRAM (0e4h) Enable Register provides control status refresh counter. EDRAM register contains 0000h reset. [8:0]
(bit When one, refresh counter enabled msc3_n configured rfsh_n. Clearing clears refresh counter disables refresh requests. refresh address unaffected clearing (bits 14-9) Reserved. These bits read back zero. [8:0] (bits 8-0) These bits hold current value refresh counter. These bits read-only.
CDRAM (0e2h) Clock Prescaler Register determines period between refresh cycles. CDRAM register undefined reset. [8:0]
(bits 15-9) Reserved. These bits read back zero. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
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[8:0] (bits 8-0) These bits hold clock count interval between refresh cycles. This value should less than (12h), else there would never sufficient cycles available processor execute code. power-save mode, refresh counter value should adjusted account clock divider value SYSCON.
MDRAM (0e0h) Memory Partition Register holds A19-A13 address bits 20-bit base refresh address. MDRAM register contains 0000h reset. [6:0]
[6:0] (bits 15-9) Upper bits corresponding address bits a19-a13 20-Bit memory refresh address. These bits available a19-a0 bus. When using PSRAM mode, M6-M0 must programmed 0000000b. Reserved [8:0] (bits 8-0) Reserved. These bits read back zero.
D1CON (0dah) CONtrol Registers. D0CON (0cah) Control Registers control operation channels. D0CON D1CON registers undefined reset, except that
DM/IOn
DDEC
DINC
SM/IOn
SDEC
SINC
TDRQ
Bn/W
SYN1SYN0
DM/IOn (bit Destination Address Space Select selects memory space destination address. When DM/IO destination address memory space, while when destination address space. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page
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DDEC (bit Destination Decrement automatically decrements destination address after each transfer when address decremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). DINC (bit Destination Increment, when automatically increments destination address after each transfer. address incremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). SM/IOn (bit Source Address Space Select selects memory space source address. When SM/IOn source address memory space, while when source address space. SDEC (bit Source Decrement, when automatically decrements destination address after each transfer. address decremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). SINC (bit Source Increment, when automatically increments destination address after each transfer. address incremented depending byte/word (Bn/W, address does change increment decrement bits same value (00b 11b). (bit Terminal Count. decrements transfer count each transfer. When source destination synchronized transfers terminate when count reaches when source destination synchronized transfers terminate when count reaches Unsynchronized transfers always when count reaches irrespective setting this bit. (bit Interrupt. channel generates interrupt request completion transfer count when this However, interrupt generated, must also SYN1-SYN0 (bits 7-6) Synchronization Type bits select channel synchronization shown following table. value these bits ignored TDRQ (bit processor reset causes these bits 11b. SYN1 SYN0 Sync Type Unsynchronized Source Synchronized Destination Synchronized Reserved
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(bit Relative Priority. Selects high priority this channel relative other channel during simultaneous transfers when TDRQ (bit Timer Synchronization. Enables requests from timer when disables requests from timer when (bit Reserved. (bit Change Start Bit. This must allow modification during write. During write, when changed when writing control word. result reading this always (bit Start/Stop Channel. When start channel started. must this modified only during same register write. processor reset causes this Bn/W (bit Byte/Word Select. When word transfers selected, when byte transfers selected. (The IA188EM does support word transfers furthermore they supported chip selects programmed 8-bit transfers.)
D1TC (0d8h) Transfer Count Registers. D0TC (0c8h) Transfer Count registers maintained each channel. They decremented after each state control register influence this activity. But, unsynchronized transfers programmed control word set, activity ceases when transfer count register reaches D0TC D1TC registers undefined reset.
TC15 [15:0] (bits 15-0) Transfer Count contains transfer count respective channel. value decremented after each transfer.
D1DSTH (0d6h) DeSTination Address High Register. D0DSTH (0c6h) 20-bit destination address consists these four bits combined with 16-bits respective Destination Address Register. transfer requires that complete 16-bit registers (high registers) used both source destination addresses each channel involved. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
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These four registers must initialized. Each address incremented decremented independently each other after each transfer. addresses incremented decremented word transfers incremented decremented byte transfers. D0DSTH D1DSTH registers undefined reset. Reserved Reserved [15:4] (bits 15-4) Reserved. [19:16] (bits 3-0) Destination Address High bits driven onto A19-A16 during write phase transfer.
DDA19-DDA16
DIDSTL (0d4h) DeSTination Address Register. D0DSTL (0c4h) sixteen bits these registers combined with four bits respective Destination Address High Register produce 20-bit destination address. D0DSTL D1DSTL registers undefined reset.
DDA15 DDA0 [15:0] (bits 15-0) Destination Address bits driven onto A15-A0 during write phase transfer.
D1SRCH (0d2h) SouRCe Address High Register. D0SRCH (0c2h) 20-bit source address consists these four bits combined with 16-bits respective Source Address Register. transfer requires that complete 16-bit registers peripheral control block (high registers) used both source destination addresses each channel involved. Each channel requires that four address registers initialized. Each address incremented decremented independently each other after each transfer. addresses incremented decremented word transfers incremented decremented byte transfers. D0SRCH D1SRCHL registers undefined reset. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Production Version
Reserved
DSA19 -DSA16
Reserved [15:4] (bits 15-4) Reserved [19:16] (bits 3-0) Source Address High bits driven onto A19-A16 during read phase transfer.
D1SRCL (0d0h) SouRCe Address Register. D0SRCL (0c0h) sixteen bits these registers combined with four bits respective Source Address High register produce 20-bit source address. D0SRCL D1SRCL registers undefined reset.
DSA15-DSA0
[15:0] (bits 15-0) Source Address bits placed onto a15-a0 during read phase transfer.
MPCS (0a8h) Auxiliary Register. This register controls more than type chip select, making different from other chip select control registers. MPCS register contains information following, mcs3_n mcs0_n well pcs6_n pcs5_n pcs3_n pcs0_n. MPCS register also contains that configures pcs6_n pcs5_n pins either chip selects alternate sources address bits. Either address bits pcs6_n pcs5_n selected exclusion other. When programmed address bits, these outputs used provide latched address bits pcs6_n pcs5_n high active processor reset. access MPCS register causes pins activate, when pcs6_n pcs5_n configured address pins. pcs6_n pcs5_n pins require corresponding access PACS register activated. value MPCS register undefined reset. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
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M6-M0
R1-R0
Reserved (bit [6:0] (bits14-8) MCS_n Block Size These bits determine total block size MCS3_n MCS0_n chip selects. total block size divided equally among four chip selects. following table shows relationship between [6:0] size memory block.
Total Block Size 128K 256K 512K
Individual Select Size 128K
0000001b 0000010b 0000100b 0001000b 0010000b 0100000b 1000000b
(bit7) Selector This determines whether pcs6_n pcs5_n pins configured chip selects alternate outputs When this pcs6_n pcs5_n configured peripheral chip select pins, whereas when pcs6_n pcs5_n become address address respectively. (bit Memory/ Space Selector determines whether pcs_n pins active either during memory cycles. When pcs_n outputs active memory cycles, active cycles when Reserved (bits 5:3) (bit Ready Mode This influences only pcs6_n pcs5_n chip selects. external ready required, while external ready ignored. each case, values R1-R0 bits determine number wait states inserted. [1:0] (bits 1-0) Wait-State Value These bits influence only pcs6_n pcs5_n chip selects. value R1-R0 determines number wait states inserted into access depending whether PCS_n memory area. three wait states inserted 11b).
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IA186EM/IA188EM
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MMCS (0a6h) Midrange Memory Chip Select Register. Four chip-select pins, mcs3_n mcs0_n, provided within user- locatable memory block. memory block base address located anywhere within 1-Mbyte memory address space, excluding areas associated with ucs_n lcs_n chip selects (and, mapped memory, address range Peripheral Chip Selects, pcs6_n pcs5_n pcs3_n pcs0_n). pcs_n chip selects mapped space mcs_n address range overlap pcs_n address range registers program Midrange Chip Selects. Midrange Memory Chip Select (MMCS) register determines base address, ready condition wait states memory block that accessed through mcs_n pins. pcs_n mcs_n Auxiliary (MPCS) register configures block size. reset mcs3_n mcs0_n pins active. Accessing with write both MMCS MPCS registers activates these chip selects. mcs3_n mcs0_n outputs assert with multiplexed address (ad15 ao15 ad0) rather than earlier timing unlike ucs_n lcs_n chip selects. timing delayed half cycle later than that ucs_n lcs_n used address selection. value MMCS register undefined reset.
BA19 BA13
[15:9] (bits 15-9) Base Address. value BA19 BA13 determines Base Address memory block that addressed mcs_n chip select pins. These bits correspond bits 20-bit memory address. remaining bits base address always base address integer multiple size memory clock selected MPCS register. example, midrange block Kbytes, block could located 20000h 28000h 24000h. lcs_n chip select inactive, base address midrange chip selects 00000h, because lcs_n chip select defined 00000h unused. further limitation that base address must integer multiple block size means that 512K MMCS block size only used with lcs_n chip select inactive base address midrange chip selects 00000h. Reserved [8:3] (bits 8-3) (bit Ready mode. This determines mcs_n chip selects ready mode. When external ready necessary, external ready ignored. each case number wait states inserted access determined value bits. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
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[1:0] (bits 1-0) Wait-State Value. number wait states inserted access determined value bits. three wait states inserted 11b). PACS (0a4h) PeripherAl Chip Select Register. Peripheral Chip Selects asserted over 256-byte range with same timing address bus. There chip selects, pcs6_n pcs5_n pcs3_n pcs0_n that utilized either userlocatable memory blocks. pcs4_n chip select implemented ia18xEM family Micro controllers. Excluding areas utilized ucs_n, lcs_n, mcs_n chip selects, memory block located anywhere within Mbyte address space. These chip selects also configured access Kbyte space. Programming Peripheral Chip Selects uses registers, Peripheral Chip Select (PACS) register pcs_n mcs_n Auxiliary (MPCS) register. PACS register establishes base address, configures ready mode, determines number wait states pcs3_n pcs0_n outputs. MPCS register configures pcs6_n pcs5_n pins either chip selects address pins When these pins configured chip selects, MPCS register determines whether they active during memory cycles determines ready state wait states these output pins. These pins active reset activated chip selects writing registers (PACS MPCS). configure activate them address pins necessary write both PACS MPCS registers. pcs6_n pcs5_n configured wait states while pcs3_n pcs0_n programmed wait states. value PACS register undefined reset.
BA19 BA11
[19:11] (bits 15-7) Base Address bits determine base address correspond bits 20-bit programmable base address peripheral chip select block. However PCS_n chip selects mapped space, these bits must 0000b, addresses only bits wide. Address Ranges PCSn Line PCS0n PCS1n PCS2n PCS3n Reserved PCS5n PCS6n Range High Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address 1023 Base Address 1280 Base Address Base Address 1536 Base Address www.innovasic.com Customer Support: 1.888.824.4184
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Reserved [6:4] (bits 6-4) (bit Wait State Value. following table.
Production Version
(bit Ready Mode. When external ready required. When external ready ignored, each case number wait states determined following table. [1:0] (bits Wait-State Value. following table. should noted that pcs6_n pcs5_n pcs3_n pcs0_n pins multiplexed with programmable pins them function chip selects, mode direction settings these pins must normal operation.
PCS3n PCS0n Wait-State Encoding
Wait States
LMCS (0a2h) Memory Chip Select Register configures Memory Chip Select that been provided facilitate access interrupt vector table located 00000h bottom memory. lcs_n active reset. width data lcs_n space should configured AUXCON register before activating lcs_n chip select pin, write access LMCS register. value LMCS register undefined reset except which
R1-R0
Reserved [15] (bit Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
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[2:0] (bits Upper Boundary. These bits define upper boundary memory accessed lcs_n chip select. following table gives possible configurations block size (max 512Kbytes). LMCS Block Size Programming Values Memory Block Size 128K 256K 512K Reserved [11:8] (bits 11-8) (bit Disable Address When address driven onto address (ad15 ad0) during address phase cycle, while address disabled, providing some measure power saving. This reset. BHE_n/ADEN_n held during rising edge res_n, then address always driven, independent setting (bit PSRAM Mode Enable PSRAM support lcs_n chip select memory space enabled when EDRAM, MDRAM, CDRAM refresh control unit registers must configured auto refresh before PSRAM support enabled. Setting enable (EN) enable register (EDRAM, offset e4h) configures mcs3_n/rfsh_n rfsh_n. Reserved (bits 5-3) (bit Ready Mode. When this external ready required, while when external ready ignored. either case however, value bits determine number wait states inserted. [1:0] (bits R1-R0) Wait-State Value. number wait states inserted into access LCS_n memory area determined value these bits. This number ranges from 11b)
Ending Address 0FFFFh 1FFFFh 3FFFFh 7FFFFh
000b 001b 011b 111b
UMCS (0a0h) Upper Memory Chip Select Register configures Upper Memory Chip Select pin, which used memory. reset first fetch takes place memory location FFFF0h thus this area memory usually used instruction memory. With this mind UCS_n defaults active state reset with memory range Kbytes (F0000h FFFFFh), external ready required, three wait states automatically inserted. upper memory range always ends FFFFFh, whereas lower this upper memory range programmable. value UMCS register F03Bh reset. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
Production Version
R1-R0
Reserved [15] (bit [2:0] (bits 14-12) Lower Boundary. These bits determine bottom memory accessed ucs_n chip selects.
UMCS Block Size Programming Values Memory Starting Block Address Size F0000h 128K E0000h 256K C0000h 512K 80000h Reserved (bits
111b 110b 100b 000b
Comments Default
(bit Disable Address. When address driven onto address (ad15 during address phase cycle when ucs_n asserted, while address disabled, address driven address when ucs_n asserted, providing some measure power saving. This reset. bhe_n/aden_n held during rising edge res_n, then address always driven independent setting Reserved (bit Reserved (bit (bit Ready Mode When this external ready required, while when external ready ignored. either case however, value bits determine number wait states inserted. [1:0] (bits 1-0) Wait-State Value. number wait states inserted into access lcs_n memory area determined value these bits. This number ranges from 11b).
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IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
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SPBAUD (088h) Serial Port BAUD Rate Divisor Register. value this register determines number internal processor cycles phase (half-period) serial clock. contents these registers must adjusted reflect processor clock frequency powersave mode effect. baud rate divisor calculated from: BAUDDIV (Processor Frequency baud rate)) setting BAUDDIV 0000h, maximum baud rate 1/32 internal processor frequency clock set. Setting BAUDDIV (81h) provides baud rate 9600 40MHz. baud rate tolerance +4.6% -1.9% with respect actual serial port baud rate, target baud rate. Baud Rates Baud Rate 1200 2400 4800 9600 14400 19200 Kbaud 781.25 Kbaud 1.041 Mbaud 1.25 Mbaud 2082 1040 Divisor Based Clock Rate 2603 1301 3471 1735 4165 2082 1040
value SPBAUD register reset undefined.
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BAUDDIV [15:0] (bits 15-0) Baud Rate Divisor. Defines divisor internal processor clock.
SPRD (086h) Serial Port Receive Data Register. Data received over serial port stored this register until read. data received initially receive shift register software access) permitting data received while previous data being read. (Receive Data Ready) serial port status register indicates status SPRD register. When indicates that there valid data receive register. value SPRD register undefined reset. Reserved Reserved (bits 15-8) Reserved. RDATA [7:0] (bits 7-0) Holds valid data while status register set. RDATA
SPTD (084h) Serial Port Transmit Data Register. Data written this register, software, with values transmitted serial port. Double buffering transmitter allows transmission data from transmit shift register software access), while next data written into transmit register. THRE Serial Port Status register indicates whether there valid data SPDT register. THRE must before writing data this register prevent overwriting valid data that already SPDT register. value SPTD register undefined reset. Reserved Reserved (bits 15-8) Reserved. TDATA [7:0] (bits 7-0) Holds data transmitted. TDATA
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SPSTS (082h) Serial Port STatuS Register. This register stores information concerning current status port. status bits described below. value SPSTS register undefined reset.
Reserved Reserved (bits 15-7) Reserved
TEMT THRE BRKI
TEMT (bit Transmitter Empty. When both transmit shift register transmit register empty, this indicating software that safe disable transmitter. This read only. THRE (bit Transmit Holding Register Empty. When this indicates that corresponding transmit holding register ready accept data. This read only bit. (bit Receive Data Ready. When this indicates that respective SPRD register contains valid data. This read/write only reset reading corresponding Receive register. BRKI (bit -Break Interrupt. This indicates that break been received when this causes serial port interrupt request. NOTE: This should reset software. (bit Framing Error Detected. When receiver samples line when stop expected (line high) framing error generated setting this bit. NOTE: This should reset software. (bit Parity Error Detected. When parity error detected either mode this set. NOTE: This should reset software. (bit Overrun Error Detected. When data overwrites valid data receive register (because hasn't been read) overrun error detected setting this bit. NOTE: This should reset software.
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SPCT (080h) Serial Port ConTrol Register. This register controls both transmit receive parts serial port. value SPCT register 0000h reset.
Reserved
LOOP
WLGN
TMODE
RSIE
RMODE
PMODE
Reserved (bits 15-12) Reserved. TXIE (bit Transmitter Ready Interrupt Enable. This enables generation interrupt requests whenever transmit holding register empty (THRE respective port does generate interrupts when this Interrupts continue generated long THRE TXIE RXIE (bit Receive Data Ready Interrupt Enable. This enables generation interrupt requests whenever receive register contains valid data (RDR respective port does generate interrupts when this Interrupts continue generated long RXIE LOOP (bit Loop-back. serial port placed into loop-back mode this set. (bit Send Break. When this driven overriding data that course being shifted transmit shift register. definitions long short break Serial Port Status register definition. BRKVAL (bit Break Value. This ninth data transmitted when modes This cleared each transmitted word buffered. transmit data with this high following procedure recommended. TEMT serial port status register must high. writing serial port control register. Finally write transmit character serial port transmit register. Serial port special case that this associated pins used flow control overriding Peripheral Chip Select signals. This reset. PMODE (bits6:5) Parity Mode. When this driven overriding data course being shifted transmit shift register. definitions long short break Serial Port Status register definition.
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WLGN (bit Word Length. number bits transmitted received frame determined value this bit. When this number data bits frame whereas when this number data bits frame This reset. (bit Stop Bits. This specifies number stop bits used indicate frame. When this number stop bits when number stop bits This reset. TMODE (bit Transmit Mode. transmit section serial port enabled when this disabled when this RSIE (bit Receive Status Interrupt Enable. When exception occurs during data reception interrupt request generated enabled this (RSIE Interrupt requests made error conditions listed (BRK, OER, PER, FER) serial port status register. This reset. RMODE (bit Receive Mode. receive section serial port enabled when this disabled when this This reset.
PDATA1 (07ah) DATA Registers. PDATA0 (074h), When configured output value corresponding data register driven onto pin. other hand, configured input then value input into corresponding data register. following table lists default states pins. Assignments Number
Associated Name
tmrin1 tmrout1 pcs6/A2 pcs5/A1 dt/r_n den_n/ds_n srdy
Power-On Reset Status
Input with pull-up Input with pull-down Input with pull-up Input with pull-up Normal operation(c) Normal operation(c) Normal operation(d)
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Number
7(a) 8(a) 9(a) 26(a, 29(a,
Associated Name
tmrout0 tmrin0 drq0 drq1 mcs0_n mcs1_n pcs0_n pcs1_n pcs2_n pcs3_n sclk sdata sden0 sden1 mcs2_n mcs3_n/rfsh_n s6/clkdiv2_n int4 int2
Power-On Reset Status
Normal operation(c) Normal operation(c) Normal operation(c) Input with pull-down Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull- down Input with pull- down Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up
Notes: Emulators these pins. (s2_n-s0_n, res_n, nmi, clkouta, bhe_n, ale, ad15 ad0, used emulators also.) bhe_n/aden_n (ia186EM) rfsh2_n/aden (ia188EM) held during power-on reset these pins revert normal operation. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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When used pin, input with available pull- option. When used pin, input with available pull-down option.
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value PDATA registers undefined reset. PDATA
PDATA PDATA
PDATA
PDATA [15:0] (bits 15-0) Data Bits. This register contains values bits that either driven received from corresponding pins depending configuration each either output input. values these bits correspond those direction registers Mode registers. PDATA [31:16] (bits 15-0) Data Bits. This register contains values bits that either driven received from, corresponding pins depending configuration each either output input. values these bits correspond those direction registers Mode registers pins operated open-drain outputs Maintain data constant appropriate data register. Writing value data into respective position Direction register, that output either disabled depending value data bit.
PDIR1 (078h) DIRection Registers. PDIR0 (072h) Each configured input output corresponding direction register.
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Mode Direction Settings Mode Direction function Normal operation input with pullup/pulldown output input without pullup/pulldown
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PDIR0 value PDIR0 register FC0Fh reset.
PDIR
PDIR1 value PDIR1 register FFFFh reset.
PDIR
PDIR [15:0] (bits 15-0) Direction Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers. PDIR [31:16] (bits 15-0) Direction Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers.
PIOMODE1 (076h) MODE Registers. PIOMODE0 (070h) Each configured input output corresponding direction register. number PMODE corresponds number. table Mode Direction Settings PDIR description above. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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PIOMODE0 value PIOMODE0 register 0000h reset.
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PMODE
PIOMODE1 value PIOMODE1 register 0000h reset.
PMODE
PMODE [15:0] (bits 15-0) Mode Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers.
PMODE [31:16] (bits 15-0) Mode Bits. each bit, value then configured input output value values these bits correspond those data registers Mode registers.
T1CON (05eh) Timer Timer Mode CONtrol Registers. T0CON (056h) This registers controls operation Timer Timer respectively. value both T0CON T1CON registers 0000h reset.
INHn
CONT
(bit Enable Bit. timer enabled when timer count inhibited when This write only, with INHn same write operation. INHn (bit Inhibit Bit. Gates setting enable (EN) bit. This must same write operation that sets enable (EN) bit, otherwise will changed. This always reads (bit Interrupt Bit. interrupt request generated when Count register reaches maximum, setting dual maxcount mode interrupt request generated when count register reaches value maxcount maxcount interrupt Copyright 2003 ENG21 030617-03 www.innovasic.com innovASIC Customer Support: Obsolescence® Page 1.888.824.4184
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requests generated this interrupt request generated then enable cleared before said interrupt serviced, interrupt request will remain. (bit Register Bit. This when maxcount register used compare timer count value. when maxcount compare register used. Reserved (bits 11-6) (bit Maximum Count. When timer reaches maximum count this regardless interrupt enable bit. This also every time Maxcount Compare register reached, when dual maxcount mode. This used software polling monitor timer status rather than through interrupts desired. (bit Retrigger Bit. This controls timer function timer input pin. When count reset transition timrin0 tmrin1. When high input tmrin0 tmrin1 enables count holds timer value. This ignored external clocking (EXT=1)bit set. (bit Prescaler Bit. ignored external clocking enabled (EXT Timer prescales timer when Otherwise timer incremented every fourth CLKOUT cycle. (bit External Clock Bit. This determines whether external internal clock used. external clock used internal used. (bit Alternate Compare Bit. timer will count Maxcount Compare reset count register then count maxcount compare reset count register begin again maxcount compare timer will count maxcount compare reset count register begin again maxcount compare Maxcount compare used this case. CONT (bit Continuous Mode Bit. timer will continuously when this timer will stop after each count will cleared CONT CONT respective timer counts maxcount compare value resets, then commences counting maxcount compare value, resets ceases counting.
T2CON (066h) Timer Mode CONtrol Register. This register controls operation Timer value T2CON register 0000h reset. CONT
INHn
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(bit Enable Bit. timer enabled when timer count inhibited when Setting this writing T2CON register requires that during same write. This write only, with INHn same write operation. INHn (bit Inhibit Bit. Gates setting enable (EN) bit. This must same write operation that sets enable (EN) bit. This always reads (bit Interrupt Bit. interrupt request generated, setting when Count register reaches maximum, Reserved (bits 12-6) (bit Maximum Count. When timer reaches maximum count this regardless interrupt enable bit. This used software polling monitor timer status rather than through interrupts desired. Reserved (bits 4-1) CONT (bit Continuous Mode Bit. timer will continuously when this timer will stop after each count will cleared this
T2COMPA (062h), Timer Maxcount COMpare Registers. T1COMPB (05ch) T1COMPA (05ah) T0COMPB (054h) T0COMPA (052h) These registers contain maximum count value that compared respective count register. Timer Timer have these compare registers each. Timer and/or Timer is/are configured count compare firstly register then register tmrout0 tmrout1 signals used generate various duty-cycle wave forms. Timer only compare register, T2COMPA. these timer maxcount compare registers 0000h, respective timer will count from 0000h FFFFh before generating interrupt request. example timer configured this manner with 40MHz clock will interrupt every 6.5536 value these registers undefined reset.
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[15:0] (bits 15-0) Timer Compare Value. timer will count value respective register before resetting count value
T2CNT (060h) Timer CouNT Registers. T1CNT (058h) T0CNT (050h), These registers incremented every four internal clock cycles relevant timer enabled. Increment Timer Timer also controlled external signals tmrin0 tmrin1 respectively, prescaled Timer Comparisons made between count registers maxcount registers action taken dependant achieving maximum count. value these registers undefined reset.
TC15 [15:0] (bits 15-0) Timer Count Value. This register value current count related timer that incremented every fourth processor clock internal clocked mode. Alternatively register incremented each time Timer maxcount reached using Timer prescaler. Timer Timer externally clocked tmrin0 tmrin1 signals.
SPICON (044h) Serial Port Interrupt CONtrol Register. (Master Mode) This register controls operation asynchronous serial port interrupt source (SPI, Interrupt Request register) value this register 001Fh reset. PR2-PR0
Reserved Reserved (bits 15-5) Reserved (bit to1. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page
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(bit Mask. This bit, when enables serial port cause interrupt. When this prevents serial port from generating interrupt. PR2-PR0 (bits 2-0) Priority. These bits define priority serial port interrupt relation other interrupt signals. interrupt priority lowest reset. values shown following table. Priority Level Priority (High) (Low) 000b 001b 010b 011b 100b 101b 110b 111b
WDCON (044h) WatchDog timer interrupt CONtrol Register. (Master Mode) These registers control operation Watchdog Timer interrupt source. value this register 000Fh reset. PR2-PR0
Reserved Reserved (bits 15-5) Reserved (bit
(bit Mask. This bit, when enables Watchdog Timer cause interrupt. When this prevents Watchdog Timer from generating interrupt. PR2-PR0 (bits 2-0) Priority. These bits define priority Watchdog Timer interrupt relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level). I4CON (040h) INT4 CONtrol Register. (Master Mode) Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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This register controls operation int4 signal, which only intended fully nested mode. interrupt assigned type 10h. value I4CON register 000Fh reset.
PR2-PR0
Reserved
LMSK
Reserved (bits 15-5) L(bit Level-Triggered Mode. int4 interrupt edge level triggered depending value bit. int4 active high level sensitive interrupt int4 rising edge triggered interrupt. interrupt int4 must remain active (high) until serviced. (bit Mask. int4 signal cause interrupt int4 signal cannot cause interrupt PR2-PR0 (bit 2-0) Priority. These bits define priority serial port interrupt relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
I3CON (03eh) INT2/INT3 CONtrol Register. I2CON (03ch), (Master Mode) INT2 INT3 designated interrupt type respectively. int2 int3 pins configured interrupt acknowledge pins inta0_n inta1_n respectively cascade mode. value these registers 000Fh reset. PR2-PR0
Reserved Reserved (bits 15-5)
LMSK
L(bit Level-Triggered Mode int2 int3 interrupt edge level triggered depending value this bit. int2 int3 active high level-sensitive interrupt int2 int3 rising edge triggered interrupt. interrupt int2 int3 must remain active (high) until acknowledged. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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(bit Mask. int2 int3 signal cause interrupt int2 int3 signal cannot cause interrupt Interrupt Mask Register duplicate this bit. PR2-PR0 (bit 2-0) Priority. These bits define priority serial port interrupt int2 int3 relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
I1CON (03ah) INT0/INT1 trol Register. I0CON (038h), (Master Mode) IINT0 INT1 designated interrupt type respectively. int2 int3 pins configured interrupt acknowledge pins inta0 inta1 respectively, interrupt acknowledge signals int0 int1 cascade mode. value these registers 000Fh reset.
Reserved Reserved (bits 15-7)
SFNM LMSK
PR2-PR0
SPNM (bit Special Fully Nested Mode. This enables fully nested mode int0 int1 when (bit Cascade Mode. This enables cascade mode int0 int1 when L(bit Level-Triggered Mode. int0 int1 interrupt edge level triggered depending value bit. int0 int1 active high level-sensitive interrupt int0 int1 rising edge triggered interrupt. interrupt int0 int1 must remain active (high) until acknowledged. (bit Mask. int0 int1 signal cause interrupt int0 int1 signal cannot cause interrupt Interrupt Mask Register duplicate this bit. PR2-PR0 (bit 2-0) Priority. These bits define priority serial port interrupt int0 int1 relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
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TCUCON (032h) Timer Control Unit Interrupt CONtrol Register. (Master Mode) three timers have their interrupts assigned types 08h, 12h, configured this register. value this register 000Fh reset. PR2-PR0
Reserved Reserved (bits 15-4)
(bit Interrupt Mask. interrupt source cause interrupt interrupt source cannot cause interrupt Interrupt Mask Register duplicate this bit. PR2-PR0 (bit 2-0) Priority. These bits define priority serial port interrupt relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
T2INTCON (03ah) Timer INTerrupt CONtrol Register. T1INTCON (038h) T0INTCON (032h) (Slave Mode) three timers, Timer2, Timer1, Timer0, each have interrupt control register, whereas master mode three masked prioritized register (TCUCON). value these registers 000Fh reset.
Reserved
Reserved (bits 15-4) (bit Mask. interrupt sources cause interrupt interrupt sources cannot cause interrupt Interrupt Mask Register duplicate this bit. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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PR2-PR0 (bit 2-0) Priority. These bits define priority serial port interrupts relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
DMA1CON/INT6CON (036h) INTerrupt CONtrol Register. DMA0CON/INT5CON (034h) (Master Mode) DMA0 DMA1 interrupts have interrupt type respectively. These pins configured external interrupts requests respective Control register. value these registers 000Fh reset.
Reserved
Reserved (bits 15-4) (bit Mask. interrupt sources cause interrupt interrupt sources cannot cause interrupt Interrupt Mask Register duplicate this bit. PR2-PR0 (bits 2-0) Priority. These bits define priority serial port interrupts relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
DMA1CON/INT6 (036h) INTerrupt trol Register. DMA0CON/INT5 (034h) (Slave Mode) control registers maintain their original functions addressing that they possessed Master Mode. These pins configured external interrupts requests respective Control register.
value these registers 000Fh reset. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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Reserved Reserved (bits 15-4)
(bit Mask. interrupt sources cause interrupt interrupt sources cannot cause interrupt Interrupt Mask Register duplicate this bit. PR2-PR0 (bits 2-0) Priority. These bits define priority serial port interrupts relation other interrupt signals. interrupt priority lowest reset. values shown above table (Priority Level).
INTSTS (030h) INTerrupt STatuS Register. (Master Mode) Interrupt status register contains interrupt request status each three timers, Timer2, Timer1, Timer0. DHLT TMR2 TMR0
Reserved
DHLT (bit Halt. activity halted when this automatically when non- maskable interrupt occurs cleared when IRET instruction executed. Interrupt handlers other time critical software modify this directly disable transfers. However, DHLT should modified software timer interrupts enabled function this register interrupt request register timers would compromised. Reserved (bits 14-3) [2:0] (bit 2-0) Timer Interrupt Request. pending interrupt request indicated respective timer, when these bits (N.B. REQST register logical these timer interrupt requests)
(Slave Mode) When nonmaskable interrupts occur interrupt status register controls operation interrupt request status each three timers, Timer2, Timer1, Timer0. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page
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DHLT
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TMR2 TMR0
Reserved
DHLT (bit Halt. activity halted when this automatically when non- maskable interrupt occurs cleared when IRET instruction executed. Reserved (bits 14-3) [2:0] (bit 2-0) Timer Interrupt Request. pending interrupt request indicated respective timer, when these bits (N.B. REQST register logical these timer interrupt requests)
REQST (02eh) Interrupt REQueST Register. (Master Mode) This read only register, such read results status interrupt request bits presented interrupt controller. REQST register undefined reset.
Reserved Reserved (bits
(bit Serial Port Interrupt Request. This serial port interrupt state when enabled logical serial port interrupt sources: THRE, RDR, BRKI, FER, PER, OER. (bit Watchdog Timer Interrupt Request. This watchdog interrupt state indicates that interrupt pending when [4:0] (bits Interrupt Requests. When these bits indicates that relevant interrupt pending interrupt. D1-D0 (bit 3:2) Channel Interrupt Request. When either indicates that either respective channel pending interrupt. Reserved (bit (bit Timer Interrupt Request. This timer interrupt state logical timer interrupt requests. When indicates that timer control unit pending interrupt. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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(Slave Mode)
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This read only register, such read results status interrupt request bits presented interrupt controller. status these bits available when this register read. When internal interrupt request (D1, TMR2, TMR1, TMR0 occurs, respective internally generated interrupt acknowledge resets these bits. REQST register contains 0000h reset. TMR0
Reserved Reserved (bits
TMR2 TMR1
TMR2 (bit Interrupt Requests. When indicates that timer pending interrupt. TMR1 (bit Interrupt Requests. When indicates that timer pending interrupt. D1:D0 (bits 3:2) Channel Interrupt Request. When either indicates that either respective channel pending interrupt. Reserved (bit TMR0 (bit Timer0 Interrupt Request. When indicates that timer pending interrupt.
INSERV (02ch) IN-SERVice Register. (Master Mode) interrupt controller sets bits this register when interrupt taken. Writing corresponding interrupt type End-of-Interrupt (EOI) register clears each these bits. When these bits set, interrupt request will generated microcontroller respective source, preventing interrupt from interrupting itself interrupts enabled ISR. This restriction bypassed fully Special Fully nested mode INT0 INT1 sources. INSERV register contains 0000h reset
Reserved Reserved (bits
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(bit Serial Port Interrupt Request. This serial port interrupt state. (bit Watchdog Timer Interrupt In-Service Request. This In-Service state Watchdog Timer. [4:0] (bits Interrupt Requests. When these bits indicates that relevant interrupt pending interrupt. D1-D0 (bit 3:2) Channel Interrupt In-Service. This In-Service state respective channel. Reserved (bit (bit Timer Interrupt Request. This timer interrupt state logical timer interrupt requests. When indicates that timer control unit pending interrupt.
(Slave Mode This read only register, such read supplies status interrupt request bits presented interrupt controller. When internal interrupt request (D1, TMR2, TMR1, TMR0 occurs, respective internally generated interrupt acknowledge resets these bits. REQST register contains 0000h reset. TMR0
Reserved
TMR2 TMR1
Reserved (bits TMR2 (bit Timer2 Interrupt Service. Timer being serviced when this TMR1 (bit Timer1 Interrupt Service. Timer being serviced when this D1-D0 (bit 3:2) Channel Interrupt Service. respective channel being serviced when this Reserved (bit TMR0 (bit Timer Interrupt Service. Timer being serviced when this
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PRIMSK (02ah) PRIority MaSK Register. (Master Slave Mode)
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This register contains value that sets minimum priority level which interrupt generated maskable interrupt. PRIMSK register contains 0007h reset
PRM2 PRM0
Reserved (bits 2-PRM0 (bits Priority Field Mask. This three-bit field sets minimum priority necessary maskable interrupt generate interrupt. maskable interrupt, with numerically higher value than that contained these three bits, masked. Priority Level Priority (High) (Low)
unmasked interrupt generate interrupt priority level other hand priority level only unmasked interrupts with priority permitted generate interrupts. IMASK (028h) Interrupt MASK Register. (Master Mode) interrupt mask register read/write. Setting this register effectively same setting corresponding interrupt control register. Setting masks interrupt. interrupt request enabled when corresponding IMASK register contains 07fdh reset
Reserved
D1-D0
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Reserved (bits
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(bit Serial Port Interrupt Mask. Setting this indication that asynchronous serial port interrupt masked. (bit Watchdog Timer Interrupt In-Service Request. Setting this indication that Watchdog Timer interrupt masked. [4:0] (bits Interrupt Mask. When these bits indication that relevant interrupt masked. D1-D0 (bit 3:2) Channel Interrupt Mask. Setting this indication that respective channel interrupt masked. Reserved (bit (bit Timer Interrupt Mask. When indicates that timer control unit interrupt masked.
(Slave Mode) interrupt mask register read/write. Setting this register effectively same setting corresponding interrupt control register. Setting masks interrupt request. interrupt request enabled when corresponding IMASK register contains 003dh reset. TMR0
Reserved Reserved (bits
TMR2 TMR1
TMR2 (bit Timer2 Interrupt Mask. This provides indication state mask Timer Interrupt Control register. When indicates that interrupt request masked. TMR1 (bit Timer1 Interrupt Mask. This provides indication state mask Timer Interrupt Control register. When indicates that interrupt request masked. D1-D0 (bit 3:2) Channel Interrupt Mask. This provides indication state mask respective channel Interrupt Control register. When indicates that interrupt request masked. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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Reserved (bit
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TMR0 (bit Timer Interrupt Mask. This provides indication state mask Timer Interrupt Control register. indicates that interrupt request masked.
POLLST (026h) POLL STatus Register. (Master Mode) This register reflects current state Poll register read without affecting contents. However when Poll Register read, causes current interrupt acknowledged replaced next interrupt. poll status register read only. IREQ
Reserved
IREQ (bit Interrupt Request. This when interrupt pending during this state, bits contain valid data. Reserved (bits 14-6) [4:0] (bit 4-0) Poll Status. These bits show interrupt type highest priority pending interrupt. interrupt service routine does begin execution automatically with rather application software must execute appropriate ISR.
POLL (024h) POLL Register. (Master Mode) When Poll Register read, causes current interrupt acknowledged replaced next interrupt. poll status register reflects current state Poll register read without affecting contents. POLL register read only. IREQ www.innovasic.com Customer Support: 1.888.824.4184
Reserved
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IREQ (bit Interrupt Request. This when interrupt pending during this state, bits contain valid data. Reserved (bits 14-6) [4:0] (bit 4-0) Poll Status. These bits show interrupt type highest priority pending interrupt.
(022h) End-Of-Interrupt Register. (Master Mode) Service flags In-Service register reset when write made register. interrupt service routine (ISR) should write reset bit, In-Service register, interrupt before executing IRET instruction than ends interrupt service routine. specific reset preferred method resetting bits most secure. register write only. NSPEC
Reserved
NSPEQ (bit Non-Specific EOI. This non-specific when indicates specific EOI. Reserved (bits 14-5) [4:0] (bit 4-0) Source Interrupt Type. These bits show interrupt type highest priority pending interrupt.
(022h) Specific End-Of-Interrupt Register. (Slave Mode) Service flag specific priority, In-Service register, reset when write made register. three-bit user supplied priority-level value that points in-service that reset. Writing this value this register resets specific bit. register write only undefined reset. www.innovasic.com Customer Support: 1.888.824.4184
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Reserved (bits 15-3) Write L[2:0] (bit 2-0) Interrupt Type. priority (interrupt service) reset encoded these three bits. Writing these bits caused issuance interrupt type. Table Interrupt Types.
INTVEC (020h) -INTerrupt VECtor Register. (Slave Mode) shifts left bits (multiplies 8-bit interrupt type, generated interrupt controller, produce offset into interrupt vector table. INTVEC register undefined reset.
Reserved (bits 15-8) Read [4:0] (bits 7-3) Interrupt Type. These five bits contain most significant bits interrupt types used internal interrupt type. least significant bits interrupt type supplied interrupt controller, priority level interrupt request. Reserved (bits 2-0) Read
(018h) Synchronous Serial Receive Register. This register holds serial data received port. value register undefined reset.
Reserved
SR7-SR0
Reserved (bits 15-8) Reserved Bits. SR[7:0] (bits 7-0) Data received over SDATA pin.
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SSD0 (016h) Synchronous Serial Transmit Registers. SSD0 (014h) These registers hold data transmitted ports. value these registers undefined reset.
Reserved Reserved (bits 15-8) Reserved Bits. SD[7:0] (bits 7-0) Data transmitted over SDATA pin.
SD7-SD0
(012h) Synchronous Serial Control Register. This register controls operation sden1 sden0 outputs baud rate port. sden1 sden0 outputs held high when respective event that both then only sden0 will held high. value register 0000h reset.
Reserved Reserved (bits 15-6) Reserved Bits.
SCLKDIV
DE1-DE0
SCLKDIV (bits 5-4) SCLK Divide. These bits SCLK frequency. SCLK result dividing internal processor clock following table. SCLKDIV (bits 3-2) Reserved Bits. SCLK Frequency Divider Processor Clock Processor Clock Processor Clock Processor Clock
(bit1) SDEN1. SDEN1 held high when this SDEN1 held when this Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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(bit0) SDEN0. SDEN0 held high when this SDEN0 held when this
(010h) Synchronous Serial Status Register. This read only register that indicates state port. value register 0000h reset.
Reserved Reserved (bits 15-3) Reserved Bits.
RE/TE DR/DT
RE/TE (bit Receive/Transmit Error Detect. This when read Synchronous Serial Received register write transmit register detected while interface busy This reset when SDEN output active (DE1-DE0 register 00h). DR/DT (bit Data Receive/Transmit Complete. This when transmission data completed (SCLK rising edge) during transmit receive operation. This reset read register, when either SSD0 SSD1 register written, when register read (unless completes operation sets same cycle), when both SDEN0 SDEN1 become inactive. (bit Port busy. This indicates that data transmit receive occurring when When indicates that port ready transmit receive data.
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Clock Power Management
phase- lock- loop (PLL) second programmable system clock output (CLKOUTB) included clock power management unit. internal clock same frequency crystal with duty cycle worse case, generated obviating need external clock. power-on reset (POR) resets PLL. Recommended range values are: 15pF 22pF
Crystal
Am186/188EM
Figure Crystal Configuration
System Clocks.
required internal oscillator driven external clock source that should connected leaving unconnected. clock outputs clkouta clkoutb enabled disabled individually (Power-Save Control register (PDCON) bits 8)). These clock control bits allow clock output frequency other power-save frequency. Processor Internal Clock
Power-Save Divisor /128)
clkouta
Drive enable Time Delay 2.5nS Drive enable clkoutb
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Power-Save Mode.
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operation peripherals operate slower clock frequency when power save mode reducing power consumption thermal dissipation. Should interrupt occur, microcontroller returns normal operating frequency automatically internal clock's next rising edge clock dependant devices should reprogrammed changed frequency during power-save mode period.
Initialization Reset.
res_n (Reset), highest priority interrupt, must held during power- initialize microcontroller correctly. This operation makes device cease instruction execution local activity. microcontoller begins instruction execution physical address FFFF0h when res_n becomes inactive after internal processing interval with ucs_n asserted three wait states. Reset also sets certain registers predetermined values resets Watchdog timer.
Reset Configuration Register.
data address/data (ad15 Am186EM ao15 Am188EM) written into Reset Configuration register when reset low. This data system dependant held Reset Configuration register after Reset de-asserted. This configuration data placed address/data using weak external pull- pull-down resistors applied external driver, processor does drive during reset. method supplying software with some initial data after reset; example, option jumper positions.
Chip-Selects
Chip-select generation programmable memories peripherals. Programming also available produce ready wait-state generation plus latched address bits memory cycles, chip-select lines active within their programmed areas, regardless whether they generated internal unit CPU. There chip-selects outputs memories further peripherals whether memory space. memory chip-selects able address three memory ranges, whereas peripheral chip-selects used address 256-byte blocks that offset from programmable base address. Writing chip-select register enables related logic even event that question another function, example case that programmed PIO.
Chip-Select Timing
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Ready Wait-State Programming
Each memory peripheral chip-select lines have ready signal programmed that ardy signal. chip-select control registers (UMCS, LMCS, MMCS, PACS, MPCS) have single that selects external ready signal used (R2, (bits 1-0) these registers control number wait-states that inserted during each access memory peripheral location (from control registers pcs3_n pcs0_n utilize three bits, (bits provide wait-states addition original values wait states. case where external ready been selected required, internally programmed wait-states will always completed before external ready finish extend cycle. example, consider system which number wait-states inserted been three; external ready sampled processor during first wait cycle. access completed after seven cycles cycles plus wait-cycles) ready asserted; alternatively ready asserted during first wait cycle access prolonged until ready asserted more wait-states inserted followed
Chip-Select Overlap
Overlapping chip-selects those configurations which more than chip-select asserted same physical address. example configured space with other chip select configured memory, address 00000h overlapping chip selects. recommended that multiple chip-select signals asserted same physical address, although inescapable certain systems. this case, then overlapping chip-selects must have same external ready configuration same number wait-states inserted into access cycles. Internal signals employed access peripheral control block (PCB) these signals serve chip selects that configured with wait-states external ready. programmed with addresses that overlap external chip-selects only these chip selects configured same manner. Care should exercised Disable Address (DA) LMCS UMCS registers when overlapping additional chip-select with either lcs_n ucs_n chip-selects. Setting prevents address from being driven onto accesses which respective chip-select active, including those accesses which multiple selects active. mcs_n pcs_n pins dual-purpose pins, either chip-selects inputs outputs, however their respective ready wait-state configurations their chip-select function will effect matter which function these pins actually programmed. This requires that even these pins configured enabled, writing MMCS MPCS registers mcs_n chipselects PACS MPCS registers pcs_n chip-selects), ready wait-state settings these signals must agree with settings over- lapping chip-selects they been configured chip-selects. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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Even though pcs4_n available external ready wait-state logic must therefore follow rules overlapping chip-selects. pcs6_n pcs5_n other hand have ready waitstate logic that disabled when these pins configured address bits respectively. chip-select configuration rules followed processor hang with appearance waiting ready signal even system which ready (ardy srdy) always
Upper Memory Chip Select
ucs_n chip-select memory. reset micro controller begins fetching executing instructions memory locatio FFFF0h, upper memory usually utilized instruction memory. this ucs_n active reset memory range 64Kbytes (F0000h FFFFFh) default along with external ready required three wait-states automatically inserted. lower boundary ucs_n programmable provide ranges 64Kbytes 512Kbytes.
Memory Chip Select
lcs_n chip-select lower memory. interrupt vector table bottom memory beginning 00000h, this usually utilized control data memory. Unlike ucs_n this inactive reset, activated read write LMCS register.
Midrange Memory Chip Selects
There four midrange chip-selects, mcs3_n-mcs0_n, which used user- located memory block. base address memory block located anywhere 1-Mbyte memory address space with some exceptions. memory spaces used ucs_n lcs_n chip-selects excluded, pcs6_n, pcs5_n, pcs3_n pcs0_n. pcs_n chip-selects mapped space then address range overlap address range. Both Midrange Memory Chip Select (MMCS) register Auxiliary register (MPCS) registers used program four midrange chip-selects. MPCS register used configure block size, whereas MMCS register configures base address, ready condition, wait states memory block accessed mcs_n pin. chip selects (mcs3_n-mcs0_n) activated performing read write operation MMCS MPCS registers. assertion outputs occurs with same timing multiplexed address (ad15ad0 ao15-ao8 ad7-ad0). a19-a0 used address selection timing will delayed half clock cycle over timing used ucs_n lcs_n.
Peripheral Chip Selects
There peripheral chip-selects, pcs6_n, pcs5_n, pcs3_n pcs0_n, that used within user defined memory block. base address this user defined memory block located Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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anywhere within 1-Mbyte memory address space except spaces associated with ucs_n, lcs_n, mcs_n chip selects, programmed 64Kbyte space. pcs4_n available. Both Peripheral Chip Select (PACS) register Auxiliary register (MPCS) registers used program peripheral chip-selects, pcs6_n, pcs5_n, pcs3_n pcs0_n. PACS register sets base address, ready condition, wait states pcs3_n pcs0_n outputs. MPCS register configures pcs6_n pcs5_n pins either chip selects address pins respectively. When these pins chip selects MPCS register also configures them being active during memory cycles, their ready wait states. None pcs_n pins active reset. Both Peripheral Chip Select (PACS) register Auxiliary register (MPCS) registers must read written activate pcs_n pins chip selects. pcs6_n pcs5_n programmed have wait-states, whereas pcs3_n pcs0_n programmed have these wait-states.
Refresh Control
Refresh Control Unit (RCU) generates refresh cycles. generates memory read request after programmable period time interface unit. Enable register (EDRAM) enables refresh cycles, operating processor internal clock. processor power-save mode, must reconfigured clock rate. hlda asserted when refresh request initiated (indicating hold condition), processor disables hlda allow refresh cycle performed. external circuit master must deassert hold signal least clock period permit execution refresh cycle.
Interrupt Control
Interrupt requests originate from variety internal external sources, that arranged internal interrupt controller priority order presented processor. external interrupt sources, five maskable (int4-int0) nonmaskable (NMI) connected processor, internal interrupt sources (three timers, channels, asynchronous serial port that brought external pins. Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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five external maskable interrupt request pins used direct interrupt requests. However should more interrupts needed int3-int0 with external interrupt controller 82C59A type. programming internal interrupt controller slave mode, external 82C59A compatible interrupt controller used system master. Interrupt nesting used cases that permit interrupts higher priority interrupt those lower priority. When interrupt accepted, other interrupts disabled, re-enabled setting Interrupt Enable Flag (IF), Processor Status Flags register, during Interrupt Service Routine (ISR). Setting permits interrupts equal greater priority interrupt currently running ISR. Further interrupts from same source will blocked until corresponding In-Service register (INSERV) cleared. Special Fully Nested mode invoked int0 int1 SFNM INT0 INT1 Control register respectively, when this this mode interrupt generated these sources regardless in-service bit. following table shows priorities interrupts power-on reset. Interrupt Types
Interrupt Name Divide Error Exception Trace Interrupt Non-maskable Interrupt (NMI) Breakpoint Interrupt INT0 Detected Overflow Exception Array Bounds Exception Unused Opcode Exception Opcode Exception Timer Interrupt
Interrupt Type
Vector Table Address
Type
Overall Priority
Related Instructions DIV, IDIV INT3 INT0 BOUND Undefined Opcodes Opcodes
Timer Interrupt Timer Interrupt Reserved Interrupt Interrupt INT0 Interrupt INT1 Interrupt INT2 Interrupt INT3 Interrupt INT4 Interrupt Watchdog Timer Interrupt Asynchronous Serial Port Interrupt Reserved
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Interrupt Table Notes: user does changed priority levels then default priority level will used interrupt sources. Instruction execution generates interrupts. Performed same manner 8086 8088. opcode causes trap. Only generated three timers they share priority level with regard other sources. timers themselves have interrupt priority order among themselves 2C). These interrupt types programmable Slave mode. available slave mode.
Timer Control
IA186EM IA188EM each have three programmable timers. Timer0 timer1 each have input output connected external pins that permit them count time events, produce variable duty-cycle waveforms non-repetitive waveforms. Timer1 also configured Watchdog timer. Timer2 does have external connections confined internal functions such real- time coding, time-delay applications, prescaler timer0 timer1, synchronize transfers. Peripheral Control Block contains eleven 16-bit registers control programmable timers. present value timer located associated timer-count register, which read from written time regardless whether timer operation not. value timer-count register incremented microcontroller every time timer event takes place. maximum value that each timer reach determined value stored associated maximum count register. Upon reaching this maximum count value; timer count register reset same clock cycle that this count attained, that timer count register does store this maximum value. Both timer0 timer1 have maximum count registers, primary secondary register, permitting each timer alternate between discrete maximum values. Timer0 timer1 have maximum count registers configured ways, primary only both primary secondary. only primary configured operate then reaching maximum count output will clock period. both primary secondary registers enabled then output reflects state whichever registers control time, generating required waveform that dependant values maximum count registers.
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timers operate quarter internal clock frequency they polled every fourth clock period. Alternatively external clock used, this case timer output take clock cycles respond input.
Direct Memory Access (DMA)
Direct memory access (DMA) relieves involvement transfer data between memory peripherals over either both high-speed channels. Data transferred from memory I/O, memory, memory-to-memory, I/O-to-I/O. Furthermore channels connected asynchronous serial port. IA186EM microcontroller supports transfer both bytes words, from, even addresses, does support word transfers memory that configured byte accesses. IA188EM does support word transfers all. Each data transfer will take cycles minimum clock cycles). There three sources requests each channel, channel request (drq1 drq0), Timer2, system software. channels programmed have different priorities facilitate resolution simultaneous requests interrupt transfer other channel.
Operation
Peripheral Control Block contains registers each channel control specify operation channels. registers consist pair registers store 20-bit source address, pair registers store 20-bit destination address, 16-bit transfer count register, 16-bit control register. number transfers required designated Transfer Count register bytes words furthermore will automatically. channel function defined Control registers, which along with other registers changed time including during transfer implemented immediately.
Channel Control Registers D1CON (0dah) D0CON (0cah) CONtrol Registers above. Briefly, these registers specify following: data destination memory space? (Bit 15). destination address incremented, decremented, unchanged after each transfer? (Bit 13). data source memory space? (Bit 12).
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source address incremented, decremented, unchanged after each transfer? (Bit 10). transfers cease upon reaching designated count? (Bit Does last transfer generate interrupt? (Bit Synchronization mode. (Bits relative priority channel with respect other. (Bit Acceptance requests from Timer2. (Bit Byte Word transfers. (Bit Adder Control Logic Timer Request drq1
20-bit Adder/Subtractor Transfer Counter Destination Address Source Address Transfer Counter Destination Address Source Address
Request Selection Logic Control Logic
drq0 Interrupt Request
Channel Control Register Channel Control Register
Internal Address/Data Figure Unit
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Priority transfers have higher priority than transfers with exception word accesses memory locations between locked memory addresses. cannot access memory during transfer transfer cannot suspended interrupt request; continuous activity will thus cause interrupt latency suffer. However request halts activity, enabling respond promptly request.
Asynchronous Serial Port
asynchronous serial port employs standard industry communication protocols implementation full duplex, bi-directional data transfers. port source destination transfers. following features supported: Full-duplex data transfers 9-Bit data transfers Odd, even, parity stop bits Error detection provided Parity, Framing, Overrun errors Hardware handshaking achieved with following selectable control signals: Clear-to-send (cts_n) Enable receiver request (enrx_n) Ready send (rts_n) Ready receive (rtr_n)
from port port maskable interrupt port independent baud rate generator Maximum baud rate 1/32 processor clock Transmit Receive lines double buffered
power-save mode baud rate generator divide factor must re-programmed compensate change clock rate.
Synchronous Serial Port
synchronous serial port allows microcontrollers communicate with ASICs that require programmed have shortage. four-pin interface allows half-duplex bi-directional data transfer maximum Mbits/sec with clock.
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synchronous serial interface AI186EM/AI188EM operates master port master/slave arrangement. There four pins synchronous serial interface communication with system elements. These pins enables (SDEN0 SDEN1), clock (SCLK), data (SDATA). power-save mode baud rate generator divide factor must re-programmed compensate change clock rate.
Programmable (PIO)
pins programmable signals. following tables list these pins with their name number, firstly numerical order, then name alphabetical order. Programming should only performed normal function required normal function disabled longer affect pin. programmed input output with without either weak pull- pull-down, open-drain output. Following power reset pins have default status shown following tables.
(1,2) (1,2)
Associated tmrin1 tmrout1 pcs6_n/a2 pcs5_n/a1 dt/r_n den_n srdy tmrout0 tmrin0 drq0 drq1 mcs0_n mcs1_n pcs0_n pcs1_n pcs2_n pcs3_n sclk sdata sden0 sden1 mcs2_n mcs3_n/rfsh_n uzi_n s6/clkdiv2 int4 int2
Power-On Reset Status Input with pull-up Input with pull-down Input with pull-up Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Input with pull-down Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up
Associated den_n/ds_n drq0 drq1 dt/r_n int2/ int4 mcs0_n mcs1_n mcs2_n mcs3_n/rfsh_n pcs0_n pcs1_n pcs2_n pcs3_n pcs5_n/a1 pcs6_n/a2 s6/clkdiv2 sclk sdata sden0 sden1 srdy tmrin0 tmrin1 tmrout0 tmrout1 uzi_n
Power-On Reset Status Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Input with pull-up Input with pull-up Normal operation(3) Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up (1,2 Input with pull-up Input with pull-up Input with pull-up Input with pull-up Normal operation(4) Input with pull-up Input with pull-up Input with pull-down Input with pull-down Input with pull-up Input with pull-up
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These notes apply both tables Emulators these pins also s2_n-s0_n, res_n, nmi, clkouta, bhe_n ale, ad15-ad0, a15-a0. bhe_n/aden_n (IA186EM) rfsh_n/aden_n (IA188M) held during power-on reset then these pins will revert normal operation. Input with pull- option available when used PIO. Input with pull-down option available when used PIO. These default status setting changed desired. three most significant bits address (a19 a17) start with their normal function power reset, permitting processor begin fetching instructions from boot address FFFF0h. Furthermore, normal function default setting dt/r_n, den_n, srdy power reset. s6/clkdiv2_n uzi_n automatically return normal operation event that ad15-ad0 override enabled. ad15-ad0 override enabled bhe_n/aden_n IA186EM, rfsh2_n/aden_n IA188EM, held during power reset.
Descriptions
(pio9), (pio8), (pio7), Address (synchronous outputs with tristate)
These pins system's source non- multiplexed memory addresses occur half CLKOUTA cycle before multiplexed address/data (ad15-ad0 IA186EM ao15_ao8 ad7-ad0 AI188EM). address tristated during hold reset.
ad15 IA186EM Address/Data (level-sensitive synchronous inouts with tristate)
These pins system's source time-multiplexed memory addresses data. address function these pins disabled. (See bhe_n/aden_n description.) address function these pins enabled, address will present this during cycle data will present during same cycle. whb_n active then these pins tristated during cycle. address/data tristated during hold reset. These pins used load internal Reset Configuration register (RESCON, offset 0F6h) with configuration data during power-on reset.
Address/Data (level-sensitive synchronous inouts with tristate)
These pins system's source time-multiplexed order byte addresses memory 8-bit data. order address byte will present this during cycle 8bit data will present during same cycle. address function these pins disabled. (See bhe_n/aden_n description.) Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page
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wlb_n active, these pins tris tated during cycle. address/data tristated during hold reset. ao15 IA188EM Address-only (level-sensitive synchronous outputs with tristate) Address-only will contain valid high order address bits during cycle enabled. These pins combined with ad7-ad0 complete multiplexed address tristated during hold reset condition.
Address Latch Enable (synchronous output)
This signal indicates presence address address (ad15-ad0 IA186EM ao15ao8 ad7-ad0 AI188EM), which guaranteed valid falling edge ale.
ardy Asynchronous Ready (level-sensitive asynchronous input)
This asynchronous signal provides indication microcontroller that addressed device memory space will complete data transfer. This active high signal asynchronous with respect clkouta falling edge ardy sync hronized clkouta additional clock cycle added ardy should tied high maintain permanent assertion ready condition. other hand ardy signal used system should tied which passes control srdy signal.
bhe_n/aden_n IA186EM only High Enable (synchronous output with tristate) /Address Enable (input with internal pull-up)
bhe_n bhe_n address inform system which bytes data (upper, lower, both) involved current memory access cycle shown following table. bhe_n Type Cycle Word Transfer High Byte Transfer (Bits 15-8) Byte Transfer (Bits 7-0) Refresh
bhe_n does require latching during hold reset tristated. asserted during remains through high byte write enable functions bhe_n performed whb_n wlb_n respectively.
When using bus, DRAM refresh cycles icated bhe_n/aden_n both being high. During refresh cycles busses have same address during address phase cycle necessitating determinant refresh cycle rather than Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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additional signal utilized PSRAM refreshes (see mcs3_n/rfsh_n description). aden_n There weak internal pull- bhe_n/aden_n obviating need external pull- reducing power consumption. Holding aden_n high letting float during power-on reset passes control address function (ad15-ad0) during cycles from aden_n LMCS UMCS registers. When address function selected memory address placed a19-a0 pins. Holding aden_n during power-on reset, both address data driven onto independently setting. This normally sampled clock cycle after rising edge res_n.
clkouta Clock Output (synchronous output)
This internal clock output system. Bits Power-Save Control register (PDCON) control output this pin, which tristated, output crystal input frequency (X1), output power save frequency (internal processor frequency after divisor). clkouta used full speed clock source power-save mode. A.C. timing specifications that clock related refer clkouta, which remains active during reset hold conditions.
clkoutb Clock Output (synchronous output)
This additional clock system. Bits Power-Save Control register (PDCON) control output this pin, which tristated, output frequency, output power save frequency (internal processor frequency after divisor). clkoutb remains active during reset hold conditions.
den_n (pio5) Data Enable Strobe synchronous output with tristate)
This provides output enable external data transmitter receiver. This signal asserted during I/O, memory, interrupt acknowledge processes deasserted when dt/r_n undergoes change state. tristated hold reset.
drq1-drq (pio12-pio13) Requests (synchronous level-sensitive inputs)
drq0 external device, that ready channel carry transfer, indicates microcontroller this readiness these pins. They level triggered, internally synchronized, latched, must remain asserted until dealt with.
dt/r_n (pio4) Data Transmit Receive (synchronous output with tristate)
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microntroller transmits data when dt/r_n pulled high receives data when this pulled low. floats during reset hold condition.
Ground
seven pins, depending package, connect microcontroller system ground.
hlda Hold Acknowledge (synchronous output)
This pulled high signal system that microntroller ceded control local bus, response high hold signal external master, after microcontroller completed current cycle. assertion hlda accompanied tristating den_n, rd_n, wr_n, s2_n-s0_n, ad15-ad0, a19-a0, bhe_n, whb_n, wlb_n, dt/r_n, followed driving high chip selects ucs_n, lcs_n, mcs3_n mcs0_n, pcs6_n pcs5_n, pcs3_n pcs0_n. external master releases control local deassertion hold that turn induces microcontroller deassert hlda. microcontroller take control necessary, execute refresh example), deasserting hlda without master first deasserting hold. This requires that external master must able deassert hold permit microcontroller access bus.
hold Hold Request (synchronous level-sensitive input)
This pulled high signal microcontroller that system requires control local bus. hold latency time (time between hold hlda) depends current processor activity when hold received. hold request second only refresh request priority processor activity requests. hold request received moment transfer starts, hold latency cycles. IA186EM only this happens when word transfer taking place from address). This means that latency clock cycles without wait states. Furthermore lock transfers being performed then latency time increased during locked transfer.
int0 Maskable Interrupt Request (asynchronous input)
int0 provides indication that interrupt request occurred, provided that int0 masked, program execution will continue location specified INT0 vector interrupt vector table. Although interrupt requests asynchronous, they synchronized internally edge level triggered. assertion interrupt request must maintained until handled, ensure that recognized.
int1/select_n Maskable Interrupt Request 1/Slave Select (both asynchronous inputs)
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vector table. Although interrupt requests asynchronous, they synchronized internally edge level triggered. assertion interrupt request must maintained until handled, ensure that recognized. select_n This provides indication microcontroller that interrupt type been placed address/data when internal Interrupt Control Unit slaved external interrupt controller. Before this occurs however, int0 must have indicated interrupt request occurred.
int2/inta0_n (pio31) Maskable Interrupt Request (asynchronous input) Interrupt Acknowledge (synchronous output)
int2 int2 provides indication that interrupt request occurred, provided that int2 masked, program execution will continue location specified int2 vector interrupt vector table. Although interrupt requests asynchronous, they synchronized internally edge level triggered. assertion interrupt request must maintained until handled, ensure that recognized. When int0 configured cascade mode, int2 changes function inta0_n. inta0_n this function indicates system that microcontroller requires interrupt type response interrupt request int0 when microcontroller's Interrupt Control Unit cascade mode. peripheral device that issued interrupt must provide interrupt type.
int3/inta1_n/irq Maskable Interrupt Request (asynchronous input) Interrupt Acknowledge (synchronous output) Interrupt Acknowledge (synchronous output)
int3 int3 provides indication that interrupt request occurred, provided that int3 masked, program execution will continue location specified int3 vector interrupt vector table. Although interrupt requests asynchronous, they synchronized internally edge level triggered. assertion interrupt request must maintained until handled, ensure that recognized. When int1 configured cascade mode, int3 changes function inta1_n. inta1_n this function indicates system that microcontroller requires interrupt type response interrupt request int1 when microcontroller's Interrupt Control Unit cascade mode. peripheral device that issued interrupt must provide interrupt type. With Interrupt Control Unit microcontroller slave mode, signal this allows microcontroller output interrupt request external master interrupt controller.
int4/pio30 Maskable Interrupt Request (asynchronous input)
int4 int4 provides indication that interrupt request occurred, provided that int4 masked, program execution will continue location specified int4 vector interrupt vector table. Although interrupt requests asynchronous, they synchronized internally Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS
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edge level triggered. assertion interrupt request must maintained until handled, ensure that recognized.
lcs_n/once0_n Lower Memory Chip Select (synchronous output with internal pullup) ONCE Mode Request (input)
lcs_n lcs_n provides indication that memory access occurring lower memory block. size Lower Memory Block base address programmable, with size adjustable Kbytes. lcs_n held high during hold. once0_n (ONCE Circuit Emulation). This companion once1_n define microcontroller mode during reset. These pins sampled rising edge res_n both asserted microcontroller starts ONCE mode, else starts normally. ONCE mode pins tristated remain until subsequent reset. prevent microcontroller from entering ONCE mode inadvertently, this weak pull- that only present during reset. Finally this tristated during hold.
mcs2_n mcs0_n pio15 Midrange Memory Chip Selects (synchronous outputs with internal pull-up)
mcs0_n mcs2_n mcs0_n pins provide indication that memory access train either second third midrange memory block. size Midrange Memory Block base address programmable. mcs2_n mcs0_n held high during hold have weak pull- that only present during reset.
mcs3_n/rfsh_n (pio25) Midrange Memory Chip Select (synchronous output with internal pull-up) Automatic Refresh (synchronous output)
mcs3_n mcs3_n provides indication that memory access train fourth region midrange memory block. size Midrange Memory Block base address programmable. mcs3_n held high during hold weak pull- that only present during reset. rfsh_n This signal timed auto refresh PSRAM DRAM devices. refresh pulse only output when PSRAM DRAM mode (EDRAM register 15). This pulse clock pulse duration with rest refresh cycle made deassertion period such that overall refresh time met. Finally this tristated during hold.
Nonmaskable Interrupt (synchronous edge-sensitive input)
This highest priority interrupt signal cannot masked, unlike int4 int0. Program execution transferred nonmaskable interrupt vector interrupt vector table, upon assertion this interrupt (transition from High), this interrupt initiated next instruction boundary. recognition assured must held high least clkouta Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
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period that transition from high latched synchronized internally. interrupt will begin next instruction boundary. involved priority resolution process, that deals with maskable interrupts, does have associated interrupt flag. This allows request interrupt service routine that already underway. interrupt flag cleared, disabling maskable interrupts, when interrupt taken processor. during service routine, maskable interrupts reenabled, instruction example, priority resolution maskable interrupts will unaffected servicing NMI. strongly recommended, this reason, that interrupt service routine does enable maskable interrupts.
pcs3_n pcs0_n (pio19 pio16) Peripheral Chip Selects (synchronous outputs)
These pins provide indication that memory access under corresponding region peripheral memory block (I/O memory address space). base address Peripheral memory block programmable. pcs3_n pcs0_n held high during both hold reset. These outputs asserted with address over 256-byte range each.
pcs5_n/A1- Peripheral Chip Select (synchronous output) latched Address (synchronous output)
pcs5_n This signal provides indication that memory access under sixth region peripheral memory block (I/O memory address space). base address Peripheral memory block programmable. pcs5_n held high during both hold reset. This output asserted with address over 256-byte range. This provides internally latched address system when (bit MCS_n PCS_n auxiliary (MPCS) register retains previously latched value during hold.
pcs6_n/A2/ Peripheral Chip Select (synchronous output) latched Address (synchronous output)
pcs6_n This signal provides indication that memory access under seventh region peripheral memory block (I/O memory address space). base address Peripheral memory block programmable. pcs6_n held high during both hold reset. This output asserted with address over 256-byte range. This provides internally latched address system when (bit MCS_n PCS_n auxiliary (MPCS) register retains previously latched value during hold.
pio31 pio0 Programmable Pins (asynchronous input/output open -drain)
individually programmable pins provided. page Copyright 2003 ENG21 030617-03 innovASIC Obsolescence® Page www.innovasic.com Customer Support: 1.888.824.4184
IA186EM/IA188EM
8/16-BIT MICROCONTROLLERS rd_n Read strobe (synchronous output with tristate)
Production Version
This provides indication system that memory read cycle under way. will asserted before floated during address data transition. rd_n tristated during hold.
res_n Reset (asynchronous level-sensitive input)
This forces reset microcontroller. Schmitt trigger allow power-on reset generation network. When this signal asserted, microcontroller immediately terminates present activity, clears internal logic, transfers control reset address, FFFF0h. res_n must asserted least asserted asynchronously clkouta synchronized internally. Furthermore, must within specification clkouta must stable more than four clock periods period that res_n asserted. microcontroller starts fetch instructions clkouta clock periods after deassertion res_n.
rfsh2_n/aden_n IA188EM only Refresh (synchronous output with tristate) Address Enable (input with internal pull-up)
rfsh2_n Indicates that DRAM refresh cycle being performed when asserted low. However this valid PSRAM mode where mcs3_n/rfsh_n used instead. aden_n this held high during power-on reset, (ao15-ao8 ad7-ad0) controlled during address portion cycles (bit registers. address accessed a19-a0 pins reducing power consumption. weak pull- this obviates necessity external pull- this held during power-on reset, used both addresses data without regard setting bits. rfsh2_n/aden_n sampled crystal clock after rising edge res_n tristated during holds ONCE mode.
(pio28) Receive Data (asynchronous input)
This signal connects asynchronous serial receive data from system asynchronous serial port.
s2_n-s0_n Cycle Status (synchronous outputs with tristate)
These three signals inform system type cycle progress. s2_n used indicate whether current access memory I/O, s1_n used indicate whether data being transmitted received. These signals tristated during hold hold acknowledge. coding these pins shown following table.
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IA186EM/IA188EM
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s2_n
s1_n
s0_n
Cycle Interrupt acknowledge Read data from Write data Halt Instruction fetch Read data from memory Write data memory None (passive)
s6/clkdiv2_n (pio29) Cycle Status (synchronous output) /Clock Divide (input with internal pull-up)
This signal high during second remaining cycle periods, i.e. indicating that initiated cycle under way. tristated during hold reset. clkdiv2_n microcontroller enters clock divide-by-2 mode, this signal held during poweron-reset. this mode, disabled processor receives external clock divided Sampling this occurs rising edge res_n. Should this used pio29 configured input, care taken that driven during power-on-reset. This internal pull- necessary drive high even though defaults input PIO.
sclk Serial Clock (synchronous outputs with tristate)
This provides slave device with synchronous serial clock permitting synchronization transmit receive data exchanges between slave microcontroller. sclk result dividing internal clock dependant contents Synchronous Serial Control (SSC) register bits 5-4. Accessing either registers activates sclk eight cycles. When sclk active microcontroller hold high.
sdata Serial Data (synchronous inout)
This connects slave device synchronous serial transmit receive data. last value maintained this when inactive.
sden1 sden0 Serial Data Enables (synchronous outputs with tristate)
These pins facilitate transfer data ports Synchronous Serial Interface (SSI). Either sden1 sden0 asserted microcontroller start data transfer
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