SATC Controller 32-bit interface, interrupt lines support LS100s.

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SATC Controller 32-bit interface, interrupt lines support LS100s.

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LS105
SATC Controller
32-bit interface, interrupt lines support LS100s. 32/48 Interface with standard asynchronous SRAM cache addresses. Supports Port based VLAN with internal port registers. Optional Multicast type field usage bits implemented using additional SRAM. Selectable auto-learning hardware address learning without intervention. Selectable auto-aging hardware age-out old/unused address LS105. Provides MDC/MDIO interface. Provides µAccess interface. JTAG compliant. micron, 3.3V CMOS technology. PQFP package.
Description
LS105 Secondary Address Translation Cache (SATC) controller intended I-Cube Fast Ethernet SwitchSetTM. providing cache entries increases cache ratio backbone switch applications. LS105 master requires glue logic interface rest chipset. LS105 integrates master interface, hash generator, search engine, address learning hardware aging 208PQFP package. used auto (hardware) address learning mode directed address learning mode. LS105 provides µAccess interface perform bridging functions desired. complete secondary subsystem constructed using LS105 minimum external asynchronous SRAMs. 32Kx8, 32Kx16, 64Kx16, 256Kx16 SRAMs supported.
Input FIFO (Master) ATC_MISS#
Miss Controler Output FIFO (Master)
Hash
Search Engine
PCI_CLK
Hash
SRAM Address SRAM Data SRAM VLAN Data SRAM OE#,
SATC_MISS# PCI_RST#
SATC Miss FIFO (Slave)
Miss
Learn
Load Engine
SRAM Memory Controller
Data Control
µAccess Interface (Master)
Memory Window (Slave)
Device Registers (Slave)
Hash
Interface
SATC Load/Srch (Slave)
Results
MDIO
MDIO
Config (Slave)
Figure LS105 Functional Block Diagram
LS105 SATC Controller
Introduction
SwitchSet uses hierarchical cache architecture port mapping. primary cache LS100. stores port mappings most recently used addresses. system capable learning addresses; these stored main memory card) LS105's SRAM. Address maps transferred from CPU, LS105 secondary cache, LS100 quad port controller Bus. backbone switch application where large number users expected switch, performance address lookup port mapping improved using second level cache LS105 cache system. This allows faster port mapping look reduces flooding. Figure shows LS105, LS101 twenty five port switching element, LS100 quad port controller combined create scaleable workgroup switching hub. Variations this architecture used backbone stackable switch applications.
SSRAM
Physical Layer Devices
Port Port Port Port MII0 MII1 MII2 MII3
LS100
P(n-4)I P(n-3)I P(n-2)I P(n-1)I
P(n-4)O P(n-3)O P(n-2)O P(n-1)O
LS101
LS106
Interface
SSRAM
Physical Layer Devices
Port Port Port Port MIIn-3 MIIn-2 MIIn-1 MIIn
LS100
ETHERNET
DRAM FLASH
LS105
Figure Family System Block Diagram
Packets transferred between input output ports connections established through switch. These connections dynamic constructed demand basis. Requests connections through switch generated quad port ethernet switch devices (LS100s). These requests sent LS101 same port interfaces used transfer packet data. This process referred in-band signaling. 4B5B coding scheme used LS101 lets discriminate between packet data signaling data. port datapath between LS100s LS101 bits wide. Each general purpose port consists separate input output pins, allowing full duplex operation. Each port identified unique port code. Page I-Cube, Inc.
LS105 SATC Controller secondary address translation cache improves performance based switch caching addresses port mappings. LS100 quad contains sixty-four entry ATC. system where large number simultaneous users using switch, there possibility that entry enough additional port mappings will have fetched from main memory. incorporating secondary cache, system address look performance significantly improved. cache used destination addresses output port numbers check appearance source addresses learning. LS100 compares source addresses incoming packets. there match, generates miss interrupt. LS105 interrupt lines support LS100s. absence LS105, learn this address load port mapping this address from main memory. LS105 secondary controller off-loads task from CPU.
I-Cube, Inc.
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LS105 SATC Controller
Overview
Address lookup
LS105 uses pipelined architecture allow address lookups occur parallel read write cycles. When LS100 receives packet which does have address port mapping LS100 Primary ATC, LS100 will generate ATC_Miss# interrupt LS105 present system). LS105 will read double words from LS100 (composed address bits extra information, including port number which packet received on). LS105 will generate hash address from received address. LS105 stores address mappings within quad entry "buckets" pointed hash value. Address mapping lookup operations compare received address addresses stored within quad entry bucket until found. Assuming that mapping present LS105 SATC system, address mapping (MAC address port number) automatically loaded into LS100 ATC, with appropriate VLAN information (see VLAN section).
Address Learning
There learning modes supported LS105; Auto learning, CPU-directed learning. Auto learning mode, LS105 acts central address mapping database. mappings stored LS105, cached LS100 primary ATC. CPU-directed learning mode, LS105 acts secondary ATC; central address mapping database held storage, address mappings cached LS105 secondary LS100s' primary ATCs.
Memory configuration
LS105 SATC utilizes standard asynchronous SRAMs maintain secondary cache port mappings. algorithm used generate hash value each hash points bucket four addresses. following table shows different possible SRAM configurations achieve different cache sizes.
Hash pointers
Addresses cached
Address Cache SRAM
Multicast type field support SRAM 32Kx16 32Kx8 64Kx16 256Kx16
32Kx16 32Kx8 64Kx16 256Kx16
Table Memory configuration table
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I-Cube, Inc.
LS105 SATC Controller
VLAN
LS105 uses 32x32 system wide port register support Port based VLAN filtering. This port stores overall VLAN relationship between possible source destination ports. compares source ports destination ports. Each column represents source port. Each represents destination port. Each divided into eight segments, each which contain usage bits representing four ports particular LS100. LS100 implements port based VLAN using usage bits control mappings Unicast traffic. usage particular port, Unicast packets arriving that port forwarded using mapping. usage set, Unicast packets arriving that port will denied that mapping will forwarded according default behavior. Multicasts undergo lookup operations LS100 Multicast output queue. Usage bits used vectors Multicast traffic; usage particular port particular mapping set, multicast traffic flow that port. set, multicast traffic will flow that port. Address mapping entries external LS105 SRAM stored with source port information. When address mapping entry loaded from LS105 into LS100 during miss operation, source port information used select VLAN information from appropriate port register row. usage bits corresponding LS100 into whose entry will loaded drawn from that row, stored with mapping LS100 ATC. VLAN support SRAM present, usage bits drawn from port register row. VLAN support SRAM present, usage bits drawn from VLAN support SRAM multicast address. usage bits will control which ports LS100 utilize that mapping. LS105 SRAM optionally extended support mulitcast type filtering. optional VLAN support SRAM required multicast type field filtering because source port Multicast packets hence available VLAN table look operation. When address learned, VLAN support SRAM present, 1x32 slice (row) from system wide port register stored adjacent address parallel VLAN support SRAM. This slice indicates VLAN port numbers making particular VLAN which that address belongs Each address stored double words (2x32 bits). Each VLAN slice stored words (2x16 bits).
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LS105 SATC Controller
Description
Name PCI_AD [31:0] PCI_CBE [3:0]# PCI_RESET# PCI_PAR PCI_CLK PCI_STOP# PCI_FRAME# PCI_DEVSEL# PCI_IRDY# PCI_TRDY# PCI_IDSEL SATC_MISS# PCI_INTA# PCI_REQ# PCI_GNT#
Type Bi-directional Bi-directional Input Bi-directional Input Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Input Open Drain Output Open Drain Output Open Drain Output Input
Description Address/Data Command Byte Enable Reset Signal Parity Signal Clock Input Transaction Stop Signal Frame Signal Device Select Signal Initiator Ready Target Ready Signal Initialization Device Select Signal Secondary Address Translation Cache Miss Interrupt Interrupt Request Request Grant
Table Interface Description
Interface pads have internal resistors.
Name M_DATA [47:0] [17:0] M_OE# M_WE0# M_WE1#
Type Bi-directional Output Output Output Output
Description SRAM Databus Internal pull-down resistor SRAM Address Internal pull-down resistor SRAM Output Enable Signal Internal pull-up resistor SRAM Write Signal M_DATA [31:0] Internal pull-up resistor SRAM Write Signal M_DATA [47:32] (VLAN) Internal pull-up resistor
Table SRAM Interface Description
Name
Type Input Input Output Input
Description JTAG Test Clock Internal pull-up resistor JTAG Test Data Internal pull-up resistor JTAG Test Data Tristate Output JTAG Test Mode Select Internal pull-down resistor
Table JTAG Interface Description
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I-Cube, Inc.
LS105 SATC Controller
Name MDIO Type Output Bi-directional Description Serial Clock Output LS101 Internal pull-up resistor Data Input/Output LS101 Internal pull-up resistor
Table MDC/MDIO Interface Description
Name ATC_MISS [7:0]#
Type Input
Description Address Translation Cache Miss Interrupt from LS100 Internal pull-up resistor
Table LS100 Interface Description
Name µA_RST
Type Input
µA_RD# µA_WR# µA_CS# µA_ALE µA_AD[7:0] TEST
Input Input Input Input Bi-directional Input
GPIO[7]/µA_EN#
Bi-directional
GPIO[6:0]
Bi-directional
Description µAccess Reset This reset only resets µAccess interface. Internal pull-up resistor µAccess Read Internal pull-up resistor µAccess Write Internal pull-up resistor µAccess Chip Select Internal pull-up resistor µAccess Address Latch Enable Internal pull-up resistor µAccess Address/Data Internal pull-up resistor Test pin. Reserved future use. This must tied gnd. Internal pull-down resistor User Definable General Purpose I/O/µAccess Enable This must tied through resistor enable µAccess Interface. Internal pull-down resistor User Definable General Purpose Pins Internal pull-down resistor
Table µAccess Interface Description
Name
Type Power Ground
Description +3.3 Power chip Ground chip
Table Power Interface
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LS105 SATC Controller
Mechanical Specifications
PQFP Package Dimensions
Detail
Detail
Dimension (in.) 0.10 (0.004)
Symbol
3.99 0.25 0.43 3.43 3.56 30.40 30.91 27.93 28.14 30.40 30.91 27.93 28.14 0.45 0.76 0.15 0.28 0.50
inch inch 0.157 0.010 0.017 0.135 0.140 1.195 1.215 1.098 1.106 1.195 1.215 1.098 1.106 0.018 .030 0.006 0.011 0.0197
Table PQFP/208 Packeage Dimensions
Note: controlling dimension when used building footprint.
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I-Cube, Inc.
LS105 SATC Controller
Pinout
LS105 [PQFP/208L Package] Pinout: Name
Name µA_AD0 µA_AD1 µA_AD2 µA_AD3 µA_AD4 µA_AD5 µA_AD6 µA_AD7 µA_ALE µA_CS# µA_WR# µA_RD# µA_RST RESERVED RESERVED RESERVED TEST ATC_MISS0# ATC_MISS1# ATC_MISS2# ATC_MISS3# ATC_MISS4# ATC_MISS5# ATC_MISS6# ATC_MISS7# GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7/ µA_EN# MDIO PCI_RESET# PCI_PAR PCI_CLK PCI_STOP# PCI_FRAME# PCI_DEVSEL# PCI_IRDY# PCI_TRDY# PCI_IDSEL PCI_REQ# PCI_GNT# Name SATC_MISS# PCI_INTA# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 M_A0 M_A1 M_A2 M_A3 M_A4 M_A5 M_A6 M_A7 M_A8 M_A9 M_A10 Name M_A11 M_A12 M_A13 M_A14 M_A15 M_A16 M_A17 M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 Name M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_OE# M_WE0# M_WE1#
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LS105 SATC Controller
LS105 [PQFP/208L Package] Pinout: Sequence
Name M_DATA13 M_DATA12 M_A5 M_DATA11 M_DATA10 M_A4 M_DATA9 M_DATA8 M_A3 M_DATA7 M_DATA6 M_A2 M_DATA5 M_DATA4 M_A1 M_DATA3 M_DATA2 M_A0 M_DATA1 M_DATA0 PCI_CLK PCI_GNT# PCI_REQ# PCI_INTA# SATC_MISS# PCI_RESET# PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_CBE3# PCI_IDSEL Name PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_CBE2# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PAR PCI_CBE1# PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_CBE0# PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 Name ATC_MISS0# ATC_MISS1# ATC_MISS2# ATC_MISS3# ATC_MISS4# ATC_MISS5# ATC_MISS6# ATC_MISS7# MDIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7/µA_EN# µA_AD7 µA_AD6 µA_AD5 µA_AD4 µA_AD3 µA_AD2 µA_AD1 µA_AD0 RESERVED RESERVED RESERVED µA_RST µA_RD# µA_WR# µA_CS# µA_ALE TEST M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_WE1# M_DATA43 Name M_DATA42 M_WE0# M_DATA41 M_DATA40 M_OE# M_DATA39 M_DATA38 M_A17 M_DATA37 M_DATA36 M_A16 M_DATA35 M_DATA34 M_A15 M_DATA33 M_DATA32 M_A14 M_DATA31 M_DATA30 M_A13 M_DATA29 M_DATA28 M_A12 M_DATA27 M_DATA26 M_A11 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_A10 M_DATA21 M_DATA20 M_A9 M_DATA19 M_DATA18 M_A8 M_DATA17 M_DATA16 M_A7 M_DATA15 M_DATA14 M_A6
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I-Cube, Inc.
LS105 SATC Controller
LS105 [PQFP/208L Package] Pinout
M_DATA13 M_DATA12 M_A5 M_DATA11 M_DATA10 M_A4 M_DATA9 M_DATA8 M_A3 M_DATA7 M_DATA6 M_A2 M_DATA5 M_DATA4 M_A1 M_DATA3 M_DATA2 M_A0 M_DATA1 M_DATA0 PCI_CLK PCI_GNT# PCI_REQ# PCI_INTA# SATC MISS# PCI_RESET# PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_CBE3# PCI_IDSEL
M_A6 M_DATA14 M_DATA15 M_A7 M_DATA16 M_DATA17 M_A8 M_DATA18 M_DATA19 M_A9 M_DATA20 M_DATA21 M_A10 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_A11 M_DATA26 M_DATA27 M_A12 M_DATA28 M_DATA29 M_A13 M_DATA30 M_DATA31 M_A14 M_DATA32 M_DATA33 M_A15 M_DATA34 M_DATA35 M_A16 M_DATA36 M_DATA37 M_A17 M_DATA38 M_DATA39 M_OE# M_DATA40 M_DATA41 M_WE0# M_DATA42
View
M_DATA43 M_WE1# M_DATA44 M_DATA45 M_DATA46 M_DATA47 TEST µA_ALE µA_CS# µA_WR# µA_RD# µA_RST RESERVED RESERVED RESERVED µA_AD0 µA_AD1 µA_AD2 µA_AD3 µA_AD4 µA_AD5 µA_AD6 µA_AD7 GPIO7/µA_EN# GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 MDIO ATC_MISS7# ATC_MISS6# ATC_MISS5# ATC_MISS4# ATC_MISS3# ATC_MISS2# ATC_MISS1# ATC_MISS0#
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PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_CBE2# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PAR PCI_CBE1# PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_CBE0# PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
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LS105 SATC Controller
Component Availability Ordering Information
following table lists LS105 package options, operating temperature ranges that currently available. Contact I-Cube Marketing more up-to-date information.
Package Pins
Package Type PQFP
Package Code PQ208
Temperature Range
Commercial +70°
Table Component Availability
Package Code Plastic Quad Flat Pack Package Count Temperature Range Blank Commercial Industrial (-40
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I-Cube, Inc.
LS105 SATC Controller
SwitchSet trademark I-Cube Inc. other trademarks registered trademarks property their respective holders. I-Cube, Inc., does assume liability arising applications product described herein; does convey license under patents, copyright rights rights others. information contained this document believed current accurate publication date. I-Cube, Inc., reserves right make changes, time, order improve reliability, function, performance design supply best product possible. I-Cube, Inc., assumes obligation correct errors contained herein advise user this text correction such made. This product protected under U.S. patents: 5202593, 5282271. Additional patents pending. I-Cube, Inc., Copyright 1997. rights reserved.
I-Cube Inc.
2605 Winchester Blvd. Campbell, 95008,
Phone: (408) 341-1888 Fax: (408) 341-1899 eMail: marketing@icube.com Internet: http://www.icube.com
LS105 Data Sheet July 1998 [Advance v1.01] Document #D-11-023
I-Cube, Inc.
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SATC Controller 32-bit interface, interrupt lines support LS100s.

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