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8101 8101
Gigabit Ethernet Controller
99110
This document Logic document. reference SEEQ Technology should considered Logic.
Note: Check latest Data Sheet revision before starting designs. SEEQ Data Sheets Web, access SEEQ Home Page www.seeq.com Logic www.lsilogic.com
Features
Compatible Upgrade Seeq 8100 Combined Ethernet 8B10B Data Rate 1000 Mbps 64-Bit Interface External Gbps Bandwidth 10-Bit Interface External SerDes Chip 16-Bit Interface Internal Registers Management Counters Full RMON, SNMP, Ethernet Management Counter Support Independent Receive Transmit FIFO's with Programmable Watermarks Receive FIFO Size Bytes Transmit FIFO Size Bytes AutoNegotiation Algorithm Chip Full Duplex Only Flow Control IEEE 802.3x Automatic Generation Checking Automatic Packet Error Discarding Programmable Transmit Start Threshold Interrupt Capability Supports Fiber Short Haul Copper Media 3.3v Power Supply, Tolerant Inputs Meets applicable IEEE 802.3 802.3z Specifications 208L PQFP
Description
8101 Ethernet controller gigabit applications. 8101 integrates Media Access Control sublayer (MAC) Physical Coding Sublayer (PCS) fiber short haul copper media. 8101 improved version Seeq 8100. 8101 also compatible with 8100 with exception that 8101 powered from 3.3V supply voltage. inputs outputs 8101 tolerant. 8101 consists full duplex Ethernet MAC, receive/ transmit FIFO's, 32-bit System Interface, 8B10B encoder/ decoder, 10-bit Interface, 16-bit Register Interface. 8101 also contains necessary circuitry implement flow control algorithm defined IEEE 802.3x. Flow control messages sent automatically without host intervention. 8101 contains counters that completely satisfies management objectives RMON Statistics Group MIB, (RFC 1757), SNMP Interfaces Group (RFC 1213 1573), Ethernet-Like Group (RFC 1643) Ethernet (IEEE 802.3z Clause 30). 8101 contains hundred thirty internal 16-bit registers that accessed though Register Interface. These registers contain configuration inputs, status outputs, management counter results. 8101 ideal Ethernet controller Gigabit Ethernet switch ports, uplinks, backbones, adapter cards
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8101
Configuration
RXEOF RXSOF RXBE3 RXBE1 RXBE0 RXBE2 RXD10 RXD11 RXD12 RXD13 RXD14 RXD16 RXD17 RXD18 RXD19 RXD20 RXD21 RXD22 RXD23 RXD24 RXD25 RXD26 RXD27 RXD28 RXD15 RXD29 RXD30 RXD31 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD8 RXD0 RXD7 RXD9
RXEN RXOE RESERVED TEST RBC0 RBC1 LCK_REF EN_CDET EWRAP TCLK
TXD26 TXD25 TXD24
RXWM1 RXWM2 RXDC CLR_RXDC RXABORT SCLK
TXEN TXSOF TXEOF TXBE0 TXBE1 TXBE2 TXBE3
TXWM1
8100 (208 PQFP)
TXWM2 TXDC CLR_TXDC TXCRC TXD0 TXD1 TXD2 TXD3
8101 (208 PQFP)
TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12
TXD13 TXD14 TXD15 TXD16 TXD17 TXD18 TXD19 TXD20
TXD21 TXD22 TXD23
REGCS
REGD7
REGD15
RESERVED
FCNTRL
LINK REGA0
REGA1
REGA3
REGWR
TXD31
REGRD
REGD5
REGD4
REGA4 REGA5
REGA7
REGD12
REGD13
REGD14
REGD11
REGD10
RESET
TXD30
TXD29
TXD28
REGINT
REGCLK
REGD3
REGD2
REGD9
REGD8
REGD6
REGD1
REGA2
REGA6
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REGD0
TXD27
8101
Table Contents Description Block Diagram Functional Description
GENERAL ETHERNET FRAME FORMAT 3.2.1 General 3.2.2 Preamble 3.2.3 Destination Address 3.2.4 Source Address 3.2.5 Length/Type Field 3.2.6 Data 3.2.7 Frame Check Sequence 3.2.8 Interpacket SYSTEM INTERFACE 3.3.1 General 3.3.2 Data Format Order 3.3.3 Transmit Timing 3.3.4 Receive Timing 3.3.5 Width 3.3.6 System Interface Disable TRANSMIT 3.4.1 General 3.4.2 Preamble Generation 3.4.3 AutoPad 3.4.4 Generation 3.4.5 Interpacket 3.4.6 Control Frame Generation RECEIVE 3.5.1 General 3.5.2 Preamble Stripping 3.5.3 Stripping 3.5.4 Unicast Address Filter 3.5.5 Multicast Address Filter 3.5.6 Broadcast Address Filter 3.5.7 Reject Accept Packets 3.5.8 Frame Validity Checks 3.5.9 Maximum Packet Size 3.5.10 Control Frame Check TRANSMIT FIFO 3.6.1 General 3.6.2 AutoSend 3.6.3 Watermarks 3.6.4 Underflow 3.6.5 Overflow 3.6.6 Link Down FIFO Flush RECEIVE FIFO 3.6.1 General 3.6.2 Watermarks 3.6.3 Overflow 3.6.4 Underflow 8B10B 3.7.1 Transmit 3.7.2 Receive 3.7.3 8B10B Encoder 3.7.4 8B10B Decoder 3.7.5 Start Packet 3.7.6 Packet 3.7.7 Idle 3.7.8 Receive Word Synchronization 3.7.9 AutoNegotiation 10-BIT INTERFACE 3.8.1 General 3.8.2 Data Format Order 3.8.3 Transmit 3.8.4 Receive 3.8.5 Lock Reference 3.8.6 Loopback 3.8.7 Signal Detect 3.8.8 Disable PACKET DISCARD 3.9.1 General 3.9.2 Transmit Discards 3.9.3 Receive Discards 3.9.4 Discard Output Indication 3.9.5 AutoClear Mode 3.9.6 AutoAbort Mode 3.10 RECEIVE STATUS WORD 3.10.1 General 3.10.2 Format 3.10.3 Append Options 3.10.4 Status Word Discarded Packets 3.10.5 Status Word RXABORT Packets 3.11 AUTONEGOTIATION 3.11.1 General 3.11.2 Next Page 3.11.3 Negotiation Status 3.11.4 AutoNegotiation Restart 3.11.5 AutoNegotiation Disable 3.11.6 Link Indication 3.12 FLOW CONTROL 3.13 CONTROL FRAMES
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Table Contents (cont'd)
3.13.1 General 3.13.2 Automatic Pause Frame Generation 3.13.3 Transmitter Pause Disable 3.13.4 Passthrough FIFO 3.13.5 Reserved Multicast Address Disable 3.13.6 Control Frame AutoSend 3.14 RESET 3.15 COUNTERS 3.15.1 General 3.15.2 Counter Half Full 3.15.3 Counter Reset Read 3.15.4 Counter Rollover 3.15.5 Counter Maximum Packet Size 3.15.6 Counter Reset 3.16 LOOPBACK 3.17 TEST MODE 3.18 REGISTER INTERFACE 3.18.1 General 3.18.2 Types 3.18.3 Interrupt 3.18.4 Register Structure
Application Information
EXAMPLE SCHEMATICS INTERFACE 5.2.1 External Physical Layer Devices 5.2.2 Layout SYSTEM INTERFACE 5.3.1 Watermarks 5.3.2 Layout RESET LOOPBACK AUTONEGOTIATION 5.6.1 AutoNegotion Powerup 5.6.2 Negotiation with Non-AutoNegotiation Able Device MANAGEMENT COUNTERS 5.7.1 Relationship IETF IEEE Specs 5.7.2 Packet Octet Counters POWER SUPPLY DECOUPLING
Specifications
ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Registers
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8101
Description
Name VCC[22:0] Description Positive Supply. +3.3v +/-5% Volts. Power Supplies
GND[30:0]
Ground. Volts.
10-Bit Interface Transmit Clock Output. This 10-Bit Interface output clocks transmit data TX[0:9] rising edges. clock generated from TCLK. Transmit Data Output. These 10-Bit Interface outputs contain transmit data which clocked rising edges TBC.
TX[0:9]
RBC[1:0]
Receive Clock Input. These 10-Bit Interface inputs clock receive data RX[0:9] rising edges. RBC[1:0] 62.5 clocks, 180° phase, used clock data RX[0:9] effective rate. device acquire sync, comma code must input RXD[0:9] RBC1 rising edges. Receive Data Input. These 10-Bit Interface inputs contain receive data which clocked rising edges RBC[1:0].
RX[0:9]
EN_CDET
Comma Detect Enable Output. This 10-Bit Interface output asserted when either receive 8B10B state machine loss synchronization state EN_CDET internal Registers. This output typically used enable comma detect function external Physical Layer device.
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8101 DESCRIPTION (cont'd)
Name EWRAP Description Loopback Output Enable. This 10-Bit Interface output asserted whenever EWRAP internal Registers. This output typically used enable loopback external Physical Layer device. Receiver Lock Output. This 10-Bit Interface output asserted whenever LCK_REF internal Registers. This output typically used enable receive lock-to-reference mechanism external Physical Layer device. System Interface Clock Input. This input clocks data receive transmit FIFO's TXD[31:0] RXD[31:0], respectively. System Interface inputs outputs also clocked rising edges SCLK, with exception RXOE. SCLK clock frequency must between 33-66 MHZ. Transmit Enable Input. This input asserted active enable current data word TXD[31:0] clocked into transmit FIFO. TXEN clocked rising edges system interface clock, SCLK. Transmit Data Input. This input contains 32-bit data word that clocked into transmit FIFO rising edges system interface clock, SCLK.
LCK_REF
System Interface SCLK
TXEN
TXD[31:0]
TXBE[3:0]
Transmit Byte Enable Input. These inputs determine which bytes current 32-bit word TXD[31:0] contain valid data. TXBE[3:0] clocked into device rising edges system interface clock, SCLK. Transmit Start Frame Indication. This input asserted active high same clock cycle when first word packet being clocked TXD[31:0]. TXSOF clocked into device rising edges system interface clock, SCLK. Transmit Frame Indication. This input asserted active high same clock cycle when last word packet being clocked TXD[31:0]. TXEOF clocked into device rising edges system interface clock, SCLK. Transmit FIFO Watermark Output. Transmit FIFO Data Transmit FIFO Watermark Threshold Above Threshold TXWM1 clocked rising edges system clock, SCLK.
TXSOF
TXEOF
TXWM1
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8101 DESCRIPTION (cont'd)
Name TXWM2 Description Transmit FIFO Watermark Output. Transmit FIFO Data Transmit FIFO Watermark Threshold Above Threshold TXWM2 clocked rising edges system clock, SCLK TXDC Transmit Packet Discard Output. Device Detects that Current Packet Being Input System Interface Error, Rest Packet Ignored. Discard TXDC clocked rising edges system clock, SCLK. Autoclear Mode enabled, this output latched high stays latched until cleared with CLR_TXDC pin. Autoclear Mode enabled, this output latched high automatically clears itself clock cycles after next TXEOF occurrence. CLR_TXDC Clear TXDC Input. TXDC Cleared Cleared TXDC clocked rising edges system clock, SCLK. This only clears TXDC when Autoclear Mode disabled. When Autoclear Mode enabled, this ignored TXDC automatically cleared clock cycles after next TXEOF occurrence. FCNTRL Flow Control Enable Input. Transmitter Automatically Transmit Control Pause Frame Normal Operation FCNTRL clocked rising edges system clock, SCLK. TXCRC Transmit Enable Input. Calculated Appended Current Packet Being Inputted System Interface TXCRC clocked rising edges system clock, SCLK, must asserted same SCLK clock cycle TXSOF. RXEN Receive Enable Input. This input asserted active enable current data word clocked receive FIFO RXD[31:0]. RXEN clocked rising edges system interface clock, SCLK. Receive Output Enable Input. Receive Outputs High Impedance (RXD[31:0], RXBE[3:0], RXSOF, RXEOF) Receive Outputs Active
RXOE
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8101 DESCRIPTION (cont'd)
Name RXD[31:0] Description Receive Data Input. This output contains 32-bit data word that clocked receive FIFO rising edges system interface clock, SCLK.
RXBE[3:0]
Receive Byte Enable Output. These outputs determine which bytes current 32-bit word RXD[31:0] contain valid data. RXBE[3:0] clocked device rising edges system interface clock, SCLK. Receive Start Frame Indication. This output asserted active high same clock cycle when first word packet being read receive FIFO RXD[31:0]. RXSOF clocked device rising edges system interface clock, SCLK. Receive Frame Indication. This output asserted active high same clock cycle when last word packet being read receive FIFO RXD[31:0]. RXEOF clocked device rising edges system interface clock, SCLK. Receive FIFO Watermark Output. Receive FIFO Data Receive FIFO Watermark Threshold Equal Below Threshold RXWM1 clocked rising edges system clock, SCLK. Data valid RXD[31:0] when either RXWM1 RXWM2 asserted high, independent RXEN.
RXSOF
RXEOF
RXWM1
RXWM2
Receive FIFO Watermark Output. Receive FIFO Receive FIFO Watermark Threshold Complete Packet Loaded Into Receive FIFO Equal Below Threshold FIFO RXWM2 clocked rising edges system clock, SCLK. Data valid RXD[31:0] when either RXWM1 RXWM2 asserted high, independent RXEN.
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DESCRIPTION (cont'd)
Name RXDC Description Receive Packet Discard Output. Device Detects that Current Packet Being Output System Interface Error Should Discarded. Discard Packet being output System Interface discarded asserting RXABORT automatically discarded AUTORXAB set. RXDC clocked rising edges system clock, SCLK. Autoclear Mode enabled, this output latched high stays latched until cleared with CLR_RXDC pin. Autoclear Mode enabled, this output latched high automatically clears itself clock cycles after next RXEOF occurrence. RXDC also cleared with RXABORT programmed CLR_RXDC Clear RXDC Input. RXDC Cleared Cleared CLR_RXDC clocked rising edges system clock, SCLK. This only clears RXDC when Autoclear Mode disabled. When Autoclear Mode enabled, this ignored RXDC automatically cleared clock cycles after next RXEOF occurrence. RXABORT Receive FIFO Data Abort Input. Abort Discard Receive Packet Being Read RXD[31:0] Discard RXABORT clocked rising edges system clock, SCLK. Register Interface REGCS Register Interface Chip Select Input. This input asserted active enable reading writing data REGD[15:0] REGA[7:0]. This input clocked rising edges REGCLK. Register Interface Clock Input. This input clocks data REGD[15:0], REGA[7:0], REGRD, REGWR rising edges. REGCLK frequency must between 5-40 MHz. Register Interface Data Bus. This bidirectional 16-bit data path from internal registers. Data read/written from/to internal registers rising edges register clock, REGCLK.
REGCLK
REGD[15:0]
REGA[7:0]
Register Interface Address Input. These inputs provide address specific internal register accessed. These inputs clocked into device rising edges REGCLK. Register Interface Read Input. When this input asserted active low, accessed internal register read out, i.e. data outputted from register. This input clocked into device rising edges REGCLK.
REGRD
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8101 DESCRIPTION (cont'd)
Name REGWR Description Register Interface Write Input. When this input asserted active low, accessed internal register written i.e. data inputted register. This input clocked into device rising edges REGCLK. Register Interface Interrupt Output. This output asserted active high when certain interrupt bits registers set, remains latched high until interrupt bits read cleared. Transmit Clock Input. This input clock used 8B10B Section generates transmit output clock, TBC, used output data 10-Bit Interface. Receive Link Output. Link Receive Link Synchronized Configured.
REGINT
Miscellaneous TCLK
LINK
Signal Detect Input Data Detected Receive 10-Bit Interface Valid Data Valid, 8B10B Receiver Forced Loss Sync State This ignored (assumed high) unless enabled setting enable Configuration Register.
RESET
Reset Input. Normal Device Reset, FIFO's Cleared, Counters Cleared, Register Bits Defaults
Tristate Input. This used testing purposes only. Output Bidirectional Pins Placed High Impedance State Normal Operation
TEST RESERVED
Test Mode Input. This reserved factory test must tied proper operation. Reserved. These pins reserved must left floating.
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RESET TCLK 8B10B
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TRANSMIT FIFO PACKET GENERATOR TRANSMIT 8B10B ENCODER TX[9:0] GENERATOR CONTROL FRAME GEN. EWRAP LCK_REF TRANSMIT RECEIVE TRANSMIT RECEIVE 10-BIT INTERFACE CONTROL FRAME CHECK LINK CONFIGURATION ADDRESS FILTER EN_CDET CHECK RECEIVE SYNC. RECEIVE FIFO PACKET DECOMPOSE 8B10B DECODER RECEIVE RX[0:9] RBC[1:0] MANAGEMENT COUNTERS LINK
SCLK
TXEN
TXD[31:0]
TXBE[3:0]
Block Diagram
TXSOF
TXEOF
TXWM1
TXWM2
SYSTEM INTERFACE
TXDC
CLR_TXDC
TXCRC
FCNTRL
RXEN
RXD[31:0]
RXBE[3:0]
RXSOF
RXEOF
8101 Block Diagram
RXWM1
RXWM2
RXDC
CLR_RXDC
RXABORT
RXOE
REGCLK
REGCS
REGD[15:0]
REGAD[7:0]
REGRD
REGISTER INTERFACE REGISTERS
REGWR
REGINT
8101
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8101
Functional Description
GENERAL 8101 complete Media Access Controller (MAC sublayer) with integrated coding logic fiber short haul copper media (8B10B sublayer) 1000 Mbps Gigabit Ethernet systems. 8101 main sections: System Interface, FIFO's, MAC, 8B10B PCS, 10-Bit Interface, Register Interface. block diagram shown Figure 8101 transmit data path receive data path. transmit data path goes System Interface 10-Bit Interface, shown half Figure receive data path goes 10-Bit Interface System Interface, shown bottom half Figure transmit data path, data input into System Interface from external bus. data then sent transmit FIFO. transmit FIFO provides temporary storage data until sent transmit section. transmit takes data formats into Ethernet packet IEEE 802.3 specifications shown Figure Ethernet packet then goes 8B10B section. 8B10B section encodes data adds appropriate framing delimiters create 10-Bit frame specified IEEE 802.3z shown Figure encoded data then goes 10-Bit Interface transmission external chip. transmit side also generates Control frames includes logic AutoNegotiation. receive data path, 10-Bit Interface receives incoming encoded data from external chip. incoming encoded data must encoded 10-Bit format specified IEEE 802.3z shown Figure incoming encoded data then sent receive 8B10B block which strips framing delimiters, decodes data, converts encoded data into
FRAME FORMAT BYTES BYTES PREAMBLE START FRAME DELIMITER (SFD) DESTINATION ADDRESS (DA) SOURCE ADDRESS (SA) LENGHT/TYPE (L/T) DATA
BYTES
BELOW
BYTES BYTES 1500 BYTES
BITS WITHIN FRAME TRANSMITTED BOTTOM
BYTES
FRAME CHECK SEQUENCE (FCS)
BITS WITHIN FRAME TRANSMITTED LEFT RIGHT
ADDRESS FIELD FORMAT ADDRESS BITS REGISTERS
MULTICAST BROADCAST UNICAST
BROADCAST MULTICAST
Figure Ethernet Frame Format
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Ethernet packet IEEE 802.3 specifications shown Figure Ethernet packet data then sent receive section. receive section decomposes packet, checks validity packet against certain error criteria address filters, checks Control frames. receive then sends valid packets receive FIFO. receive FIFO provides temporary storage data until demanded System Interface. System Interface outputs data external bus. Register Interface separate bidirectional 16-bit data through which configuration inputs set, status outputs read, management counters accessed from internal registers. Each block plus operating modes described more detail following sections.
broadcast, remaining 46-bits actual address bits, shown Figure 3.2.4 Source Address source address 48-bit field containing specific station address from which frame originated. format address field same defined IEEE 802.3 shown Figure 3.2.5 Length/Type Field 16-bit length/type field takes meaning either packet length packet type, depending numeric value, described Table
Table Length/Type Field Definition Length/Type Field Value (Decimal) 0-1500 Length Type Length Definition
ETHERNET FRAME FORMAT 3.2.1 General Information Ethernet network transmitted received packets frames. basic function 8101 process Ethernet frames. Ethernet frame defined IEEE 802.3 consists preamble, start frame delimiter (SFD), destination address (DA), source address (SA) length/type field (L/T), data, frame check sequence (FCS), interpacket (IPG). format Ethernet frame shown Figure Ethernet frame specified IEEE 802.3 have minimum length bytes maximum length 1518 bytes, exclusive preamble SFD. Packets which less than bytes greater than 1518 bytes referred undersize oversize packets, respectively. 3.2.2 Preamble preamble combined 64-bit field consisting alternating followed preamble indicator. first 56-bits considered preamble, last 8-bits 10101011 considered (Start Frame Delimiter). 3.2.3 Destination Address destination address 48-bit field containing address station(s) which frame directed. format address field same defined IEEE 802.3 shown Figure destination address either unicast address specific station, multicast address group stations, broadcast address stations. first second bits determine whether address unicast, multicast
Total Number Bytes Data Field minus padding Undefined Frame Type
1501-1517 1518
Neither Type
3.2.6 Data data 46-1500 byte field containing actual data transmitted between stations. actual data less than bytes, extra added increase data field byte minimum size. Adding these extra referred padding. 3.2.7 Frame Check Sequence frame check sequence (FCS), 32-bit cyclic redundancy check (CRC) value computed entire frame, exclusive preamble SFD. algorithm defined IEEE 802.3. appended frame used determine frame validity. 3.2.8 Interpacket interpacket (IPG) time interval between packets. minimum value defined bits, where Gigabit Ethernet. There maximum limit.
SYSTEM INTERFACE 3.3.1 General System Interface 64-bit wide data interface consisting separate 32-bit data transmit separate 32-bit data receive.
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3.3.2 Data Format Order format data word TXD[31:0] RXD[31:0] relationship frame format 10-Bit Interface format shown Figure Note that device programmed append additional 32-bit status word receive packet; refer Receive Status Word section more details this status word. byte ordering data bits programmable setting endian select Configuration register. byte order shown Figure with little endian format mode (default). device placed endian format, then byte order shown Figure reversed, i.e. DA[0:7] occurs pins RXD[24:31], DA[24:31] occurs pins RXD[0:7], etc. bytes frame affected endian select bit, including receive status word appended. difference between little endian endian format illustrated Figure 3.3.3 Transmit Timing transmit portion System Interface consists signals: transmit data input bits (TXD[31:0]), transmit enable (TXEN), four transmit byte enable inputs (TXBE[3:0]), transmit start frame frame inputs (TXSOF TXEOF), transmit FIFO watermark outputs (TXWM1 TXWM2), transmit discard output (TXDC), transmit discard clear input (CLR_TXDC), transmit enable input (TXCRC), flow control enable input (FCNTRL). receive transmit data clocked in/out rising edges system clock, SCLK. SCLK must operate between 33-66 MHZ. SCLK input needs continuously input device 33-66 MHz. When TXEN deasserted, transmit interface selected subsequently, input data accepted device from transmit System Interface inputs. When TXEN asserted, data word TXD[31:0] input clocked into transmit FIFO each rising edge SCLK clock input. Multiple packets clocked TXEN assertion. TXD[31:0] input data 32-bit wide packet data whose format relationship packet 10-Bit data described Figure transmit byte enable inputs, TXBE[3:0], determine which bytes 32-bit TXD[31:0] data word contain valid data. TXBE[3:0] clocked rising edges SCLK along with each TXD[31:0] data word. correspondence between byte enable inputs valid bytes each data word TXD[31:0] defined Table logic combination TXBE[3:0] inputs allowed, with exception that TXBE[3:0] must 0000 SCLK cycle when TXSOF TXEOF asserted.
Table Byte Enable Valid Byte Position TXBE/RXBE Pins TXBE3/RXBE3 TXBE2/RXBE2 TXBE1/RXBE1 TXBE0/RXBE0 Valid Bytes TXD/RXD Pins TXD[31:24]/RXD[31:24] TXD[23:16]/RXD[23:16] TXD[15:8]/RXD[15:8] TXD[7:0]/RXD[7:0]
transmit start frame frame inputs, TXSOF TXEOF, indicate device which data words start Ethernet data packet, respectively. These signals input same SCLK rising edge first last word data packet. transmit watermark outputs, TXWM1 TXWM2, indicate when transmit FIFO exceeded programmable watermark thresholds. watermarks will asserted deasserted device rising edges SCLK, depending fullness transmit FIFO. Refer transmit FIFO section more details these watermarks. TXDC transmit packet discard output. TXDC asserted every time transmission packet being input System Interface halted packet discarded some error. This signal latched active high cleared either asserting clearing signal, CLR_TXDC, cleared automatically device placed AutoClear mode. Packet Discard section more details discards TXDC. TXCRC input which enable internal generation appending byte value onto data packet. TXCRC sampled rising edges SCLK asserted beginning packet, coincident with TXSOF, cause removal addition that packet. generation also enabled setting transmit enable Configuration register. interaction between TXCRC enable defined Table FCNTRL input which will cause automatic generation transmission Control Pause frame. FCNTRL input rising edges SCLK. Control Frame section more details about this feature.
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10BIT INTERFACE /I2/ /I2/ 10101010 10101010 10101010 10101010 10101010 10101010 10101010 10101011 [0:7] [8:15] [16:23] [24:31] [32:39] [40:47] [0:7] [8:15] [16:23] [24:31] [32:39] [40:47] [0:7] [8:15] DATA [0:7] DATA [8:15] DATA [16:23] DATA [24:31] [31:24] [23:16] [15:8] [7:0] D21.2 D21.2 D21.2 D21.2 D21.2 D21.2 D21.6 [0:7]> [8:15]> [16:23]> [24:31]> [32:39]> [40:47]> [0:7]> [8:15]> [16:23]> [24:31]> [32:39]> [40:47]> [0:7]> [8:15]> <DATA [0:7]> <DATA [8:15]> <DATA [16:23]> <DATA [24:31]> <FCS [31:24]> <FCS [23:16]> <FCS [15:8]> <FCS [7:0]> Note Second added only Transmit Packet ends Bytes Note Preamble Appended Preamble Stripped Note Appended Stripped Note Means Encoded Note /I1/ /I2/ Depends Running Disparity /I1/ /I2/ /I2/ /I2/
SYSTEM INTERFACE
TXD31 RXD31 [8:15] [40:47] [24:31] [8:16] DATA [24:31] [16:23] [0:7] [32:39] DATA [0:7] [24:31] [8:15] [40:47] DATA [7:15]
TXDO RXDO [0:7] [32:39] [16:23] [0:7] DATA [16:23]
[31:24] STATUS WORD
[23:16]
[15:8]
[7:0]
INVALID DATA
NOTES Note Status Word only Progammable Note Position Programmable Note Little Endian Format (Default)
ABCDEFGH
abcdefghij
BYTES TRANSMITTED
BITS TRANSMITTED
Figure Frame Formats Ordering
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10-BIT INTERFACE
8101
3.3.4 Receive Timing receive portion System Interface consists signals: receive output data bits (RXD[31:0]), receive enable input (RXEN), four receive byte enable outputs (RXBE[3:0]), receive start frame frame outputs (RXSOF RXEOF), receive FIFO watermark outputs (RXWM1 RXWM2), receive discard output (RXDC), receive discard clear input (CLR_RXDC), receive packet abort input (RXABORT),and receive output enable (RXOE). receive transmit data clocked in/out with system clock, SCLK. SCLK must operate between 33-66 MHz. SCLK input needs continuously input 33-66 Mhz. When RXEN deasserted, receive interface selected subsequently, data from receive FIFO output over System Interface. receive watermarks asserted while RXEN deasserted, next data word from receive FIFO appears RXD[31:0] outputs stays there until RXEN asserted. When RXEN asserted, data word from receive FIFO clocked onto RXD[31:0] outputs after each rising edge SCLK input. Once entire packet been clocked out, then more data clocked RXD[31:0] until RXEN deasserted reasserted, thus allowing extra dribble SCLK clock cycles occur after packet. RXD[31:0] output data 32-bit wide packet data whose format relationship packet 10-Bit data described Figure receive byte enable outputs, RXBE[3:0], determine which bytes 32-bit RXD[31:0] data word contain valid data. RXBE[3:0] clocked rising edges SCLK along with each RXD[31:0] data word. Note that RXBE[3:0]=1111 words packet except last word; last word packet four byte boundaries 32-bit data word. correspondence between byte enable inputs valid data bytes each data word RXD[31:0] defined Table receive start frame frame outputs, RXSOF RXEOF, indicate which words start Ethernet data packet, respectively. These signals generally clocked same SCLK rising edge first last word data packet, respectively. However their exact position relative data packet dependent programming position status word option bits Configuration register. exact RXSOF RXEOF position combinations these bits depicted Figure More details about definition these bits found Configuration Register Definition, more details about status word found Receive Status Word section. receive watermarks, RXWM1 RXWM2, indicate when receive FIFO exceeded programmable watermark thresholds. watermarks will asserted deasserted rising edges SCLK, depending fullness receive FIFO. Refer Receive FIFO section more details these watermarks. RXDC receive packet discard output. RXDC asserted every time reception packet being output over System Interface halted packet discarded some error. This signal latched active high cleared either asserting clearing signal, CLR_RXDC, cleared automatically device placed AutoClear mode. Packet Discard section more details discards RXDC. RXABORT input, when asserted, will discard current packet being output System Interface. When packet discarded asserting RXABORT, remaining contents that packet receive FIFO flushed. process flushing receive packet from receive FIFO with RXABORT requires extra SCLK cycles equal (packet length bytes)/8 Refer
LITTLE ENDIAN (DEFAULT)
TXD0 TXD7 RXD0 RXD7
TXD8 TXD15 RXD8 RXD15
TXD16 TXD23 RXD16 RXD23
TXD24 TXD31 RXD24 RXD31
TXD0 TXD7 RXD0 RXD7
TXD8 TXD15 RXD8. RXD15
TXD16 RXD16
PREAMBLE
DA15
DA16 DA23
DA24 DA31
DA32 DA39
DA40 DA47
SOURCE ADDRESS
ENDIAN
TXD24 TXD31 RXD24 RXD31
TXD16 TXD23 RXD16 RXD23
TXD8 TXD15 RXD8 RXD15
TXD0 TXD7 RXD0 RXD7
TXD24 TXD31 RXD24 RXD31
TXD16 TXD23 RXD16. RXD23
TXD15 RXD15
Figure Little Endian Endian Format
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Packet Discard section more information about discarded packets. device programmed ignore RXABORT clearing discard RXABORT enable Configuration register. device also programmed discard either data packet status word just data packet itself exclusive status word setting RXABORT definition Configuration register. RXOE output enable input which, when asserted, will place certain receive outputs high impedance state. output pins affected RXOE RXD[31:0], RXBE[3:0], RXSOF, RXEOF. 3.3.5 Width receive word width changed from 32-bits 16bits appropriately setting word width select Configuration register. When width configured 16-bits, receive System Interface data outputs appear RXD[15:0] data words 16-bits wide instead 32-bits wide. Note that transmit word width adjusted appropriately setting transmit byte enable inputs, TXBE[3:0], described Table 3.3.6 System Interface Disable system interface disabled setting system interface disable Configuration register. When System Interface disabled, device
places System Interface outputs high impedance state (i.e. TXWM1/2, TXDC, RXD, RXBE, RXSOF, RXEOF, RXWM1/2, RXDC), ignores inputs (i.e. SCLK, TXEN, TXD, TXBE, TXSOF, TXEOF, CLR_TXDC, FCNTRL, TXCRC, RXEN, RXOE, CLR_RXDC, RXABORT), transmits ordered sets with remote fault bits RF[1:0]=10 over 10-Bit Interface outputs. TRANSMIT 3.4.1 General transmit (Media Access Control) section generates Ethernet frame from transmit FIFO data generating preamble SFD, padding undersize packet with meet minimum packet size requirements, calculating appending value, maintaining minimum interpacket between packets. Each above four operations individually disabled altered, desired. transmit then sends fully formed Ethernet packet 8B10B block encoding. transmit section also generates Control frames. 3.4.2 Preamble Generation transmit normally appends preamble packet. device programmed append preamble transmit packet clearing transmit preamble enable Configuration register.
FIFO DATA
RXSOF/RXEOF POSITION BITS (STSWRD [1:0], PEOF)
FIRST DATA WORD
PACKET DATA
LAST DATA WORD STATUS WORD DISCARD STATUS WORD
SOF,
SOF,
NOTE STATUS WORDS EXIST WITH THIS COMBINATION
Figure RXSOF/RXEOF Position
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3.4.3 AutoPad transmit normally AutoPad's packets. AutoPadding process automatically adding enough zeroes packets with data fields less than bytes make data field exactly bytes length meet byte minimum data field requirement IEEE 802.3. device programmed AutoPad clearing AutoPad Configuration register. 3.4.4 Generation transmit normally appends value packet. device programmed append value packet from transmit FIFO asserting TXCRC appropriately setting transmit enable Configuration register, described Table
Table TXCRC TXCRC Logic TXCRC
Append Append
3.4.6 Control Frame Generation transmit automatically generate transmit Control Pause frames. Control Pause frames used flow control. This function described more detail Control Frame section.
RECEIVE 3.5.1 General receive (Media Access Control) section decomposes Ethernet packets received from receive 8B10B section stripping preamble SFD, stripping CRC, checking destination address against address filters determine packet validity, checking frame validity against discard conditions, checking length/type field Control frames. Each above five operations individually disabled altered, desired. receive then sends valid packets receive FIFO storage. 3.5.2 Preamble Stripping transmit normally strips preamble from receive packet. device programmed strip preamble setting receive preamble enable Configuration register. When this set, preamble left receive packet stored receive FIFO part packet. 3.5.3 Stripping receive normally strips from receive packet. device programmed strip field setting receive enable Configuration register. When this set, last 4bytes packet containing value left receive packet stored receive FIFO part packet. 3.5.4 Unicast Address Filter Unicast packets filtered comparing destination address receive packet against 48-bit value stored three Address registers. When destination address unicast packet matches value stored this register, unicast packet deemed valid passed receive FIFO; otherwise, packet rejected. correspondence between bits Address register incoming bits destination address receive packet defined Address register definition table. device programmed always reject unicast packets setting reject unicast packet Configuration register. When this set, unicast packets rejected regardless their address.
TXCRC
Append Append
Appended Packet?
3.4.5 Interpacket packets from transmit FIFO arrive transmit sooner than minimum interpacket time (referred IPG), transmit will enough time between packets equal minimum value. default time bits bit=1ns), programmed other values appropriately setting transmit select bits Configuration register also summarized Table
Table Transmit Selection Select Bits 7.[9:7] (Bits) IEEE Spec IEEE Spec IEEE Spec Comments IEEE Spec
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reception Control frames unaffected unicast packet address filtering functions controlled other bits described Control Frame section. 3.5.5 Multicast Address Filter Multicast packets filtered processing destination address with multicast address filter function. multicast address filter function computes incoming produces 6-bit number that compared against values stored Address Filter registers. When multicast packet destination address passes address filter, packet deemed valid passed receive FIFO; otherwise, packet rejected. multicast address filter requires address filter bits written into Address Filter registers. multicast address filtering algorithm follows: Compute separate 32-bit destina tion address field using same IEEE 802.3 defined method that computes transmit CRC. bits destination address select bytes 64-bit address filter, shown Table bits destination address select bits within byte selected shown Table selected "1", destination address passes filter; otherwise, address fails filter packet rejected discarded. Note that 64-bits address filter programmed 1's, then address filter passes multicast addresses. device programmed reject multicast packets setting reject multicast packet Configuration register. When this set, multicast packets rejected regardless their address. reception Control frames unaffected multicast packet address filtering functions controlled other bits described Control Frame section
Table Multicast Address Filter Bits [0:2] Address Filter Byte F0[7:0] F1[7:0] F2[7:0] F3[7:0] F4[7:0] F5[7:0] F6[7:0] F7[7:0] Bits [3:5] Address Filter Fx[0] Fx[1] Fx[2] Fx[3] Fx[4] Fx[5] Fx[6] Fx[7]
F[7:0] bytes Address Filter Registers. Fx[7:0] bits within each byte Address Filter Registers. Bits least significant bits CRC.
3.5.6 Broadcast Address Filter device does filtering broadcast packets. However, device programmed reject broadcast packets setting reject broadcast packet Configuration register. When this set, broadcast packets rejected regardless their address. reception Control frames unaffected broadcast packet address filtering functions controlled other bits described Control Frame section 3.5.7 Reject Accept Packets device programmed accept reject packets regardless type whether packet passes address filter setting accept packet reject packet bits, respectively, Configuration register. reception Control frames unaffected these bits controlled other bits described Control Frame section. 3.5.8 Frame Validity Checks receive determines validity each receive packet checking valid FCS, oversize packet, undersize packet.
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Valid determined computing value incoming receive packet IEEE 802.3 specifications comparing against actual value field received packet. values same, frame determined invalid packet discarded. Refer Packet Discard section more information about discards. device programmed discard packet with clearing discard error Configuration register. Oversize packets packets whose length greater than maximum packet size. received packet oversize packet, then packet determined invalid discarded. Refer Packet Discard section more information about discards. maximum packet size programmed either 1518 bytes, 1522 bytes, 1535 bytes, exclusive preamble SFD, appropriately setting maximum packet size Configuration register. device programmed discard oversize packet thus allow packets unlimited length clearing discard oversize packet Configuration register. Undersize packets packets whose length less than minimum packet size. Minimum packet size defined bytes, exclusive preamble SFD. received packet undersize packet, then frame determined invalid discarded. Refer Packet Discard section more information about discards. device programmed discard undersize packet clearing discard oversize packet Configuration register. 3.5.9 Maximum Packet Size maximum packet size used receive frame validity checking programmed four values appropriately setting receive maximum packet size select bits Configuration register discard oversize packet enable Configuration register shown Table This selection also described register descriptions those registers. bits shown Table affect receive section only; maximum packet size management counters determined other bits described Counters section.
Table Receive Maximum Packet Size Selection Receive Packet Size Select Bits Discard Oversize Packet, Packet Size Select, Bits 9.[5:4] Packet Size (bytes)
unlimited 1535 1522 1518
3.5.10 Control Frame Check length/type field checked detect whether packet valid Control frame. Refer Control Frame section more details Control frames.
TRANSMIT FIFO 3.6.1 General transmit FIFO acts temporary buffer between System Interface transmit section. transmit FIFO size bytes. Data clocked into transmit FIFO with 33-66 System Interface clock, SCLK. Data automatically clocked transmit FIFO with 8B10B clock whenever full packet been loaded into FIFO (evidenced being written into FIFO System Interface), FIFO data exceeds transmit FIFO AutoSend threshold. There programmable watermark outputs, TXWM1 TXWM2, which managing data flow into transmit FIFO. 3.6.2 AutoSend AutoSend feature causes packet transmit FIFO automatically transmitted once transmit FIFO data exceeds certain threshold. transmit AutoSend threshold programmable over lower byte transmit FIFO. AutoSend threshold programmed with transmit
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AutoSend threshold bits that reside Transmit FIFO Threshold register. Once data FIFO exceeds this threshold, then packet automatically transmitted 8B10B section 10-Bit Interface. packet will also automatically transmitted written into transmit FIFO that packet, regardless autosend threshold setting. settings transmit autosend threshold evenly distributed over lower transmit FIFO range, except 000000 setting. 000000 setting automatically starts transmission when transmit FIFO full, thus facilitating transmission oversize packets. Refer Transmit FIFO Threshold Register description more details autosend settings. 3.6.3 Watermarks There transmit watermarks transmit FIFO. These watermarks output TXWM1 TXWM2 pins. These watermarks asserted when transmit FIFO data exceeds thresholds associated with watermarks. transmit watermark thresholds TXWM1 TXWM2 programmed over entire FIFO range. Each watermark thresholds independently programmed with five bits that reside Transmit FIFO Threshold register. Once data FIFO exceeds threshold either watermark, then respective watermark either TXWM1 TXWM2 asserted active low. watermarks stay asserted until data FIFO goes below respective thresholds. 3.6.4 Underflow transmit FIFO underflow condition occurs when FIFO empty still requesting data complete transmission packet. transmit FIFO underflows, then packet transmission 8B10B halted, code appended partially transmitted packet, data partially transmitted packet discarded. Refer Packet Discard section more information about discards. 3.6.5 Overflow transmit FIFO overflow condition occurs when FIFO full additional data still being written into from System Interface. transmit FIFO overflows, then input FIFO blocked will accept more data from System Interface until FIFO space freed data already stored FIFO partially loaded last packet transmitted with code appended packet indicate error, data partially loaded last
packet discarded. Refer Packet Discard section more information about discards. 3.6.6 Link Down FIFO Flush When link down (also referred Link Fail defined either receiver lost sync AutoNegotiation process completed), transmitter 10-Bit Interface occupied with sending either idle AutoNegotiation codes (/I/ /C/). result, data cannot exit transmit FIFO transmit section. data continues input transmit FIFO from System Interface while device Link Fail, transmit FIFO overflow. Enabling link down FIFO flush feature will cause data exiting transmit FIFO automatically discarded when device Link Fail, thus preventing possible overflow transmit FIFO. link down FIFO flush mode enabled setting link down FIFO flush Configuration register. RECEIVE FIFO 3.6.1 General receive FIFO acts temporary buffer between receive section System Interface. receive FIFO size bytes. Data clocked into receive FIFO with 8B10B clock. Data clocked receive FIFO with 33-66 System Interface clock, SCLK. There programmable watermark outputs, RXWM1 RXWM2, which managing data flow receive FIFO. 3.6.2 Watermarks There watermarks receive FIFO. These watermarks output RXWM1 RXWM2 pins. These watermarks asserted when receive FIFO data exceeds thresholds associated with watermarks. receive watermark thresholds RXWM1 RXWM2 programmed over entire byte receive FIFO range. Each watermark thresholds independently programmed with eight bits that reside Receive FIFO Threshold register. Once data FIFO exceeds threshold either watermark, then respective watermark either RXWM1 RXWM2 asserted active high. RXWM2 also asserted complete packet loaded into receive FIFO from 8B10B section. watermarks stay asserted until data FIFO goes below respective thresholds RXWM2 will also stay asserted until packets (EOF) have been read receive FIFO. Once EOFs been read receive FIFO, watermarks cannot active again until RXEN deasserted.
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3.6.3 Overflow receive FIFO overflow condition occurs when receive FIFO full additional data still being written into from MAC. receive FIFO overflows, then input FIFO blocked will accept more data from 8B10B until FIFO space freed data already stored FIFO partially loaded last packet normally discard, data partially loaded last packet also normally discarded. Refer Packet Discard section more information about discards. device programmed discard packet corrupted overflow clearing discard overflow packet Configuration register. 3.6.4 Underflow receive FIFO underflow condition occurs when FIFO empty data still being attempted read FIFO over System Interface. FIFO underflows, then data read FIFO while underflow condition persists invalid, data partially loaded last packet will stored FIFO will discarded. 8B10B 3.7.1 Transmit transmit 8B10B section accepts Ethernet formatted packet data from transmit encodes data with 8B10B encoder, adds start packet delimiter, adds packet delimiter, adds idle code stream, formats packet according format defined IEEE 802.3z shown Figure 8B10B encoded data stream then sent transmit 10-bit Interface transmission. transmit 8B10B section also generates AutoNegotiation code stream when device AutoNegotiation process. 3.7.2 Receive receive 8B10B section takes 8B10B encoded packet data from incoming 10-Bit Interface acquires maintains word synchronization, strips start packet delimiter, strips packet delimiter, strips idle code stream, decodes data with 8B10B decoder, converts packet Ethernet packet format shown Figure Ethernet packet then sent receive processing. receive 8B10B section also decodes AutoNegotiation code stream when device AutoNegotiation process.
3.7.3 8B10B Encoder 8B10B encoder converts each data byte packet into unique 10-bit word defined IEEE 802.3z shown Table abbreviated form). encoder also converts start packet delimiter, packet delimiter, idle code streams, AutoNegotiation code streams into unique code words. These unique code words referred ordered sets. Table describes ordered sets defined used IEEE 802.3z. 8B10B encoder also keeps running disparity outgoing word close possible Running disparity difference between number transmitted outgoing stream. algorithm calculating running disparity defined 802.3z. After each word transmitted, running disparity recalculated. current running disparity negative, then next word chosen from "Current RD-" column Table abbreviated form). current running disparity positive, then next word chosen from "Current RD+" column Table
Table 8B10B Coding Table
Bytes Data Bits Byte HGFEDCBA Name D0.0 D1.0 D2.0 D3.0 00000 00001 00010 00011 Codes CurrentRDabcdei fghj 100111 0100 011101 0100 101101 0100 110001 1011 CurrentRD+ abcdei fghj 011000 1011 100010 1011 010010 1011 110001 0100
D28.7 D29.7 D30.7 D31.7
11100 11101 11110 11111
001110 1110 101110 0001 011110 0001 101011 0001
001110 0001 010001 1110 100001 1110 010100 1110
3.7.4 8B10B Decoder 8B10B decoder performs reverse process that described above 8B10B Encoder section. 8B10B decoder converts each 10-bit word back into 8bit byte using code conversion tables defined IEEE 802.3z shown Table abbreviated form) Table 8B10B decoder also checks running disparity incoming word insure that correct.
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8B10B decoder detects word that valid (not Table detects ordered that valid (not Table detects error running disparity, then codeword error results. Packets with codeword errors normally discarded. Refer Packet Discard section more details discards. device programmed discard packets with codeword errors clearing discard codeword enable Configuration register.
Table Defined Ordered Sets Code Sym. /C1/ Description Codes Begin flip
beginning packet. 8B10B receiver detects transition from Idle pattern (/I/ code stream) non-Idle pattern without intervening code, then packet assumed have SPD. Packets with normally discarded codeword errors. Refer Packet Discard section more details discards. device programmed discard packets with codeword errors clearing discard codeword enable Configuration register. 3.7.6 Packet packet indicated Packet Delimiter, referred EPD. consists codes, called /R/, inserted packet, defined IEEE 802.3z shown Table also shown Figure maintain synchronization proper word boundaries, outgoing packet must also have even number 10-bit words transmitted. packet number 10-bit words transmitted after /T/R/ codes, then extra code inserted after /T/R/ (now /T/R/R/) meet even word requirement defined IEEE 802.3z shown Figure transmit 8B10B section appends either /T/R/ /T/R/R/ codes each transmit packet. receive 8B10B section constantly monitors incoming stream. /T/R/ codes detected, then packet indication given receive MAC, /T/R/ /T/R/R/ codes stripped from packet. 8B10B receiver detects transition from non-Idle pattern Idle pattern (/I/ code stream) without intervening /T/R/ codes, then packet assumed have EPD. Packets with discarded device programmed Refer Packet Discard section more details discards. device programmed discard packets with errors clearing discard codeword enable Configuration register. 3.7.7 Idle interpacket time filled with continuous stream codes referred idle pattern. idle pattern consists continuous stream /I2/ codes, defined IEEE 802.3z shown Figure running disparity during idle defined negative. running disparity after last code packet positive, single /I1/ code must transmitted first idle code make running disparity negative. subsequent idle codes must /I2/, defined IEEE 802.3z shown Figure /I1/ /I2/ codes defined Table transmit 8B10B section inserts continuous stream /I1/I2/I2/I2/. /I2/I2/I2/I2/. codes between packets.
Link Configuration
/C2/
/K28.5/ /D21.5/ config_word1 config_word2 Link /K28.5/ Configuration /D2.2/ config_word1 config_word2 Link Configuration Idle Idle Idle Alternating /C1/ /C2/ /K28.5/ /D5.6/ /K28.5/ /D16.2/ /I1/ /I2/ /K27.7/ /K29.7/ /K23.7/ Error (Void) /K30.7/
same
/I1/ /I2/
-same same same same
Start Packet Delimiter (SPD) Packet Delimiter (EPD)
determined characters only, config_word. config_word contain 16-Bit AutoNegotiation data word. AutoNegotiation section details.
3.7.5 Start Packet Start packet indicated unique Start Packet Delimiter, referred SPD. consists single code inserted beginning packet place first preamble octet, defined IEEE 802.3z shown Figure code defined Table transmit 8B10B section inserts code beginning each transmit packet place first word preamble. receive 8B10B section constantly monitors incoming stream. code detected, then start packet indication given receive MAC, preamble octet substituted place code
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receive 8B10B section constantly monitors incoming stream. /I2/ /I1/ code detected, then packet indication given receive /I1/ /I2/ codes stripped from packet. 3.7.8 Receive Word Synchronization order correctly decode incoming encoded data, 8B10B receiver must identify word boundaries incoming data stream. process detecting these word boundaries referred word synchronization. receiver uses state machine compatible with algorithm defined IEEE 802.3z acquire maintain word synchronization. comma code used acquire maintain receive word synchronization, specified IEEE 802.3z. comma code consists unique pattern that only appears defined ordered sets shown Table comma code does appear normal data words across data word boundaries. Word synchronization signaled external device asserting EN_CDET when 8B10B receiver lost word synchronization. Word synchronization status also determined reading receive word sync detect Status register. 3.7.9 AutoNegotiation AutoNegotiation algorithm uses ordered sets, defined Table configure link correct operation. Refer AutoNegotiation section more details this process. 10-BIT INTERFACE 3.8.1 General 10-Bit Interface standardized interface between 8B10B section external Physical Layer device. 10-Bit Interface meets requirements outlined IEEE 802.3z. device directly connect, without external logic, Physical Layer device which also complies with IEEE 802.3z 10Bit Interface specifications. 10-Bit Interface frame format defined IEEE 802.3z shown Figure 10-Bit Interface consists twenty signals: transmit data output bits (TX[0:9]), transmit clock output (TBC), receive data input bits (RX[0:9]), receive clock inputs (RBC0 RBC1), comma detect enable output (EN_CDET), loopback output (EWRAP), receiver lock output (LCK_REF).
3.8.2 Data Format Order format order data word TX[0:9] RX[0:9] relationship frame System Interface data words shown Figure Note that Figure assumes that device Little Endian format (default). device Endian Format, byte order System Interface data word reversed. System Interface section more details needed. 3.8.3 Transmit transmit side, output clock generated from TCLK input clock runs continuously MHz. Data TX[0:9] clocked device rising edges clock output. 3.8.4 Receive receive side, RX[0:9] data clocked rising edges RBC[1:0] input clocks. RBC1 RBC0 required frequency 62.5 180° phase. data RX[0:9] clocked using alternate rising edges RBC[1:0] clocks latch data RX[0:9]. incoming data RX[0:9] also required word aligned RBC1 clock, that words that contain comma codes must clocked with RBC1 clock, specified IEEE 802.3z. comma detect output, EN_CDET, asserted when receiver 8B10B section lost word synchronization. EN_CDET also asserted setting EN_CDET assert Configuration register. EN_CDET output used enable synchronization process external Physical Layer device. device does have designated standardized comma detect input, COM_DET, because receive 8B10B section necessary logic acquire word synchronization from contents receive data stream alone. 3.8.5 Lock Reference LCK_REF output controlled exclusively setting LCK_REF assert Configuration register. This output typically used enable locking process external Physical Layer device. 3.8.6 Loopback EWRAP output controlled exclusively setting EWRAP assert Configuration register. This output typically used enable loopback function external Physical Layer device.
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When EWRAP asserted, signal detect input pin, from external Physical Layer Device unknown state. counteract this, signal detect enable Configuration register should also written when EWRAP assert written "1". 3.8.7 Signal Detect There additional signal detect input pin, which indicates device that receive data detected RXD[0:9] contains valid data. asserted high, input data assumed valid receive 8B10B section unaffected. deasserted low, data assumed invalid receive 8B10B section forced into loss sync state. Although part IEEE defined 10-Bit Interface, typically sourced from external Physical Layer device. device powers with disabled, that affect receive word synchronization state machine. enable pin, enable must Configuration register. There also signal detect status Status register which reflects state input pin. high, then signal detect status forced high; low, then signal detect status also forced low. 3.8.8 Disable transmit side 10-bit interface disabled disable Configuration register. When this set, TX[0:9] outputs placed high impedance state.
Table Transmit Discard Conditions Discard Condition Transmit FIFO Underflow Description FIFO empty. Packet transmission 8B10B halted. Partially transmitted packet terminated with code followed normal codes. FIFO full. more data accepted from System Interface. Partially transmitted packet terminated with code followed normal codes.
Transmit FIFO Overflow
3.9.3 Receive Discards Receive packets discarded certain error conditions detected. These error conditions described Table discard behavior dependent whether packet being output System Interface when discard condition detected. packet containing error being output System Interface when discard condition detected (referred internal discard), packet discarded, that data from packet containing error flushed from receive FIFO. packet containing error being output System Interface when discard condition detected (referred external discard), error condition indicated assertion RXDC pin. packet then discarded asserting RXABORT pin, packet automatically discarded automatic AutoAbort Configuration register. both internal external discarded packets, appended status word updated reflect discard error condition. Each receive discard conditions individually removed discard condition appropriately setting discard bits Configuration register. When these bits set, packet that afflicted with error condition indicated that will discarded.
PACKET DISCARD 3.9.1 General device programmed discard receive transmit packets when certain error conditions detected. detection these error conditions occur MAC, FIFO, 8B10B sections. 3.9.2 Transmit Discards Transmit packets will automatically discarded certain error conditions detected. These error conditions described Table When discard error detected transmit packet, remaining data that packet being input from System Interface ignored, code appended packet indicate error remote station, TXDC asserted packet being input from System Interface when discard occurred.
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device programmed send status words discarded packets receive FIFO. Receive Status Word Section more details status word configuration. Note that receive FIFO underflow listed discard condition Table That packets discarded when corrupted receive FIFO underflow. However, receive FIFO underflow does cause assertion RXDC.
3.9.5 AutoClear Mode TXDC RXDC made automatically self clear putting device AutoClear mode. AutoClear mode enabled setting AutoClear enable Configuration register. When device AutoClear mode, TXDC RXDC automatically cleared three SCLK cycles after next packet occurs (TXEOF RXEOF). 3.9.6 AutoAbort Mode When AutoClear mode enabled, device also made automatically abort current packet System Interface receive FIFO when discard condition detected RXDC asserted. This referred AutoAbort mode. AutoAbort mode enabled setting AutoAbort Configuration register.
Table Receive Discard Conditions Discard Condition Receive FIFO Overflow Error Undersize Packet Description Receive FIFO full. more data accepted from 8B10B PCS. Receive packet Error Receive packet less than bytes, exclusive preamble Receive packet greater than maximum packet size, exclusive preamble Receive packet contains least word with 8B10B coding error. RXABORT asserted while receive packet read System Interface. process flushing receive packet with RXABORT requires extra SCLK cycles equal [(packet length bytes)/8
3.10 RECEIVE STATUS WORD 3.10.1 General 32-bit status word appended each good receive data packet stored receive FIFO. This status word contains byte count error information receive data packet. 3.10.2 Format format status word shown Table 16-bits contain actual byte count packet, bottom 16-bits contain status information related packet. Note that endian select will affect byte order status word same that affects normal data byte order System Interface. byte count value status word total number actual bytes received packet minus preamble bytes bytes. byte count independent whether preamble been stripped receive MAC. packet overflows receive FIFO, then byte count will stop counting moment that receive FIFO overflow been detected remaining bytes incoming packet will counted. 3.10.3 Append Options status word normally appended good receive packets. However, device also programmed either store status word receive FIFO discarded packets well append status word good (non-discarded) packets, append status word all. These status word options selected appropriately setting receive status word append bits Configuration register.
Oversize Packet
Codeword Error RXABORT
3.9.4 Discard Output Indication When discard condition detected packet that being received transmitted over System Interface, TXDC RXDC output pins asserted indicate that discard error detected. TXDC RXDC normally latched high when discard takes place. TXDC RXDC cleared asserting clearing pins, CLR_TXDC CLR_RXDC, respectively. When CLR_TXDC CLR_RXDC pins asserted, TXDC RXDC outputs cleared SCLK after clearing signal asserted.
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3.10.4 Status Word Discarded Packets When device programmed status word discarded packets, only status word stored receive FIFO each discarded packet. status word discarded packet contains indication error that caused discard. receive FIFO full more than consecutive packet discarded, then more status word stored receive FIFO next consecutive group discarded packets, status word indicating that multiple status words have been discarded. When status word multiple discard set, then other status bits reflect status second discarded packet only. 3.10.5 Status Word RXABORT Packets When RXABORT asserted, both packet data associated status word normally flushed from receive FIFO. device programmed allow RXABORT discard packet data only leave status word aborted packet receive FIFO setting RXABORT definition Configuration register.
3.11 AUTONEGOTIATION 3.11.1 General AutoNegotiation algorithm negotiation sequence between stations over 10-Bit Interface that establishes good link between stations, configures both stations same mode operation. AutoNegotiation algorithm 8101 meets specifications defined IEEE 802.3z. AutoNegotiation uses stream ordered sets pass AutoNegotiation data word from remote station. ordered stream consists alternating sequence /C1/ /C2/ ordered sets. /C1/ /C2/ ordered sets composed unique code words plus 16-bit AutoNegotiation data word, defined IEEE 802.3z shown Figure AutoNegotiation algorithm initiated following conditions: device reset, AutoNegotiation restart set, ordered sets received from remote end, device reacquires receive word synchroniza-
Table Receive Status Word Definition
RXD31 BC15 BC14 BC13 BC12 BC11 BC10 MPKT RXD15 RXD16
CWRD OSIZE USIZE
OVFL RXD0
Symbol BC[15:0] -MPKT
Name Byte Count -Multiple Packet Reject Codeword Error Oversize Packet Undersize Packet Receive FIFO Overflow Error
Definition Contains Actual Byte Count Receive Packet Reserved FIFO full multiple consecutive packets were discarded. Status word indicates error condition first packet discarded group. Receive Packet Coding Error Receive Packet Greater Than Maximum Size Receive Packet Less Than Minimum Size Receive FIFO Full Received Additional Data Receive Packet Error
Position RXD[31:0] RXD[31:16] RXD[15:6] RXD5
CWRD OSIZE USIZE OVFL
RXD4 RXD3 RXD2 RXD1 RXD0
Note This byte order little endian format. endian format will reverse this byte order.
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tion. Once negotiation been initiated, device uses contents AutoNegotiation Base Page Transmit register advertise capabilities remote device. remote device does same, capabilities read back from remote device stored AutoNegotiation Base Page Receive register. device's advertised capabilities then externally compared capabilities received from remote device, device then configured compatible mode operation. 8101 also Next Page capability. complete description AutoNegotiation algorithm device, refer IEEE 802.3z clause specification. 8B10B receiver lost word synchronization, device needs acquire synchronization before AutoNegotiation words successfully received. While loss synchronization state, transmitter outputs ordered sets with remote fault bits RF[1:0]=01 indicate link failure condition remote end. Once 8B10B receiver acquired word synchronization, then negotiation process ready begin. 3.11.2 Next Page device also Next Page capability defined IEEE 802.3z. Next Page feature allows transfer additional 16-bit data words between stations during negotiation sequence addition original base page message information. These additional 16-bit data words referred next pages contain arbitrary data. next page transmitted, next page must written NP=1 AutoNegotiation Base Page Transmit register indicate this remote station. Conversely, remote station wants send next page device, will next page NP=1 base page, which stored AutoNegotiation Base Page Receive register. next pages transmitted remote station have written into AutoNegotiation Next Page Transmit register order transmitted. next pages received from remote station stored AutoNegotiation Next Page Receive register. Both stations must have Next Page functionality successful next page transfer. Next Page operation complicated; refer IEEE 802.3z full description this feature works. There status bits related Next Page operation. Negotiation Status section details.
3.11.3 Negotiation Status There bits Status register which indicate status AutoNegotiation. These bits summarized Table also described more detail Status register description. Some bits related AutoNegotiation programmed interrupt, described Status register description.
Table AutoNegotation Status Bits Name 11.11 11.7 11.6 11.5 11.4 11.3 LINK AN_NP AN_TX_NP AN_RX_NP AN_RX_BP What Indicates Link AutoNegotation compeleted. Next Page been exchanged. Next Page been transmitted. Next Page been received. Base Page been received.
AN_REM_RST AutoNegotiation restarted remote station.
INTERFACE
K28.5 D21.5
<BITS [0:7]> <BITS [8:15]> K28.5
FROM REGISTERS
D2.2 <BITS [0:7]> <BITS [8:15]> FROM REGISTERS
ABCDEFGH abcdefghij
CODES CODES
PHY. INT. PHY. INT.
NOTE: MEANS ENCODED
Figure AutoNegotiation Data Format
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3.11.4 AutoNegotiation Restart AutoNegotiation algorithm restarted setting AutoNegotiation restart Configuration register. AutoNegotiation restart clears itself automatically once AutoNegotiation process starts transmitting ordered sets. 3.11.5 AutoNegotiation Enable AutoNegotiation algorithm enabled setting AutoNegotiation disable Configuration register. When AutoNegotiation disabled, transmitter will output ordered sets. 3.11.6 Link Indication successful completion AutoNegotiation process (and definition receiver also acquired word synchronization) indicated asserting LINK active low, setting link detect status Status Register. LINK output drive from also drive another digital input. 3.12 FLOW CONTROL Flow control refers ability cause remote station temporarily halt sending packets order prevent packet loss congested system. 8101 uses Control frames flow control, IEEE 802.3x specifications. Refer Control Frame section more details Control Frame flow control scheme. 8101 normally treats Control frames according IEEE 802.3 Clause algorithm. When receive detects Control frame with Pause opcode with destination address equal reserved multicast address address stored Address registers, then transmitter paused time equal number pause times specified parameter field. Each unit pause time equals bits (512 Gigabit). Pause frame received while another packet being transmitted, then transmission completed current packet being transmitted, then transmitter paused. there other packets transmit FIFO, their transmission will delayed until pause timer expired. Control frames normally passed into receive FIFO; they terminated receive MAC. 8101 also incorporated some additional features facilitate Control frame operation. These features described following sections. 3.13.2 Automatic Pause Frame Generation Pause frames automatically generated when either FCNTRL asserted, receive FIFO data exceeds Control Autosend threshold. These automatically generated Pause frames, referred autogenerated Pause frames, will internally generated transmitted over 10-Bit Interface. transmission autogenerated Pause frames affected reception receive Pause frame; receive Pause frames only inhibit transmission regular packets from transmit FIFO. packet transmission progress when autogenerated Pause frame transmitted, device will wait until transmission that packet completed then transmit autogenerated Pause frame before other subsequent packets FIFO transmitted. When first autogenerated Pause frame begins transmission, internal timer will start whose value equal pause_time value pause frame (and obtained from Flow Control Register FCNTRL still asserted Control Frame Autosend threshold still exceeded when internal pause timer expires, then another autogenerated Pause frame will transmitted. This process will continue repeat itself long FCNTRL remains asserted Control Frame Autosend threshold exceeded. When FCNTRL deasserted Control Autosend threshold exceeded, then last autogenerated Pause frame pause_time will transmitted. compensate latency, internal pause timer will internally shorten itself units from value programmed into Flow Control register.
3.13 CONTROL FRAMES 3.13.1 General Control frames packets which pass signaling information between stations specified IEEE 802.3 Clause Control frames used primarily flow control. Control frames defined IEEE 802.3 Clause differentiated from other packets having unique value 8808H length/type field. Control frames have same packet format normal Ethernet packets except Data field composed opcode field parameter field. opcode field contains opcode command, parameter field contains value associated with opcode command. only opcode command defined date IEEE 802.3x Pause opcode; parameter field Pause opcode defines pause time. Control frames with Pause opcode, referred Pause frames, only allowed have destination address equal specific reserved multicast address address receive station itself. value reserved multicast address 0180-C2-00-00-01H.
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device programmed eliminate last autogenerated Pause frame with pause_time clearing Control frame pause Flow Control register. structure autogenerated Pause frame described Figure Note that source address pause_time parameter fields programmable through internal registers shown Figure FNTRL Control Autosend threshold individually disabled, that they programmed longer initiate transmission autogenerated Pause frames. FCNTRL default enabled disabled setting FCNTRL disable Configuration register. Control Autosend default disabled, enabled appropriately setting Control Autosend threshold bits Flow Control register. 3.13.3 Transmitter Pause Disable Receive Pause frames normally pause transmitter. Receive Pause frames programmed pause transmitter clearing Control frame enable Flow Control Register. When this cleared low, received Pause frames affect transmitter. 3.13.4 Passthrough FIFO Receive Pause frames normally discarded passed receive FIFO. Receive Pause frames passed receive FIFO appropriately setting
Control frame passthrough bits Flow Control register. These bits allow either Control frames non-Pause frames only Pause frames only passed receive FIFO. 3.13.5 Reserved Multicast Address Disable Receive Pause frames normally rejected invalid they have reserved multicast address destination address field. Receive Pause frames accepted without regard contents destination address field appropriately setting Control frame address filter Flow Control register. When this cleared low, value destination address field will accepted valid address. 3.13.6 Control Frame AutoSend transmission autogenerated Pause frames also triggered level data receive FIFO. This feature referred Control Frame AutoSend. AutoSend feature enabled appropriately setting Control Frame AutoSend bits Flow Control register. When Control Frame AutoSend enabled, autogenerated Pause frames will transmitted when receive FIFO data exceeds programmable threshold level, called Control AutoSend threshold. Control AutoSend threshold with four Control frame autosend bits Flow Control register. automatic Pause frame generation mechanism described more detail previous section.
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10BIT INTERFACE /I2/ /I2/ 10101010 10101010 10101010 10101010 10101010 10101010 10101010 10101011 10000000 00000001 01000011 00000000 00000000 10000000 [0:7] REG2 [8:15] REG2 [16:23] REG1 [24:31] REG1 [32:39] REG0 [40:47] REG0 00010001 00010000 00000000 10000000 P[8:15] REG20 P[0:7] REG20 00000000 00000000 [31:24] [23:16] [15:8] [7:0] D21.2 D21.2 D21.2 D21.2 D21.2 D21.2 D21.6 D1.0 D0.4 D2.6 D0.0 D0.0 D1.0 [0:7] REG2> [8:15] REG2> [16:23] REG1> [24:31] REG1> [32:39] REG0> [40:47] REG0> D8.4 D8.0 D0.0 D1.0 <P[8:15] REG20> [0:7] REG20> D0.0 D0.0 <FCS [31:24]> <FCS [23:10]> <FCS [15:8]> <FCS [7:0]> /I1/ /I2/ /I2/ /I2/ BITS TRANSMITTED
DATA PARAM
BYTES)
ABCDEFGH
NOTES MEANS ENCODED /I1/ /I2/ DEPENDS RUNNING DISPARITY
Figure Autogenerated Pause Frame Format
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BYTES TRANSMITTED
10-BIT INTERFACE
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3.14 RESET device four resets. four resets described Table device should ready normal operation after reset sequence been completed that bit.
Table Reset Description Name Device Reset Initiated Reset Action RESET Reset Datapath Asserted Flush Transmit FIFO Config. Flush Receive FIFO Reset Bits Defaults Reset Counters Transmit Reset TXRST Config Reset Transmit Data Path Flush Transmit FIFO Reset Counters Receive Reset RXRST Config. Reset Receive Data seperate path Flush Receive FIFO Reset Counters AutoNegotiation Restart Counter Reset ANRST Config. CTRRST Config. Starts AutoNegotiation Sequence Reset Counters
lower value address register counter LSB; higher value address register counter MSB. When counter read operation initiated, 32-bit counter result accessed transferred internal 16-bit holding registers. These holding registers freeze store counter result duration read operation while allowing internal counter continue increment needed. timing delay associated with reading counters described Register Interface section Register Interface Timing Characteristics. When counter read out, count automatically reset zero remain unchanged (programmable). Counters configured either stop counting when they reach their maximum count rollover (programmable). Each counter associated status which when counter becomes half full. These status bits individually programmed assert interrupt. counter Table includes packet octet statistics transmit side well receive. RMON specs literally state that packet octet counters should only tabulate received information. This sometimes interpreted mean both transmitted received information because Ethernet originally shared media protocol. such, packet octet counters both transmit receive available device, transmit receive packet octets counts summed together desired. exact correspondence actual objects from IETF IEEE specifications actual 8101 counters locations described Applications section shown there Tables 45-48. 3.15.2 Counter Half Full Each 32-bit counter half full status output associated with that counter. half full bits stored Counter Half Full registers. These half full bits when counter value reaches 80000000H (i.e. goes from they high when counter becomes half full. counter half full bits will latch themselves when they high, each will stay latched high until either read out, counter register which associated with read out. Counter half full bits also interrupt bits; that setting counter half full programmed cause assertion interrupt pin, REGINT. When counter half full cleared read, interrupt caused that also cleared. Note that REGINT stays asserted until interrupt bits
3.15 COUNTERS 3.15.1 General 8101 management counters. Each counter responsible tabulating number times specific event occurs. complete list counters along with their definitions shown Table These counters provide necessary statistics completely support following specifications: RMON Statistics Group SNMP Interfaces Group Ethernet-Like Ethernet (IETF RFC1757) (IETF RFC1213 1573) (IETF RFC1643) (IEEE 802.3z Clause
counters 32-bits wide. Each 32-bit counter result obtained performing read operation from adjacent 16-bit register address locations over Register Interface. address locations each counter shown both Table Table 16-bit register locations associated with each 32-bit counter, register with lower value address always contains least significant 16-bits counter result. Thus,
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cleared. Each counter half full individually programmed assert assert) interrupt appropriately setting mask associated with that counter half full Counter Half full Mask registers. 3.15.3 Counter Reset Read counter value normally unaffected read operation that counter. However, counters programmed automatically reset count zero when read appropriately setting counter reset read Configuration Register. When counter reset read high, counter reset zero whenever 16-bit counter registers associated with 32-bit counter read out. There internal holding register inside device which stores entire 32-bit counter result that 32bit result will correctly read long successive 16-bit counter register reads performed from same counter. When counter reset read cleared (default), count inside counters unaffected read long counter maximum count. counter maximum count, count always reset zero when read out. 3.15.4 Counter Rollover counters normally rollover zero when they exceed their maximum count (i.e. receive increment when counter maximum count). counters programmed freeze stop counting once they reach
their maximum count setting counter rollover Configuration register. 3.15.5 Counter Maximum Packet Size maximum packet size used management counter statistics programmed four values appropriately setting counter packet size select bits Configuration register. This selection described register descriptions those registers also summarized Table bits Table affect maximum packet size counters only; maximum packet size section determined other bits described Receive section.
Table Counter Maximum Packet Size Selection Counter Packet Size Select Bits 10.[7:6] Packet Size (bytes) Unlimited 1535 1522 1518
3.15.6 Counter Reset counters reset zeroes setting counter reset Configuration register. Asserting device reset RESET will also reset counters zero.
Table Counter Definition Ctr. Counter Name (MIB Object Name) Counter Description Definition Size (Bits) Register Address
REGAD[7:0]
(Lo/Hi) RMON Statistics Group (RFC 1757) etherStatsDropEvents etherStatsOctets Packets with receive FIFO overflow error. Bytes, exclusive preamble, good packets. Bytes packets with excluded. packets, good bad. Broadcast packets, good only. Multicast packets, good only. 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001
etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts
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Table Counter Definition (cont'd) Ctr. Counter Name (MIB Object Name) Counter Description Definition Size (Bits) Register Address
REGAD[7:0]
(Lo/Hi) etherStatsCRCAlignErrors Packets legal-length with error alignment error. There alignment errors 8B10B Gigabit Ethernet, this counter will only count errors legal length packets. etherStatsUndersizePkts etherStatsOversizePkts etherStatsFragments Packets length bytes with other errors. Packets length Max_Packet_Length with other errors. Packets length bytes with error alignment error. There alignment errors 8B10B Gigabit Ethernet, this counter will only count errors with length etherStatsJabber Packets length Max_Packet_Length with error alignment error. There jabber function Gigabit Ethernet, this counter undefined etherStatsCollisions asserted more collsions occurred. Since device Full Duplex only, this counter undefined. etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets etherStatsPkts512to1023Octets Packets length bytes, good bad. Packets length between 65-127 bytes, inclusive, good bad. Packets length between 128-255 bytes, inclusive, good bad. Packets length between bytes, inclusive, good bad. Packets length between 1023 bytes, inclusive, good bad. Packets length between 1024 Max_Packet_Length, inclusive, good bad. Bytes, exclusive preamble, good packets. packets, good bad. Broadcast packets, good only. 10010110 10010111 10011000 10011001 10011010 10011011 10011100 10011101 10011110 10011111 10100000 10100001 10100010 10100011 10100100 10100101 10100110 10100111 10010100 10010101 10010010 10010011 10001100 10001101 10001110 10001111 10010000 10010001 10001010 10001011
etherStatsPkts1024to1518Octets
etherStatsOctets_TX etherStatsPkts_TX etherStatsBroadcastPkts_TX
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Table Counter Definition (cont'd) Ctr. Counter Name (MIB Object Name) Counter Description Definition Size (Bits) Register Address
REGAD[7:0]
(Lo/Hi) etherStatsMulticastPkts_TX etherStatsPkts64Octets_TX etherStatsPkts65to127Octets_TX etherStatsPkts128to255Octets_TX etherStatsPkts256to511Octets_TX Multicast packets, good only.
10101000 10101001 10101010 10101011 10101100 10101101 10101110 10101111 10110000 10110001 10110010 10110011 10110100 10110101
Packets length bytes, good bad. Packets length between 65-127 bytes, inclusive, good bad. Packets length between 128-255 bytes, inclusive, good bad. Packets length between bytes, inclusive, good bad. Packets length between 1023 bytes, inclusive, good bad. Packets length between 1023 Max_Packet _Length, inclusive, good bad.
SNMP Interfaces Group (RFC 1213 1573) ifInOctets ifInUcastPkts ifInMulticastPkts ifInBroadcastPkts ifInNUcastPkts Bytes, including preamble, good packets. Unicast packets, good only. Multicast packets, good only. Equivalent "etherStatsMulticastPkts" Broadcast packets, good only. Equivalent "etherStatsBroadcastPkts" Broadcast multicast packets, good only. Equivalent "etherStatsBroadcastPkts etherStatsMulticastPkts" Packets with receive FIFO overflow error. Equivalent "etherStatsDropEvents" packets, only. Equivalent "etherStatsCRCAlignError etherStatsUndersizePkts etherStatsOversizePkts" Bytes, including preamble, good packets. Unicast packets, good bad. Multicast packets, good bad. 10110110 10110111 10111000 10111001 Ctr.
Ctr. Ctr. #4+5 Ctr. Ctr. #6+7+8
ifInDiscards ifInErrors
ifOutOctets ifOutUcastPkts ifOutMulticastPkts
10111010 10111011 10111100 10111101 10111110 10111111
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Table Counter Definition (cont'd) Ctr. Counter Name (MIB Object Name) Counter Description Definition Size (Bits) Register Address
REGAD[7:0]
(Lo/Hi) ifOutBroadcastPkts ifOutNUcastPkts Broadcast packets, good bad. Broadcast multicast packets, good bad. Equivalent "ifOutMulticastPkts ifOutBroadcastPkts" Packets with transmit FIFO underflow error. Packets, only, exclusive legal-length errors. Packets with alignment error only. There alignment errors 8B10B Gigabit Ethernet, this counter undefined. dot3StatsFCSErrors dot3StatsSingleCollisionFrames Packets with error only. Equivalent "etherStatsCRCAlignErrors" Packets successfully transmitted after only collision (ie: attempt value=2). Since device Full Duplex only, this counter undefined. Packets successfully transmitted after more than collision (ie: 2<attempt value<16). Since device Full Duplex only, this counter undefined. dot3StatsSQETestErrors Number times asserted. There Gigabit Ethernet, this counter undefined. dot3StatsDeferredTransmissions Packets deferred, i.e. packets whose transmission delayed busy medium, first attempt only. Since device Full Duplex only, this counter undefined. dot3StatsLateCollisions Packets that encounter late collision, i.e. encountered collisions more than times into transmitted packet. late collision counted twice, collision late collision. Since device Full Duplex only, this counter undefined. 11010010 11010011 11010000 11010001 11001110 11001111 11001100 11001101 Ctr. 11001010 11001011 11000000 11000001 Ctr. #32+33
ifOutDiscards ifOutErrors
11000010 11000011 11000100 11000101 11000110 11000111
Ethernet-Like Group (RFC 1643) dot3StatsAlignmentErrors
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Table Counter Definition (cont'd) Ctr. Counter Name (MIB Object Name) Counter Description Definition Size (Bits) Register Address
REGAD[7:0]
(Lo/Hi) dot3StatsExcessiveCollisions Packets successfully transmitted after more than collisions (ie: attempt value=16). Since device Full Duplex only, this counter undefined.
11010100 11010101
Packets with transmit FIFO underflow error. Equivalent "ifOutDiscards" Carrier sense dropout errors, i.e. number times that carrier sense asserted deasserted during packet transmission, without collision. This counter only incremented once packet, regardless number dropout errors packet There loopback 8B10B Ethernet, this counter undefined
Ctr. 11010110 11010111
dot3StatsCarrierSenseErrors
dot3StatsFrameTooLongs
Packets length Max_Packet_Length with other errors. Equivalent "etherStatsOversizePkts" Packets with receive FIFO overflow error. Equivalent "etherStatsDropEvents" packets, good only. Equivalent "etherStatsPkts_TX ifOutErrors" Packets successfully transmitted after only collision (ie: attempt value=2).
Equivalent
Ctr.
Ctr.
Ethernet (IEEE 802.3z Clause aFramesTransmittedOK Ctr. #19-35 Ctr.
aSingleCollisionFrames
aMultipleCollisionFrames
Packets successfully transmitted after more than collision (ie: 2<attempt value<16).
Equivalent
Ctr.
aFramesReceivedOK
packets, good only. Equivalent "ifInUcastPkts etherStatsBroadcastPkts etherStatsMulticastPkts" Packets with error only. Equivalent "dot3StatsFCSErrors" Packets with alignment error only. Equivalent "dot3StatsAlignmentErrors"
Ctr. #29+4+5
aFrameCheckSequenceErrors aAlignmentErrors
Ctr. Ctr.
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Table Counter Definition (cont'd) Ctr. Counter Name (MIB Object Name) Counter Description Definition Size (Bits) Register Address
REGAD[7:0]
(Lo/Hi) aOctetsTransmittedOK aFramesWithDeferredXmissions Bytes, exclusive preamble, good packets only. Packets deferred, i.e. packets whose transmission delayed busy medium, first attempt only.
Equivalent
11011000 11011001 Ctr.
aLateCollisions
Packets that encounter late collision, i.e. encountered collisions more than times into transmitted packet. late collision counted twice, collision late collision. Equivalent "dot3StatsLateCollisions" Packets successfully transmitted after more than collisions (ie: attempt value=16). Equivalent "dot3StatsExcessiveCollisions" Packets with transmit FIFO underflow error. Equivalent "ifOutDiscards" Carrier sense dropout errors, i.e. number times that carrier sense asserted deasserted during packet transmission, without collision. This counter only incremented once packet, regardless number dropout errors packet Equivalent "dot3StatsCarrierSenseErrors" Bytes, exclusive preamble good packets only. Packets with receive FIFO overflow error. Equivalent "etherStatsDropEvents" Multicast packets, good only. Equivalent "etherStatsMulticastPkts_TX" Broadcast packets, good only. Equivalent "etherStatsBroadcastPkts_TX" Packets with excessive deferral, i.e. packets waiting transmission longer than packet times.
Since device Full Duplex only, this counter undefined.
Ctr.
aFrameAbortedDueToXSCollisions
Ctr. Ctr. Ctr.
aCarrierSenseErrors
aOctetsReceivedOK
aFramesLostDueToIntMACRcvrError
11011010 11011011 Ctr. Ctr. Ctr.
aMulticastFrameXmittedOK aBroadcastFramesXmittedOK aFramesWithExcessiveDefferal
11011100 11011101
aMulticastFramesReceivedOK
Multicast packets, good only. Equivalent "etherStatsMulticastPkts" Broadcast packets, good only. Equivalent "etherStatsBroadcastPkts"
Ctr.
aBroadcastFramesReceivedOK
Ctr.
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Table Counter Definition (cont'd) Ctr. Counter Name (MIB Object Name) Counter Description Definition
Size (Bits)
Register Address
REGAD[7:0]
(Lo/Hi) aInRangeLengthErrors aOutOfRangeLengthField aFrameTooLongErrors Packets legal-length whose actual length different from length/type field value. Packets with length/type field value Max_Packet_Length. Packets length Max_Packet_Length with other errors. Equivalent "etherStatsOversizePkts" aSQETestErrors aSymbolErrorDuringCarrier Number times asserted. Equivalent "dot3StatsSQETestError" more symbol errors received from during packet reception, exclusive collision. This counter only incremented once packet, regardless number symbol errors that packet. Valid Control packets.
Equivalent
11011110 11011111 11100000 11100001 Ctr.
Ctr. 11100010 11100011
aMACControlFramesTransmitted aMACControlFramesReceived aUnsupportedOpcodesReceived aPauseMACCtrlFramesTransmitted aPauseMACCtrlFramesReceived
Ctr. Ctr. 11100100 11100101 11100110 11100111 11101000 11101001
Valid Control packets.
Equivalent "aPauseMACCtrlFramesReceived"
Valid Control packets with non-Pause opcode. Valid Control packets with Pause opcode. Valid Control packets with Pause opcode.
packet legal-length error, error receive FIFO overflow, symbol error. Where: Error with integral number octets. Alignment Error with non-integral number octets. Symbol Error invalid codeword /V/. packet legal-length error, transmit FIFO underflow. Legal-length packet between Max_Packet_Length bytes. Preamble included length count. Max_Packet_Length counters programmed either 1518, 1522, 1535, unlimited bytes. 1518 default both transmit receive. counter result stored 16-bit registers. Thus, there register addresses each counter. registers given counter, register with lower value address contains least significant counter bits. RMON specs explicitly states that packet octet counters should only tabulate received information. This sometimes interpreted mean both transmitted received information because Ethernet originally shared media. such, transmit packet octet counters also available counters 18-27 summed with receive packet octet counts ifdesired.
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3.16 LOOPBACK diagnostic loopback mode enabled setting loopback enable Configuration register. When loopback mode enabled, transmit data that input transmit System Interface output from 8B10B Encoder internally looped back into receive 8B10B Decoder available read from receive System Interface. 3.17 TEST MODES TEST reserved factory test. TEST must tied normal operation. inputs outputs made high impedance state asserting active high. This intended device board diagnostic testing. 3.18 REGISTER INTERFACE 3.18.1 General Register Interface 16-bit bidirectional data interface that allows access internal registers. Register Interface consists twenty nine signals: sixteen bidirectional data bits (REGD[15:0]), eight register address inputs (REGA[7:0]), chip select input (REGCS), clock input (REGCLK), read select input (REGRD), write select input (REGWR), interrupt output (REGINT). REGCLK, clock frequency must between 5-40 Mhz. register accesses done single rising edge REGCLK clock. access register through Register Interface, REGCS needs asserted active sampled rising edges REGCLK. that same rising edge REGCLK, address register that will accessed clocked REGA[7:0]. that same rising edge REGCLK, either REGRD REGWR also needs asserted active these will clocked into device; which signal asserted will determine whether this read write cycle. cycle write cycle, then data written specific register will clocked rising edge same clock that clocked other inputs. cycle read cycle, then data will output REGD[15:0] after some delay after rising edge REGCLK that clocked input information. REGCS remain multiple REGCLK cycles that many registers read written REGCS assertion. During read cycles, delay from REGCLK data valid REGD[15:0] pins function which register being accessed. Data read from register, exclusive Counter 1-53 registers, appears REGD[15:0] pins
REGCLK cycle. Data read from Counter 1-53 registers takes most REGCLK cycles available REGD[15:0] first 16-bits counter result, most REGCLK cycles second 16-bits counter result. Refer Register Interface Timing Characteristics more details. 3.18.2 Types Register Interface bidirectional, there many types bits registers. type definitions summarized Table Write bits inputs during write cycle logic during read cycle. Read bits
Table Register Type Definition
Sym. Name Definition Write Cycle Write Read Read/ Write Read/ Write Self Clearing Input Operation, Input Ignored Input Input Clears Itself After Operation Completed Operation Latching Output Input Ignored When Goes Low, Latched Interrupt Asserted Masked) When Read Updated Interrupted Cleared R/LH R/LHI Read/ Latching High with Interrupt Operation, Input Ignored Output When Goes High, Latcched Interrupt Assert Masked) When Read, Updated Interrupt Cleared R/LT R/LTI Read/ Latching Transition with Interrupt Operation, Input Ignored Output When Transitions, Latched Interrupt Asserted Masked) When Read, Updated Interrupt Cleared Read Cycle Operation Output Valid Output Ouput Ouput
R/LL R/LLI
Read/ with Interrupt
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outputs during read cycle ignored high impedance during write cycle. Read/Write bits (R/W) actually write bits which read during read cycle. R/WSC bits bits that self clearing after period time after specific event completed. R/LL bits read bits that latch themselves when they low, they stay latched until read. After they read, they reset high. R/LH bits same R/LL bits except that they latch high. R/LT read bits that latch themselves whenever they make transition change value, they stay latched until they read. After R/LT bits read, they updated their current value. R/LLI, R/LHI, R/LTI bits function same R/LL, R/LH R/LT bits, respectively, except they also assert interrupt programmed (not masked). Interrupt bits described more detail Interrupt section. 3.18.3 Interrupt interrupt triggered when certain output status bits change state. These bits called interrupt bits designated R/LLI, R/LHI, R/LTI bits descriibed previous section. interrupt bits reside
Status Counter Half Full registers. Interrupt bits automatically latch themselves assert interrupt pin, REGINT, when they latch themselves. Interrupt bits stay latched until they read. When interrupt bits read, interrupt REGINT deasserted interrupt bits that caused interrupt happen updated their current value. Each interrupt individually masked subsequently removed interrupt setting appropriate mask register bits Status Mask Counter Half Full Mask registers. 3.18.4 Register Structure device internal 16-bit registers. Twenty registers available setting configuration inputs reading status outputs, remaining registers associated with management cunters. location registers described register addressing table Table register shown Table definition each each register described Tables 19-43.
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Registers
Table Register Address Table Register 12-13 15-16 25-31 33-111 112-115 116-119 120-123 124-127 128-129 130-131 132-133 134-135 136-137 138-139 Register Address (REGAD[7:0] Pins) 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001- 00011111 00100000 00011001 01101111 01110000 01110011 01110100 01110111 01111000 01111011 01111100 01111111 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 Register Name Address Address Address Address Filter Address Filter Address Filter Address Filter Configuration Configuration Configuration Configuration Status Reserved Status Mask Reserved Transmit FIFO Threshold Receive FIFO Threshold Flow Control Flow Control AutoNegotiation Base Page Transmit AutoNegotiation Base Page Receive AutoNegotiation Next Page Transmit AutoNegotiation Next Page Receive Reserved Device Reserved Counter Half Full Reserved Counter Half Full Mask Reserved Counter etherStatsDropEvents Counter etherStatsOctets Counter etherStatsPkts Counter etherStatsBroadcastPkts Counter etherStatsMulticastPkts Counter etherStatsCRCAlignErrors
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Table Register Address Table (cont`d) Register 140-141 142-143 144-145 146-147 148-149 150-151 152-153 154-155 156-157 158-159 160-161 162-163 164-165 166-167 168-169 170-171 172-173 174-175 176-177 178-179 180-181 182-183 184-185 186-187 188-189 190-191 192-193 194-195 196-197 198-199 200-201 202-203 204-205 206-207 208-209 210-211 212-213 214-215 Register Address (REGAD[7:0] Pins) 10001100 10001101 10001110 10001111 10010000 10010001 10010010 10010011 10010100 10010101 10010110 10010111 10011000 10011001 10011010 10011011 10011100 10011101 10011110 10011111 10100000 10100001 10100010 10100011 10100100 10100101 10100110 10100111 10101000 10101001 10101010 10101011 10101100 10101101 10101110 10101111 10110000 10110001 10110010 10110011 10110100 10110101 10110110 10110111 10111000 10111001 10111010 10111011 10111100 10111101 10111110 10111111 11000000 11000001 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 Register Name Counter etherStatsUndersizePkts Counter etherStatsOversizePkts Counter etherStatsFragments Counter etherStatsJabber Counter etherStatsCollisions Counter etherStatsPkts64Octets Counter etherStatsPkts65to127Octets Counter etherStatsPkts128to255Octets Counter etherStatsPkts256to511Octet Counter etherStatsPkts512to1023Octets Counter etherStatsPkts1024to1518Octets Counter etherStatsOctets_TX Counter etherStatsPkts_TX Counter etherStatsBroadcastPkts_TX Counter etherStatsMulticastPkts_TX Counter etherStatsPkts64Octets_TX Counter etherStatsPkts65to127Octets_TX Counter etherStatsPkts128to255Octets_TX Counter etherStatsPkts256to511Octets_TX Counter Counter Counter ifInOctets Counter ifInUcastPkts Counter ifOutOctets Counter ifOutUcastPkts Counter ifOutMulticastPkts Counter ifOutBroadcastPkts Counter ifOutDiscards Counter ifOutErrors Counter dot3StatsAlignmentErrors Reserved Counter dot3StatsSingleCollisionFrames Counter Counter dot3StatsSQETestErrors Counter dot3StatsDeferredTransmissions Counter dot3StatsLateCollisions Counter dot3StatsExcessiveCollisions Counter dot3StatsCarrierSenseErrors
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Table Register Address Table (cont`d) Register 216-217 218-219 220-221 222-223 224-225 226-227 228-229 230-231 232-233 234-255 Register Address (REGAD[7:0] Pins) 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11111111 Register Name Counter aOctetsTransmittedOK Counter aOctetsReceivedOK Counter aFramesWithExcessiveDefferal Counter aInRangeLengthErrors Counter aOutOfRangeLengthField Counter aSymbolErrorDuringCarrier Counter aUnsupportedOpcodesReceived Counter aPauseMACCtrlFramesTransmitted Counter aPauseMACCtrlFramesReceived Reserved
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Table Register
x.15 F6[2] F4[2] F2[2] F0[2] F0[3] RXCRC RMXPKT1 RMXPKT0 AN_EN CMXPKT0 F6[3] F4[3] F2[3] F6[1] F4[1] F2[1] F0[1] STSWRD1 STSWRD0 DIS_RXAB RXAB_DEF SINTF_DIS FCNTRL_DIS CMXPKT1 F6[7] F4[7] F2[7] F0[7] IPG0 TXPRMBL TXCRC RXPRMBL F0[6] F0[5] F0[4] F2[6] F2[5] F2[4] F4[6] F4[5] F4[4] F6[6] F6[5] F6[4] F7[0] F5[0] F3[0] F1[0] IPG1 DIS_USIZE DIS_OSIZE DISCWRD LCKREF CDET F7[1] F5[1] F3[1] F1[1] IPG2 DIS_CRC EWRAP F7[6] F7[5] F5[5] F3[5] F1[5] CTRRST APAD DIS_OVF CTR_ROLL TBC_DIS R/SCW ACPTALL TXRST R/WSC REJBCST AUTOCLR AUTORXAB CTR_RD LNKDN LPBK REJALL R/WSC ANRST F1[4] F1[3] F1[2] F3[4] F3[3] F3[2] F5[4] F5[3] F5[2] F7[3] F5[6] F3[6] F1[6] RXRST R/WSC REJMCST BUSSIZE F7[4] F7[2] F7[7] F5[7] F3[7] F1[7] R/WSC x.14 x.13 x.12 x.11 x.10 F6[0] F4[0] F2[0] F0[0] PEOF SD_EN
MD400176/B
RSYNC R/LTI MASK_ RSYNC TWM1[1] RWM1[4] TWM1[0] RWM1[3] TWM1[3] TWM1[2] RWM1[5] RWM1[6] MASK_ LINK TWM2[4] RWM1[2] R/LTI TWM2[3] RWM1[1] TWM2[2] RWM1[0] LINK AN_NP R/LHI AN_TX_NP AN_RX_NP AN_RX_BP AN_RMTRST MASK_ AN_NP TWM2[1] RWM2[7] TWM2[0] RWM2[6] TASND5 RWM2[5] TASND4 RWM2[4] R/LHI MASK_ AN_RMTRST TASND3 RWM2[3] TASND2 RWM2[2] TASND1 RWM2[1] TASND0 RWM2[0]
Addr Register Name
Address
Address
Filter
Configuration
Configuration
REJUCST
Configuration
Configuration
ENDIAN
Status
Status Mask
Transmit FIFO
TWM1[4]
Threshold
SEEQ Technology Inc. Proprietary Information
Receive FIFO Threshold
RWM1[7]
8101
Table Register (cont'd)
x.15 x.14 MCPASS1 MCFLTR MCPASS0 MCENDPS MCASND3 MCASND2 MCASND1 MCASND0 x.10 x.13 x.12 x.11
Addr Register Name
MD400176/B
PS_DIR MSG10 MSG9 MSG8 MSG6 MSG7 MSG5 MSG4 PS_DIR MSG2 MSG3 MSG0 MSG1 PAGETYPE ACK2 TOGGLE PAGETYPE ACK2 TOGGLE MSG10 MSG8 MSG7 MSG9 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0 PART3 PART0 HREV0 HREV3 HREV2 HREV1 PART2 PART1 SREV3 SREV2 SREV1 SREV0 HFULL14 HFULL13 R/LHI R/LHI R/LHI R/LHI R/LHI HFULL9 R/LHI HFULL12 HFULL11 HFULL10 HFULL8 R/LHI HFULL7 R/LHI HFULL6 R/LHI HFULL5 R/LHI HFULL4 R/LHI HFULL3 R/LHI HFULL2 R/LHI HFULL1 R/LHI HFULL0 R/LHI R/LHI MASK_ HFULL14 MASK_ HFULL13 MASK_ HFULL12 MASK_ HFULL11 MASK_ HFULL10 MASK_ HFULL9 MASK_ HFULL8 MASK_ HFULL7 MASK_ HFULL6 MASK_ HFULL5 MASK_ HFULL4 MASK_ HFULL3 MASK_ HFULL2 MASK_ HFULL1 MASK_ HFULL0
Flow Control
MCNTRL
Flow Control
AutoNegotiation Base Page Transmit
AutoNegotiation Base Page Receive
AutoNegotiation Next Page Transmit
AutoNegotiation Next Page Receive
Device
Counter Half Full
HFULL15
Counter Half Full Mask
MASK_ HFULL15
Counter
Counter
SEEQ Technology Inc. Proprietary Information
8101
8101
Table Register (MAC Address Register) Definition
0.15
0.14
0.13
0.12
0.11
0.10
0.15 0.14 0.13 0.12 0.11 0.10
Symbol
Name Address, Word
Definition This Words That Comprise 48-Bit Address. Address Used Receive Unicast Address Filtering Automatic Generated Control Pause Frames. corresponds first transmitted received section (DA[0] SA[0] Figure
Def.
x.15 Occurs REGD15
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (MAC Address Register) Definition
1.15
1.14
1.13
1.12
1.11
1.10
1.15 1.14 1.13 1.12 1.11 1.10
Symbol
Name Address, Word
Definition This Words That Comprise 48-Bit Address. Address Used Receive Unicast Address Filtering Automatic Generated Control Pause Frames. corresponds first transmitted received section (DA[0] SA[0] Figure
Def.
x.15 Occurs REGD15
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (MAC Address Register) Definition 2.15 2.14 2.13 2.12 2.11 2.10
2.15 2.14 2.13 2.12 2.11 2.10
Symbol
Name Address, Word
Definition This Words That Comprise 48-Bit Address. Address Used Receive Unicast Address Filtering Automatic Generated Control Pause Frames. corresponds first transmitted received section (DA[0] SA[0] Figure
Def.
x.15 Occurs REGD15
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (MAC Address Filter Register) Definition
3.15 F7[7]
3.14 F7[6]
3.13 F7[5]
3.12 F7[4]
3.11 F7[3]
3.10 F7[2]
F7[1]
F7[0]
F6[7]
F6[6]
F6[5]
F6[4]
F6[3]
F6[2]
F6[1]
F6[0]
3.15 3.14 3.13 3.12 3.11 3.10
Symbol F7[7] F7[6] F7[5] F7[4] F7[3] F7[2] F7[1] F7[0] F6[7] F6[6] F6[5] F6[4] F6[3] F6[2] F6[1] F6[0]
Name Address Filter
Definition This Words That Comprise 64-Bit Address Filter. Address Filter Used Filtering Destination Address Multicast Packets.
Def.
x.15 Occurs REGD15
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (MAC Address Filter Register) Definition
4.15 F5[7]
4.14 F5[6]
4.13 F5[5]
4.12 F5[4]
4.11 F5[3]
4.10 F5[2]
F5[1]
F5[0]
F4[7]
F4[6]
F4[5]
F4[4]
F4[3]
F4[2]
F4[1]
F4[0]
4.15 4.14 4.13 4.12 4.11 4.10
Symbol F5[7] F5[6] F5[5] F5[4] F5[3] F5[2] F5[1] F5[0] F4[7] F4[6] F4[5] F4[4] F4[3] F4[2] F4[1] F4[0]
Name Address Filter
Definition This Words That Comprise 64-Bit Address Filter. Address Filter Used Filtering Destination Address Multicast Packets.
Def.
x.15 Occurs REGD15
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (MAC Address Filter Register) Definition
5.15 F3[7]
5.14 F3[6]
5.13 F3[5]
5.12 F3[4]
5.11 F3[3]
5.10 F3[2]
F3[1]
F3[0]
F2[7]
F2[6]
F2[5]
F2[4]
F2[3]
F2[2]
F2[1]
F2[0]
5.15 5.14 5.13 5.12 5.11 5.10
Symbol F3[7] F3[6] F3[5] F3[4] F3[3] F3[2] F3[1] F3[0] F2[7] F2[6] F2[5] F2[4] F2[3] F2[2] F2[1] F2[0]
Name Address Filter
Definition This Words That Comprise 64-Bit Address Filter. Address Filter Used Filtering Destination Address Multicast Packets.
Def.
x.15 Occurs REGD15
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (MAC Address Filter Register) Definition
6.15 F1[7]
6.14 F1[6]
6.13 F1[5]
6.12 F1[4]
6.11 F1[3]
6.10 F1[2]
F1[1]
F1[0]
F0[7]
F0[6]
F0[5]
F0[4]
F0[3]
F0[2]
F0[1]
F0[0]
6.15 6.14 6.13 6.12 6.11 6.10
Symbol F1[7] F1[6] F1[5] F1[4] F1[3] F1[2] F1[1] F1[0] F0[7] F0[6] F0[5] F0[4] F0[3] F0[2] F0[1] F0[0]
Name Address Filter
Definition This Words That Comprise 64-Bit Address Filter. Address Filter Used Filtering Destination Address Multicast Packets.
Def.
x.15 Occurs REGD15
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (Configuration Register) Definition 7.15 R/WSC IPG0 7.15 7.14 Symbol RXRST 7.14 RXRST R/WSC TXPRMBL Name Reset Receive Reset 7.13 TXRST R/WSC TXCRC 7.12 ANRST R/WSC RXPRMBL Definition Chip Reset, Self Clearing Normal Receive Data Path Reset, Self Clears When Start Packet Detected. Normal Transmit Data, Data Reset, Self Clearing Normal AutoNegotiation Algorithm Restarted, Self Clearing After AutoNegotiation Process Starts Reset Counters Reset Self Clearing Reset Undersize Transmit Pkts Padded Bytes Autopad Tranmsit Bits (IEEE spec Min) Transmit Bits Transmit Bits Transmit Bits Transmit Bits IEEE spec Min) Transmit Bits IEEE spec Min) Transmit Bits IEEE spec Min) Transmit Bits 7.11 CTRRST R/WSC RXCRC 7.10 APAD IPG2 IPG1 PEOF Def.
STSWRD1 STSWRD0
7.13 7.12
TXRST ANRST
Transmit Reset AutoNegotiation Restart Counter Reset AutoPad Enable Transmit Interpacket Select
7.11 7.10
CTRRST APAD IPG2 IPG1 IPG0
TXPRMBL TXCRC RXPRMBL RXCRC STSWRD1 STSWRD0
Transmit Preamble Preamble Added Beginning Transmit Enable Preamble Added Transmit Enable Receive Preamble Enable Receive Enable Receive Status Word Append Select Calculated Added Added Preamble Stored FIFO With Rest Preamble Stripped Stored FIFO With Rest Stripped Reserved Receive Status Word Non-Discarded Pkt's Discarded Pkt's Receive Status Word Non-Discarded Pkt's Receive Status Word Receive Packet Data Receive Receive Status Word x.15 Occurs REGD15
PEOF
Receive Position Select
MD400176/B
SEEQ Technology Inc. Proprietary Information
8101
Table Register (Configuration Register) Definition 8.15 REJUCST 8.15 8.14 8.13 8
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