PCnetTM-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller L
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Am79C971
PCnetTM-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller Local
DISTINCTIVE CHARACTERISTICS
Single-chip Fast Ethernet controller Peripheral Component Interconnect (PCI) local 32-bit glueless host interface Supports clock frequency from independent network clock Supports network operation with clock from High performance mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit utilization specification revision compliant Supports Subsystem/Subvendor Vendor programming through EEPROM interface Supports both 5.0-V 3.3-V signaling environments Plug Play compatible Supports unlimited burst length endian little endian byte alignments supported Integrated 10BASE-T 10BASE-2/5 (AUI) Physical Layer Interface Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3 Blue Book Ethernet-compliant solution Automatic Twisted-Pair receive polarity detection correction Internal 10BASE-T transceiver with Smart Squelch Twisted-Pair medium IEEE 802.3-compliant auto-negotiable 10BASE-T interface Supports General Purpose Serial Interface (GPSI) Media Independent Interface (MII) connecting external 100-Megabit second (Mbps) transceivers IEEE 802.3-compliant Intelligent Auto-Pollexternal status monitor interrupt Includes intelligent on-chip Network Port Manager that provides auto-port selection between MII, on-chip 10BASE-T port, without software support Supports both auto-negotiable auto-negotiable external PHYs Supports 10BASE-T, 100BASE-TX/FX, 100BASE-T4, 100BASE-T2 IEEE 802.3compliant PHYs full- half-duplex Internal/external loopback capabilities ports Supports patented External Address Detection Interface (EADI) Receive frame tagging support internetworking applications Dual-speed CSMA/CD Mbps Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 Blue Book Ethernet standards Full-duplex operation supported AUI, 10BASE-T, MII, GPSI ports with independent Transmit (TX) Receive (RX) channels Flexible buffer architecture Large independent internal FIFOs SRAM-based FIFO buffer extension supporting kilobytes (Kbytes) Gigabit second (Gbps) internal data bandwidth Programmable FIFO watermarks both operations frame queuing high latency host operation Programmable allocation buffer space between queues EEPROM interface supports jumperless design provides through-chip programming Supports full programmability half-/fullduplex operation external Mbps PHYs through EEPROM mapping Extensive status support
Publication# 20550 Rev: Amendment: Issue Date: 2000
Supports Megabyte (Mbyte) optional Boot PROM Flash diskless node application Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead allowing protocol analysis begin before receive frame Includes Programmable Inter Packet (IPG) address less network aggressive controllers Offers Modified Back-Off algorithm address Ethernet Capture Effect IEEE 1149.1-compliant JTAG Boundary Scan test access port interface NAND tree test
mode board-level production connectivity test Implements low-power management critical battery powered application green Includes power-saving sleep modes (sleep snooze) Integrated Magic Packettechnology support remote power networked Software compatible with PCnet Family LANCE/C-LANCE register descriptor architecture Compatible with existing PCnet Family driver/diagnostic software Available 160-pin TQFP 176-pin TQFP packages
GENERAL DESCRIPTION
Am79C971 controller single-chip 32-bit full-duplex, 10/100-Megabit second (Mbps) highlyintegrated Ethernet system solution, designed address high-performance system application requirements. flexible mastering device that used application, including network-ready bridge/router designs. master architecture provides high data throughput system system utilization. Am79C971 controller fabricated with AMD's advanced low-power Complementary Metal Oxide Semiconductor (CMOS) process provide operating standby current power sensitive applications. Am79C971 controller complete Ethernet node integrated into single VLSI device. contains interface unit, Direct Memory Access (DMA) Buffer Management Unit, ISO/IEC 8802-3 (IEEE 802.3)compliant Media Access Controller (MAC), large Transmit FIFO large Receive FIFO, SRAMbased FIFO extension with support 128K bytes external frame buffering, IEEE 802.3u-compliant MII, IEEE 802.3-compliant Twisted-Pair Transceiver Media Attachment Unit (10BASE-T MAU), IEEE 802.3-compliant Attachment Unit Interface (AUI). Both proprietary full-duplex IEEE 802.3 compliant half-duplex operation supported MII, AUI, GPSI, 10BASE-T interfaces. 10Mbps operation supported through MII, AUI, 10BASE-T interfaces, Mbps operation supported through MII. 10BASE-T interface includes IEEE 802.3-compliant auto-negotiation implementation, which will automatically negotiate between half- full-duplex with another IEEE 802.3compliant auto-negotiation 10BASE-T device. Am79C971 controller register compatible with LANCE (Am7990) Ethernet controller, CLANCE (Am79C90) Ethernet controller, Ethernet controllers PCnet Family except ILACC (Am79C900), including PCnet-ISA controller (Am79C960),PCnet-ISA+ controller (Am79C961), PCnet-ISA controller (Am79C961A), PCnet-32 controller (Am79C965), PCnet-PCI controller (Am79C970), PCnet-PCI controller (Am79C970A). Buffer Management Unit supports LANCE PCnet descriptor software models. 32-bit multiplexed interface unit provides direct interface local bus, simplifying design Ethernet node system. Am79C971 controller provides complete interface Expansion Flash device allowing add-on card designs with only single load interface pin. With built-in support both little endian byte alignment, this controller also addresses non-PC applications. Am79C971 controller's advanced CMOS design allows interface connected either +5-V +3.3-V signaling environment. compliant IEEE 1149.1 JTAG test interface board-level testing also provided, well NAND tree test structure those systems that cannot support JTAG interface. Am79C971 controller supports auto-configuration configuration space. Additional Am79C971 controller configuration parameters, including unique IEEE physical address, read from external non-volatile memory (EEPROM) immediately following system reset. integrated Manchester encoder/decoder (MENDEC) eliminates need external Serial Interface Adapter (SIA) system. built-in GPSI allows MENDEC bypassed.
Am79C971
addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity, activity, link active, address match, full-duplex, select, Mbps, jabber status. Am79C971 controller also provides EADI allow external hardware address filtering internetworking applications receive frame tagging feature. power sensitive applications where standby current desired, device incorporates sleep functions reduce overall system power consumption, excellent notebooks green PCs. conjunction with these power modes, PCnet-FAST controller also integrated functions support Magic Packet technology, inexpensive technology that allows remote wake networked PCs. controller capability automatically select either MII, AUI, Twisted-Pair transceiver. Only interface active time. network interfaces programmed operate either half-duplex full-duplex mode (AUI full-duplex only supports 10BASE-F standard). dual Transmit Receive FIFOs optimize system overhead, providing sufficient latency tolerance Mbps 100-Mbps systems where latencies
guaranteed during frame transmission reception. highly loaded 10-Mbps systems, such servers when using controller 100-Mbps environment, additional frame buffering capability provided 16-bit wide SRAM interface provides high performance high latency tolerance system network. Am79C971 controller Kbytes SRAM extension dual Transmit Receive FIFOs. When SRAM used, Am79C971 controller's FIFOs programmed bypass SRAM interface. IMPORTANT NOTE: SRAM configuration" only valid 10Mb mode. 100Mb mode, SRAM mandatory must always used. ISO/IEC 8802-3 IEEE 802.3 will used interchangeably when referring half-duplex Mbps networks. IEEE 802.3 IEEE 802.3u will used interchangeably only when referring half-duplex 100Mbps Ethernet networks, since IEEE standard approved yet. Full-duplex proprietary standard approved IEEE ISO.
Am79C971
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below.
Am79C971
ALTERNATE PACKAGING OPTION Trimmed formed tray TEMPERATURE RANGE Commercial +70° PACKAGE TYPE Plastic Quad Flat Pack (PQR160) Thin Quad Flat Pack (PQL176) SPEED OPTION applicable
DEVICE NUMBER/DESCRIPTION Am79C971 Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller Local
Valid Combinations Am79C971 KC\W, VC\W
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C971
BLOCK DIAGRAM
EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS ERAMCS AS_EBOE EBWE EBCLK
Expansion Interface
GPSI Port
AD[31:00] C/BE[3:0] FRAME TRDY IRDY STOP IDSEL DEVSEL PERR SERR INTA SLEEP
Interface Unit
FIFO
FIFO
Port
802.3 Core FIFO FIFO EADI Port
TXEN TXCLK TXDAT RXEN RXCLK RXDAT CLSN TX_E TXD[3:0] TX_EN TX_CLK RXD[3:0] RX_ER RX_CLK RX_DV MDIO SRDCLK SF/BD RXFRTGD/MIIRXFRTGD RXFRTGE/MIIRXFRTGE XTAL1 XTAL2 DO+/DI+/CI+/TXD+/TXP+/RXD+/EECS EESK EEDI EEDO LED0 LED1 LED2 LED3
Network Port Manager Buffer Management Unit FIFO Control
Manchester Encoder/ Decoder (PLS) Port
Auto Negotiation
10BASE-T
JTAG Port Control
93C46 EEPROM Interface
Control
20550D-1
Am79C971
TABLE CONTENTS
AM79C971 DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION ORDERING INFORMATION Standard Products BLOCK DIAGRAM. RELATED PRODUCTS CONNECTION DIAGRAM (PQR160) CONNECTION DIAGRAM (PQL176) DESIGNATIONS (PQR160) Listed Number DESIGNATIONS (PQL176). Listed Number DESIGNATIONS (PQR160, PQL176). Listed Group DESIGNATIONS Listed Group DESIGNATIONS Listed Group Listed Driver Type DESCRIPTIONS Interface AD[31:0] C/BE[3:0] DEVSEL. FRAME IDSEL INTA IRDY. PERR Board Interface LED0 LED1 LED2 LED3 SLEEP XTAL1 XTAL2 EEPROM Interface EECS EEDI EEDO. EESK Expansion Interface EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS ERAMCS AS_EBOE EBWE EBCLK Media Independent Interface
Am79C971
TX_CLK TXD[3:0]. TX_EN TX_ER RX_CLK RXD[3:0] RX_DV RX_ER MDC. MDIO Attachment Unit Interface CI±. DI±. DO±. 10BASE-T Interface RXD± TXD±. TXP± General Purpose Serial Interface CLSN RXCLK RXDAT RXEN TXCLK TXDAT TXEN External Address Detection Interface SFBD SRDCLK RXFRTGD RXFRTGE MIIRXFRTGD. MIIRXFRTGE. IEEE 1149.1 (1990) Test Access Port Interface. Power Supply Pins AVDDB. AVSSB VDD_PLL VSS_PLL VDDB VSSB VDD_PCI BASIC FUNCTIONS System Interface. Software Interface Network Interfaces DETAILED FUNCTIONS Slave Interface Unit.
Am79C971
Slave Configuration Transfers Slave Transfers. Master Interface Unit Buffer Management Unit Software Interrupt Timer Media Access Control Transmit Operation. Receive Operation Loopback Operation. Manchester Encoder/Decoder Attachment Unit Interface Twisted-Pair Transceiver General Purpose Serial Interface Full-Duplex Operation Media Independent Interface Auto-Negotiation Automatic Network Port Selection External Address Detection Interface (EADI). Expansion Interface EEPROM Interface Support Power Savings Modes IEEE 1149.1 (1990) Test Access Port Interface. contents Device register same contents CSR88. .100 NAND Tree Testing .100 Reset .102 Software Access .102 USER ACCESSIBLE REGISTERS .106 Configuration Registers .108 Register .114 Control Status Registers .115 Configuration Registers .148 Initialization Block .180 Receive Descriptors. .183 Transmit Descriptors .186 REGISTER SUMMARY .190 Configuration Registers .190 Control Status Registers .191 Configuration Registers .195 REGISTER PROGRAMMING SUMMARY .196 Am79C971 Programmable Registers .196 ABSOLUTE MAXIMUM RATINGS .200 OPERATING RANGES .200 CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED .200 SWITCHING CHARACTERISTICS: INTERFACE. .203 SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE .206 SWITCHING CHARACTERISTICS: ATTACHMENT UNIT INTERFACE. .207 SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE .208 SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE .209 SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE .210 SWITCHING WAVEFORMS .211 SWITCHING TEST CIRCUITS .211 SWITCHING WAVEFORMS: SYSTEM INTERFACE .213 SWITCHING WAVEFORMS: EXPANSION INTERFACE. .217 SWITCHING WAVEFORMS: 10BASE-T INTERFACE .219 SWITCHING WAVEFORMS: ATTACHMENT UNIT INTERFACE .221 SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE .224
Am79C971
SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE .226 SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE. .227 SWITCHING WAVEFORMS: RECEIVE FRAME TAG. .228 PHYSICAL DIMENSIONS* .229 PQR160 .229 PQL176 .230 AM79C971 COMPATIBLE MEDIA INTERFACE MODULES .A-1 RECOMMENDATION POWER GROUND DECOUPLING. .B-1 ALTERNATIVE METHOD INITIALIZATION* .C-1 LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT. .D-1 AUTO-NEGOTIATION REGISTERS AM79C971A PCNET-FAST 10/100 MBPS ETHERNET CONTROLLER ERRATA
Am79C971
RELATED PRODUCTS
Part Am79C90 Am7996 Am79C98 Am79C100 Am79865 An79866A Am79C870 Am79C871 Am79C940 Am79C960 Am79C961 Am79C961A Am79C965 Am79C970A Am79C981 Am79C987
Description CMOS Local Area Network Controller Ethernet (C-LANCE) IEEE 802.3/Ethernet/Cheapernet Transceiver Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) Mbps Physical Data Transmitter (PDT) Mbps Physical Data Receiver (PDR) Quad 100BASE-X Transceiver Quad 100BASE-X Repeater Transceiver Media Access Controller Ethernet (MACETM) PCnet-ISA Single-Chip Ethernet Controller (for bus) PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug Play support) PCnet-ISA Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug Play support) PCnet-32 Single-Chip 32-Bit Ethernet Controller (for buses) PCnet-PCI Single-Chip Full-Duplex Ethernet Controller Local Integrated Multiport Repeater Plus(IMR+TM) Hardware Implemented Management Information Base(HIMIBTM)
Am79C971
CONNECTION DIAGRAM (PQR160)
marked orientation.
20550D-2
VDD_PCI VSSB ERAMCS EBROMCS EBWE AS_EBOE EBCLK EBUA_EBA0 EBUA_EBA1 EBUA_EBA2 EBUA_EBA3 VSSB EBUA_EBA4 VDDB EBUA_EBA5 EBUA_EBA6 EBUA_EBA7 VDDB EBDA8 EBDA9 EBDA10 EBDA11 VSSB EBDA12 EBDA13 EBDA14 EBDA15 EBD7 EBD6 VSSB EBD5
IDSEL AD23 AD22 AD21 AD20 VDD_PCI AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP VSSB PERR SERR VDD_PCI C/BE1 AD15 AD14 AD13 AD12 VSSB AD11 AD10 C/BE0 VSSB
AD24 C/BE3 VSSB AD25 VDD_PCI AD26 AD27 AD28 AD29 AD30 AD31 VSSB INTA VDD_PCI EECS VSSB EESK/LED1/SFBD LED2/SRDCLK/MIIRXFRTGE EEDI/LED0 EEDO/LED3/SRD/MIIRXFRTGD VDDB VDD_PLL CIDI+ DIAVDDB DOAVSSB
PCnetTM-FAST
Am79C971 KC/W Am79C971
XTAL2 VSS_PLL XTAL1 AVDDB TXD+ TXP+ TXDTXPAVDDB RXD+ RXDVSS MDIO SLEEP/EAR RXD3 RXD2 RXD1 RXD0/RXFRTGD VDDB RX_DV/RXFRTGE RX_CLK/RXCLK RX_ER/RXDAT VSSB TX_ER TX_CLK/TXCLK TX_EN/TXEN VDDB TXD0/TXDAT TXD1 TXD2 TXD3 COL/CLSN CRS/RXEN VSSB EBD0 EBD1 EBD2 EBD3 EBD4
2055A-2
Am79C971
CONNECTION DIAGRAM (PQL176)
VDD_PCI VSSB ERAMCS EBROMCS EBWE AS_EBOE EBCLK EBUA_EBA0 EBUA_EBA1 EBUA_EBA2 EBUA_EBA3 VSSB EBUA_EBA4 VDDB EBUA_EBA5 EBUA_EBA6 EBUA_EBA7 VDDB EBDA8 EBDA9 EBDA10 EBDA11 VSSB EBDA12 EBDA13 EBDA14 EBDA15 EBD7 EBD6 VSSB EBD5
IDSEL AD23 AD22 AD21 AD20 VDD_PCI AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP VSSB PERR SERR VDD_PCI C/BE1 AD15 AD14 AD13 AD12 VSSB AD11 AD10 C/BE0 VSSB
AD24 C/BE3 VSSB AD25 VDD_PCI AD26 AD27 AD28 AD29 AD30 AD31 VSSB INTA VDD_PCI EECS VSSB EESK/LED1/SFBD LED2/SRDCLK/MIIRXFRTGE EEDI/LED0 EEDO/LED3/SRD/MIIRXFRTGD VDDB VDD_PLL CIDI+ DIAVDDB DOAVSSB
FAST Am79C971 VC/W Am79C971 VC/W
XTAL2 VSS_PLL XTAL1 AVDDB TXD+ TXP+ TXDTXPAVDDB RXD+ RXDVSS MDIO SLEEP/EAR RXD3 RXD2 RXD1 RXD0/RXFRTGD VDDB RX_DV/RXFRTGE RX_CLK/RXCLK RX_ER/RXDAT VSSB TX_ER TX_CLTXCLK TX_EN/TXEN VDDB TXD0/TXDAT TXD1 TXD2/RXEN TXD3 COL/CLSN CRS/RXEN VSSB EBD0 EBD1 EBD2 EBD3 EBD4
20550D-3
marked orientation.
Am79C971
DESIGNATIONS (PQR160) Listed Number
Name IDSEL AD23 AD22 AD21 AD20 VDD_PCI AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP VSSB PERR SERR VDD_PCI C/BE1 AD15 AD14 AD13 AD12 VSSB AD11 AD10 C/BE0 VSSB Name VDD_PCI VSSB ERAMCS EROMCS EBWE AS_EBOE EBCLK EBUA_EBA0 EBUA_EBA1 EBUA_EBA2 EBUA_EBA3 VSSB EBUA_EBA4 VDDB EBUA_EBA5 EBUA_EBA6 EBUA_EBA7 VDDB EBDA8 EBDA9 EBDA10 EBDA11 VSSB EBDA12 EBDA13 EBDA14 EBDA15 EBD7 EBD6 VSSB EBD5 Name EBD4 EBD3 EBD2 EBD1 EBD0 VSSB CRS/RXEN COL/CLSN TXD3 TXD2 TXD1 TXD0/TXDAT VDDB TX_EN/TXEN TX_CLK/TXCLK TX_ER VSSB RX_ER/RXDAT RX_CLK/RXCLK RX_DV/RXFRTGE VDDB RXD0/RXFRTGD RXD1 RXD2 RXD3 SLEEP/EAR MDIO RXDRXD+ AVDDB TXPTXDTXP+ TXD+ AVDDB XTAL1 VSS_PLL XTAL2 Name AVSSB DODO+ AVDDB DIDI+ CICI+ VDD_PLL VDDB EEDO/LED3/SRD/ MIIRXFRTGD EED1/LED0 LED2/SRDCLK/ MIIRXFRTGE EESK/LED1/SFBD VSSB EECS VDD_PCI INTA VSSB AD31 AD30 AD29 AD28 AD27 AD26 VDD_PCI AD25 VSSB C/BE3 AD24
Am79C971
DESIGNATIONS (PQL176) Listed Number
Name IDSEL AD23 AD22 AD21 AD20 VDD_PCI AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP VSSB PERR SERR VDD_PCI C/BE1 AD15 AD14 AD13 AD12 VSSB AD11 AD10 C/BE0 VSSB Name VDD_PCI VSSB ERAMCS EROMCS EBWE AS_EBOE EBCLK EBUA_EBA0 EBUA_EBA1 EBUA_EBA2 EBUA_EBA3 VSSB EBUA_EBA4 VDDB EBUA_EBA5 EBUA_EBA6 EBUA_EBA7 VDDB EBDA8 EBDA9 EBDA10 EBDA11 VSSB EBDA12 EBDA13 EBDA14 EBDA15 EBD7 EBD6 VSSB EBD5 Name EBD4 EBD3 EBD2 EBD1 EBD0 VSSB CRS/RXEN COL/CLSN TXD3 TXD2/RXEN TXD1 TXD0/TXDAT VDDB TX_EN/TXEN TX_CLK/TXCLK TX_ER VSSB RX_ER/RXDAT RX_CLK/RXCLK RX_DV/RXFRTGE VDDB RXD0/RXFRTGD RXD1 RXD2 RXD3 SLEEP/EAR MDIO RXDRXD+ AVDDB TXPTXDTXP+ TXD+ AVDDB XTAL1 VSS_PLL XTAL2 Name AVSSB DODO+ AVDDB DIDI+ CICI+ VDD_PLL VDDB EEDO/LED3/SRD/ MIIRXFRTGD EED1/LED0 LED2/SRDCLK/ MIIRXFRTGE EESK/LED1/SFBD VSSB EECS VDD_PCI INTA VSSB AD31 AD30 AD29 AD28 AD27 AD26 VDD_PCI AD25 VSSB C/BE3 AD24
Am79C971
DESIGNATIONS (PQR160, PQL176) Listed Group
Name Interface AD[31:0] C/BE[3:0] DEVSEL FRAME IDSEL INTA IRDY PERR SERR STOP TRDY Board Interface LED0 LED1 LED2 LED3 SLEEP XTAL1 XTAL2 EEPROM Interface EECS EEDI EEDO EESK AS_EBOE EBCLK EBD[7:0] EBDA[15:8] EBUA_EBA[7:0] EBWE ERAMCS EROMCS Serial EEPROM Chip Select Serial EEPROM Data Serial EEPROM Data Serial EEPROM Clock Address Strobe/Expansion Output Enable Expansion Clock Expansion Data [7:0] Expansion Data/Address [15:8] Expansion Upper Address /Expansion Address [7:0] Expansion Write Enable Expansion Chip Select Expansion Chip Select LED0 LED1 LED2 LED3 Sleep Mode Crystal Input Crystal Output XTAL Address/Data Command/Byte Enable Clock Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Parity Parity Error Request Reset System Error Stop Target Ready STS6 STS6 STS6 STS6 STS6 STS6 Function Type1 Driver Pins
Expansion Interface
Note: including test features
Am79C971
DESIGNATIONS Listed Group
Name Function Type1 Media Independent Interface (MII) Collision Carrier Sense Management Data Clock MDIO Management Data RX_CLK Receive Clock RXD[3:0] Receive Data RX_DV Receive Data Valid RX_ER Receive Error TX_CLK Transmit Clock TXD[3:0] Transmit Data TX_EN Transmit Data Enable TX_ER Transmit Error Attachment Unit Interface (AUI) Collision Data Data 10BASE-T Interface RXD+/RXDReceive Differential Pair TXD+/TXDTransmit Differential Pair TXP+/TXPTransmit Pre-distortion Differential Pair General Purpose Serial Interface (GPSI) CLSN Collision RXCLK Receive Clock RXDAT Receive Data RXEN Receive Enable TXCLK Transmit Clock TXDAT Transmit Data TXEN Transmit Enable External Address Detection Interface (EADI) External Address Reject SFBD Start Frame Byte Delimiter Serial Receive Data SRDCLK Serial Receive Data Clock Receive Frame Data/MII Receive Frame RXFRTGD/MIIRXFRTGD Data Receive Frame Enable/MII Receive Frame RXFRTGE/MIIRXFRTGE Enable IEEE 1149.1 Test Access Port Interface (JTAG) Test Clock Test Data Test Data Test Mode Select Note: including test features.
Driver OMII2 TSMII OMII1 OMII1 OMII1
Pins
Am79C971
DESIGNATIONS Listed Group
Name Power Supplies AVDDB AVSSB VDD_PLL VSS_PLL VDDB VSSB VDD_PCI Function Analog Buffer Power Analog Buffer Ground Analog Power Analog Ground Digital Power Digital Ground Buffer Power Buffer Ground Buffer Power Type1 Driver Pins
Note: including test features.
Listed Driver Type
following table describes various types output drivers used Am79C971 controller. values shown table apply signaling. Characteristics section values applying signaling.
Name OMII1 OMII2 STS6 TSMII Type Totem Pole Totem Pole Totem Pole Open Drain Sustained Tri-State Tri-State Tri-State Tri-State
sustained tri-state signal active signal that driven high clock period before left floating. TDO, differential output drivers. Their characteristics XTAL output described Characteristics section.
(mA)
(mA) -0.4 -0.4
Load (pF)
Am79C971
DESCRIPTIONS Interface AD[31:0]
Address Data Input/Output Address data multiplexed same interface pins. During first clock transaction, AD[31:0] contain physical address bits). During subsequent clocks, AD[31:0] contain data. Byte ordering little endian default. AD[07:0] defined least significant byte (LSB) AD[31:24] defined most significant byte (MSB). FIFO data transfers, Am79C971 controller programmed endian byte ordering. CSR3, (BSWP) more details. During address phase transaction, when Am79C971 controller master, AD[31:2] will Am79C971 controller always drives AD[1:0] '00' during address phase indicating linear burst order. When Am79C971 controller master, AD[31:0] lines continuously monitored determine address match exists slave transfers. During data phase transaction, AD[31:0] driven Am79C971 controller when performing master write slave read operations. Data AD[31:0] latched Am79C971 controller when performing master read slave write operations. When active, AD[31:0] inputs NAND tree testing.
eration section details. Am79C971 controller will support clock frequency after certain precautions taken ensure data integrity. This clock derivation used drive network functions. When active, input NAND tree testing.
DEVSEL
Device Select Input/Output Am79C971 controller drives DEVSEL when detects transaction that selects device target. device samples DEVSEL detect target claims transaction that Am79C971 controller initiated. When active, DEVSEL input NAND tree testing.
FRAME
Cycle Frame Input/Output FRAME driven Am79C971 controller when master indicate beginning duration transaction. FRAME asserted indicate transaction beginning. FRAME asserted while data transfers continue. FRAME deasserted before final data phase transaction. When Am79C971 controller slave mode, samples FRAME determine address phase transaction. When active, FRAME input NAND tree testing.
C/BE[3:0]
Command Byte Enables Input/Output command byte enables multiplexed same interface pins. During address phase transaction, C/BE[3:0] define command. During data phase, C/BE[3:0] used byte enables. byte enables define which physical byte lanes carry meaningful data. C/BE0 applies byte (AD[07:0]) C/BE3 applies byte (AD[31:24]). function byte enables independent byte ordering mode (BSWP, CSR3, When active, C/BE[3:0] inputs NAND tree testing.
Grant Input This signal indicates that access been granted Am79C971 controller. Am79C971 controller supports parking. When idle system arbiter asserts without active from Am79C971 controller, device will drive AD[31:0], C/BE[3:0] lines. When active, input NAND tree testing.
Clock Input This clock used drive system interface internal buffer management unit. signals sampled rising edge parameters defined with respect this edge. Am79C971 controller normally operates over frequency range networking demands. Frequency Demands Network
IDSEL
Initialization Device Select Input This signal used chip select Am79C971 controller during configuration read write transactions. When active, IDSEL input NAND tree testing.
including test features.
Am79C971
INTA
Interrupt Request Output
Name MAPINT
Table Interrupt Flags
Description Auto-Poll Interrupt Mask CSR7, Interrupt CSR7,
attention signal which indicates that more following status flags set: BABL, EXDINT, IDON, JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MCCINT, MPDTINT, MAPINT, MREINT, STINT. Each status flag either mask enable which allows suppression INTA assertion. Table shows flag meanings. Table
Name BABL EXDINT IDON MERR MISS MFCO MPINT RCVCCO RINT SLPINT SINT TINT TXSTRT UINT Description Babble Excessive Deferral Initialization Done Jabber Memory Error
MREINT
Management CSR7, Frame Read Error Interrupt Software Timer CSR7, Interrupt
CSR7,
STINT
CSR7,
Interrupt Flags
Mask CSR3, CSR5, CSR3, CSR4, CSR3, Interrupt CSR0, CSR5, CSR0, CSR4, CSR0, CSR0, CSR4, CSR5, CSR4, CSR0, CSR5, CSR5, CSR0, CSR4, CSR4,
default INTA open-drain output. applications that need high-active edge-sensitive interrupt signal, INTA configured this mode setting INTLEVEL (BCR2, When active, INTA output NAND tree testing.
IRDY
Initiator Ready Input/Output IRDY indicates ability initiator transaction complete current data phase. IRDY used conjunction with TRDY. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When Am79C971 controller master, asserts IRDY during write data phases indicate that valid data present AD[31:0]. During read data phases, device asserts IRDY indicate that ready accept data. When Am79C971 controller target transaction, checks IRDY during write data phases determine valid data present AD[31:0]. During read data phases, device checks IRDY determine initiator ready accept data. When active, IRDY input NAND tree testing.
Missed Frame CSR3, Missed Frame Count OverCSR4, flow Magic Packet Interrupt CSR5,
Receive Collision Count CSR4, Overflow Receive Interrupt System Error Transmit Interrupt Transmit Start User Interrupt Internal Management Command Complete Interrupt Management Command Complete Interrupt CSR3,
Sleep Interrupt CSR5, CSR5, CSR3, CSR4, CSR4,
CSR7, CSR7,
MCCIINT
Parity
Input/Output
MCCINT
CSR7,
CSR7,
MPDTINT
Detect CSR7, Transition Interrupt
Parity even parity across AD[31:0] C/BE[3:0]. When Am79C971 controller master, generates parity during address write data phases. checks parity during read data phases. When Am79C971 controller operates slave mode, checks parity during every address phase. When target cycle, checks parity during write data phases generates parity during read data phases. When active, input NAND tree testing.
CSR7,
Am79C971
PERR
Parity Error Input/Output During slave write transaction master read transaction, Am79C971 controller asserts PERR when detects data parity error reporting error enabled setting PERREN (PCI Command register, During master write transaction, Am79C971 controller monitors PERR target reports data parity error. When active, PERR input NAND tree testing.
controller checks STOP determine target wants disconnect current transaction. When active, STOP input NAND tree testing.
TRDY
Target Ready Input/Output TRDY indicates ability target transaction complete current data phase. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When Am79C971 controller master, checks TRDY during read data phases determine valid data present AD[31:0]. During write data phases, device checks TRDY determine target ready accept data. When Am79C971 controller target transaction, asserts TRDY during read data phases indicate that valid data present AD[31:0]. During write data phases, device asserts TRDY indicate that ready accept data. When active, TRDY input NAND tree testing.
Request Input/Output Am79C971 controller asserts signal that wishes become master. driven high when Am79C971 controller does request bus. During Magic Packet mode, will driven. When active, input NAND tree testing.
Reset Input When asserted low, then Am79C971 controller performs internal system reset type H_RESET (HARDWARE_RESET, section RESET). must held minimum clock periods. While H_RESET state, Am79C971 controller will disable deassert outputs. asynchronous clock when asserted deasserted. When active, NAND tree testing enabled.
Board Interface
Note: Before programming pins, description LEDPE BCR2, first.
LED0
LED0 Output This output designed directly drive LED. default, LED0 indicates active link connection 10BASE-T interface. This also programmed indicate other network status (see BCR4). LED0 polarity programmable, default active LOW. When LED0 polarity programmed active LOW, output open drain driver. When LED0 polarity programmed active HIGH, output totem pole driver. Note: LED0 multiplexed with EEDI pin. When active, LED0 input NAND tree testing.
SERR
System Error Input/Output During slave transaction, Am79C971 controller asserts SERR when detects address parity error, reporting error enabled setting PERREN (PCI Command register, SERREN (PCI Command register, default SERR open-drain output. component test, programmed active-high totem-pole output. When active, SERR input NAND tree testing.
LED1
LED1 Output This output designed directly drive LED. default, LED1 indicates receive activity network. This also programmed indicate other network status (see BCR5). LED1 polarity programmable, default, active LOW. When LED1 polarity programmed active LOW, output open drain driver. When LED1
STOP
Stop Input/Output slave mode, Am79C971 controller drives STOP signal inform master stop current transaction. master mode, Am79C971
Am79C971
larity programmed active HIGH, output totem pole driver. Note: LED1 multiplexed with EESK SFBD pins. LED1 also used during EEPROM AutoDetection determine whether EEPROM present Am79C971 controller interface. last rising edge while active LOW, LED1 sampled determine value EEDET BCR19. important maintain adequate hold time around rising edge this time ensure correctly sampled value. sampled HIGH value means that EEPROM present, EEDET will sampled value means that EEPROM present, EEDET will EEPROM Auto-Detection section more details. circuit attached this pin, then pull pull down resistor must attached instead order resolve EEDET setting. When active, LED1 input NAND tree testing. WARNING: input signal level LED1 must insured correct EEPROM detection before deassertion RST.
while EEPROM used system, then buffering required between LED3 circuit. circuit were directly attached this pin, would create requirement that could serial EEPROM attached this pin. EEPROM included system design, then LED3 signal directly connected without buffering. more details regarding connection, section Support. Note: LED3 multiplexed with EEDO, SRD, MIIRXFRTGD pins. When active, LED3 input NAND tree testing.
SLEEP
Sleep Input When SLEEP asserted, Am79C971 controller performs internal system reset H_RESET type then proceeds into power savings mode. Am79C971 controller outputs will placed their normal reset condition. Am79C971 controller inputs will ignored except SLEEP itself. system must refrain from starting network operations Am79C971 controller seconds following deassertion SLEEP order allow internal analog circuits stabilize. effects with Magic Packetmodes, Magic Packet section. Both XTAL1 inputs must have valid clock signals present order SLEEP command take effect. SLEEP should asserted during power supply ramp desired that SLEEP asserted power supply ramp then system must delay assertion SLEEP until three clock cycles after completion hardware reset. WARNING: SLEEP must left unconnected. should tied power saving mode used. Note: SLEEP multiplexed with pin. When active, SLEEP input NAND tree testing.
LED2
LED2 Output This output designed directly drive LED. default, LED2 indicates correct receive polarity 10BASE-T interface. This also programmed indicate other network status (see BCR6). LED2 polarity programmable, default active LOW. When LED2 polarity programmed active LOW, output open drain driver. When LED2 polarity programmed active HIGH, output totem pole driver. Note: LED2 multiplexed with SRDCLK MIIRXFRTGE pins. When active, LED2 input NAND tree testing.
LED3
LED3 Output This output designed directly drive LED. default, LED3 indicates transmit activity network. This also programmed indicate other network status (see BCR7). LED3 polarity programmable, default active LOW. When LED3 polarity programmed active LOW, output open drain driver. When LED3 polarity programmed active HIGH, output totem pole driver. Special attention must given external circuitry attached this pin. When this used drive
XTAL1
Crystal Oscillator Input internal clock generator uses 20-MHz crystal that attached pins XTAL1 XTAL2. network data rate one-half crystal frequency. XTAL1 alternatively driven using external 20-MHz CMOS level clock signal. Refer section External Crystal Characteristics more details. This clock always required whether inter 10BASE-T/AUI ports enabled. internal
Am79C971
used, ±10% accuracy sufficient clock source. Note: When Am79C971 controller coma mode, there internal resistor from XTAL1 ground. external source drives XTAL1, some power consumption will consumed driving this resistor. XTAL1 driven this time, power consumption will minimized. this case, XTAL1 must remain active least cycles after assertion SLEEP deassertion REQ.
Note: EEDO multiplexed with LED3, MIIRXFRTGD, pins. When active, EEDO input NAND tree testing.
EESK
EEPROM Serial clock Input/Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EESK connected EEPROM's clock pin. controlled either Am79C971 controller directly during read entire EEPROM, indirectly host system writing BCR19, Note: EESK multiplexed with LED1 SFBD pins. EESK also used during EEPROM AutoDetection determine whether EEPROM present Am79C971 controller interface. rising edge last edge while asserted, EESK sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will sampled value means that EEPROM present, EEDET will EEPROM Auto-Detection section more details. circuit attached this pin, then pull pull down resistor must attached instead resolve EEDET setting. When active, EESK input NAND tree testing. WARNING: input signal level EESK must valid correct EEPROM detection before deassertion RST.
XTAL2
Crystal Oscillator Output internal clock generator uses 20-MHz crystal that attached pins XTAL1 XTAL2. network data rate one-half crystal frequency. external clock source used XTAL1, then XTAL2 should left unconnected.
EEPROM Interface EECS
EEPROM Chip Select Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EECS connected EEPROM's chip select pin. controlled either Am79C971 controller during command portions read entire EEPROM, indirectly host system writing BCR19, When active, EECS input NAND tree testing.
EEDI
EEPROM Data Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EEDI connected EEPROM's data input pin. controlled either Am79C971 controller during command portions read entire EEPROM, indirectly host system writing BCR19, Note: EEDI multiplexed with LED0 pin. When active, EEDI input NAND tree testing.
Expansion Interface EBUA_EBA[7:0]
Expansion Upper Address/ Expansion Address [7:0] Output
EEDO
EEPROM Data Input This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EEDO connected EEPROM's data output pin. controlled either Am79C971 controller during command portions read entire EEPROM, indirectly host system reading from BCR19,
EBUA_EBA[7:0] pins provide least most significant bytes address Expansion Bus. most significant address byte (address bits [15:8] during SRAM accesses; address bits [19:16] during boot device accesses) valid these pins beginning SRAM boot device access, rising edge AS_EBOE. This upper address byte must stored externally flip-flop. During subsequent cycles SRAM boot device access, address bits [7:0] present these pins. EBUA_EBA[7:0] outputs forced constant level conserve power while access Expansion being performed.
Am79C971
EBDA[15:8]
Expansion Data/Address [15:8] Input/Output When ERAMCS asserted, EBDA[15:8] contain data bits [15:8] SRAM accesses. When EROMCS asserted low, EBDA[15:8] contain address bits [15:8] boot device accesses. EBDA[15:8] signals driven constant level conserve power while access Expansion being performed.
clock used drive Expansion cycles depends values EBCS CLK_FAC settings BCR27. Refer SRAM Interface Bandwidth Requirements section details determining required EBCLK frequency. clock source other than EBCLK programmed (BCR27, bits 5:3) used Expansion interface, this input should tied through resistor. EBCLK used drive interface, internal buffer management unit, network functions.
EBD[7:0]
Expansion Data [7:0] Input/Output EBD[7:0] pins provide data bits [7:0] RAM/ROM accesses. EBD[7:0] signals internally forced constant level conserve power while access Expansion being performed.
Media Independent Interface TX_CLK
Transmit Clock Input TX_CLK continuous clock input that provides timing reference transfer TX_EN, TXD[3:0], TX_ER signals Am79C971 device. TX_CLK must provide nibble rate clock (25% network data rate). Hence, transceiver operating Mbps must provide TX_CLK frequency transceiver operating Mbps must provide TX_CLK frequency MHz. Note: TX_CLK multiplexed with TXCLK pin.
EROMCS
Expansion Chip Select Output EROMCS serves chip select boot device. asserted during data phases boot device accesses.
ERAMCS
Expansion Chip Select Output ERAMCS asserted during SRAM read write operations expansion bus.
When active, TX_CLK input NAND tree testing. port selected, TX_CLK left floating.
AS_EBOE
Address Strobe/Expansion Output Enable Output
TXD[3:0]
Transmit Data Output TXD[3:0] nibble-wide transmit data bus. Valid data generated TXD[3:0] every TX_CLK rising edge while TX_EN asserted. While TX_EN deasserted, TXD[3:0] values driven TXD[3:0] transitions synchronous TX_CLK rising edges. Note: TXD[0] multiplexed with TXDAT pin. When active, TXD[3:0] inputs NAND tree testing. port selected, TXD[3:0] pins left floating.
AS_EBOE functions address strobe upper address bits EBUA_EBA[7:0] pins output enable Expansion Bus. address strobe, rising edge AS_EBOE supplied beginning SRAM boot device accesses. This rising edge provides clock edge `374 D-type edge-triggered flip-flop which must store upper address byte during Expansion accesses EPROM/Flash/SRAM. AS_EBOE asserted active during boot device SRAM read operations expansion deasserted during boot device SRAM write operations.
TX_EN
Transmit Enable Output TX_EN indicates when Am79C971 device presenting valid transmit nibbles MII. While TX_EN asserted, Am79C971 device generates TXD[3:0] TX_ER TX_CLK rising edges. TX_EN asserted with first nibble preamble remains asserted throughout duration packet until deasserted prior first TX_CLK following final
EBWE
Expansion Write Enable Output EBWE provides write enable write accesses SRAM devices and/or Flash device.
EBCLK
Expansion Clock Input EBCLK used fundamental clock drive Expansion access cycles. actual internal
Am79C971
nibble frame. TX_EN transitions synchronous TX_CLK rising edges. Note: TX_EN multiplexed with TXEN pin. When active, TX_EN input NAND tree testing. port selected, TX_EN left floating.
switches RX_CLK TX_CLK, must provide glitch-free clock pulses. Note: RX_CLK multiplexed with RXCLK pin. When active, RX_CLK input NAND tree testing. port selected, RX_CLK left floating.
TX_ER
Transmit Error Output TX_ER output that, asserted while TX_EN asserted, instructs device connected Am79C971 device transmit code group error. TX_ER unused reserved future will always driven logical zero. When active, TX_ER input NAND tree testing. port selected, TX_ER left floating.
RXD[3:0]
Receive Data Input RXD[3:0] nibble-wide receive data bus. Data RXD[3:0] sampled every rising edge RX_CLK while RX_DV asserted. RXD[3:0] ignored while RX_DV de-asserted. When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, selected, RXD[0] becomes data input Receive Frame (RXFRTGD). Receive Frame Tagging section details. Note: RXD[0] multiplexed with RXFRTGD pin. When active, RXD[3:0] inputs NAND tree testing. port selected, RXS[3:0] left floating.
Collision Input input that indicates that collision been detected network medium. Note: multiplexed with CLSN pin. When active, input NAND tree testing. port selected, left floating.
RX_DV
Receive Data Valid Input RX_DV input used indicate that valid received data being presented RXD[3:0] pins RX_CLK synchronous receive data. order frame fully received Am79C971 device MII, RX_DV must asserted prior RX_CLK rising edge, when first nibble Start Frame Delimiter driven RXD[3:0], must remain asserted until after rising edge RX_CLK, when last nibble driven RXD[3:0]. RX_DV must then deasserted prior RX_CLK rising edge which follows this final nibble. RX_DV transitions synchronous RX_CLK rising edges. When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, 14), selected, RX_DV becomes data input enable Receive Frame (RXFRTGE). Receive Frame Tagging section details. Note: RX_DV multiplexed with RXFRTGE pin. When active, RX_DV input NAND tree testing.
Carrier Sense Input input that indicates that non-idle medium, either transmit receive activity, been detected. Note: multiplexed with RXEN pin. When active, input NAND tree testing. port selected, left floating.
RX_CLK
Receive Clock Input RX_CLK clock input that provides timing reference transfer RX_DV, RXD[3:0], RX_ER signals into Am79C971 device. RX_CLK must provide nibble rate clock (25% network data rate). Hence, transceiver operating Mbps must provide RX_CLK frequency transceiver operating Mbps must provide RX_CLK frequency MHz. When exter-
Am79C971
port selected, RX_DV left floating.
Attachment Unit Interface
Collision Input differential input pair signaling Am79C971 controller that collision been detected network media, indicated inputs being driven with 10-MHz pattern sufficient amplitude pulse width meet 8802-3 (IEEE/ANSI 802.3) standards. operates pseudo levels. pins used, they should tied together.
RX_ER
Receive Error Input RX_ER input that indicates that transceiver device detected coding error receive frame currently being transferred RXD[3:0] pins. When RX_ER asserted while RX_DV asserted, error will indicated receive descriptor incoming receive frame. RX_ER ignored while RX_DV deasserted. Special code groups generated while RX_DV deasserted ignored (e.g., IDLE T4). RX_ER transitions synchronous RX_CLK rising edges. Note: RX_ER multiplexed with RXDAT pin. When active, RX_ER input NAND tree testing. port selected, RX_ER left floating.
Data Input differential input pair Am79C971 controller carrying Manchester encoded data from network. operates pseudo levels. pins used, they should tied together.
Data Output differential output pair from Am79C971 controller transmitting Manchester encoded data network. operates pseudo levels. used, should left floating minimum power consumption.
Management Data Clock Output non-continuous clock output that provides timing reference bits MDIO pin. During management port operations, runs nominal frequency MHz. When management operations progress, driven LOW. derived from external 20-MHz crystal. port selected, left floating.
10BASE-T Interface RXD±
10BASE-T Receive Data Input RXD± 10BASE-T port differential receivers. 10BASE-T interface used design, RXD+ RXD- should connected each other.
MDIO
Management Data Input/Output MDIO bidirectional management port data pin. MDIO output during header portion management frame transfers during data portions write transfers. MDIO input during data portions read data transfers. When operation progress management port, MDIO driven. MDIO transitions from Am79C971 controller synchronous Falling edges. attached through physical connector, then MDIO should externally pulled down with 10-k resistor. board, then MDIO should externally pulled with 10-k resistor. When active, MDIO input NAND tree testing.
TXD±
10BASE-T Transmit Data TXD± 10BASE-T port differential drivers. Output
TXP±
10BASE-T Pre-Distortion Control Output These outputs provide transmit pre-distortion control conjunction with 10BASE-T port differential drivers.
General Purpose Serial Interface CLSN
Collision Input CLSN input that indicates collision occurred network. Note: CLSN multiplexed with pin. When active, CLSN input NAND tree testing.
Am79C971
RXCLK
Receive Clock Input RXCLK input. rising edges RXCLK signal used sample data RXDAT input whenever RXEN input HIGH. Note: RXCLK multiplexed with RX_CLK pin. When active, RXCLK input NAND tree testing.
TXEN
Transmit Enable Output TXEN output that provides enable signal transmission. Data TXDAT valid unless TXEN signal HIGH. Note: TXEN multiplexed with TX_EN pin. When active, TXEN input NAND tree testing.
RXDAT
Receive Data Input RXDAT input. rising edges RXCLK signal used sample data RXDAT input whenever RXEN input HIGH. Note: RXDAT multiplexed with RX_ER pin. When active, RXDAT input NAND tree testing.
External Address Detection Interface
External Address Reject Input incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. value OR'd with internal address detection result determine current frame should accepted rejected. must left unconnected, should tied through resistor. Note: multiplexed with SLEEP pin. When active, input NAND tree testing.
RXEN
Receive Enable Input RXEN input. When this signal HIGH, indicates core logic that data RXDAT input valid. Note: RXEN multiplexed with pin. When active, RXEN input NAND tree testing.
SFBD
Start Frame-Byte Delimiter Output Internal during External Address Detection:
TXCLK
Transmit Clock Input TXCLK input that provides clock signal activity, both transmit receive. rising edges TXCLK used validate TXDAT output data. Note: TXCLK multiplexed with TX_CLK pin. When active, TXCLK input NAND tree testing.
TXDAT
Transmit Data Output TXDAT output that provides serial stream transmission, including preamble, SFD, data, field, applicable. Note: TXDAT multiplexed with TXD[0] pin. When active, TXDAT input NAND tree testing.
initial rising edge SFBD signal indicates that start frame delimiter been detected. serial stream will follow signal, commencing with destination address field. SFBD will high times (400 when operating Mbps) after detecting second (Start Frame Delimiter) received frame. SFBD will subsequently toggle every times (1.25 frequency when operating Mbps) with each rising edge indicating first each subsequent byte received serial stream. EADI Rejection Timing with Internal timing diagram details. SFBD will active only during frame reception. External attached Media Independent Interface during External Address Detection: initial rising edge SFBD signal indicates that start valid data present RXD[3:0] pins. SFBD will high nibble time (400 when operating Mbps when operating Mbps) RX_CLK period after RX_DV been asserted RX_ER deasserted detection
Am79C971
(Start Frame Delimiter) received frame. Data RXD[3:0] will start destination address field. SFBD will subsequently toggle every nibble time (1.25 frequency when operating Mbps 12.5 frequency when operating Mbps) indicating first nibble each subsequent byte received nibble stream. RX_CLK should used conjunction with SFBD latch correct data external address matching. SFBD will active only during frame reception. Note: SFBD multiplexed with EESK LED1 pins. When active, SFBD input NAND tree testing.
Note also that SRDCLK multiplexed with LED2 pin. When active, SRDCLK input NAND tree testing.
RXFRTGD
Receive Frame Data Input When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, 14), selected, RXFRTGD becomes data input Receive Frame Tag. Receive Frame Tagging section details. Note: RXFRTGD multiplexed with RXD[0] pin. When active, RXFRTGD input NAND tree testing.
Serial Receive Data Input/Output decoded data from network. This signal used external address detection. When 10BASE-T port selected, transitions will only occur during receive activity. When port selected, transitions will occur during both transmit receive activity. When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, selected, becomes data input Receive Frame (MIIRXFRTGD). Receive Frame Tagging section details. Note: When port selected, will generate transitions receive data must derived from Media Independent Interface RXD[3:0] pins. Note also that multiplexed with EEDO LED3 pins. When active, input NAND tree testing.
RXFRTGE
Receive Frame Enable Input When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, 14), selected, RXFRTGE becomes data input enable Receive Frame Tag. Receive Frame Tagging section details. Note: RXFRTGE multiplexed with RX_DV pin. When active, RXFRTGE input NAND tree testing.
MIIRXFRTGD
Receive Frame Enable Input/Output When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, 14), selected, MIIRXFRTGD becomes data input Receive Frame Tag. Receive Frame Tagging section details. Note: MIIRXFRTGD multiplexed with pin. When active, MIIRXFRTGD input NAND tree testing.
SRDCLK
Serial Receive Data Clock Input/Output Serial Receive Data synchronous with reference SRDCLK. When 10BASE-T port selected, transitions SRDCLK will only occur during receive activity. When port selected, transitions SRDCLK will occur during both transmit receive activity. When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, 14), selected, SRDCLK becomes data input enable Receive Frame (MIIRXFRTGE). Receive Frame Tagging section details. Note: When port selected, SRDCLK will generate transitions receive clock must derived from RX_CLK pin.
MIIRXFRTGE
Receive Frame Enable Input/Output When EADI enabled (EADISEL, BCR2, Receive Frame Tagging enabled (RXFRTG, CSR7, 14), selected, MIIRXFRTGE becomes data input enable Receive Frame Tag. Receive Frame Tagging section details. Note: MIIRXFRTGE multiplexed with SRDCLK pin.
Am79C971
When active, MIIRXFRTGE input NAND tree testing.
VDD_PLL
Power Pin) Power There analog supply pin. Special attention should paid printed circuit board layout avoid excessive noise this line. Refer Appendix Recommendation Power Ground Decoupling, details.
IEEE 1149.1 (1990) Test Access Port Interface
Test Clock Input clock input boundary scan test mode operation. operate frequency MHz. internal pull resistor.
VSS_PLL
Ground Pin) Power There analog ground pin. Special attention should paid printed circuit board layout avoid excessive noise this line. Refer Appendix Recommendation Power Ground Decoupling, details.
Test Data Input test data input path Am79C971 controller. internal pull resistor.
Test Data Output test data output path from Am79C971 controller. tri-stated when JTAG port inactive.
VDDB
Buffer Power Pins) Power There five power supply pins that used input/output buffer drivers. VDDB pins must connected supply.
Test Mode Select Input serial input stream used define specific boundary scan test executed. internal pull resistor.
VSSB
Buffer Ground Pins) Power There thirteen ground pins that used input/output buffer drivers.
VDD_PCI
Buffer Power Pins) Power There five power supply pins that used input/output buffer drivers. system with signaling environment, VDD_PCI pins must connected supply. system with +3.3 signaling environment, VDD_PCI pins must connected +3.3 supply.
Power Supply Pins AVDDB
Analog Power Pins) Power There three analog supply pins that provide power Twisted Pair drivers. Hence, they very noisy. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix Recommendation Power Ground Decoupling, details.
Digital Power Pins) Power There four power supply pins that used internal digital circuitry. pins must connected supply.
AVSSB
Analog Ground Pins) Power There analog ground that provides ground Twisted Pair drivers. Hence, very noisy. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix Recommendation Power Ground Decoupling, details.
Digital Ground Pins) Power There ground pins that used internal digital circuitry.
Am79C971
BASIC FUNCTIONS System Interface
Am79C971 controller designed operate master during normal operations. Some slave accesses Am79C971 controller required operations well. Initialization Am79C971 controller achieved through combination Configuration Space accesses, slave accesses, master accesses, optional read EEPROM that perfor Am79C971 controller. EEPROM read operation performed through 93C46 EEPROM interface. 8802-3 (IEEE/ANSI 802.3) Ethernet Address reside within serial EEPROM. Some Am79C971 controller configuration registers also programmed EEPROM read operation. Address PROM, on-chip board-configuration registers, Ethernet controller registers occupy bytes address space. memory mapped accesses supported. Base Address registers configuration space allow locating address space wide variety starting addresses. diskless stations, Am79C971 controller supports Flash-based (both referred Expansion throughout this specification) boot device Mbyte size. host boot device memory address that aligns 1-Mbyte boundary modifying Expansion Base Address register configuration space.
status, request particular functions executed Am79C971 controller. third portion software interface descriptor buffer areas that shared between software Am79C971 controller during normal network operations. descriptor area boundaries software change during normal network operations. There descriptor area receive activity there separate area transmit activity. descriptor space contains relocatable pointers network frame data, used transfer frame status from Am79C971 controller software. buffer areas locations that hold frame data transmission that accept frame data that been received.
Network Interfaces
Am79C971 controller connected IEEE 802.3 proprietary network four network interfaces. Media Independent Interface (MII) provides IEEE 802.3-compliant nibble-wide interface external 100- and/or 10-Mbps transceiver device. Attachment Unit Interface (AUI) provides 8802-3 (IEEE/ANSI 802.3) defined differential interface. On-board off-board connection with without cable supported. 10BASE-T interface provides twisted-pair Ethernet port, which 8802-3 (IEEE/ANSI 802.3)-compliant, contains auto-negotiation capability, which IEEE 802.3u-compliant. General Purpose Serial Interface (GPSI) allows bypassing Manchester Encoder/Decoder (MENDEC) functionally equivalent GPSI found LANCE. While auto-selection mode, interface determined Network Port Manager. quiescent state MDIO HIGH, activated. MDIO LOW, Am79C971 device checks link status 10BASE-T port. 10BASE-T link status good, 10BASE-T port selected. there active link status, then device assumes connection. 10BASE-T port will continue monitor link status while active. software driver override this automatic configuration anytime disabling auto-selection forcing network port attached internal MAC. GPSI port only enabled disabling auto-selection manually selecting GPSI network port. Am79C971 controller supports half-duplex full-duplex operation four network interfaces (i.e., AUI, 10BASE-T, GPSI, MII).
Software Interface
software interface Am79C971 controller divided into three parts. part configuration registers used identify Am79C971 controller setup configuration device. setup information includes memory mapped base address, mapping Expansion ROM, routing Am79C971 controller interrupt channel. This allows jumperless implementation. second portion software interface direct access resources Am79C971 controller. Am79C971 controller occupies bytes address space that must begin 32-byte block boundary. address space mapped into memory space (memory mapped I/O). Base Address Register Configuration Space controls start address address space mapped space. Memory Mapped Base Address Register controls start address address space mapped memory space. 32-byte address space used software program Am79C971 controller operating mode, enable disable various features, monitor operat-
Am79C971
DETAILED FUNCTIONS Slave Interface Unit
slave interface unit (BIU) controls accesses configuration space, Control Status Registers (CSR), Configuration Registers (BCR), Address PROM (APROM) locations, Expansion ROM. Table shows response Am79C971 controller each commands slave mode.
select DWord location configuration space. Am79C971 controller ignores AD[10:8], because single function device. AD[31:11] don't care.
AD31 AD11 Don't care AD10 Don't care DWord index
Table Slave Commands
C[3:0] 0000 0001 0010 0011 0100 0101 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory mapped read CSR, BCR, APROM, Reset registers Read Expansion Memory mapped write CSR, BCR, APROM used used Read CSR, BCR, APROM, Reset registers Write CSR, BCR, APROM
active bytes within DWord determined byte enable signals. Eight-bit, 16-bit, 32-bit transfers supported. DEVSEL asserted clock Am79C971 controller will assert TRDY third clock data phase. Am79C971 controller does support burst transfers access configuration space. When host keeps FRAME asserted second data phase, Am79C971 controller will disconnect transfer. When host tries access configuration space while automatic read EEPROM after H_RESET (see section RESET) on-going, Am79C971 controller will terminate access with disconnect/retry response. Am79C971 controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired Am79C971 controller capable detecting configuration cycle even when address phase immediately follows data phase transaction different target without idle state in-between. There will contention DEVSEL, TRDY, STOP signals, since Am79C971 controller asserts DEVSEL second clock after FRAME asserted (medium timing).
0110
Memory Read
0111 1000 1001 1010 1011 1100 1101 1110 1111
Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate
Read Configuration Space Write Configuration Space Aliased Memory Read used Aliased Memory Read Aliased Memory Write
Slave Transfers
After Am79C971 controller configured device setting IOEN (for regular mode) MEMEN (for memory mapped mode) Command register, starts monitoring access CSR, BCR, APROM locations. configured regular mode, Am79C971 controller will look address that falls within bytes address space (starting from base address). Am79C971 controller asserts DEVSEL detects address match access cycle. configured memor mapped mode, Am79C971 controller will look address that falls within bytes memory address space (starting from memory mapped base address). Am79C971 controller asserts DEVSEL detects address match access memory cycle. DEVSEL asserted clock cycles after host asserted FRAME. Figure Figure
Slave Configuration Transfers
host access Am79C971 configuration space with configuration read write command. Am79C971 controller will assert DEVSEL during address phase when IDSEL asserted, AD[1:0] both access configuration cycle. AD[7:2]
Am79C971
since internal Buffer Management Unit clock divide-by-two version signal.
FRAME
Am79C971 controller does support burst transfers access resources. When host keeps FRAME asserted second data phase, Am79C971 controller will disconnect transfer.
ADDR
DATA
C/BE
1010
FRAME
IRDY
ADDR DATA
TRDY
C/BE 1011
DEVSEL
STOP
IRDY
IDSEL
DEVSEL sampled
TRDY
20550D-4
DEVSEL
Figure
Slave Configuration Read
STOP
IDSEL
Am79C971 controller will assert DEVSEL detects address match, command correct type. memory mapped mode, Am79C971 controller aliases accesses resources command types Memory Read Multiple Memory Read Line basic Memory Read command. accesses type Memory Write Invalidate aliased basic Memory Write command. Eight-bit, 16-bit, 32-bit non-burst transactions suppor ted. Am79C971 controller decodes address lines determine which resource accessed. typical number wait states added slave memory mapped read write access part Am79C971 controller seven clock cycles, depending upon relative phases internal Buffer Management Unit clock signal,
20550D-5
Figure
Slave Configuration Write
Am79C971 controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired Am79C971 controller capable detecting memory-mapped cycle even when address phase immediately follows data phase transaction different target, without idle state in-between. There will contention DEVSEL, TRDY, STOP signals, since Am79C971 controller asserts DEVSEL second clock after FRAME asserted (medium timing) Figure Figure
Am79C971
FRAME
ADDR
DATA
C/BE
0010
IRDY
TRDY
DEVSEL
STOP
20550D-6
Figure
Slave Read Using Command
FRAME
ADDR
DATA
C/BE
0011
IRDY
TRDY
DEVSEL
STOP
20550D-7
Figure Slave Write Using Memory Command
Am79C971
Expansion Transfers host must initialize Expansion Base Address register offset configuration space with valid address before enabling access device. Am79C971 controller will react access Expansion until both MEMEN (PCI Command register, ROMEN (PCI Expansion Base Address register, After Expansion enabled, Am79C971 controller will assert DEVSEL memory read accesses with address between ROMBASE ROMBASE Am79C971 controller aliases accesses Expansion command types Memory Read Multiple Memory Read Line basic Memory Read command. Eight-bit, 16-bit, 32-bit read transfers supported. Since setting MEMEN also enables memory mapped access resources, attention must given Memory Mapped Base Address register before enabling access Expansion ROM. host must Memory Mapped Base Address register value that prevents Am79C971 controller from claiming memory cycles intended Am79C971 controller will always read four bytes every host Expansion read access. TRDY will
asserted until four bytes loaded into internal scratch register. cycle TRDY asserted depends programming Expansion interface timing. following figure (Figure assumes that ROMTMG (BCR18, bits 15-12) default value. Note: Expansion should read only during configuration time system. When host tries write Expansion ROM, Am79C971 controller will claim cycle asserting DEVSEL. TRDY will asserted clock cycle later. write operation will have effect. Writes Expansion done through BCR30 Expansion Data Port. section Expansion Interface more details. Am79C971 controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired Am79C971 controller capable detecting memory cycle even when address phase immediately follows data phase transaction different target without idle state inbetween. There will contention DEVSEL, TRDY, STOP signals, since Am79C971 controller asserts DEVSEL second clock after FRAME asserted (medium timing). Figure
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
20550D-8
Figure Expansion Read
Am79C971
During boot procedure, system will find Expansion ROM. system assumes that Expansion present when reads signature (byte (byte design without Expansion guarantee that Expansion detection fails connecting adjacent pins together. Slave Cycle Termination There three scenarios besides normal completion transaction where Am79C971controller target slave cycle will terminate access. Disconnect When Busy Am79C971controller cannot service slave access while reading contents EEPROM. Simultaneous access possible avoid conflicts, since EEPROM used initialize some configuration space locations most BCRs. EEPROM read operation will always happen automatically after deassertion pin. addition, host start read operation setting PREAD (BCR19, 14). While EEPROM read on-going, Am79C971controller will disconnect slave access where target asserting STOP together with DEVSEL, while driving TRDY high. STOP will stay asserted until cycle. Note that memory slave accesses will only disconnected they enabled setting IOEN MEMEN Command register. Without enable set, cycles will claimed all. Since H_RESET clears IOEN MEMEN bits automatic EEPROM read after H_RESET, disconnect only applies configuration cycles. second situation where Am79C971controller will generate disconnect/retry cycle when host tries access resources right after having read Reset register. Since access generates internal reset pulse about length, further slave accesses will deferred until internal reset operation completed. Figure Disconnect Burst Transfer Am79C971controller does support burst access configuration space, resources, Expansion Bus. host indicates burst transaction keeping FRAME asserted during data phase. When Am79C971controller sees FRAME IRDY asserted clock cycle before wants assert TRDY, also asserts STOP same time. transfer first data phase still successful, since IRDY TRDY both asserted. Figure
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
20550D-9
Figure
Disconnect Slave Cycle When Busy
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
20550D-10
Figure Disconnect Slave Burst Transfer Host Wait States
Am79C971
host ready when Am79C971 controller asserts TRDY, device will wait host assert IRDY. When host asserts IRDY FRAME still asserted, Am79C971controller will finish first data phase deasserting TRDY clock later. same time, will assert STOP signal disconnect host. STOP will stay asserted until host removes FRAME. Figure
address parity error when PERREN SERREN Figure
FRAME
FRAME
ADDR
DATA
C/BE
DATA
DATA
C/BE
SERR
DEVSEL
IRDY
20550D-12
TRDY
Figure
Address Parity Error Response
DEVSEL
STOP
20550D-11
Figure Disconnect Slave Burst Transfer Host Inserts Wait States
Parity Error Response When Am79C971controller current master, samples AD[31:0], C/BE[3:0], lines during address phase command parity error. When detects address parity error, controller sets PERR (PCI Status register, When reporting that error enabled setting SERREN (PCI Command register, PERREN (PCI Command register, Am79C971controller also drives SERR signal clock cycle sets SERR (PCI Status register, assertion SERR follows address phase clock cycles. Am79C971controller will assert DEVSEL transaction that
During data phase write, memory-mapped write, configuration write command that selects Am79C971controller target, device samples AD[31:0] C/BE[3:0] lines parity clock edge, data transferred indicated assertion IRDY TRDY. sampled following clock cycle. parity error detected reporting that error enabled setting PERREN (PCI Command register, PERR asserted clock later. parity error will always PERR (PCI Status register, even when PERREN cleared Am79C971controller will finish transaction that data parity error normal asserting TRDY. corrupted data will written addressed location. Figure shows transaction that suffered parity error time data transferred (clock IRDY TRDY both asserted). PERR driven high beginning data phase then drops parity error clock clock cycles after data transferred. After PERR driven low, Am79C971controller drives PERR high clock cycle, since PERR sustained tri-state signal.
Am79C971
FRAME
ADDR
DATA
C/BE
PERR
IRDY
TRDY
DEVSEL
20550D-13
Figure Slave Cycle Data Parity Error Response
Master Interface Unit
master Interface Unit (BIU) controls acquisition accesses initialization block, descriptor rings, receive transmit buffer memory. Table shows usage commands Am79C971controller master mode.
Table Master Commands (Continued)
C[3:0] 0111 1000 1001 1010 1011 1100 1101 Command Memory Write Reserved Reserved Configuration Read used Configuration Write Memory Read Multiple used Read transmit buffer burst mode Read transmit buffer burst mode used Write descriptor rings receive buffer
Table Master Commands
C[3:0] 0000 0001 0010 0011 0100 0101 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Read initialization block descriptor rings Read transmit buffer non-burst mode used used used used
Dual Address Cycle used Memory Read Line Memory Write Invalidate
1110 1111
Acquisition Am79C971microcode will determine when transfer should initiated. first step Am79C971bus master transfer acquire ownership bus. This task handled synchronous logic within BIU. ownership requested with signal ownership granted arbiter through signal.
0110
Memory Read
Am79C971
Figure shows Am79C971controller acquisition. asserted arbiter returns while othe tran sfer Am79C971 controller waits until idle (FRAME IRDY deasserted) before starts driving AD[31:0] C/BE[3:0] clock FRAME asserted clock indicating valid address command AD[31:0] C/BE[3:0]. Am79C971 controller does address stepping which reflected ADSTEP (bit Command register being hardwired
controller non-burst read accesses command type Memory Read (type Note that during non-burst read operation, byte lanes will always active. Am79C971 controller will internally discard unneeded bytes. Am79C971 controller typically performs more than non-burst read transactions within single mastership period. FRAME dropped between consecutive non-burst read cycles. however stays asserted until FRAME asserted last transaction. Am79C971 controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL. Figure shows non-burst read transactions. first transaction zero wait states. second transaction, target extends cycle asserting TRDY clock later. Basic Burst Read Transfer Am79C971 controller supports burst mode master read operations. burst mode must enabled setting BREADE (BCR18, allow burst transfers descriptor read operations, Am79C971 controller must also programmed SWSTYLE (BCR20, bits 7-0). burst read accesses initialization block descriptor ring command type Memory Read (type Burst read accesses transmit buffer typically longer than data phases. When MEMCMD (BCR18, cleared burst read accesses transmit buffer command type Memory Read Line (type 14). When MEMCMD (BCR18, to1, burst read accesses transmit buffer command type Memory Read Multiple (type 12). AD[1:0] will both during address phase indicating linear burst order. Note that during burst read operation, byte lanes will always active. Am79C971 controller will internally discard unneeded bytes. Am79C971 controller will always perform only single burst read transaction mastership period, where transaction defined address Am79C971 controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL. FRAME deasserted when next last data phase completed. Figure shows typical burst read access. Am79C971 controller arbitrates bus, granted access, reads three 32-bit words (DWord) from system memory, then releases bus. example, memory system extends data phase each access wait state. example assumes that EXTREQ (BCR18, cleared therefore, deasserted same cycle FRAME asserted.
FRAME
ADDR
C/BE
IRDY
20550D-14
Figure Acquisition burst mode, deassertion depends setting EXTREQ (BCR18, EXTREQ cleared deasserted same time FRAME asserted. (The Am79C971 controller never performs more than burst transaction within single mastership period.) EXTREQ Am79C971 controller does deassert until starts last data phase transaction. Once asserted, remains active until become active independent subsequent setting STOP (CSR0, SPND (CSR5, assertion H_RESET S_RESET, however, will cause inactive immediately. Master Transfers There four primary types transfers. Am79C971 controller uses non-burst well burst cycles read write access main memory. Basic Non-Burst Read Transfer default, Am79C971 controller uses non-burst cycles master read operations. Am79C971
Am79C971
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
GNT3
DEVSEL sampled
20550D-15
Figure Non-Burst Read Transfer
FRAME
ADDR
DATA
DATA
DATA
C/BE
1110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-16
Figure Burst Read Transfer (EXTREQ MEMCMD
Am79C971
Basic Non-Burst Write Transfer default, Am79C971 controller uses non-burst cles ster operations. Am79C971 controller non-burst write accesses command type Memory Write (type byte enable signals indicate byte lanes that have valid data.The Am79C971 controller typically performs more than non-burst write transaction within single mastership period. FRAME dropped between consecutive non-burst write cycles. REQ, however, stays asserted until FRAME asserted last transaction. Am79C971 supports zero wait state write cycles except with descriptor write transfers. (See section Descriptor Transfers only exception.) asserts IRDY immediately after address phase. Figure shows non-burst write transactions. first transaction wait states. target inserts wait state asserting DEVSEL clock late another wait state also asserting TRDY clock late. second transaction shows zero wait state write cycle. target asserts DEVSEL TRDY same cycle Am79C971 controller asserts IRDY.
Basic Burst Write Transfer Am79C971 controller supports burst mode master write operations. burst mode must enabled setting BWRITE (BCR18, allow burst transfers descriptor write operations, Am79C971 controller must also programmed SWSTYLE (BCR20, bits 7-0). Am79C971 controller burst write transfers command type Memory Write (type AD[1:0] will both during address phase indicating linear burst order. byte enable signals indicate byte lanes that have valid data. Am79C971 controller will always perform single burst write transaction mastership period, where transaction defined address phase multiple data phases. Am79C971 controller supports zero wait state write cycles except with case descriptor write transfers. (See section Descriptor Transfers only exception.) device asserts IRDY immediately after address phase same time star sampling DEVSEL. FRAME deasserted when next last data phase completed.
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0111
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-17
Figure Non-Burst Write Transfer
Am79C971
Figure shows typical burst write access. Am79C971 controller arbitrates bus, granted access, writes four 32-bit words (DWords) system memory then releases bus. this example, memory system extends data phase first access wait state. following three data phases take clock cycle each, which determined timing TRDY. example assumes that EXTREQ (BCR18, therefore, deasserted until next last data phase finished. Target Initiated Termination When Am79C971 controller master, cycles produces terminated target three different ways.
Disconnect With Data Transfer Figure shows disconnection which last data transfer occurs after target asserted STOP. STOP asserted clock start termination sequence. Data still transferred during this cycle, since both IRDY TRDY asserted. Am79C971 controller terminates current transfer with deassertion FRAME clock IRDY clock later. finally releases clock Am79C971 controller will again request after clock cycles, wants transfer more data. starting address transfer will address next non-transferred data.
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
EVSEL
DEVSEL sampled
20550D-18
Figure
Burst Write Transfer (EXTREQ
Am79C971
FRAME
ADDRi
DATA
DATA
ADDRi+8
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
20550D-19
Figure
Disconnect With Data Transfer
Disconnect Without Data Transfer Figure shows target disconnect sequence during which data transferred. STOP asserted clock without TRDY being asserted same time. Am79C971 controller terminates access with deassertion FRAME clock IRDY clock cycle later. finally releases clock Am79C971 controller will again request after clock cycles retry last transfer. starting address transfer will address last non-transferred data. Target Abort Figure shows target abort sequence. target asserts DEVSEL clock. then deasserts DEVSEL asserts STOP clock target target abort sequence indicate that cannot service data transfer that does want transaction retr ied. Additionally, Am79C971 controller cannot make assumption
about success previous data transfers current transaction. Am79C971 controller terminates current transfer with deassertion FRAME clock IRDY clock cycle later. finally releases clock Since data integrity guaranteed, Am79C971 controller cannot recover from target abort event. Am79C971 controller will reset locations their STOP_RESET values. configuration registers will cleared. on-going networ transmission minated order sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station.
Am79C971
FRAME
ADDRi
DATA
ADDRi
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
20550D-20
Figure Disconnect Without Data Transfer
RTABORT (PCI Status register, will indicate that Am79C971 controller received target abort. addition, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. Master Initiated Termination There three scenarios besides normal completion transaction where Am79C971 controller will terminate cycles produces bus. Preemption During Non-Burst Transaction When Am79C971 controller performs multiple nonburst transactions, keeps asserted until assertion FRAME last transaction. When removed, Am79C971 controller will finish current transaction then release bus.
last transaction, will remain asserted regain ownership soon possible. Figure Preemption During Burst Transaction When Am79C971 controller operates burst mode, only performs single transaction mastership period, where transaction defined address phase multiple data phases. central arbiter remove time during transaction. Am79C971 controller will ignore deassertion continue with data transfers, long Latency Timer expired. When Latency Timer deasserted, Am79C971 controller will finish current data phase, deassert FRAME, finish last data phase, release bus. EXTREQ (BCR18, cleared will immediately assert regain ownership soon possible. EXTREQ will stay asserted.
Am79C971
FRAME
ADDR
DATA
C/BE
0111
0000
Am79C971 controller will reset locations their STOP_RESET values. configuration registers will cleared. on-going network transmission terminated orderly sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station. RMABORT Status register, will indicate that Am79C971 controller terminated transaction with master abort. addition, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. Figure Parity Error Response During every data phase read operation, when target indicates that data valid asserting TRDY, Am79C971 controller samples AD[31:0], C/BE[3:0] lines data parity error. When detects data parity error, controller sets PERR (PCI Status register, When reporting that error enabled setting PERREN (PCI Command register, Am79C971 controller also drives PERR signal sets DATAPERR (PCI Status register, assertion PERR follows corrupted data/byte enables clock cycles clock cycle. Figure shows transaction that parity error data phase. Am79C971 controller asserts PERR clock clock cycles after data valid. data clock checked parity, since read access only required valid clock after target asser TRDY. Am79C971 controller then drives PERR high clock cycle, since PERR sustained tri-state signal. During every data phase write operation, Am79C971 controller checks PERR input target reports parity error. When sees PERR input asserted, controller sets PERR (PCI Status register, When PERREN (PCI Command register, Am79C971 controller also sets DATAPERR (PCI Status register,
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
20550D-21
Figure Target Abort When preemption occurs after counter counted down Am79C971 controller will finish current data phase, deassert FRAME, finish last data phase, release bus. Note that important host program Latency Timer according bandwidth requirement Am79C971 controller. host determine this bandwidth requirement reading MAX_LAT MIN_GNT registers. Figure assumes that Latency Timer counted down clock Master Abort Am79C971 controller will terminate cycle with Master Abort sequence DEVSEL asserted within clocks after FRAME asserted. Master Abort treated fatal error Am79C971 controller.
Am79C971
FRAME
ADDR
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-22
Figure
Preemption During Non-Burst Transaction
FRAME
ADDR
DATA
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-23
Figure Preemption During Burst Transaction Am79C971
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-24
Figure
Master Abort
FRAME
ADDR
DATA
C/BE
0111
PERR
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-25
Figure Master Cycle Data Parity Error Response
Am79C971
Whenever Am79C971 controller current master data parity error occurs, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. setting SINT data parity error dependent setting PERREN (PCI Command register, default, data parity error does affect state engine. Am79C971 controller treats data master transfers that have parity error nothing happened. network activity continues. Advanced Parity Error Handling cycles, Am79C971 controller provides second, more advanced level parity error handling. This mode enabled setting APERREN (BCR20, When APERREN bits (RMD1 TMD1, used indicate parity error data transfers receive transmit buffers. Note that since advanced parity error handling uses additional descriptor, SWSTYLE (BCR20, bits 7-0) must program
Am79C971 controller 32-bit software structures. Am79C971 controller will react following when data parity error occurs: Initialization block read: STOP (CSR0, causes STOP_RESET device. Descriptor ring read: on-going network activity terminated orderly sequence then STOP (CSR0, cause STOP_RESET device. Descriptor ring write: on-going network activity terminated orderly sequence then STOP (CSR0, cause STOP_RESET device. Transmit buffer read: (TMD1, current transmit descriptor. on-going network transmission terminated orderly sequence. Receive buffer write: (RMD1, last receive descriptor associated with frame. Terminating on-going network transmission orderly sequence means that less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet.
FRAME
IADDi
DATA
IADDi+4
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-26
Figure
Initialization Block Read Non-Burst Mode
Am79C971
bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station. APERREN does affect reporting address parity errors data parity errors that occur when Am79C971 controller target transfer. Initialization Block Transfers During execution Am79C971 controller master initialization procedure, Am79C971 microcode will repeatedly request transfers from BIU. During each these initialization block transfers, will perform data transfer cycles reading DWord transfer then will relinquish bus. When SSIZE32 (BCR20, (i.e., initialization block organized 32-bit software structures), there seven DWords transfer during master initialization procedure, four mastership periods needed order complete initialization sequence. Note that last DWord transfer last mastership period initialization sequence accesses unneeded location. Data from this transfer discarded internally. When SSIZE32 cleared (i.e., initialization block organized 16-bit software structures), then three mastership periods needed complete initialization sequence. Am79C971 supports transfer modes reading initialization block: non-burst burst mode, with burst mode being preferred mode when Am79C971 controller used application. Figure Figure When BREADE cleared (BCR18, initialization block read transfers will executed nonburst mode. There address phase every data phase. FRAME will dropped between transfers. phases within mastership period will have addresses ascending contiguous order. When BREADE (BCR18, initialization block read transfers will executed burst mode. AD[1:0] will during address phase indicating linear burst order. Descriptor Transfers Am79C971 microcode will determine when descriptor access required. descriptor read will consist data transfers. descriptor write will consist data transfers. descriptor transfers within single mastership period will always same type (either read write). During descriptor read accesses, byte enable signals will indicate that byte lanes active. Should
some bytes needed, then Am79C971 controller will internally discard extraneous information that gathered during such read. settings SWSTYLE (BCR20, bits 7-0) BREADE (BCR18, affect Am79C971 controller performs descriptor read operations. When SWSTYLE descriptor read operations performed non-burst mode. setting BREADE effect this configuration. Figure When SWSTYLE descriptor entries ordered allow burst transfers. Am79C971 controller will perform descriptor read operations burst mode, BREADE Figure Table shows descriptor read sequence. During descriptor write accesses, only byte lanes which need written enabled.
Table
Descriptor Read Sequence
Sequence Address XXXX XX00h Turn around cycle Data MD1[31:24], MD0[23:0]
SWSTYLE BREADE BCR20[7:0] BCR18[6]
Idle Address XXXX XX04h Turn around cycle Data MD2[15:0], MD1[15:0] Address XXXX XX04h Turn around cycle Data MD1[31:0]
Idle Address XXXX XX00h Turn around cycle Data MD0[31:0] Address XXXX XX04h Turn around cycle Data MD1[31:0]
Idle Address XXXX XX08h Turn around cycle Data MD0[31:0] Address XXXX XX04h Turn around cycle Data MD1[31:0] Data MD0[31:0]
Am79C971
FRAME
IADDi 0110
DATA
DATA
C/BE
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-27
Figure Initialization Block Read Burst Mode
FRAME
DATA
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550C-28
Figure Descriptor Ring Read Non-Burst Mode
Am79C971
buffer chaining used, accesses descriptors intermediate buffers consist only data transfer return ownership buffer system. When SWSTYLE (BCR20, bits 7-0) cleared (i.e., descriptor entries organized 16-bit software structures), descriptor access will write single byte. When SWSTYLE (BCR20, bits 7-0) (i.e., descriptor entries organized 32-bit software structures), descriptor access will write single word. single buffer transmit receive descriptors, well last buffer chain, writes descriptor consist data transfers. first data transfer writes DWord containing status information. second data transfer writes byte (SWSTYLE cleared otherwise word containing additional status ownership (i.e., MD1[31]). settings SWSTYLE (BCR20, bits 7-0) BWRITE (BCR18, affect Am79C971 controller performs descriptor write operations.
When SWSTYLE descriptor write operations performed non-burst mode. setting BWRITE effect this configuration. When SWSTYLE descriptor entries ordered allow burst transfers. Am79C971 controller will perform descriptor write operations burst mode, BWRITE Table descriptor write sequence. write transaction descriptor ring entries only case where Am79C971 controller inserts wait state when being master. Every data phase non-burst burst mode extended clock cycle, during which IRDY deasserted. Note that Figure assumes that Am79C971 controller programmed 32-bit software structures (SWSTYLE byte enable signals second data transfer would 0111b, device programmed 16-bit software structures (SWSTYLE
FRAME
DATA
DATA
C/BE
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-29
Figure
Descriptor Ring Read Burst Mode
Am79C971
Table
SWSTYLE BCR20[7:0]
Descriptor Write Sequence
Sequence Address XXXX XX04h Data MD2[15:0], MD1[15:0]
Non-Burst FIFO Transfers default mode, Am79C971 controller uses non-burst transfers read write data when accessing FIFOs. Each non-burst transfer will performed sequentially with issue address transfer corresponding data with appropriate output signals indicate selection active data bytes during transfer. FRAME will deasserted after every address phase. Several factors will affect length mastership period. possibilities follows: cycles will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers). exact number total transfer cycles mastership period dependent following variables: settings FIFO watermarks, conditions FIFOs, latency system Am79C971 controller's request, speed operation preemption events. TRDY response time memory device will also affect number transfers, since speed accesses will affect state FIFO. During accesses, FIFO filling emptying network end. example, receive operation, slower TRDY response will allow additional data accumulate inside FIFO. accesses slow enough, complete DWord become available before mastership period and, thereby, increase number transfers that period. general rule that longer Grant latency, slower transfer operations; slower clock speed, higher transmit watermark; higher receive watermark, longer mastership period will Note: Latency Timer significant during non-burst transfers.
BWRITE BCR18[5]
Idle Address XXXX XX00h Data MD1[31:24] Address XXXX XX08h Data MD2[31:0]
Idle Address XXXX XX04h Data MD1[31:16] Address XXXX XX00h Data MD2[31:0]
Idle Address XXXX XX04h Data MD1[31:16] Address XXXX XX00h
Data MD2[31:0] Data MD1[31:16]
FIFO Transfers Am79C971 microcode will determine when FIFO transfer required. This transfer mode will used transfers data from Am79C971 FIFOs. Once Am79C971 been granted mastership, will perform series consecutive transfer cycles before relinquishing bus. transfers within master cycle will either read write cycles, transfers will contiguous, ascending addresses. Both non-burst burst cycles used, with burst mode being preferred mode when device used application.
Am79C971
FRAME
DATA
DATA
C/BE
0111
0000
0111
0011
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-30
Figure
Descriptor Ring Write Non-Burst Mode
FRAME
DATA
DATA
C/BE
0110
0000
0011
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-31
Figure
Descriptor Ring Write Burst Mode
Am79C971
Burst FIFO Transfers Bursting only performed Am79C971 controller BREADE and/or BWRITE bits BCR18 set. These bits individually enable/disable ability Am79C971 controller perform burst accesses during master read operations master write operations, respectively. burst transaction will start with address phase, followed more data phases. AD[1:0] will always during address phase indicating linear burst order. During FIFO read operations, byte lanes will always active. Am79C971 controller will internally discard unused bytes. During first last data phases FIFO burst write operation, more byte enable signals inactive. other data phases will always write complete DWord. Figure shows beginning FIFO write with beginning buffer aligned DWord boundary. Am79C971 controller starts writing only three bytes during first data phase. This operation aligns address other data transfers 32-bit boundary that Am79C971 controller continue bursting full DWords. receive buffer does DWord boundary, Am79C971 controller will perform non-DWord write last transfer buffer. Figure shows final three FIFO transfers receive buffer. Since there were only nine bytes space left receive buffer, Am79C971 controller bursts three data phases. first data phases write full DWord, last only writes single byte. Note that Am79C971 controller will always perform DWord transfer long owns buffer space, even when there less then four bytes write. example, there only byte left current receive frame, Am79C971 controller will write full DWord, containing last byte receive frame least significant byte position (BSWP cleared CSR3, content other three bytes undefined. message byte count receive descriptor always reflects exact length received frame. receive buffer aligned DWord boundary, IWAIT (BCR18, must stay default value This will result wait state added every data phase burst write transaction. When software ensures that receive buffers DWord boundary, IWAIT this mode, Am79C971 controller will only insert wait state first data phase burst write transaction.
FRAME
DATA
DATA
DATA
C/BE
0111
0001
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-32
Figure
FIFO Burst Write Start Unaligned Buffer
application, Am79C971 controller should have length mastership period controlled only Latency Timer. Timer (CSR4, should remain default value this mode, Am79C971 controller will continue transferring FIFO data until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers), Am79C971 controller preempted, Latency Timer expired. host should values MIN_GNT MAX_LAT registers determine value Latency Timer. applications that Latency Timer that support preemption, following rules apply limit time Am79C971 controller takes bus:
Am79C971
Buffer Management Unit
Buffer Management Unit (BMU) microcoded state machine which implements initialization procedure manages descriptors buffers. buffer management unit operates half speed input. Initialization Am79C971 initialization includes reading initialization block memory obtain operating parameters. initialization block organized ways. When SSIZE32 (BCR20, default value initialization block entries logically 16-bits wide backwards compatible with Am79C90 C-LANCE Am79C96x PCnet-ISA family. When SSIZE32 (BCR20, initialization block entries logically 32-bits wide. Note that Am79C971 controller always performs 32-bit transfers read initialization block entries. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. Once initialization block been completely read internal registers have been updated, IDON will CSR0, generating interrupt IENA set). Am79C971 controller obtains start address initialization block from contents CSR1 (least significant bits address) CSR2 (most significant bits address). host must write CSR1 CSR2 before setting INIT bit. initialization block contains user defined conditions Am79C971 operation, together with base addresses length information transmit receive descriptor rings. There alter nate method initial Am79C971 controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method combination used discretion programmer. Please refer Appendix Alternative Method Initialization details this alternate method. Re-Initialization transmitter receiver sections Am79C971 controller turned initialization block (DTX, DRX, CSR15, bits 1-0). states transmitter receiver monitored host through CSR0 (RXON, TXON bits). Am79C971 controller should re-initialized transmitter and/or receiver were turned during original initialization, subsequently required activate them either section shut detection error condition (MERR, UFLO, BUFF error). Re-initialization done initialization block setting STOP CSR0, followed writing CSR15, then setting START CSR0.
FRAME
DATA
DATA
DATA
C/BE
0111
0000
1110
IRDY
TRDY
DEVSEL
DEVSEL sampled
20550D-33
Figure FIFO Burst Write Unaligned Buffer
exact number total transfer cycles mastership period dependent following variables: settings FIFO watermarks, conditions FIFOs, latency system Am79C971 controller's request, speed operation. TRDY response time memory device will also affect number transfers, since speed accesses will affect state FIFO. During accesses, FIFO filling emptying network end. example, receive operation, slower TRDY response will allow additional data accumulate inside FIFO. accesses slow enough, complete DWord become available before mastership period and, thereby, increase number transfers that period. general rule that longer Grant latency, slower transfer operations; slower clock speed, higher transmit watermark; lower receive watermark, longer total burst length will When FIFO burst operation preempted, Am79C971 controller will relinquish ownership until Latency Timer expires.
Am79C971
Note that this form restart will perform same Am79C971 controller C-LANCE device. particular, upon restart, Am79C971 controller reloads transmit receive descriptor pointers with their respective base addresses. This means that software must clear descriptor bits reset descriptor ring pointers before restar ting Am79C971 controller. reload descriptor base addresses performed C-LANCE device only after initialization, that restart C-LANCE without initialization leaves C-LANCE pointing same descriptor locations before restart. Suspend Am79C971 controller offers suspend modes that allows easy updating registers without going through full re-initialization device. suspend modes also allow stopping device with orderly termination network activity. host requests Am79C971 controller enter suspend mode setting SPND (CSR5, host must poll SPND until reads back determine that Am79C971 controller entered suspend mode. When host sets SPND procedure taken Am79C971 controller enter suspend mode depends setting fast suspend enable (FASTSPND, CSR7, 15). When fast suspend requested (FASTSPND Am79C971 controller performs quick entry into suspend mode. time SPND set, Am79C971 controller will continue process transmit and/or receive packets that have already begun activity until network activity been completed. addition, transmit packet that started transmission will fully transmitted receive packet that begun reception will fully received. However, additional packets will transmitted received additional transmit receive activity will begin after network activity ceased. Hence, Am79C971 controller enter suspend mode with transmit and/or receive packets still FIFOs external SRAM. This offers worst case suspend time maximum length packet over possibility completely emptying external SRAM. Care must exercised this mode, because entire memory subsystem Am79C971 controller suspended. changes either descriptor ings exter SRAM cause Am79C971 controller start unknown condition could cause data corruption. When FASTSPNDE SPND set, Am79C971 controller take longer before entering suspend mode. time SPND set, Am79C971 controller will complete process transmit packet already begun Am79C971 controller will completely receive receive
packet already begun. Am79C971 controller will receive packets after completion current reception. Additionally, transmit packets stored transmit FIFOs transmit buffer area external SRAM present) will transmitted, receive packets stored receive FIFOs receive buffer area external SRAM present) will transferred into system memory. Since FIFO external SRAM contents flushed, take much longer before Am79C971 controller enters suspend mode. amount time that takes depends many factors including size external SRAM, latency, network traffic level. Upon completion described operations, Am79C971 controller sets read-version SPND enters suspend mode. suspend mode, registers accessible. long Am79C971 controller reset while suspend mode H_RESET, S_RESET, setting STOP bit), re-initialization device required after device comes suspend mode. When SPND Am79C971 controller will leave suspend mode will continue transmit receive descriptor ring locations, where been when entered suspend mode. section Magic Packettechnology details that affects suspension Am79C971 controller. Buffer Management Buffer management accomplished through message descriptor entries organized ring structures memory. There descriptor rings, transmit receive. Each descriptor describes single buffer. frame occupy more buffers. multiple buffers used, this referred buffer chaining. Descriptor Rings Each descriptor ring must occupy contiguous area memory. During initialization, user-defined base address transmit receive descriptor rings, well number entries contained descriptor rings programming software style (SWSTYLE, BCR20, bits 7-0) affects descriptor rings their entries arranged. When SWSTYLE default value descriptor rings backwards compatible with Am79C90 C-LANCE Am79C96x PCnet-ISA family. descriptor ring base addresses must aligned 8-byte boundary maximum ring entries allowed when ring length through TLEN RLEN fields initialization block. Each ring entry contains subset three 32-bit transmit receive message descriptors (TMD, RMD) that organized four 16-bit structures
Am79C971
(SSIZE32 (BCR20, Note that even though Am79C971 controller treats descriptor entries 16-bit structures, will always perform 32-bit transfers access descriptor entries. value CSR2, bits 15-8, used upper 8-bits memory addresses during master transfers. When SWSTYLE descriptor ring base addresses must aligned 16-byte boundary, maximum ring entries allowed when ring length through TLEN RLEN fields initialization block. Each ring entry organized three 32-bit message descriptors (SSIZE32 (BCR20, fourth DWord reserved. When SWSTYLE order message descriptors optimized allow read write access burst mode. software style, ring lengths beyond this range 65535) writing transmit receive ring length registers (CSR76, CSR78) directly. Each ring entry contains following information: address actual message data buffer user host memory length message buffer Status information indicating condition buffer
permit queuing de-queuing message buffers, ownership each buffer allocated either Am79C971 controller host. within descriptor status information, either RMD, used this purpose. When signifies that Am79C971 controller currently ownership this ring descriptor associated buffer. Only owner permitted relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field entry. device may, however, read from descriptor that does currently own. Software should always read descriptor entries sequential order. When software finds that current descriptor owned Am79C971 controller, then software must read ahead next descriptor. software should wait descriptor does until Am79C971 controller sets release ownership software. (When LAPPEN (CSR3, this rule modified. LAPPEN description. initialization, Am79C971 controller reads base address both transmit receive descriptor rings into CSRs Am79C971 controller during subsequent operations. Figure illustrates relationship between initialization base address, initialization block, receive transmit descriptor ring base addresses, receive transmit descriptors, receive transmit data buffers, when SSIZE32 cleared
Am79C971
Descriptor Ring
CSR2 IADR[31:16] CSR1 IADR[15:0] RMD0 desc. desc.
Initialization Block PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RDRA[23:16] TDRA[15:0] TDRA[23:16]
Buffers
Data Buffer
Data Buffer
Data Buffer
Descriptor Ring
desc. desc.
Buffers
Data Buffer
Data Buffer
Data Buffer
20550D-34
Figure 16-Bit Software Model
Note that value CSR2, bits 15-8, used upper 8-bits memory addresses during master transfers. Figure illustrates relationship between initialization base address, initialization block, receive transmit descriptor ring base addresses, receive transmit descriptors, receive transmit data buffers, when SSIZE32 Polling there network channel activity there pre- post-receive pre- post-transmit activity being performed Am79C971 controller, then Am79C971 controller will periodically poll current receive transmit descriptor entries order ascertain their ownership. TXDPOLL CSR4 set, then transmit polling function disabled. typical polling operation consists following sequence. Am79C971 controller will current receive descriptor address stored internally vector
appropriate Receive Descriptor Table Entry (RDTE). will then current transmit descriptor address (stored internally) vector appropriate Transmit Descriptor Table Entry (TDTE). accesses will made following order: RMD1, then RMD0 current RDTE during arbitration, after that, TMD1, then TMD0 current TDTE during second arbitration. information collected during polling activity will stored internally appropriate CSRs, (i.e., CSR18, CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52). typical receive poll product following conditions: Am79C971 controller does current RDTE poll time elapsed RXON (CSR0, Am79C971 controller does next RDTE there more than receive descriptor ring poll time elapsed RXON
Am79C971
CSR2
IADR[31:16]
CSR1
IADR[15:0]
desc. start
Descriptor Ring
desc. start
Initialization Block
MODE PADR[31:0] PADR[47:32] LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0]
Buff
Data Buffer
Data Buffer
Data Buffer
desc. start
Descriptor Ring
desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buff
Data Buffer
Data Buffer
Data Buffer
20550D-35
Figure 32-Bit Software Model
RXON cleared Am79C971 controller will never poll RDTE locations. order avoid missing frames, system should have least RDTE available. minimize poll activity, RDTEs should available. this case, poll operation will only consist check status current TDTE. typical transmit poll product following conditions: Am79C971 controller does current TDTE TXDPOLL (CSR4, TXON (CSR0, poll time elapsed, Am79C971 controller does current TDTE TXDPOLL TXON frame just been received, Am79C971 controller does current TDTE TXDPOLL TXON frame just been transmitted.
Setting TDMD CSR0 will cause microcode co
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