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High Speed / Logic Gate Optocoupler SFH67XX Series Appnote 73

SFH6700 / 19 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 Out 6 VE 5 GND Three-State-Output SFH6705 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 NC 6 Out 5 GND Anode 1 Cathode 2 Cathode 3 Anode 4 NC 1 Anode 2 Cathode 3 NC 4

High Speed / Logic Gate Optocoupler (SFH67XX Series) Appnote 73
SFH6700 / 19 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 Out 6 VE 5 GND Three-State-Output SFH6705 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 NC 6 Out 5 GND Anode 1 Cathode 2 Cathode 3 Anode 4 NC 1 Anode 2 Cathode 3 NC 4
Table 1. Truth Table (Positive Logic) SFH6700 / 19
LED On Off On Off Enable L L H H Output H L Z Z
LED On Off Output H L
2. Design Considerations The circuits shown below are intended to give the design engineer a guideline for logic family interconnection. Input Circuitry Below are stated the most common interface circuits which work for this coupler series. Totem Pole Drive Circuits Figures 2 and 3 are two of the most common used circuits. The designer chooses R1 according to the equation:
SFH6702 / 12 8 VCC 7 Out 6 NC 5 GND NC 1 Anode 2 Cathode 3 NC 4 Totem-Pole-Output 8 VCC 7 NC 6 Out 5 GND
SFH6701 / 11
Totem-Pole-Output SFH6731 / 32 8 VCC 7 Out 1 6 Out 2 5 GND
Open-Collector-Output
Dual / Totem-Pole-Output
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(valid for Figure 2) (valid for Figure 3)
Figure 4. Typical Input Current Threshold (Normalized) vs. Temperature
40 30 20 10 0 -10 -20 -30 -60 -40 -20 0 20 40 60 Temperature, TA (°C) 80 100
SFH6700 / 19 VDD
Data LS TTL IN LOGIC
Figure 3. Series LED Drive
SFH6700 / 19 1 NC VDD
TTL / CMOS LOGIC
Figure 5. Shunt LED Drive Circuit with Leakage Current Protection
SFH6700 / 19 1 NC VDD
Data IN
Data CMOS IN LOGIC
Figure 2 3 Logic Gate (e.g.) 74LS04 74LS04 74HCT04 R1 Value 750 1.10 k 1.10 k
Table 3. Typical Input Circuit Values to Shunt Around 250 µA Away from the LED (According to Figure 5)
VDD 5V IF 3 mA R1 Value 1.0 k R2 Value 4.7 k
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Appnote 73 October 27. 1999-14
Figure 6. Logic Gate Shunt Drive Circuit
SFH6700 / 19 VDD
TTL / CMOS LOGIC
Figure 8. Series LED Drive with Speed-up Capacitor
CS VDD R1 R2 2 Data IN
TTL / CMOS LOGIC
SFH6700 / 19 1 NC VCC 8 Out 7
Data IN
SFH6700 / 19 VDD Data Open Collector IN Drain R1 2 3 GND 4 NC GND 5 1 NC VCC 8 Out 7
VDD 5V CS Value 100 pF R1 Value 1.0 k R2 Value 75
Drive Circuits for the Dual Channel Devices The SFH6731 / 32 can be driven as simple as the single channel devices. All drive circuits and the equations (1) to (8) can be adapted to drive the dual channel devices. (The use of the dual channel devices reduces the number of parts and the required board space.) Output Circuitry The advantage of the SFH67XX series is its easy connection to any logic system, because of the active output stage (totem pole / three state output). Either direct or via a pull-up resistor, all couplers can drive up to 16 LS TTL loads (4 TTL loads) easily. In general, a 0.1 µF bypass capacitor is strongly recommended for proper operation. The SFH6700 / 19 with its three state output fits best in bus applications because of the possibility to switch the couplers output into the high ohmic state (for a typical setup please refer to Figure 28). Interfacing to TTL / TTL Compatible Logic Interfacing the SFH67XX coupler to LS TTL or any other compatible logic is quite simple. The active output of this coupler eliminates the use of an external pull up resistor, and minimizes the number of parts and saves board space. The typical connection is seen in Figure 9. Even HCT logic can be interfaced this way.
Table 4. Typical Input Circuit Values for a Circuit According to Figure 7
VDD 5V 10 V 15 V IF 3 mA 3 mA 3 mA R1 Value 1.10 k 2.80 k 4.42 k
Input Circuitry for Improved Switching Speed If switching speed is a concern, the use of a speed-up capacitor is a good solution. The resistor R2 limits the peek transient current IFpeak, whereas R1 and R2 determine the current at steady operation. The equations and reasonable resistor values are printed below. A reasonable value for the speed-up capacitor CS is 100 pF.
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Appnote 73 October 27. 1999-14
Figure 9. Interfacing the Coupler to TTL, LS TTL or Compatible Logic
TTL / LS TTL INPUT
In CMOS applications however, where IIH is in the µA region, the limiting factor can also be determined by the maximum allowable rise time tr (500 ns for HC logic). The equation
VCC Data Out
NC 6 0.1 µF GND 5 GND
HCT Input
in which CL represents the total capacitance of the load, including the coupler (which is around 6 pF). The resistor value is a compromise between the two requirements, power dissipation and switching speed. A low RP produces symmetrical and short switching times but results in a higher power dissipation. Reasonable values are shown in Table 6. To have an impression on the relationship between the rise time t r and the pull-up resistor RP / load capacitance CL, please refer to Figure 14 for details. Figure 11. Interfacing SFH6705 (Open Collector Output) to CMOS Logic
SFH6705 1 NC 2 3 4 NC VCC Data Out at CMOS Logic Level G ND V CC 8 NC 7 Out 6 5 0.1 µF VCC
CMOS Input
Data Out GND
0.1 µF GND
By using a totem pole device, the equations (9) and (10) are also valid, but the pull-up resistor has only to bring up the voltage difference between VOH (VCC -1.8 V) and the input switching limit, e.g. 3.5 V for HC logic, which makes a V of 0.3 V. This allows to use a higher RP which results in lower power consumption. Figure 12. Interfacing SFH67XX (Totem Pole Output) to CMOS Logic
CMOS Input
VCC Data Out
NC 6 0.1 µF GND 5 GND
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Appnote 73 October 27. 1999-14
Table 6. Typical Values for RP by Connecting to CMOS Logic (According to Figures 11 and 12)
VCC 5V RP (Open Collector) 820 RP (Totem Pole) 1.10 k
1000 900 800 Rise Time, tr (ns) 700 600 500 400 300 200 100 0
1 10 100 RC Time Constant (ns) 1000
Figure 15. Test Circuit for Rise Time tr vs. Time Constant
3.3 V Logic
RP Out CL GND
Data Out
IF Time
NC 6 0.1 µF GND 5 GND
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Appnote 73 October 27. 1999-14
Figure 16. Principle Board Layout for Enhanced CMTI (Fits to Schematic in Figure 18)
SFH6719 VCC (top layer)
0.1 µF
GND (bottom layer)
A circuit which brings additional safety concerning CMTI is shown in Figure 17. The diode D1 is intended to sink parasitic current, which is caused by stray capacitance, away from the LED to prevent a false turn-on. Figure 17. Input Circuitry for Improved CMTI
SFH6719 D1 VDD R1 Data IN
CMOS LOGIC
Pulse Width Distortion, PWD (ns)
50 40 30 20 10 0 -60 -40 -20 0 20 40 60 Temperature, TA (°C) 80 100
GND Diode D1: Any signaling diode
SFH6719 1 NC VDD R1 2 Data IN RS Q1 3 4 NC GND Transistor Q1: Any switching transistor (e.g. 2N2222) VE 6 GND 5 VCC 8 Out 7
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Appnote 73 October 27. 1999-14
Propagation Delay Skew, tPSK (ns)
Figure 23. Typical 5 Mb / s Eye Pattern Diagram-NRZ Code (Test Circuit See Figure 24)
SFH6701 / 11 1 NC
-40 -20 0 20 40 60 Temperature, TA (°C) 80 100
5V 1.1 k Output Monitoring 5V
74LS04
In logic circuits it must be noticed that the overall PWD and tPSK are determined by all input and output logic gates in the signal path. To minimize the overall PWD, the use of two identical couplers compensates their influence, like seen on Figure 22. Note that the minimum PWD is achieved on costs of a higher overall propagation delay. Figure 22. Minimization of PWD by Using Two SFH67XX in Series
74LS04
0.1 µF
Input Monitoring
5. Design Ideas Optocouplers are commonly used as an interface between two circuits, where galvanic insulation is required, either to protect humans or sensitive electronic equipment behind or in front of it. Based on this requirement, some designs are presented below, which use the SFH67XX series.
SFH6702 / 12 1 NC
0.1 µF
74LS04
Eye Pattern Diagram A typical eye pattern diagram for 5 Mb / s data transmission is presented in Figure 23. The eye pattern testing was done with a pseudo random data sequence (NRZ coding).
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Appnote 73 October 27. 1999-14
Figure 25. SFH6711 as a Fast IPM-IGBT Driver
Galvanic Insulation +VCC SFH6711 1 NC BAR 74 5V 1.1 k Data IN
74HCT04
+VS IPM - Intelligent Power Module
IGBT / MOSFET Driver
IGBT Module
Out 7 Protection / Suppression Unit
GND 5 GND
Figure 26. Switching High Current and Voltage Loads
SFH6712 1 NC 2 3 4 NC V CC 8 NC 7 Out 6 G ND 5 5V LOAD R1 1k Q1 BSP89 0.1 µF BUZ104SL BUZ73L G ND V SS
Opto-Insulated DAC Interface When galvanic insulation in digital-to-analog-conversion or analog-to-digital-conversion systems is required, the SFH67XX series is a good choice for an interface. Setups like the one in Figure 29 provide a fast and part saving insulation barrier. The low propagation delay skew of the SFH67XX family makes them ideal for use in parallel data transfer. The SFH67XX series provide an optimal interface solution for the SAB 80 C167 / C165 microcontrollers by supporting the 5 Mb / s data rate at a 20 MHz CPU clock.
Transistor Q1: Any n-channel enhancement transistor Resistor R1: R1 might be omitted, depending on the necessary VGS of Q1 to turn Q1 fully on
Figure 27. Switching High Current Loads
SFH6711 1 NC 2 3 4 NC V CC 8 Out 7 NC 6 G ND 5 0.1 µF LOAD G ND 1k Q1 SP0610T V SS
Transistor Q1: Any p-channel enhancement transistor
Time Multiplexed Bus Line Access with Optical Insulation Barrier The schematic in Figure 28 shows the use of a common data bus line with 4 independent data lines in time multiplexing mode. The 2-line to 4-line address decoder selects one of the 4 data lines by enabling the output, whereas all the other outputs remain in the high ohmic state.
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Appnote 73 October 27. 1999-14
Figure 28. Typical Setup for a Common Bus Line with 4 Different Lines in Time Multiplex Mode
Galvanic Insulation Barrier 5V SFH6700 / 19 1 NC 1.1 k 2 3 4 NC V CC 8 Out 7 0.1 µF Data Line 1
74HCT04
Common Data Bus
SFH6700 / 19 1 NC 1.1 k 2 3 4 NC V CC 8 Out 7 0.1 µF Data Line 2
74HCT04
VE 6 G ND 5 Y0 B Y1 74HCT139 2-Line to 4-Line Y2 Decoder G Enable Y3 0.1 µF A
Select Inputs
Data Line 3
74HCT04
Truth Table
Active on Bus Line none (all high ohmic) Data Line 1 Data Line 2 Data Line 3 Data Line 4
SFH6700 / 19 1 NC 1.1 k 2 3 4 NC V CC 8 Out 7 0.1 µF Data Line 4
74HCT04
Common Data Bus
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Appnote 73 October 27. 1999-14
Figure 29. Fully Galvanic Insulated Digital-to-AnalogConversion System (4 Channel DAC)
5V 0.33 µF V CC FS D1 MAX845 Transformer Driver SD D2 GND1 GND2 Galvanic Insulation Barrier 78L05 0.33 µF +
5V 2.2 µF
MAX873
0.33 µF
2 x BAW56 Diodes HALO TGM-030P3 Transformer V DD SFH6731 / 32
0.1 µF
SAB 80C167 Microcontroller Synchronous Serial Channel (SSC) / SPI P3.13 / SCLK CLK P3.9 / MTSR Data
74HCT04
REFAB CL SCLK REFCD 10 k 10 k DIN MAX525 Digital-to-Analog Converter OUTA FBB OUTB 10 k FBC 10 k 7 0.1 µF CS DOUT UPO PDL GNDD OUTD AGND OUTC FBD 10 k 10 k Channel D 0..5 V Channel C 0..5 V 10 k 10 k Channel B 0..5 V Channel A 0..5 V
74HCT04
Inverter 74HCT04 is used to allow 3 mA LED current Any C16X microcontroller can be used
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Appnote 73 October 27. 1999-14