FlexQII Volt Synchronous First-In/First-Out Queue Memory Configur
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
FlexQII Volt Synchronous First-In/First-Out Queue
Memory Configuration
262,144 131,072 65,536 32,768 16,384 8,192
Part Number
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
Features
Industry leading First-In/First-Out Queues MHz) Write cycle time independent Read cycle time (Data Setup time 2.0ns) Read cycle time independent Write cycle time (Data Access time 4.0ns) 3.3V power supply input tolerant control data input pins output tolerant flags data output pins Master Reset clears previously programmed configurations including Write Read pointers Partial Reset clears Write Read pointers maintains previously programmed configurations First Word Fall Through (FWFT) Standard Timing modes Presets eight different Almost Full Almost Empty offset values Parallel/Serial programming PRAF PRAE offset values Full, Empty, Almost Full, Almost Empty, Half Full indicators Asynchronous output enable tri-state data output drivers Data retransmission Available package: Plastic Thin Quad Flat Pack (TQFP) (0°C 70°C) Commercial operating temperature available cycle time above (-40°C 85°C) Industrial operating temperature available cycle time above
Product Description
HBA's FlexQII offers industry leading FIFO queuing bandwidth Gbps), with wide range memory configurations (from 8,192 262,144 18). System designer full flexibility implementing deeper wider queues using FWFT mode width expansion features. Full, Empty, Half-Full indicators allow easy handshaking between transmitters receivers. User programmable Almost Full Almost Empty (Parallel/Serial) indicators allow implementation virtual queue depths. tolerant input output pins allow easy interfacing with devices operating higher voltage levels. Asynchronous Output Enable configures tri-state data output drivers. Independent Write Read controls provide rate-matching capability. Master Reset clears previously programmed configurations providing pulse MRST pin. addition, Write Read pointers queue initialized zero. Partial Reset will alter previously programmed configurations will initialize Write Read pointers zero. FWFT mode, first data written into queue appears output data after specified latency period high transition RCLK. Subsequent reads from queue will require asserting This feature useful when implementing depth expansion functions. this mode, DRDY QRDY used instead FULL EMPTY respectively. Standard mode, always assert read operation. FULL EMPTY used instead DRDY QRDY respectively. PRAF PRAE HALF available either FWFT Standard mode. time, data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. Both zero normal latency timing modes available retransmit operation.
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Product Description (Continued)
These FlexQII devices have power consumption, hence minimizing system power requirements. addition, industry standard Plastic TQFP. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.
Block Diagram Single Synchronous Queue 262,144 131,072 65,536 32,768 16,384 8,192
PARTIAL RESET PRST)
MASTER RESET (MRST
WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD LOAD) DATA (D17 SERIAL DATA ENABLE (SDEN) FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG INPUT READY FULL DRDY PROGRAMMABLE ALMOST-FULL (PRAF FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE DATA (Q17 RETRANSMIT RET) EMPTY FLAG OUTPUT READY EMPTY/ QRDY PROGRAMMABLE ALMOSTEMPTY PRAE) HALF-FULL FLAG (HALF
Figure Single Device Configuration Signal Flow Diagram
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
WCLK
LOAD SDEN FWFT/SDI Write Control Logic
FULL DRDY PRAF EMPTY QRDY Flag Logic PRAE HALF FWFT/SDI
Offset Register
Write Pointer
17-0
Input Register
SRAM
Output Register
Output Buffer
17-0
Read Pointer
Read Control Logic
Reset
RCLK
MRST PRST
Figure Device Architecture
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
FULL/DRDY
FWFT/SDI
EMPTY/QRDY
WCLK
MRST
LOAD
PRAF
HALF
PRAE
PRST
RCLK
Index
SDEN DC(1)
TQFP (Order code: View
Don't Care. Must tied Vcc, cannot left open.
Figure Device
NOTES:
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
Name Symbol Input/Output Description
Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK low. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming eight default offset values. LOAD high select serial programming eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively. conjunction with
Master Reset
MRST
Input
Partial Reset
PRST
Input
Write Clock Write Enable
WCLK
Input Input
Load Enable
LOAD
Input
6,7,8,9, 10,11,12,13, 14,15,16,17, 18,19,20,21, 22,23
Data Inputs
Input
wide input data bus.
Read Clock Read Enable
RCLK
Input Input
Reads data from queue during high transitions RCLK low. Controls read operation from queue offset registers during high transition RCLK. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z).
48,47,45,44, 42,41,40,38, 37,36,35,34, 32,31,29,28, 26,25
Output Enable
Input
Data Outputs
Output
wide output data bus.
First Word Fall Through/Serial Data Input
FWFT/SDI
Input
Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN
Table Descriptions
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Name
Serial Data Input Enable
Symbol
SDEN
Input/Output
Input
Description
serial programming selected, setting SDEN LOAD enables serial data input written into offset registers during high transition WCLK. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue. Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue. FWFT mode, queue empty when QRDY goes high during high transition RCLK. This prohibits further reads from queue. Queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty +offset) programmed offset values determine status PRAE Queue more than half full when HALF goes low. Triggered both WCLK RCLK. This tied high low, cannot left open. 3.3V power supply. Ground.
Retransmit
Input
Full/Data Input Ready Flag
FULL DRDY
Output
Empty/Data Output Ready Flag
EMPTY QRDY
Output
Almost Full
PRAF
Output
Almost Empty
PRAE
Output
Half Full Don't Care Power Ground
HALF
Output
Table Descriptions (Continued)
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Symbol
VTERM
Rating
Terminal Voltage with respect Storage Temperature
Com'l Ind'l
-0.5
Unit
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
TSTG
+125
IOUT
Output Current
Table Absolute Maximum Ratings
Symbol Parameter Recommended Operating Conditions
Supply Voltage Com'l Ind'l Supply Voltage Input High Voltage Com'l Ind'l Input Voltage Com'l Ind'l Operating Temperature Commercial Operating Temperature Industrial Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage,
2105, FQV295, FQV285, FQV275, FQV265, FQV255 Commercial Industrial Clock 6ns, 7.5ns, 10ns, Clock 7.5ns, 10ns, 15ns 15ns Min. Typ. Max. Min. Typ. Max.
Unit
Electrical Characteristics
ILI(1)
Power Consumption
Icc1(2,3) Icc2(4) Active Power Supply Current Standby Current
Table Specifications
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Capacitance 100MHz Ambient Temperature (25°C)
Symbol
Parameter Input Capacitance Output Capacitance
Conditions VIN= VOUT=
Max.
Unit
COUT(2,4)
NOTES:
Measurement with 0.4<=VIN<=Vcc With output tri-stated High) Icc(1,2) measured with WCLK RCLK Design simulated, tested.
Table Specifications (Continued)
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Commercial FQV2105-6 FQV295-6 FQV285-6 FQV275-6 FQV265-6 FQV255-6 Symbol
tWCLK tWCLKH tWCLKL tRCLK tRCLKH tRCLKL tENS tENH tRST tRSTS tRSTR tRSTF tOLZ tOHZ tFULL tEMPTY tPRAFS tPRAES tSKEW1 tSKEW2 tSKEW3 tLOADS tLOADH
Commercial Industrial FQV2105-7.5 FQV295-7.5 FQV285-7.5 FQV275-7.5 FQV265-7.5 FQV255-7.5 Min.
FQV2105-10 FQV295-10 FQV285-10 FQV275-10 FQV265-10 FQV255-10 Min.
FQV2105-15 FQV295-15 FQV285-15 FQV275-15 FQV265-15 FQV255-15 Min.
Parameter
Clock Cycle Frequency Data Access Time Write Clock Cycle Time Write Clock High Time Write Clock Time Read Clock Cycle Time Read Clock High Time Read Clock Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset Flag Output Time Output Enable Output Low-Z(1) Output Enable Output Valid Output Enable Output High-Z Write Clock Full Flag Read Clock Empty Flag Write Clock Almost-Full Flag Read Clock Almost-Empty Flag Skew time between Read Clock Write Clock FULL DRDY Skew time between Read Clock Write Clock PRAF PRAE Skew time between Read Clock Write Clock EMPTY QRDY Load Setup Time Load Hold Time
Min.
Max.
Max.
Max.
Max.
Unit
Table Electrical Characteristics
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Commercial FQV2105-6 FQV295-6 FQV285-6 FQV275-6 FQV265-6 FQV255-6 Symbol
tRETS tHALF
Commercial Industrial FQV2105-7.5 FQV295-7.5 FQV285-7.5 FQV275-7.5 FQV265-7.5 FQV255-7.5 Min.
FQV2105-10 FQV295-10 FQV285-10 FQV275-10 FQV265-10 FQV255-10 Min.
FQV2105-15 FQV295-15 FQV285-15 FQV275-15 FQV265-15 FQV255-15 Min.
Parameter
Retransmit Setup Time Clock HALF
Min.
Max.
Max.
Max.
Max.
Unit
NOTES:
Design simulated, tested
Table Electrical Characteristics (Continued)
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Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load, clock 6ns, Output Load clock 10ns, 15ns
Include scope capacitances Table Test Condition
3.0V 1.5V 1.5V Refer Figure Refer Figure
3.3V Vcc/2 D.U.T. 30pF*
Figure Test Load clock 6ns, 7.5ns
Figure Output Load clock 10ns, 15ns *Includes scope capacitances.
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MRST Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK activated. Synchronizes FULL DRDY PRAF flags. WCLK RCLK independent each other. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming eight default offset values. LOAD high select serial programming eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively parallel programming. conjunction with During programming offset registers, PRAF PRAE flag status invalid. Serial programming, LOAD used enable serial loading offset registers together with SDEN Refer Figure details. wide input data bus. Reads data from queue during high transitions RCLK low. Synchronizes EMPTY QRDY PRAE flags. RCLK WCLK independent each other. Reads data from queue during high transitions RCLK low. This also advances Read pointer queue. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). does control advancement Read pointer. wide output data bus. Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN FWFT mode, DRDY QRDY used instead FULL EMPTY Refer Table flags status. Standard mode, FULL EMPTY used instead DRDY QRDY Refer Table flags status. serial programming selected, setting SDEN LOAD enables serial data written into offset registers during high transition WCLK. During serial programming, PRAF PRAE flags status invalid. Refer Figure details. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero), location queue. Refer Diagram details.
PRST
WCLK
LOAD
D17-0 RCLK
Q17-0 FWFT/SDI
SDEN
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FULL DRDY Standard mode, queue full when FULL goes during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. Refer Table behavior FULL DRDY Standard mode, queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. FWFT mode, queue empty when QRDY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. Refer Table behavior EMPTY QRDY Synchronous mode, queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Asynchronous timing mode, PRAF triggered both WCLK RCLK. Refer Table behavior PRAF Synchronous mode, queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE Asynchronous timing mode, PRAF triggered both WCLK RCLK. Refer Table behavior PRAE Queue more than half full when HALF goes during high transition WCLK. HALF goes high during high transition RCLK when queue less than half full. Refer Table details.
EMPTY QRDY
PRAF
PRAE
HALF
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LOAD
SDEN
WCLK
RCLK
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255 Selection Sequence
Write offset registers: Empty Offset Full Offset Parallel write registers: PRAE PRAF Parallel read from registers: PRAE PRAF
Read from offset registers: Empty Offset Full Offset
Serial shift into registers: bits FQV2105 bits FQV295 bits FQV285 bits FQV275 bits FQV265 bits FQV255 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Operation Write Memory
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence
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Device
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
PRAF Programming (bits)
D/Q15 D/Q1 D/Q15 D/Q0 D/Q15 D/Q14 D/Q13 D/Q12 7FH, when LOAD 3FFH, when LOAD Word High Word Word High Word
PRAE Programming (bits)
D/Q15 D/Q1 D/Q15 D/Q0 D/Q15 D/Q14 D/Q13 D/Q12 7FH, when LOAD 3FFH, when LOAD Word High Word Word High Word
Table Parallel Offset Register Data Mapping Default Values (DV) Table
Part Number
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
Standard Mode
262,144 131,072 65,536 32,768 16,384 8,192
FWFT
262,145 131,073 65,537 32,769 16,385 8,193
Table Maximum Depth Queue Standard FWFT Mode
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Data Width
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAE Cycle PRAF
FQV285, FQV275, FQV265, FQV255 Parallel Offset Write/Read Cycles Width
Data Width
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAE Cycle PRAE Cycle PRAF Cycle PRAF
FQV2105, FQV295 Parallel Offset Write/Read Cycles Width
Bits Offset Registers bits FQV2105 bits FQV295 bits FQV285 bits FQV275 bits FQV265 bits FQV255 Note: Don't Care applies unused bits
Figure Parallel Offset Write/Read Cycles Diagram
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
FQV2105
y(1) (y+1) 131,072 131,073 [262,144-(x+1)] (262,144-x(2)) 262,143 262,144
FULL
PRAF
HALF
PRAE
EMPTY
FQV295
y(1) (y+1) 65,536 65,537 [131,072-(x+1)] (131,072-x(2)) 131,071 131,072
FULL
PRAF
HALF
PRAE
EMPTY
FQV285
y(1) (y+1) 32,768 32,769 [65,536-(x+1)] (65,536-x(2)) 65,535 65,536
FULL
PRAF
HALF
PRAE
EMPTY
FQV275
y(1) (y+1) 16,384 16,385 [32,768-(x+1)] (32,768-x(2)) 32,767 32,768
FULL
PRAF
HALF
PRAE
EMPTY
FQV265
y(1) (y+1) 8,192 8,193 [16,384-(x+1)] (16,384 -x(2)) 16,383 16,384
FULL
PRAF
HALF
PRAE
EMPTY
FQV255
y(1) (y+1) 4,096 4,097 [8,192-(x+1)] (8,192-x(2)) 8,191 8,192
NOTES:
FULL
PRAF
HALF
PRAE
EMPTY
PRAE offset; Default Values: when parallel offset loading selected =1,023 when serial offset loading selected. PRAF offset; Default Values: when parallel offset loading selected =1,023 when serial offset loading selected.
Table Status Flags (Standard Mode)
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
FQV2105
y(1)+1 (y+2) 131,073 131,074 [262,145-(x+1)] (262,145-x(2)) 262,144 262,145
DRDY
PRAF
HALF
PRAE
QRDY
FQV295
y(1)+1 (y+2) 65,537 65,538 [131,073-(x+1)] (131,073-x(2)) 131,072 131,073 FQV285 y(1)+1 (y+2) 32,769 32,770 [65,537-(x+1)] (65,537-x(2)) 65,536 65,537 FQV275 y(1)+1 (y+2) 16,385 16,386 [32,769-(x+1)] (32,769-x(2)) 32,768 32,769 FQV265 y(1)+1 (y+2) 8,193 8,194 [16,385-(x+1)] (16,385 -x(2)) 16,384 16,385 FQV255 y(1)+1 (y+2) 4,097 4,098 [8,193-(x+1)] (8,193-x(2)) 8,192 8,193
NOTES:
DRDY
PRAF
HALF
PRAE
QRDY
DRDY
PRAF
HALF
PRAE
QRDY
DRDY
PRAF
HALF
PRAE
QRDY
DRDY
PRAF
HALF
PRAE
QRDY
DRDY
PRAF
HALF
PRAE
QRDY
PRAE offset; Default Values: when parallel offset loading selected =1,023 when serial offset loading selected. PRAF offset; Default Values: when parallel offset loading selected =1,023 when serial offset loading selected.
Table Status Flags (FWFT Mode)
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255 Timing Diagrams
tRST MRST tRSTS tRSTS tFWFT FWFT/SDI tRSTS LOAD tRSTS tRSTS SDEN tRSTF FWFT QRDY EMPTY QRDY tRSTF FULL DRDY tRSTF PRAE tRSTF PRAF HALF tRSTF FWFT FULL FWFT DRDY FWFT EMPTY tRSTR tRSTR tRSTR tRSTR
Diagram Master Reset Timing
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tRST PRST tRSTS tRSTS tRSTS tRSTS SDEN tRSTF FWFT 1,QRDY EMPTY QRDY tRSTF FWFT FULL FULL/ DRDY tRSTF PRAE tRSTF PRAF HALF tRSTF FWFT DRDY FWFT EMPTY tRSTR tRSTR
Diagram Partial Reset Timing
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Write tWCLKH
Write WCLKL
tWCLK Write tFULL tFULL
WCLK
FULL tSKEW1
tSKEW1
tFULL
FULL
RCLK
tENH tENH
tENS
Data Read Next Data Read
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
Output Register Data
NOTES:
time between rising edge RCLK rising edge WCLK greater than equal tSKEW1, FULL will high (after WCLK cycle plus tFULL). tSKEW1 met, then FULL will assert more WCLK cycles. LOAD High, Low.
Diagram Write Cycle Full Flag Timing (Standard Mode)
Preliminary
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RCLK tRCLKH
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tRCLKL tENS tENH tENS tENH tENH tEMPTY tEMPTY tEMPTY Last Word tSKEW1 tOHZ Last Word tENS tENH
RCLK
tENS
EMPTY
tOLZ
WCLK
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW11, EMPTY will high (after RCLK cycle plus tEMPTY). tSKEW1 met, then EMPTY will assert more RCLK cycles.
LOAD High. First word latency: tSKEW1 tEMPTY tRCLK.
Diagram Read Cycle, Empty Flag First Data Word Latency Timing (Standard Mode)
Preliminary
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WCLK
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DW[y+2] DW[y+3] DW[y+4] DW[(D-1)/2+1] DW[(D-1)/2+2] DW[(D-1)/2+3] DW[D-x-1] DW[D-x] DW[D-x+1] DW[D-x+2] DW[D-x+3] DW[D-1] tEMPTY tFULL
tENS
RCLK
Output Register Data
QRDY
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
Diagram Write Timing (FWFT Mode)
PRAE
HALF
PRAF
DRDY
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW1, QRDY will (after RCLK cycle plus tEMPTY). tSKEW1 met, then QRDY will assert more RCLK cycles. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES tSKEW2 met, then PRAE will assert more RCLK cycles.
LOAD High, Low. PRAE offset, PRAF offset. maximum queue depth. Please refer Table Depth. First word latency: tSKEW1 tEMPTY tRCLK
Preliminary
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WCLK
tSKEW2
tSKEW1
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tENS
RCLK
DWx+2 [(D-1)/2+2]
[(D-1)/2+1] [D-y-1] [D-y] [D-y+1] [D-y+2]
[D-1] tEMPTY
QRDY tPRAES
PRAE tHALF
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
tPRAFS FULL
HALF
PRAF
FULL
DRDY
NOTES:
time between rising edge RCLK rising edge WCLK greater than equal tSKEW1, DRDY will (after WCLK cycle plus tFULL) tSKEW1 met, then DRDY will assert more WCLK cycles.
time between rising edge RCLK rising edge WCLK greater than equal tSKEW2, PRAF will high (after WCLK cycle plus tPRAFS) tSKEW2 met, then PRAF will assert more WCLK cycles.
LOAD High PRAE Offset, PRAF offset. maximum queue depth. Please refer Table Depth.
Diagram Read Timing (FWFT Mode)
Preliminary
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FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
RCLK
tENS
tRETS
DWi+1 SKEW2
WCLK
tRETS
tENS
tENH
EMPTY
EMPTY
tEMPTY
PRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after EMPTY returns high. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid.
Diagram Retransmit Timing (Standard Mode)
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RCLK
tENS tENH tRETS tENH tENH
tSKEW2
WCLK
tRETS
tENS tENH
tEMPTY tEMPTY
QRDY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after QRDY returns low. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid. Please refer Table Depth.
Diagram Retransmit Timing (FWFT Mode)
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WCLK SDEN LOADS LOAD LOADH LOADH tENH
PRAE Offset
PRAF Offset
Refer Table
Diagram Serial Loading Programmable Flag Registers (Standard FWFT Mode)
FQV2105
FQV295
FQV285
FQV275
FQV265
FQV255
Table Reference Table Diagram
March 2001
Preliminary
Page
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
tWCLK WCLKH WCLK LOADS LOAD PRAE offset PRAF offset tLOADH LOADH WCLKL
Diagram Parallel Loadi Programmable Flag Registers (Standard FWFT Mode)
tRCLK RCLKH RCLK tLOADS LOAD Data Output Register
PRAE
tRCLKL
tLOADH
tLOADH
tENH
tENH
offset
PRAF
offset
Diagram Parallel Read Programmable Flag Registers (Standard FWFT Mode)
March 2001
Preliminary
Page
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
tWCLKH WCLK PRAF words Queue SKEW2 RCLK tENH tENH tPRAFS words Queue PRAFS D-(x+1) words Queue WCLKL
NOTES:
PRAF offset. maximum queue depth. Please refer Table Depth. time between rising edge RCLK rising edge WCLK greater than equal tSKEW2, PRAF will high (after WCLK cycle plus tPRAFS). tSKEW2 met, then PRAF will assert more WCLK cycles. PRAF synchronizes rising edge WCLK only.
Diagram Programmable Almost-Full Flag Timing (Standard FWFT Mode)
tWCLKH WCLK tWCLKH PRAE
tWCLKL
tWCLKL
words Queue(2) words Queue tSKEW2 tPRAES
words Queue(2) words Queue tPRAES tENS tENH
words Queue(2) words Queue(3)
RCLK
NOTES:
PRAE offset. Standard Mode. FWFT Mode. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES tSKEW2 met, then PRAE will assert more RCLK cycles. PRAE synchronizes rising edge RCLK only.
Diagram Programmable Almost-Empty Flag Timing (Standard FWFT Mode)
March 2001
Preliminary
Page
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
tWCLKH
tWCLKL
WCLK
tENS tENH
tHALF
HALF
words Queue [(D+1)/2] words Queue
words Queue [(D+1)/2 words Queue(2) tHALF
words Queue [(D+1)/2] words Queue(2)
RCLK
tENS
NOTES:
Standard Mode. FWFT Mode. Please refer Table Depth.
Diagram Half-Full Flag Timing (Standard FWFT Mode)
March 2001
Preliminary
Page
FQV2105 FQV295 FQV285 FQV275 FQV265 FQV255
Order Information:
Device Family
Device Type XXXX V2105 (262,144 V295 (131,072 V285 (65,536 V275 (32,768 V265 (16,384 V255 (8,192
Power
Speed (ns)
Package**
Temperature Range
Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
*Speed available only Commercial temp (0°C 70°C) **Package Plastic Thin Quad Flat Pack (TQFP) Example: FQV275L6PF FQV265L10PFI (32k Commercial temp) (16k Industrial temp)
High Bandwidth Access 2107 North First Street, Suite Jose, 95131 Tel: 408.453.8885 Fax: 408.453.8886 www.hba.com sales@hba.com
March 2001
Preliminary
Page
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