FlexQII Volt Synchronous First-In/First-Out Queue Memory Configur

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FlexQII Volt Synchronous First-In/First-Out Queue Memory Configur

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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQII Volt Synchronous First-In/First-Out Queue
Memory Configuration
524,288 262,144 131,072 65,536 32,768 16,384
Part Number
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Features
Industry leading First-In/First-Out Queues MHz) Write cycle time independent Read cycle time (Data Setup time Read cycle time independent Write cycle time (Data Access time User selectable input output port bus-sizing Endian/Little Endian user selectable byte representation 3.3V power supply input tolerant control data input pins output tolerant flags data output pins Master Reset clears previously programmed configurations including Write Read pointers. Partial Reset clears Write Read pointers maintains previously programmed configurations. First Word Fall Through (FWFT) Standard Timing modes Preset Almost Full PRAF Almost Empty PRAE offsets values Parallel/Serial programming PRAF PRAE offset values Full, Empty, Almost Full, Almost Empty Half Full indicators Asynchronous output enable tri-state data output drivers Data retransmission Available package: Plastic Thin Quad Flat Pack (TQFP) (0°C 70°C) Commercial operating temperature available cycle time above (-40°C 85°C) Industrial operating temperature available cycle time above
Product Description
HBA's FlexQII offers industry leading FIFO queuing bandwidth Gbps) with wide range memory configurations (from 16,384 524,288 System designer full flexibility implementing deeper wider queues using FWFT mode width expansion features. Full, Empty, Half-Full indicators allow easy handshaking between transmitters receivers. User programmable Almost Full Almost Empty (Parallel/Serial) indicators allow implementation virtual queue depths. tolerant input output pins allow easy interfacing with devices operating higher voltage levels. Asynchronous Output Enable configures tri-state data output drivers. Independent Write Read controls provide rate-matching capability. Master Reset clears previously programmed configurations providing pulse MRST pin. addition, Write Read pointers queue initialized zero. Partial Reset will alter previously programmed configurations will initialize Write Read pointers zero. FWFT mode, first data written into queue appears output data after specified latency period high transition RCLK. Subsequent reads from queue will require asserting This feature useful when implementing depth expansion functions. this mode, DRDY QRDY used instead FULL EMPTY respectively. Standard mode, always assert read operation. FULL EMPTY used instead DRDY QRDY respectively.
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Product Description (Continued)
PRAF PRAE HALF available either FWFT Standard mode. PRAF PRAE operate either synchronous asynchronous modes. time, data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero), location queue. These FlexQII devices have power consumption, hence minimizing system power requirements. addition, industry standard Plastic TQFP offered save system board space. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.
Block Diagram Single Synchronous Queue 524,288 262,144 131,072 65,536 32,768 16,384
PARTIAL RESET PRST
MASTER RESET MRST
WRITE CLOCK (WCLK) WRITE ENABLE WEN) LOAD LOAD) DATA SERIAL DATA ENABLE (SDEN) FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG INPUT READY FULL DRDY) PROGRAMMABLE ALMOST-FULL (PRAF) FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
READ CLOCK (RCLK) READ ENABLE (REN OUTPUT ENABLE (OE) DATA RETRANSMIT RET) EMPTY FLAG OUTPUT READY EMPTY QRDY PROGRAMMABLE ALMOSTEMPTY PRAE HALF-FULL FLAG HALF
Figure Single Device Configuration Signal Flow Diagram
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
WCLK
LOAD SDEN FWFT/SDI Write Control Logic FULL DRDY PRAF Offset Register Flag Logic
EMPTY/ QRDY PRAE
HALF FWFT/SDI
Write Pointer
Input Register
SRAM
Output Register
Output Buffer
Read Pointer
Read Control Logic
Reset
RCLK
MRST PRST
Figure Device Architecture
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
EMPTY/QRDY
FULL/DRDY
WCLK
LOAD
FWFT/SDI
MRST
HALF
RCLK
PRAE
PRAF
PRST
SDEN DC(1)
DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2)
TQFP (Order code: View NOTES:
Don't Care. Must tied Vcc, cannot left open. Connect.
Figure Device
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Name
Symbol
Input/Output
Description Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK low. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming default offset value 127. LOAD high select serial programming default offset value 1023. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively. conjunction with wide input data bus. Reads data from queue during high transitions RCLK low. Controls read operation from queue offset registers during high transition RCLK. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). wide output data bus. Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN
Master Reset
MRST
Input
Partial Reset
PRST
Input
Write Clock Write Enable
WCLK
Input Input
Load Enable
LOAD
Input
15,16,17, 18,19,20, 21,22,23
Data Inputs
RCLK
Input
Read Clock Read Enable
Input Input
36,35,34, 32,31,29, 28,26,25
Output Enable
Input
Data Outputs
Output
First Word Fall Through/Serial Data Input
FWFT/SDI
Input
Table Descriptions
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Name
Serial Data Input Enable
Symbol
Input/Output
Input
Description
serial programming selected, setting SDEN LOAD enables serial data input written into offset registers during high transition WCLK. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue. Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue. FWFT mode, queue empty when QRDY goes high during high transition RCLK. This prohibits further reads form queue. Queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE Queue more than half full when HALF goes low. Triggered both WCLK RCLK. This tied high low, cannot left open. 3.3V power supply. Ground.
SDEN
Retransmit
Input
Full Data Input Ready Flag
FULL DRDY
Output
Empty Data Output Ready Flag
EMPTY QRDY
Output
Almost Full
PRAF
Output
Almost Empty
PRAE
Output
Half Full Don't Care Power Ground Connect
HALF
Output
connect.
Table Descriptions (Continued)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Symbol VTERM
Rating Terminal Voltage with respect Storage Temperature
Com'l Ind'l -0.5
Unit
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
TSTG
+125
IOUT
Output Current
Table Absolute Maximum Ratings
FQV2111, FQV2101, FQV291, FQV281, FQV271, FQV261 Commercial Clock 6ns, 7.5ns, 10ns, 15ns Symbol Parameter Min. Typ. Max. Industrial Clock 7.5ns, 10ns, 15ns Min. Typ. Max. Unit
Recommended Operating Conditions
Supply Voltage Com'l Ind'l Supply Voltage Input High Voltage Com'l Ind'l Input Voltage Com'l Ind'l Operating Temperature Commercial Operating Temperature Industrial
Electrical Characteristics
ILI(1) Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage,
Power Consumption
Icc1(2,3) Icc2(4) Active Power Supply Current Standby Current
Table Specifications
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Capacitance 100MHz Ambient Temperature (25°C)
Symbol CIN(2) COUT(2,4)
NOTES:
Measurement with 0.4<=VIN<=Vcc With output tri-stated High) Icc(1,2) measured with WCLK RCLK Design simulated, tested.
Parameter Input Capacitance Output Capacitance
Conditions VIN= VOUT=
Max.
Unit
Table Specifications (Continued)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Commercial FQV2111-6 FQV2101-6 FQV291-6 FQV281-6 FQV271-6 FQV261-6 Symbol tWCLK tWCLKH tWCLKL tRCLK tRCLKH tRCLKL tENS tENH tRST tRSTS tRSTR tRSTF tOLZ tOHZ tFULL tEMPTY tPRAFS tPRAES tSKEW1 tSKEW2 Parameter Clock Cycle Frequency Data Access Time Write Clock Cycle Time Write Clock High Time Write Clock Time Read Clock Cycle Time Read Clock High Time Read Clock Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset Flag Output Time Output Enable Output Low-Z(1) Output Enable Output Valid Output Enable Output High-Z Write Clock Full Flag Read Clock Empty Flag Write Clock Almost-Full Flag Read Clock Almost-Empty Flag Skew time between Read Clock Write Clock Full Flag Empty Flag Skew time between Read Clock Write Clock PRAF PRAE Skew time between Read Clock Write Clock EMPTY QRDY
Commercial Industrial FQV2111-7.5 FQV2101-7.5 FQV291-7.5 FQV281-7.5 FQV271-7.5 FQV261-7.5 Min. Max. FQV2111-10 FQV2101-10 FQV291-10 FQV281-10 FQV271-10 FQV261-10 Min. Max. FQV2111-15 FQV2101-15 FQV291-15 FQV281-15 FQV271-15 FQV261-15 Min. Max. Unit
Min.
Max.
tSKEW3
Table Electrical Characteristics
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Commercial FQV2111-6 FQV2101-6 FQV291-6 FQV281-6 FQV271-6 FQV261-6 Symbol tLOADS tLOADH tRTS
NOTES:
Design simulated, tested.
Commercial Industrial FQV2111-7.5 FQV2101-7.5 FQV291-7.5 FQV281-7.5 FQV271-7.5 FQV261-7.5 Min. Max. FQV2111-10 FQV2101-10 FQV291-10 FQV281-10 FQV271-10 FQV261-10 Min. Max. FQV2111-15 FQV2101-15 FQV291-15 FQV281-15 FQV271-15 FQV261-15 Min. Max. Unit
Parameter Load Setup Time Load Hold Time Retransmit Setup Time Clock HALF
Min.
Max.
Table Electrical Characteristics (Continued)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load, clock 6ns, Output Load clock 10ns, 15ns
3.0V 1.5V 1.5V Refer Figure Refer Figure
Include scope capacitances Table Test Condition
3.3V Vcc/2
D.U.T. 30pF*
Figure Test Load clock 6ns, 7.5ns
Figure Output Load clock 10ns, 15ns *Includes scope capacitances.
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Functions
MRST Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK activated. Synchronizes FULL DRDY PRAF flags. WCLK RCLK independent each other. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming default offset value 127. LOAD high select serial programming default offset value 1023. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively parallel programming. conjunction with During programming offset registers, PRAF PRAE flag status invalid. Serial programming, LOAD used enable serial loading offset registers together with SDEN Refer Figure details. wide input data bus. Reads data from queue during high transitions RCLK low. Synchronizes EMPTY QRDY PRAE flags. RCLK WCLK independent each other. Reads data from queue during high transitions RCLK low. This also advances Read pointer queue. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). does control advancement Read pointer. wide output data bus. Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN FWFT mode, DRDY QRDY used instead FULL EMPTY Standard mode, FULL EMPTY used instead DRDY QRDY Refer Table flags status. serial programming selected, setting SDEN LOAD enables serial data written into offset registers during high transition WCLK. During serial programming, PRAF PRAE flags status invalid. Refer Figure details. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. Refer Diagram details.
PRST
WCLK
LOAD
D8-0 RCLK
Q8-0 FWFT/SDI
SDEN
March 2001
Preliminary
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Functions (Continued)
FULL DRDY Standard mode, queue full when FULL goes during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. Refer Table behavior FULL DRDY Standard mode, queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. FWFT mode, queue empty when QRDY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. Refer Table behavior EMPTY QRDY Synchronous mode, queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Asynchronous timing mode, PRAF triggered both WCLK RCLK. Refer Table behavior PRAF Synchronous mode, queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE Asynchronous timing mode, PRAE triggered both WCLK RCLK. Refer Table behavior PRAE Queue more than half full when HALF goes during high transition WCLK. HALF goes high during high transition RCLK when queue less than half full. Refer Table details.
EMPTY QRDY
PRAF
PRAE
HALF
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
LOAD
SDEN
WCLK
RCLK
FQV281 FQV271 FQV261 Selection Sequence
Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel write registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte
Serial shift into registers: bits FQV281 bits FQV271 bits FQV261 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Operation Write Memory
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV281, FQV271 FQV261)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
LOAD
SDEN
WCLK
RCLK
FQV2111 FQV2101 FQV291 Selection Sequence
Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Empty Offset (Mid Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Serial shift into registers: bits FQV2111 bits FQV2101 bits FQV291 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Operation Write Memory Parallel write registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV291, FQV2101, FQV2111)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Device
FQV2111 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5
PRAF Programming (bits)
Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5
PRAE Programming (bits)
Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
FQV2101
FQV291 FQV281 FQV271 FQV261
FQV2111 FQV2101 FQV291
Byte Byte High Byte 7FH, LOAD FFH, LOAD 00H, LOAD 03H, LOAD
FQV281 FQV271 FQV261
7FH, LOAD FFH, LOAD 00H, LOAD 03H, LOAD
Table Parallel Offset Register Data Mapping Default Values
Part Number
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Standard Mode
524,288 262,144 131,072 65,536 32,768 16,384
FWFT Mode
524,289 262,145 131,073 65,537 32,769 16,385
Table Maximum Depth Queue Standard FWFT Mode
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Data Width Cycle PRAE (Low Byte) Cycle PRAE (Mid Byte) Cycle PRAE (High Byte)
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF (Low Byte) Cycle PRAF (Mid Byte) Cycle PRAF (High Byte)
FQV2111, FQV2101, FQV291
Data Width Cycle PRAE (Low Byte) Cycle PRAE (High Byte)
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF (Low Byte) Cycle PRAF (High Byte)
FQV281 FQV271 FQV261
Bits Offset Registers bits FQV2111 bits FQV2101 bits FQV291 bits FQV281 bits FQV271 bits FQV261 Note: Don't Care applies those unused bits both High Byte Byte
Figure Parallel Offset Write/Read Cycle Diagram
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FQV2111
y(1) (y+1) 262,144 262,145 [524,288-(x+1)] (524,288-x(2))to 524,287 524,288
FULL
PRAF
HALF
PRAE
EMPTY
FQV2101
y(1) (y+1) 131,072 131,073 [262,144-(x+1)] (262,144-x(2))to 262,143 262,144
FULL
PRAF
HALF
PRAE
EMPTY
FQV291
y(1) (y+1) 65,536 65,537 [131,072-(x+1)] (131,072-x(2))to 131,071 131,072
FULL
PRAF
HALF
PRAE
EMPTY
FQV281
y(1) (y+1) 32,768 32,769 [65,536-(x+1)] (65,536-x(2))to 65,535 65,536
FULL
PRAF
HALF
PRAE
EMPTY
FQV271
y(1) (y+1) 16,384 16,385 [32,768-(x+1)] (32,768-x(2)) 32,767 32,768
FULL
PRAF
HALF
PRAE
EMPTY
FQV261
y(1) (y+1) 8,192 8,193 [16,384-(x+1)] (16,384 -x(2))t 16,383 16,384
NOTES:
FULL
PRAF
HALF
PRAE
EMPTY
PRAE offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected. PRAF offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected.
Table Status Flags (Standard Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FQV2111
y+1(1) (y+2) 262,145 262,146 [524,289-(x+1)] (524,289-x(2))to 524,288 524,289
DRDY
PRAF
HALF
PRAE
QRDY
FQV2101
y+1(1) (y+2) 131,073 131,074 [262,145-(x+1)] (262,145-x(2))to 262,144 262,145
DRDY
PRAF
HALF
PRAE
QRDY
FQV291
y+1(1) (y+2) 65,537 65,538 [131,073-(x+1)] (131,073-x(2)) 131,072 131,073
DRDY
PRAF
HALF
PRAE
QRDY
FQV281
y+1(1) (y+2) 32,769 32,770 [65,537-(x+1)] (65,537-x(2)) 65,536 65,537
DRDY
PRAF
HALF
PRAE
QRDY
FQV271
y+1(1) (y+2) 16,385 16,386 [32,769-(x+1)] (32,769-x(2)) 32,768 32,769
DRDY
PRAF
HALF
PRAE
QRDY
FQV261
y(1) (y+2) 8,193 8,194 [16,385-(x+1)] (16,385 -x(2)) 16,384 16,385
NOTES:
DRDY
PRAF
HALF
PRAE
QRDY
PRAE offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected. PRAF offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected.
Table Status Flags (FWFT Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Timing Diagrams
MRST tRSTS tRSTS tRSTS FWFT/SDI tRSTS tRSTS SDEN tRSTF FWFT 1,QRDY EMPTY QRDY tRSTF FWFT FULL FULL/ DRDY tRSTF PRAE tRSTF PRAF HALF tRSTF FWFT DRDY FWFT EMPTY= RSTR RSTR RSTR
Diagram Master Reset Timing
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
tRST PRST RSTS RSTS RSTS RSTS SDEN FWFT 1,QRDY EMPTY QRDY tRSTF FWFT FULL FULL/ DRDY tRSTF PRAE tRSTF PRAF HALF tRSTF FWFT DRDY FWFT EMPTY= tRSTR tRSTR
Diagram Partial Reset Timing
March 2001
Preliminary
Page
tWCLK tWCLKH
March 2001
Write WCLKL
Write
Write
WCLK
tFULL tFULL tFULL
SKEW1
tFULL
D8-0
FULL
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
tENH tENS Data Read
RCLK
tENS
Q8-0
Output Register Data
Next Data Read
NOTES:
time between rising edge RCLK rising edge WCLK greater than equal tSKEW1, FULL will high (after WCLK cycle plus tFULL). tSKEW1 met, then FULL will assert more WCLK cycles. LOAD High, Low.
Diagram Write Cycle Full Flag Timing (Standard Mode)
Preliminary
Page
tRCLK tRCLKH
March 2001
tRCLKL tENS tENS tENH tENS tENH tENH tEMPTY tEMPTY tEMPTY Last Word tOLZ tOHZ tOEN tOLZ Last Word tSKEW1 tENS tENH tENS tENH
RCLK
EMPTY
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
WCLK
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW1, EMPTY will high (after RCLK cycle plus tEMPTY). tSKEW1 met, then EMPTY will assert more RCLK cycles. LOAD High. First word latency: tSKEW1 tEMPTY tRCLK.
Diagram Read Cycle, Empty Flag First Data Word Latency Timing (Standard Mode)
Preliminary
Page
WCLK
March 2001
[y+2] [y+3] [y+4] [(D-1)/2+1] [(D-1)/2+2] [(D-1)/2+3] [D-x-1] [D-x] [D-x+1] [D-x+2] [D-x+3] [D-1]
RCLK
Output Register Data
QRDY
PRAE tHALF
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
HALF
PRAF
DRDY
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW1, QRDY will (after RCLK cycle plus tEMPTY). tSKEW1 met, then QRDY will assert more RCLK cycles. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES tSKEW2 met, then PRAE will assert more RCLK cycles. LOAD High, Low. PRAE offset, PRAF offset. maximum queue depth. Please refer Table Depth. First word latency: tSKEW1 tEMPTY tRCLK
Diagram Write Timing (FWFT Mode)
Preliminary
Page
WCLK tSKEW2
tENH
SKEW1
March 2001
DWx+1
DWx+2
RCLK
tENS
DWx+3 DW[(D-1)/2+1]
DW[(D-1)/2+2]
DW[D-y-1] DW[D-y] DW[D-y+1] DW[D-y+2]
DW[D-1]
EMPTY
QRDY PRAES
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
HALF PRAFS FULL
PRAE
HALF
PRAF
tFULL
DRDY
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW1, QRDY will (after RCLK cycle plus tEMPTY). tSKEW1 met, then QRDY will assert more RCLK cycles. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES tSKEW2 met, then PRAE will assert more RCLK cycles. LOAD High, Low. PRAE offset, PRAF offset. maximum queue depth. Please refer Table Depth. First word latency: tSKEW1 tEMPTY tRCLK
Preliminary
Diagram Read Timing (FWFT Mode)
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
RCLK
tENS
tENH
tRETS
tENS
tENH
Q8-0
DWi+1 tSKEW2
WCLK
tRETS tENS tEMPTY EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF tEMPTY tENH
NOTES:
Upon completion retransmit setup, read operation begin only after EMPTY returns high. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid.
Diagram Retransmit Timing (Standard Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
RCLK tENS tENH tRETS
tENS
tENH
tSKEW2
WCLK tRETS tEMPTY QRDY
tENH
tEMPTY
tPRAES PRAE tHALF HALF tPRAFS PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after QRDY returns low. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid.
Diagram Retransmit Timing (FWFT Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
WCLK tENS SDEN tLOADS LOAD tLOADH tLOADH tENH tENH
PRAE offset
PRAF offset
*Refer Table
Diagram Serial Loading Programmable Flag Registers (Standard FWFT Mode)
FQV2111
FQV2101
FQV291
FQV281
FQV271
FQV261
Table Reference Table Diagram
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
tWCLK tWCLKH WCLK tLOADS LOAD tENS D8-0
PRAE offset PRAE offset
tWCLKL
tLOADH
tLOADH
tENH
tENH
(Low Byte)
(High Byte)
PRAF offset (Low Byte)
PRAF offset (High Byte)
Diagram Parallel Loading Programmable Flag Registers FQV281, FQV271 FQV261 (Standard FWFT Mode)
tWCLK tWCLKH WCLK tLOADS LOAD tENS PRAE offset (Low Byte) PRAE offset (Mid Byte) PRAE offset (High Byte) PRAF offset (Low Byte) PRAF offset (Mid Byte) PRAF offset (High Byte) tENH tENH tLOADH tLOADH tWCLKL
Diagram Parallel Loading Programmable Flag Registers FQV291 (Standard FWFT Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
tRCLK tRCLKH RCLK tLOADS LOAD tENS Output Register Data PRAE offset (Low Byte) PRAE offset (High Byte) PRAF offset (Low Byte) PRAF offset (High Byte) tENH tENH tLOADH tLOADH tRCLKL
Diagram Parallel Read Programmable Flag Registers FQV281, FQV271 FQV261 (Standard FWFT Mode)
tRCLK tRCLKH RCLK tLOADS LOAD tENS Output Register Data PRAE offset (Low Byte) PRAE offset (Mid Byte) PRAE offset (High Byte) tENH tENH tLOADH tLOADH tRCLKL
PRAF offset (Low Byte) PRAF offset (Mid Byte) PRAF offset (High Byte)
Diagram Parallel Read Programmable Flag Registers FQV291 (Standard FWFT Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
tWCLKH WCLK tENS PRAF
tWCLKL tENH tPRAFS words Queue tSKEW2 words Queue tPRAFS D-(x+1) words Queue
RCLK tENS tENH
NOTES:
PRAF offset. maximum queue depth. Please refer Table Depth. time between rising edge RCLK rising edge WCLK greater than equal tSKEW2, PRAF will high (after WCLK cycle plus tPRAFS). tSKEW2 met, then PRAF will assert more WCLK cycles. PRAF synchronizes rising edge WCLK only.
Diagram Synchronous Programmable Almost-Full Flag Timing (Standard FWFT Mode)
tWCLKH WCLK tWCLKH PRAE
tWCLKL
tWCLKL
words Queue(2) words Queue(3) tSKEW2 tPRAES
words Queue(2) words Queue(3) tPRAES tENS tENH
words Queue(2) words Queue(3)
RCLK
NOTES:
PRAE offset. Standard Mode. FWFT Mode. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES tSKEW2 met, then PRAE will assert more RCLK cycles. PRAE synchronizes rising edge RCLK only.
Diagram Synchronous Programmable Almost-Empty Flag Timing (Standard FWFT Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
tWCLKH WCLK tENS
tWCLKL
tENH
tHALF HALF words Queue (1); [(D+1)/2] words Queue(2)
words Queue(1); [(D+1)/2 words Queue(2) tHALF
words Queue(1); [(D+1)/2] words Queue(2)
RCLK
NOTES:
Standard Mode. FWFT Mode. Refer Table Depth.
Diagram Half-Full Flag Timing (Standard FWFT Mode)
March 2001
Preliminary
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Order Information:
Device Family Device Type XXXXX V2111 (524,288 V2101 (262,144 V291 (131,072 V281 (65,536 V271 (32,768 V261 (16,384 *Speed available only Commercial (0°C 70°C) **Package Plastic Thin Quad Flat Pack (TQFP) Example: FQV281L6PF FQV271L10PFI (64k Commercial temp) (32k Industrial temp) Power Speed (ns) Package** Temperature Range Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
High Bandwidth Access 2107 North First Street, Suite Jose, 95131 Tel: 408.453.8885 Fax: 408.453.8886 www.hba.com sales@hba.com
March 2001
Preliminary
Page

FlexQII Volt Synchronous First-In/First-Out Queue Memory Configur

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