Infrared Communications Controller Chip CameraFR Mixed Voltage Su

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Infrared Communications Controller Chip CameraFR Mixed Voltage Su

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CAM35C44
Infrared Communications Controller Chip CameraFR
Mixed Voltage Support Supports 3.3V Operation Supports Mixed Internal 3.3V Operation with 3.3V/5V External Configuration Intelligent Auto Power Management Supports Multiple Power Down Modes Serial Port High Speed NS16C550A Compatible UART with 16-Byte Send/Receive FIFOs Programmable Baud Rate Generator Infrared Port Multi-Protocol Infrared Interface 128-Byte Data FIFO IrDA Compliant 4Mbps) Consumer SHARP Programmed Options General Purpose Pins Programmable Multi-Protocol Host Interface ISA-Style Address Data IOCHRDY Wait State Support Fast Non-ISA Multiplexed Address/Data Programmable Read/Write Interface Channel Programmable Chip Select Multihost Interface Support Includes Hitachi Mitsubishi Microcontrollers 24MHz Crystal Oscillator Supports Internal External Clock Source TQFP Package
GENERAL DESCRIPTION
CAM35C44 with IrDA v1.1 (4Mbps) Consumer support incorporates SMSC's advanced Infrared Communications Controller (IrCC 2.0), 16C550A-compatible UART, Multiple Host Interface options, flexible Address Decoding five General Purpose I/Os. CAM35C44 also features sophisticated power control circuitry support multiple power down modes, on-chip 24MHz crystal oscillator, 12mA host drivers. CAM35C44 particularly suited 3.3v battery-powered systems.
TABLE CONTENTS
FEATURES. GENERAL DESCRIPTION ARCHITECTURE CONFIGURATION DESCRIPTION FUNCTIONS BUFFER-TYPE SUMMARY CLOCK GENERATOR. MULTIHOST INTERFACE HOST INTERFACE SELECT HOST INTERFACE MULTIPLEXING System Data Address Address nIOR nIOW REGISTER ADDRESS MAP. NON-MULTIPLEXED (ISA) ADDRESSING MULTIPLEXED ADDRESSING CONFIGURATION CONFIGURATION ACCESS PORTS CONFIGURATION STATE CONFIGURATION REGISTERS INFRARED INTERFACE IRDA SIR/FIR ASKIR CONSUMER HARDWARE INTERFACE GENERAL PURPOSE INTRODUCTION. DESCRIPTION. REGISTERS ELECTRICAL CHARACTERISTICS A.C. TIMING CLOCK RESET TIMING READ CYCLE TIMING (NON-MULTIPLEXED). READ CYCLE TIMING (MULTIPLEXED). RITE CYCLE TIMING (NON-MULTIPLEXED) RITE CYCLE TIMING (MULTIPLEXED)
READ/W RITE CYCLE TIMING (MULTIPLEXED). SINGLE TRANSFER MODE TIMING BURST TRANSFER MODE TIMING
ARCHITECTURE
There basic architectural components CAM35C44: multihost interface, IrCC 2.0, clock generator, configuration registers, power management, general purpose IrCC multi-protocol serial communications controller that incorporates 16C550A UART Synchronous Communications Engine (SCE). Refer SMSC Infrared Communications Controller specification more information. clock generator provides connections 24MHz crystal external clock source. 24MHz clock directly drives block. internal used data rates above 115.2Kbps. Power management CAM35C44 includes various power down modes infrared wake-up option. general purpose interface provides generic programming capabilities.
PWRGD VCC[2:1],VSS[3:1],
FIGURE
multihost interface capable supporting several configurations; including, non-multiplexed ISA-style address data bus, multiplexed address/data with selectable read/write command options. multihost interface includes support Hitachi Mitsubishi microcontrollers.
X1/CLK1
SD[7:0]/AD[7:0] SA[1:0]/GPIO[4:3] SA[4:2]/BS[2:0] IOCHRDY ASTRB nNOWS RESET_DRV nDACK nIOR/RW nIOW/DSTRB MULTIHOST INTERFACE
CLOCK
POWER MGMT
POWER GENERAL PURPOSE GPIO[2:0]
CONTROL DATA IRRX ADDRESS IRTX IRCC CONFIGURATION REGISTERS IRMODE/IRRX3 RXD/IRRX TXD/IRTX
FIGURE CAM35C44 BLOCK DIAGRAM
CONFIGURATION CAM35C44 numbers shown FIGURE Functional descriptions pingroup shown TABLE Note: numbers FIGURE subject change.
SA1/GPIO4 SA0/GPIO3
SA2/BS2
ASTRB
GPIO2
GPIO1
GPIO0
SA3/BS1 SA4/BS0 TXD/IRTX IRTX IRMODE/IRRX3 nIOR/RnW nIOW/DSTRB nNOWS
X1/CLK1 IRRX RXD/IRRX IOCHRDY RESET_DRV nDACK
CAM35C44 TQFP
SD0/AD0
SD1/AD1
SD2/AD2
SD3/AD3
SD4/AD4
SD5/AD5
SD6/AD6
SD7/AD7
FIGURE CAM35C44 CONFIGURATION
DESCRIPTION FUNCTIONS
TABLE CAM35C44 FUNCTION DESCRIPTION TOTAL BUFFER PINS SYMBOL TYPE DESCRIPTION PROCESSOR/HOST INTERFACE (25) SD[7:0]/AD[7:0] IO12 This used exchange data with host. bidirectional configured either system data multiplexed address/data (TABLE These pins high-impedance state when output mode. system address used determine address during read write cycles. These system address pins general purpose pins (TABLE when multiplexed address/data host interface type selected (TABLE system address used determine address during read write cycles. These three system address pins memory block select pins (TABLE when multiplexed address/data host interface type selected (TABLE active chip select input 32-byte address block decoder when host interface type selected 256-byte page decoder when multiplexed address/data host interface type selected (TABLE
NAME System Data Bus/ Multiplexed Address/Data (Non-ISA)
System Address (SA0 SA1)/ General Purpose (GPIO3 GPIO4)
SA[1:0]/GPIO[4:3]
I/IO12
System Address (SA2 SA4)/ Memory Block Selects (BS0 BS2)
SA[4:2]/BS[2:0]
Chip Select
NAME Address Enable
TOTAL PINS
SYMBOL
BUFFER TYPE
DESCRIPTION active high Address Enable indicates operations host data bus. must inactive access CAM35C44 registers active during operations regardless selected host interface type. IOCHRDY pulled extend read/write commands. Only SCE-driven functions IrCC enabled IOCHRDY. ASTRB used internally latch addresses during read/write cycles when multiplexed address/data host interface type selected (TABLE nNOWS enabled activated IrCC SCE-driven functions indicate that access cycle shorter than standard cycle executed. RESET_DRV active high used reset CAM35C44 described appropriate sections this document. configuration registers affected this except where noted (TABLE 13). RESET_DRV must valid 500ns minimum. forced active when interrupt asserted. goes inactive soon source interrupt been cleared. active pin-state determined IRQ_LEV CR00 (see page 22).
Channel Ready
IOCHRDY
OD12
Multiplex Mode Address Strobe
ASTRB
Wait State
nNOWS
OD12
Reset Drive
RESET_DRV
OD12
NAME Request
TOTAL PINS
SYMBOL
BUFFER TYPE
DESCRIPTION forced active CAM35C44 when byte transfers host using required. goes inactive when transfer been completed. active pinstate determined DRQ_LEV CR01 (see page 22). DACK forced active host controller acknowledge CAM35C44 transfer requests. DACK goes inactive following transfer command. active DACK pin-state determined DAC_LEV CR01 (see page 23). indicates that transfer complete. only acknowledged when DACK active. active nIOR input issued host execute read commands when read/write-styled host interface type selected (TABLE input used determine command type when non-ISA read/write-styled host interface type selected. active nIOW input issued host execute write commands when read/write-styled host interface type selected (TABLE DSTRB input used execute command when non-ISA read/write-styled host interface type selected (FIGURE
Acknowledge
DACK
Terminal Count
Read/ Non-ISA Read/Write Control
nIOR/RnW
Write/ Non-ISA Data Strobe
nIOW/DSTRB
MISCELLANEOUS (12)
NAME Clock Input (24MHz CMOS Clock/Crystal)
TOTAL PINS
SYMBOL X1/CLK1
BUFFER TYPE ICLK
DESCRIPTION X1/CLK input either 24MHz clock crystal 24MHz crystal oscillator source (see section CLOCK GENERATOR page 24MHz crystal driver should left unconnected external clock source used. Host Interface Select bits determine host interface type. These bits static controls must remain stable during device operation (see section MULTIHOST INTERFACE page 13). general purpose pins provide simple programmable interface. state GPIO forced value contained GPIO data register this register reflect logical state GPIO depending values programmed GPIO direction enable registers (see section GENERAL PURPOSE page 32).
Crystal Driver
OCLK
Host Interface Select
HS[1:0]
General Purpose (GPIO0 GPIO2)
GPIO[2:0]
IO12
NAME Power Good
TOTAL PINS
SYMBOL PWRGD
BUFFER TYPE
DESCRIPTION This active high input indicates that positive supply voltage valid. normal device operation, PWRGD must active. When PWRGD inactive, device inputs disconnected placed into power state; outputs into highimpedance state. Note: crystal oscillator pins unaffected PWRGD. contents registers preserved long valid value. Output driver current drain when PWRGD inactive drops ISTDBY standby current. PWRGD input internal 30#A pull-up. internal connections made these pins. This infrared port receiver input pin. This infrared port transmitter output pin. This infrared port secondary receiver input channel transceiver mode control pin, depending state transceiver module interface type select (TABLE 27). Positive Supply Voltage Positive Interface Supply Voltage Ground Supply
Connect
INFRARED INTERFACE Infrared Infrared
IRRX IRTX IRMODE/IRRX3
O12PD O12/I
Infrared Mode/IRRX3
POWER PINS +3.3V Digital Supply Voltage Interface Supply Voltage Ground
NAME Receive Serial Data Infrared
TOTAL PINS
BUFFER SYMBOL TYPE SERIAL PORT INTERFACE RXD/IRRX
DESCRIPTION This receiver input UART port alternate infrared port receiver input. This transmitter output UART port alternate infrared port transmitter output.
Transmit Serial Data 2/Infrared
TXD/IRTX
O12PD
Note Note Note Note
MODE pins drive level. defaults zero even during POR. pins voltage tolerant level. GPIOs tolerant back drive protected.
Buffer-Type Summary characteristics buffer types shown TABLE summarized TABLE TABLE CAM35C44 BUFFER-TYPE SUMMARY BUFFER TYPE DESCRIPTION IO12 OD12 O12PD ICLK OCLK Input/Output. 12mA sink; source Output. 12mA sink; source Open Drain. 12mA sink Output. 12mA sink; source; 30#A Pulldown Tristate Input Crystal Oscillator Circuit (TTL levels) Output External Crystal Input Compatible. Input Compatible with 30#A Pullup Input with Schmitt Trigger.
CLOCK GENERATOR
internal 3.3v crystal oscillator external oscillator source required CAM35C44 (FIGURE crystal/clock pins buffer types shown TABLE X1/CLK1 pins provide external connection parallel resonant 24MHz crystal. Configuration register CR08 INT_OSC, must configure internal oscillator this arrangement (see section CRO8 Power Control page 27). external CMOS compatible oscillator required 24MHz crystal used. this case INT_OSC must "0". 24MHz crystal driver should used drive other device. This should left unconnected external clock used INT_OSC "0". 24MHz crystal used directly drive block. This saves power when 115.2Kbps slower data transfers required because block need powered. TABLE section CRO8 Power Control page
FIGURE EXAMPLE 24MHz OSCILLATOR CIRCUIT
CAM35C44
X1/CLK1 24MHz CRYSTAL
MULTIHOST INTERFACE
CAM35C44 multihost interface capable supporting three configurations; including, ISA-style address data bus, multiplexed address/data with ISA-style read/write commands like example shown (FIGURE multiplexed address/data with read/write select data strobe like example shown FIGURE interface type well typespecific multiplexing processor/host interface pins (TABLE controlled Host Interface Select pins.
FIGURE UPD781C1X READ CYCLE
AB[15:8] AB[7:0] ADDR ADDR7-ADDR0
ADDR15-ADDR8 Data
AB[15:8] AB[7:0] ADDR R/nW DATA ADDR7-ADDR0
ADDR15-ADDR8 Data
FIGURE HITACHI HD63P01M1 READ CYCLE
Host Interface Select Host Interface Select pins HS[1:0] (TABLE determine host interface type.
encoding these bits shown TABLE Host Interface Select pins static controls must remain stable during device operation.
TABLE HOST INTERFACE ENCODING HOST INTERFACE SELECT HOST INTERFACE TYPE Reserved MULTIPLEXED ADDRESS/DATA, Non-ISA Read/Write (FIGURE MULTIPLEXED ADDRESS/DATA, Read/Write (FIGURE
Host Interface Multiplexing multiplexing processor/host interface (TABLE controlled Host Interface Select pins HS[1:0].
signals that multiplexed, like IOCHRDY nNOWS, remain operative regardless state Host Interface Select bits. following tables describe processor/host interface multiplexing group.
System Data TABLE SD[7:0] MULTIPLEXING CONTROLS SELECTED FUNCTION DEFINED SD[7:0] AD[7:0] AD[7:0]
NAME SD[7:0]
Address TABLE SA[1:0] MULTIPLEXING CONTROLS SELECTED FUNCTION DEFINED SA[1:0] GPIO[4:3] GPIO[4:3]
NAME SA[1:0]
Address TABLE SA[4:2] MULTIPLEXING CONTROLS SELECTED FUNCTION DEFINED SA[4:2] BS[2:0] BS[2:0]
NAME SA[4:2]
nIOR TABLE nIOR MULTIPLEXING CONTROLS SELECTED FUNCTION DEFINED nIOR R/nW nIOR
NAME nIOR
nIOW TABLE nIOW MULTIPLEXING CONTROLS SELECTED FUNCTION DEFINED nIOW DSTRB nIOW
NAME nIOW
REGISTER ADDRESS
Register addressing CAM35C44 fixed requires 32-byte memory block. Typically, register addressing accomplished with address chip select. TABLE describes mapping four register banks CAM35C44 address space, CONFIGURATION, GPIO, SCE, that required device configuration run-time control. external address pins that responsible register addressing will depend Host Interface Select bits (see section MULTIHOST INTERFACE page 13).
8-BYTE ADDRESS BANK
TABLE CAM35C44 REGISTER BANK SELECT ADDRESS RANGE BITS SA[4:0] REGISTER BANK DECODING 0x00 0x07 CONFIGURATION 0x08 0x0F GPIO 0x10 0x17 0x18 0x1F
Note Address Enable (AEN) must access CAM35C44 registers regardless state Host Interface Select bits. Non-Multiplexed (ISA) Addressing shown TABLE five address bits SA[4:0] chip select required access CAM35C44 run-time configuration registers. mode, five bits System Address SA[4:0] determine register address, while decodes 32-byte address block. Note: address block decoding must done externally. Block Select bits BS[2:0] general purpose I/Os GPIO[4:3] unavailable mode.
Multiplexed Addressing When multiplexed address modes selected, i.e. HS[1:0] (TABLE register addresses decoded from Multiplexed Address/Data AD[7:0], Block Select bits BS[2:0] chip select pin. multiplexed addressing modes loworder bits Multiplexed Address/Data AD[4:0] determine register address while Block Select bits BS[2:0] qualify
three high-order Multiplexed Address/Data bits, AD[7:5]; i.e., BS[2:0] decodes which eight 32-byte blocks selected 256-byte page decoded nCS. Note: page address decoding must done externally. example, TABLE illustrates that BS[2:0] 01H, (active), AD[7:0] 20H, Index Register Configuration Bank been selected. extra GPIO pins GPIO[4:3] available multiplexed address modes.
TABLE EXAMPLE MULTIPLEXED ADDRESS DECODING 256-BYTE ADDRESS PAGE
32-BYTE ADDRESS BLOCK
MULTIPLEX ADDR/DATA AD[7:0]
DESCRIPTION Decode: Invalid Page Decode Configuration Bank Index Register (TABLE Decode: Invalid Block
CONFIGURATION
CAM35C44 configuration registers used program selectable chip-level device options (TABLE 13). configuration registers only programmed through configuration access ports that appear when chip placed into configuration state. Configuration register programming typically follows this sequence: Enter Configuration State, Program Configuration Register(s), Exit Configuration State.
enabled, logical devices CAM35C44 will operate normally configuration state. Configuration Access Ports configuration access ports config port, index port, data port (TABLE 11). configuration access ports only addressable registers CAM35C44 configuration bank (TABLE 12). index port data port only active configuration state.
TABLE CONFIGURATION ACCESS PORTS PORT NAME ADDRESS DIRECTION CONFIG PORT BANK ADDRESS WRITE INDEX PORT BANK ADDRESS READ/WRITE DATA PORT BANK ADDRESS READ/WRITE Note
Note Note
INDEX DATA ports active only when CAM35C44 configuration state. INDEX PORT only readable configuration state. CAM35C44 register banks described section REGISTER ADDRESS page register addresses CAM35C44 configuration bank shown TABLE
Configuration State Logical devices CAM35C44 operate state and/or configuration state. After power CAM35C44 state, default. program configuration registers configuration state must explicitly enabled. Entering Configuration State enter configuration state, configuration access must written config port. configuration access byte data. Once configuration access been written config port, CAM35C44 automatically activates configuration access ports enters configuration state. Configuration Select Register Configuration Select Register (CSR) located index port address must initialized with configuration register index before register accessed using data port.
only accessed when CAM35C44 configuration state. Configuration Register Programming CAM35C44 contains configuration registers CR00-CR09. After CAM35C44 enters configuration state, configuration registers programmed first writing register index number configuration select register (CSR) then writing reading configuration register contents through data port. Configuration register access remains enabled until configuration state explicitly exited. Exiting Configuration State exit configuration state byte data must written config port. Once been written config port, CAM35C44 automatically deactivates configuration access ports enters state. state, configuration register access cannot occur until configuration state explicitly re-enabled.
Programming Example following Intel 8086 assembly language instructions illustrate CAM35C44 configuration register programming. this example, config port located address 3F0H. ENTER CONFIGURATION STATE DX,3F0H AX,055H DX,AL CONFIGURE REGISTERS CR0-CRx DX,3F0H AL,00H DX,AL ;Point DX,3F1H AL,3FH DX,AL ;Update DX,3F0H AL,01H DX,AL ;Point DX,3F1H AL,9FH DX,AL ;Update Repeat registers EXIT CONFIGURATION STATE DX,3F0H AX,AAH DX,AL
Configuration Registers Introduction configuration registers (TABLE their default values power affected RESET, except where noted register descriptions that follow. Configuration register bits that needed CAM35C44 marked RESERVED sections below. RESERVED bits cannot written return when read.
Configuration Register references hex; e.g., CRC0.3 means Configuration Register 0xC0, 0x03. Configuration Bank Addressing CONFIGURATION register bank defined first eight addresses CAM35C44 memory (see section REGISTER ADDRESS page 16). TABLE summarizes contents CONFIGURATION bank. Index Data registers access configuration registers (TABLE described above.
TABLE CONFIGURATION REGISTER BANK ADDRESS DEFAULT REGISTER NAME 0x00 0x00 Config/Index Register 0x01 0x00 Data Register 0x00 RESERVED 0x02 0x07 Description INDEX 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 TABLE CONFIGURATION REGISTERS RESET DEFAULT DEFAULT REGISTER NAME 0x00 0x00 CONTROL 0x00 0x00 CONTROL 0x02 INFRARED OPTION 0x01 INFRARED CONTROL 0x00 TEST CONTROL SOFTWARE SELECT 0x00 SOFTWARE SELECT 0x00 0x03 HALF DUPLEX TIME-OUT 0x00 0x00 POWER CONTROL 0x00 TEST CONTROL
CR00 Control Control register CR00 determines polarity enables configuration register locking feature. CR00 only accessed
configuration state only after been initialized 00H. default value this register after power (TABLE 14). Bits[7:3, Control register RESERVED.
CR00
TABLE CONTROL REGISTER RESERVED LOCK
IRQ_LEV
DEFAULT 0x00
IRQ_LEV, IRQ_LEV determines active state output (TABLE IRQ_LEV (default), active low. IRQ_LEV "1", active high. LOCK, LOCK selects configuration register locking. "Locked" means configuration registers read cannot written, except IRCC Legacy Controls like HALF DUPLEX TIME-OUT that written through Registers appear chip-level configuration registers regardless state LOCK bit. LOCK (default), configuration registers unlocked. LOCK "1", configuration registers locked.
Note: once LOCK configuration registers permanently locked. LOCK only reset hardreset power-on-reset; i.e., configuration registers cannot changed until either hardreset power-on-reset occur. CR01 Control Control register CR01 determines DACK polarity (TABLE CR01 only accessed configuration state only after been initialized 01H. default value this register after power (TABLE 15). Bits[7:2] Control register RESERVED.
CR01
TABLE CONTROL REGISTER (CR01) RESERVED DAC_LEV DREQ_LEV
DEFAULT 0x00
DRQ_LEV, DRQ_LEV determines active state Request (DRQ) output (TABLE DRQ_LEV (default), active low. DRQ_LEV "1", active high. DAC_LEV, DAC_LEV determines active state Acknowledge (DACK) input (TABLE DAC_LEV (default), DACK active low. DAC_LEV "1", DACK active high.
CR02 Infrared Option Infrared Option register CR02 determines infrared port transmit receive polarity, port duplex mode, infrared port protocol. controls Infrared Option register also duplicated IrCC Configuration Register These controls arranged such that last write from either source determines current control state visible both registers. CR02 only accessed configuration state only after been initialized 02H. default value this register after power (TABLE 16). Bits[7:6] Infrared Option register RESERVED. TABLE INFRARED OPTION REGISTER
CR02
RES.
MODE2
MODE1
MODE0
HALF DUPLEX
XMT_
RCV_
DEFAULT 0x02
RCV_POL, RCV_POL defines active state infrared port receive pins. RCV_POL (default), IRRX active low. RCV_POL "1", IRRX active high. RCV_POL affect when port configured 16C550A UART (see section IR_MODE, Bits page 24).
XMT_POL, XMT_POL defines active state infrared port transmit pins. XMT_POL "0", IRTX active low. XMT_POL (default), IRTX active high. XMT_POL affect when port configured 16C550A UART (see section IR_MODE, Bits page 24).
HALF DUPLEX, When HALF DUPLEX (default), 16C550A UART IrCC full duplex mode. Full duplex mode effect IrCC SCE. When HALF DUPLEX "1", IrCC half duplex mode. Half duplex mode typically required infrared transactions. half duplex mode, Half Duplex TimeOut will apply IrCC transmit/receive
direction mode changes (see section CR07 Half Duplex Time-Out page 26). Half Duplex Time-Out does apply full duplex mode. IR_MODE, Bits IR_MODE bits select active IrCC encoder/decoder. default (TABLE 17). IR_MODE bits equivalent three low-order Block Control bits IrCC Configuration Register
TABLE CAM35C44 INFRARED PROTOCOL OPTIONS IR_MODE[2:0] MODE DESCRIPTION 16C550A UART (Default) IrDA SIR-A 115.2Kbps, Variable 3/16ths Pulse 500KHz Carrier, Amplitude Shift Keyed IrDA SIR-B 115.2Kbps, Fixed 1.6#s Pulse IrDA HDLC 0.576Mbps 1.152Mbps IrDA 4PPM 4Mbps CONSUMER Consumer Remote) Direct Diode Control CR03 Infrared Control Infrared Control register CR03 configures infrared interface port clock select. CR03 only accessed configuration state only after been initialized 03H. default value this register after power (TABLE 18). Bits[7:5,3:1] Infrared Control register RESERVED.
CR03
TABLE CONTROL REGISTER RESERVED MIDI RESERVED
HPMODE
DEFAULT 0x01
HPMODE, HPMODE used configure transceiver type CAM35C44 infrared interface (see FIGURE When HPMODE (default), IRMODE/IRRX3 configured input (IRRX3) support transceiver types that require receive channels. When HPMODE "0", IRMODE/IRRX3 configured output (IRMODE) support transceiver types that require receive channel mode control pin. MIDI, MIDI 16C550A UART clock divider select. When MIDI (default), 16C550A clock divider configured
generate standard UART data rates 115.2Kbaud. When MIDI "1", 16C550A clock divider configured generate UART data rates that compatible with 31.25Kbaud ($1%) Musical Instrument Digital Interface standard. CR04 Test Control Test Control register CR04 enables userlevel serial loopback testing SMSC internal test modes. CR04 only accessed configuration state only after been initialized 04H. default value this register after power (TABLE 19).
TABLE TEST CONTROL REGISTER
CR04 IR_TEST[6:0] IR_LB DEFAULT 0x00
IR_LB, IR_LB enables serial loopback testing, independent internal IrCC loopback controls. When IR_LB transmit output internally connected receiver input. When IR_LB (default), transmit output connected receive input loopback testing disabled. IR_TEST[6:0], Bits IR_TEST[6:0] bits control SMSC internal test modes. IR_TEST[6:0] bits (default) normal operation. When IR_TEST[6:0] bits "1", SMSC internal test mode activated. Note: SMSC internal test modes reserved
SMSC use, only. Activating SMSC internal test modes produce undesired results. CR05 Software Select Software Select register CR05 directly connected read-only IrCC Software Select register Register Block Three. Writing CR05 only revise contents Software Select register. CR05 only accessed configuration state only after been initialized 05H. default value this register after power (TABLE 20).
CR05
TABLE SOFTWARE SELECT REGISTER Software Select
DEFAULT 0x00
CR06 Software Select Software Select register CR06 directly connected read-only IrCC Software Select register Register Block Three. Writing CR06 only
revise contents Software Select register. CR06 only accessed configuration state only after been initialized 06H. default value this register after power (TABLE 21).
CR06
TABLE SOFTWARE SELECT REGISTER Software Select
DEFAUL 0x00
CR07 Half Duplex Time-Out CR07 Half Duplex Time-Out register (TABLE 22). Half Duplex option selected (see section HALF DUPLEX, page 24), half duplex time-out constrains timing transmit/receive direction mode changes IrCC 2.0. half duplex time-out started each message data transferred prevents direction mode changes until timeout expires. timer restarted whenever data transferred current direction mode. example, mode data loaded into transmit buffer while character being received, transmission will start
until last been received timeout expires. start another character received during this time-out, timer restarted after character received. IRCC block CAM35C44 also includes half duplex time-out register, like CR07, Register Block These registers behave like other IRCC legacy controls where either source uniformly updates value both registers when either register explicitly written using following devicelevel POR. IRCC software resets affect these registers. half duplex time-out programmable from 25.5ms 100#s increments, follows:
HALF DUPLEX TIME-OUT (CR07) 100#s
TABLE HALF DUPLEX TIME-OUT REGISTER HALF DUPLEX TIME-OUT DEFAULT 0x03
CR07
CR08 Power Control Power Control register CR08 contains power control enables select various CAM35C44 power states (TABLE also includes configure system clock
source. CR08 only accessed configuration state only after been initialized 08H. default value this register after power (TABLE 23). Bits[7:6] Power Control register RESERVED.
TABLE POWER CONTROL REGISTER
CR08 INT_ AUTO_ SCE_ PLL_ ACE_ON OSC_ON Default 0x00
OSC_ON, OSC_ON determines power state CAM35C44 clock generator, independent clock source (see section INT_OSC, page 28). When OSC_ON (default), clock generator powered down. When OSC_ON "1", clock generator running. ACE_ON, ACE_ON along with AUTO_PWR determines power state IrCC UART. When ACE_ON (default), UART powered down, regardless state AUTO_PWR; i.e., when ACE_ON "0", UART wake-up events disabled (see section AUTO_PWR, When ACE_ON "1", UART active. PLL_ON, PLL_ON determines power state clock multiplier. required IrDA transfers above 115.2Kbps. When PLL_ON (default), powered down. When PLL_ON "1", running.
SCE_ON, SCE_ON determines power state IrCC SCE. required IrDA transfers above 115.2Kbps Consumer transactions. When SCE_ON (default), powered down. When SCE_ON "1", active. AUTO_PWR, AUTO_PWR along with ACE_ON selects auto power down state UART (TABLE 24). When AUTO_PWR (default), auto power down state disabled UART power state controlled solely ACE_ON (see section ACE_ON, page 27). Note: auto power state disabled ring indicator (nRI) power-on wake-up events disabled. When AUTO_PWR ACE_ON "1", auto power down state enabled following power management events possible.
Transmitter Auto Power Down UART transmitter powered down from auto power down state when transmit buffer transmit shift registers empty. Receiver Auto Power Down
Ring Indicator Auto Power Down When UART powered down from auto power state, Ring Indicator interrupt occur active transitions Ring Indicator input nRI. Exit Auto Power Down
UART receiver powered down from auto power state when receive FIFO empty receiver waiting start bit.
transmitter exits auto power down state write transmit buffer. receiver exits auto power down state when receiver input changes state.
TABLE UART POWER STATES ACE_ON AUTO_PWR (D1) (D4) DESCRIPTION POWER POWER AUTO POWER DOWN INT_OSC, INT_ selects clock source CAM35C44 clock generator (see section CLOCK GENERATOR page 12). When INT_OSC (default), clock generator driven external clock source. When INT_OSC "1", clock generator driven internal crystal oscillator.
TABLE EXAMPLE POWER CONSUMPTION POWER CONTROL ENABLES POWER CONSUMPTION CR08[3:0] CLOCK (ICC) BLOCK GENERATO BLOCK 2.5#A (Note (Note RUNNING 500#A RUNNING 1.6mA RUNNING RUNNING RUNNING RUNNING
Note Note Note Note Note
24MHz crystal oscillator directly driving block enables data transfers 115.2Kbps. driving block enables data transfers 4Mbps. PWRGD does stop crystal from oscillating OSC_ON, configuration register CR08, "1". PWRGD "0". PWRGD "1".
CR09 Test Control IR_TEST[14:7] bits Test Control register enable SMSC internal test modes. CR09 only accessed configuration state only after been initialized 09H. default value this register after power (TABLE 26). IR_TEST[14:7] bits (default) normal operation. When IR_TEST[14:7] bits "1", SMSC internal test mode activated. Note: SMSC internal test modes reserved SMSC use, only. Activating SMSC internal test modes produce undesired results.
CR09
TABLE TEST CONTROL REGISTER IR_TEST[14:7]
DEFAULT 0x00
INFRARED INTERFACE
CAM35C44 infrared interface support various infrared protocols transceiver configurations. more information consult SMSC Infrared Communication Controller (IrCC 2.0) specification. IrDA SIR/FIR IrDA (v1.0) specifies asynchronous serial communication baud rates 115.2kbps. Each byte sent serially first beginning with zero value start bit. zero signaled sending single infrared pulse beginning serial time. signaled absence infrared pulse during time. IrDA (v1.1) includes IrDA v1.0 additionally specifies synchronous serial communications data rates 4Mbps. Data transferred first packets that 2048 bits length. IrDA v1.1 includes .576Mbps 1.152Mbps data rates using encoding scheme that similar SIR. 4Mbps data rate uses pulse position modulation (PPM) technique. ASKIR ASKIR infrared protocol allows asynchronous amplitude shift keyed serial communication baud rates 19.2kbps. Each byte sent serially first beginning with zero value start bit. zero signaled sending 500kHz carrier waveform duration serial time. signaled absence carrier during time. Consumer CAM35C44 Consumer interface general-purpose synchronous amplitude shift keyed encoder/decoder with programmable carrier bit-cell rates that emulate many popular Remote encoding formats; including, 38kHz PPM, RC-5. Each sent serially first. carrier frequency programmable from 1.6MHz 6.25kHz. bit-cell rate range 100kHz 390Hz. Hardware Interface CAM35C44 hardware interface shown FIGURE This interface supports types transceiver modules. interface type requires mode Mode) select data rate, while other interface type requires second data (IRRX3). transceiver interface type selected with HPMODE CR03 shown TABLE (see section HPMODE, page 25).
TABLE TRANSCEIVER MODULE INTERFACE TYPE SELECT MODE (CR03.0) FUNCTION Mode IRRX3
FAST FIGURE used select between mode mode receiver, regardless transceiver type. FAST
"1", mode receiver selected; FAST "0", mode receiver selected (TABLE 28).
TABLE DATA SELECTION CONTROL SIGNALS INPUTS FAST HPMODE RXD2 IRRX2 RXD2 IRRX2 MODE/IRRX3 MODE/IRRX3
FIGURE INTERFACE BLOCK DIAGRAM
(aux) G.P. DATA
HPMODE IRMODE
TXD2 RXD2
IRTX IRRX IRMODE /IRRX3
FAST
FAST
IrCC
GENERAL PURPOSE
Introduction CAM35C44 support general purpose pins, GPIO[4:0] (TABLE number available general purpose pins
depends upon Host Interface Select bits (see section MULTIHOST INTERFACE page 13). general purpose pins controlled GPIO registers contained Bank CAM35C44 memory (see section REGISTER ADDRESS page 16). TABLE summarizes contents GPIO register bank.
BANK BANK (GPIO)
TABLE GPIO REGISTER BANK ADDRESS DEFAULT REGISTER NAME 0x00 0x00 GPIOA Enable Register 0x01 0x00 RESERVED 0x02 0x00 GPIOA Data Register 0x03 0x00 RESERVED 0x04 0x00 GPIOA Direction Register 0x05 0x00 RESERVED 0x06 0x00 RESERVED 0x07 0x00 RESERVED pin. When GPIO configured input enable inactive, state changes reflected data register. When GPIO configured output enable inactive, changes data register affect pin. TABLE summarizes GPIO behavior described above. FIGURE illustrates GPIO functionality. Note: FIGURE illustration purposes only intended suggest specific implementation details.
Description state GPIO forced value contained data register, depending state direction enable bits. example, when GPIO configured output data register contains enable active, GPIO will driven high. When GPIO configured input enable active, value data register will reflect state
ENABLE
TABLE GPIO FUNCTIONAL DESCRIPTION GPIOx DIRECTION COMMAND DATA OUTPUT READ CURRENT VALUE VALUE
DESCRIPTION
Output active (driven), reads return last write. WRITE Output active (driven), writes update data register. INPUT READ CURRENT Input active, reads VALUE return current state pin. WRITE EFFECT Input active, writes have effect. INPUT READ LAST VALUE Output floating, reads return last active state. WRITE VALUE Output floating, writes update data register. INPUT READ LAST VALUE Input disabled, reads return last enabled read state. WRITE EFFECT Input disabled, writes have effect. Note This represents GPIO Enable register bit. GPIO Enable register GP00 (see section GPIOA Enable Register page 34). Note This represents GPIO Direction register bit. GPIO Direction register GP04 (see section GPIOA Direction Register page 35). Note This represents GPIO Data register bit. GPIO Data register GP02 (see section GPIOA Data Register page 35).
GPx_OUT GPx_EN
GPx_DAT
D-TYPE
GPx_nIOW GPx_nIOR
TRANSPARENT
GPIOx
FIGURE GENERAL PURPOSE BLOCK DIAGRAM Note: This figure illustration purposes only intended suggest specific implementation details) Registers disabled. affects GPx_EN bits summarized TABLE GP00 GPIOA Enable Register accessed both configuration state state (see section REGISTER ADDRESS GPIOA Enable register GP00 contains page TABLE 29). default enable bits five general purpose pins value GPIOA Enable register after power (TABLE 31). When GPx_EN bits 00H. Bits[7:5] GPIOA Enable "1", associated general purpose register RESERVED. enabled. When GPx_EN bits "0", associated general purpose TABLE GPIOA ENABLE REGISTER GP4_ GP3_ GP2_ GP1_ RESERVED
GP00
GP0_
DEFAULT 0x00
GPIOA Data Register GPIOA Data register GP02 contains data bits five general purpose pins (TABLE 32). state GPIO forced value contained data register, value data register reflect state pin, depending state direction enable bits. affects
GPx_DAT bits summarized TABLE GP02 accessed both configuration state state (see section REGISTER ADDRESS page TABLE 29). default value GPIOA Data register after power 00H. Bits[7:5] GPIOA Data register RESERVED.
TABLE GPIOA DATA REGISTER
GP02 RESERVED GP4_ GP3_ GP2_ GP1_ GP0_ DEFAULT 0x00
GPIOA Direction Register GPIOA Direction register GP04 contains direction bits five general purpose pins (TABLE 33). direction GPIO depends upon state direction enable bit, typically direction GPIO output; direction GPIO input.
affects GPx_OUT bits summarized TABLE GP04 accessed both configuration state state (see section REGISTER ADDRESS page TABLE 29). default value GPIOA Direction register after power 00H. Bits[7:5] GPIOA Direction register RESERVED.
TABLE GPIOA DIRECTION REGISTER
GP04 RESERVED GP4_ GP3_ GP2_ GP1_ GP0_ DEFAULT 0x00
ELECTRICAL CHARACTERISTICS
70°C +3.3 10%) Note: Numbers appearing parentheses represent values TXD/IRTX, IRTX, IRMODE/IRRX3 when Volt. PARAMETER Type Input Buffer Input Level High Input Level Type Input Buffer Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Input Level High Input Level Input Leakage (All buffers except PWRGD) Input Leakage High Input Leakage Input Current PWRGD IO12 Type Buffer Output Level High Output Level Output Leakage 12mA (24mA) -6mA (-12mA) (Note VILCK VIHCK VILIS VIHIS VHYS Schmitt Trigger Schmitt Trigger VILI VIHI Levels SYMBOL UNITS COMMENTS
PARAMETER Type Buffer Output Level High Output Level Output Leakage O12PD Type Buffer Output Level High Output Level Output Leakage OCLK Type Buffer Output Level High Output Level Output Leakage OD12 Type Buffer Output Level Output Leakage Supply Current Active Supply Current Standby
SYMBOL
UNITS
COMMENTS
12mA -6mA (Note
12mA (24mA) -6mA (-12mA) (Note
-2mA (Note
ICSBY
(Note outputs open. Note
TABLE ELECTRICAL CHARACTERISTICS Note output leakages measured with current pins high impedance defined PWRGD pin. Note Output leakage measured with driving output off, either high level output high impedance state defined PWRGD. Note Defined device configuration with PWRGD input low. Note Junction Temperature rise 70°C ambient will approximately 1.7°C. Junction Temperature rise Ambient Temp. +0ja Max. Power; where 56.8 Max. Power 3.6V
A.C. TIMING tcyc X1/CLK1
FIGURE EXTERNAL CLOCK INPUT TIMING Clock Reset Timing
trst RESET
FIGURE RESET_DRV PULSE TIMING TABLE CRYSTAL RESET TIMING PARAMETERS NAME DESCRIPTION UNITS tcyc Clock Cycle Time Clock Pulse Width 18.5 20.5 22.5 trst Reset Pulse Width
Read Cycle Timing (Non-Multiplexed)
SA[4:0] SD[7:0]
FIGURE READ CYCLE (NON-MULTIPLEXED ADDRESS DATA) TABLE READ CYCLE TIMING PARAMETERS (NON-MULTIPLEXED ADDRESS DATA) NAME DESCRIPTION UNITS Chip Select Address Valid Read Pulse Active Read Pulse Active Data Valid Read Pulse Width Data Hold Time Read Pulse Active Chip Select Note Address Invalid Note Chip select must latched internally released when read pulse goes inactive.
Read Cycle Timing (Multiplexed)
ASTRB AD[7:0] Address Data
FIGURE READ CYCLE (MULTIPLEXED ADDRESS DATA)
TABLE READ CYCLE TIMING PARAMETERS (MULTIPLEXED ADDRESS DATA) NAME DESCRIPTION UNITS Address Strobe Setup Time Read Pulse Active Data Valid Read Pulse Width Address Strobe Inactive Chip Select Active Chip Select Active Read Pulse Active Data Hold Time Address Strobe Hold Time Address Strobe Pulse Width Read Pulse Active Chip Select Inactive Note Address Strobe Inactive Read Pulse Active Note Chip select must latched internally released when read pulse goes inactive.
Write Cycle Timing (Non-Multiplexed)
SA[4:0]
SD[7:0]
FIGURE WRITE CYCLE (NON-MULTIPLEXED ADDRESS DATA)
TABLE WRITE CYCLE TIMING PARAMETERS (NON-MULTIPLEXED ADDRESS DATA) NAME DESCRIPTION UNITS Chip Select Address Valid Write Pulse Active Data Hold Time Write Pulse Width Data valid Write Pulse Inactive Write Pulse Active Chip Select Address Note Invalid Note Chip select must latched internally released when write pulse goes inactive.
Write Cycle Timing (Multiplexed)
ASTRB AD[8:0] Address Data
FIGURE WRITE CYCLE (MULTIPLEXED ADDRESS DATA) TABLE WRITE CYCLE TIMING PARAMETERS (MULTIPLEXED ADDRESS DATA) NAME DESCRIPTION UNITS Address Strobe Setup Time Address Strobe Hold Time Write Pulse Width Data Valid Write Pulse Inactive Chip Select Active Write Pulse Active Data Hold Time Address Strobe Inactive Active Address Strobe Pulse Width Write Pulse Active Address Strobe Inactive Note Address Strobe Inactive Write Pulse Active Note Chip select must latched internally released when write pulse goes inactive.
Read/Write Cycle Timing (Multiplexed)
ASTRB R/nW DSTRB Address
Data
AD[8:0]
FIGURE READ/WRITE CYCLE (MULTIPLEXED ADDRESS DATA) TABLE READ/WRITE CYCLE TIMING PARAMETERS (MULTIPLEXED ADDRESS DATA) NAME DESCRIPTION UNITS Address Strobe Setup Time Address Strobe Hold Time Data Strobe Pulse Width Data Valid R/nW Pulse Inactive Chip Select Active R/nW Pulse Active Data Hold time Address Strobe Inactive Active Address Strobe Pulse Width R/nW Pulse Active Address Strobe Inactive Note Address Strobe Inactive R/nW Pulse Active Note Chip select must latched internally released when write pulse goes inactive.
Single Transfer Mode Timing
nDACK
AD[7:0]
FIGURE SINGLE TRANSFER MODE TIMING Refer table following page.
NAME
TABLE SINGLE TRANSFER MODE TIMING PARAMETERS DESCRIPTION nDACK Delay Time from High Reset Delay from Reset Delay from nDACK nDACK Inactive Delay from High Delay from High Data Access Time from Data Time High Data Float Delay from High Data Hold Time from High nDACK nWR/nRD nDACK Hold after nWR/nRD High Pulse Width nRD/nWR Hold from nDACK Active Inactive nRD/nWR Pulse Width nRD/nWR Inactive Active nDACK Active
UNITS
Burst Transfer Mode Timing
nDACK
AD[7:0]
FIGURE BURST TRANSFER MODE TIMING Refer table following page.
NAME
TABLE TIMING (BURST TRANSFER MODE) PARAMETERS DESCRIPTION nDACK Delay Time from High Reset Delay from Reset Delay from nDACK nDACK Inactive Delay from High Delay from High Data Access Time from Data Time High Data Float Delay from High Data Hold Time from High nDACK nWR/nRD nDACK Hold after nWR/nRD High Pulse Width nRD/nWR Hold from nDACK Active Inactive nRD/nWR Pulse Width nRD/nWR Inactive Active nDACK Active
UNITS
FIGURE TQFP PACKAGE OUTLINE 0.05 1.35 4.40 4.40 0.09 0.45 0.17 0.08
NOMINAL 0.10 1.40 9.00 4.50 7.00 9.00 4.50 7.00 0.60 1.00 0.50 Basic
0.15 1.45 4.60 4.60 0.20 0.75 0.27
REMARK Overall Package Height Standoff Body Thickness Span Span Measure from Centerline body Size Span Span Measure from Centerline body Size Lead Frame Thickness Lead Foot Length from Centerline Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius
0.08
NOMINAL
0.20 0.0762 0.08
REMARK Lead Foot Radius Coplanarity (Assemblers) Coplanarity (Test House)
Note Controlling Unit: millimeter Note Tolerance position leads 0.04 maximum. Note Package body dimensions include mold protrusion. Maximum mold protrusion 0.25 Note Dimension foot length measured gauge plane 0.25 above seating plane 0.78-1.08 Note Details identifier optional must located within zone indicated.
CAM35C44 ERRATA SHEET
PAGE SECTION/FIGURE/ENTRY GENERAL DESCRIPTION DESCRIPTION FUNCTIONS TABLE 13/REGISTER NAME TABLE Note added TABLE TABLE Column CORRECTION 24mA changed 12mA Italicized Text Italicized Text Italicized Text Italicized Text changed 2.5#A Italicized Text DATE REVISED 1/7/98 1/7/98 1/7/98 1/7/98 1/7/98 8/10/99 8/10/99
2000 STANDARD MICROSYSTEMS CORPORATION (SMSC)
Arkay Drive Hauppauge, 11788 (631) 435-6000 (631) 273-3123
Standard Microsystems registered trademark Standard Microsystems Corporation, SMSC trademark Standard Microsystems Corporation. Product names company names trademarks their respective holders. Circuit diagrams utilizing SMSC products included means illustrating typical applications; consequently complete information sufficient construction purposes necessarily given. Although information been checked believed accurate, responsibility assumed inaccuracies. SMSC reserves right make changes specifications product descriptions time without notice. Contact your local SMSC sales office obtain latest specifications before placing your product order. provision this information does convey purchaser semiconductor devices described licenses under patent rights SMSC others. sales expressly conditional your agreement terms conditions most recently dated version SMSC's standard Terms Sale Agreement dated before date your order (the "Terms Sale Agreement"). product contain design defects errors known anomalies which cause product's functions deviate from published specifications. Anomaly sheets available upon request. SMSC products designed, intended, authorized warranted life support other application where product failure could cause contribute personal injury severe property damage. such uses without prior written approval Officer SMSC further testing and/or modification will fully risk customer. Copies this document other SMSC literature, well Terms Sale Agreement, obtained visiting SMSC's website http://www.smsc.com. SMSC DISCLAIMS EXCLUDES WARRANTIES, INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, TITLE, AGAINST INFRINGEMENT, WARRANTIES ARISING FROM COURSE DEALING USAGE TRADE. EVENT SHALL SMSC LIABLE DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, CONSEQUENTIAL DAMAGES; LOST DATA, PROFITS, SAVINGS REVENUES KIND; REGARDLESS FORM ACTION, WHETHER BASED CONTRACT; TORT; NEGLIGENCE SMSC OTHERS; STRICT LIABILITY; BREACH WARRANTY; OTHERWISE; WHETHER REMEDY HELD HAVE FAILED ESSENTIAL PURPOSE, WHETHER SMSC BEEN ADVISED POSSIBILITY SUCH DAMAGES.
CAM35C44 Rev. 03/22/2000

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