ICS5342 GENDAC combination dual programmable clock generators, 18-bit

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ICS5342 GENDAC combination dual programmable clock generators, 18-bit

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ICS5342 GENDAC 16-Bit Integrated Clock-LUT-DAC
ICS5342 GENDAC combination dual programmable clock generators, 18-bit RAM, triple 8-bit video DAC. GENDAC supports 8-bit pseudo color applications, well 15-bit, 16-bit, 24-bit True Color bypass high speed, direct access DACs. makes possible display colors selected from possible 262,144 colors. dual clock generators Phase Locked Loop (PLL) technology provide programmable frequencies graphics subsystem. video clock contains frequencies, which programmable user. memory clock programmable frequency locations. three 8-bit DACs ICS5342 capable driving singly doubly-terminated loads nominal volts pixel rates MHz. Differential integral linearity errors less than over full temperature ranges. Monotonicity guaranteed design. On-chip pixel mask register allows displayed colors changed single write cycle rather than modifying color palette. world leader aspects frequency (clock) generation graphics, using patented techniques produce jitter video timing.
Triple video DAC, dual clock generator, pixel port Dynamic mode switch allows switching color depth pixel pixel basis (packed sparse), 8-bit pseudo color pixel mode supports True Color, Hi-Color, modes High speed color palette (135 MHz) with bypass mode 8-bit DACs Eight programmable video (pixel) clock frequencies (CLK0) power down blanking mode Anti-sparkle circuitry On-chip loop filters reduce external components Standard interface Single external crystal (typically 14.318 MHz) Monitor sense Internal voltage reference (-3), (-2) (-1) versions Very clock jitter latched frequency select pins three non-latched frequency select pins (programmable) Hardware video checksum manufacturing tests
Block Schematic
PCLK COMPARE P0-P15 BUFF. LATCH PIXEL MASK D0-D7 RS0-RS2 STROBE CS0-CS2 BLANK* MICROPROCESSOR INTERFACE TIMING GEN.
PARAMETER CLK0 BYPS
SENSE* GREEN BLUE RSET VREF
COLOR PALETTE
NORM
LATCH
TRIPLE 6/8-BIT
MUX.
PCLK
MODE CLK0
XTAL
XOUT
PARAMETER CLK1
CLK1 5342_01.ai
REV. 0.9.0
ICS5342 GENDAC
Configuration Configuration
CGND CLK1 CGND
CVDD CLK0 BLANK* STROBE* SENSE* CVDD
GENDAC ICS5342
CGND PCLK XVDD XOUT XGND VREF DGND
CVDD AGND BLUE AVDD RSET DVDD
5342_02
ICS5342 (68-pin PLCC)
Description (68-pin PLCC)
Symbol 21-14 Type Description Systems data bidirectional data lines used host microprocessor internal register read write operations (using active respectively) internal registers: Pixel Address, Color Value, Pixel Mask, Address, Parameter, Command During write cycle, rising edge latches data into selected register (set status three pins). rising edge determines read cycle. logical high indicates that data lines longer contain information from selected register will tri-stated. RAM/PLL read enable control signal active state, information present internal data available Data lines, D0-D7 Active RAM/PLL write enable control signal controls write timing microprocessor interface inputs, D0-D7 Register address select inputs control selection internal registers inputs sampled falling edge active enable signal Crystal input connect 14.318 crystal Crystal output connect 14.318 crystal Mode switch digital control selecting primary secondary pixel color modes selects primary mode connect ground used
RS2-RS0 XOUT
63,24,23
Input Input Input Input Output Input
ICS5342 GENDAC
Description (68-pin PLCC)
Symbol CLK1 CLK0 VREF RSET SENSE* Type Output Output Input Input Input Output Description Memory clock output used time video memory Video clock output provides CMOS level pixel clock frequency graphics controller output frequency determined values registers Clock select status CS0-1 determines which frequency selected CLK0 (video) output. Clock select status CS0-1 determines which frequency selected CLK0 (video) output Internal reference voltage normally connects 0.1µf capacitor ground external Vref, connect 1.235V reference this Resistor used current level analog outputs usually connected through 1/4W, resistor ground Monitor sense active when red, green, blue outputs >385mV. Sense output high when analog outputs Chip on-board comparators internal 1.235 voltage reference. This signal used detect monitor type. Color signals from analog outputs Each comprises several current sources which outputs added together according applied binary value. outputs typically used drive monitor. Pixel address lines Byte-wide information latched rising edge PCLK when using color palette, masked Pixel Mask register. Values used specify word address default mode (accessing RAM). HiColor XGA, True Color modes, they represent color data DACs. Ground inputs they used. Pixel Clock rising edge PCLK controls latching Pixel Address BLANK* inputs clock also controls progress these values through threestage pipeline Color Palette RAM, DAC, outputs latches input clock select signals CS0-CS1 Composite BLANK* Signal, active low. When BLANK* asserted, outputs DACs zero which blacks screen. DACs automatically powered down save current during blanking. Color palette still updated through D0-D7 during blanking. CLK1 Power Supply connect DVDD CLK0 power supply connect AVDD power supply Connect AVDD Digital power supply Crystal oscillator power supply- connect AVDD power supply connect DVDD CLK1 connect ground. CLK0 connect ground crystal oscillator ground connect ground Digital ground connect ground connect ground connected leave floating ground
BLUE GREEN P15-
13,12,4,1 67-64, 58-51
Output Output Output Input
PCLK
Input
STROBE* BLANK*
Input Input
CVDD CVDD AVDD DVDD XVDD CVDD CGND CGND XGND AGND DGND CGND
28-35, 39,45,
ICS5342 GENDAC
Internal Registers
Register Name Description (all registers written read from) GENDAC single pixel address register which accessed through either register address 0,0,0 0,1,1 reading from either register gives same result. Writing value address 0,0,0: specifies address within color palette initializes Color Value register Writing value address 0,1,1: specifies address within color palette loads Color Value register with contents location addressed palette then: increments Pixel Address register Writing this 8-bit register done before writing more color values color palette RAM. Writing this 8-bit register done before reading more color values from color palette RAM. 18-bit Color Value register acts buffer between microprocessor interface color palette. value read from written this register using three-byte transfer sequence. color value contained least significant bits, D0-D5, byte read most significant bits zero. same bits used when writing byte. When reading writing, data transferred same order byte first, then green, then blue. Each transfer between Color Value register color palette replaces normal pixel mapping operations GENDAC single pixel. After writing three definitions this register, contents written location color palette specified Pixel Address register, before that register increments. After reading three definitions from this register, contents location color palette specified Pixel Address registers copied into Color Value register, Pixel Address register increments. 8-bit Pixel Mask register used mask selected bits Pixel Address value applied Pixel Address inputs (P7-P0). position mask register leaves corresponding Pixel Address unaltered, while zero sets that zero. Pixel Mask register does affect Pixel Address generated microprocessor interface when palette being accessed. Writing this 8-bit register performed prior writing more programming values Parameter register. Writing this 8-bit register performed prior reading more programming values from Parameter register.
Pixel Address WRITE Pixel Address READ Color Value
Pixel Mask
Address WRITE Address READ
ICS5342 GENDAC
Internal Registers
Register Name Command Description (all registers written read from) This 8-bit register selects color mode, instance 8-bit Pseudo Color, Hi-Color, True Color, XGA, power down. registers reset pseudo color mode power There parameter registers accessible indexed Read/Write registers. Parameter registers 0D-00 bytes long byte long. Register control register. bits this register include clock select enable functions, rest contain frequency parameters. After writing start index address address register, these registers accessed successive one) bytes. address register auto increments after (0E) bytes access entire register
Parameter
ICS5342 GENDAC
Absolute Maximum Ratings
Power Supply Voltage.7 Voltage other pin. 0.5V 0.5V Temperature under bias Storage Temperature. 150° Digital Output Current Analog Output Current Reference Current.-15 Power Dissipation
Note: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics CHARACTERISTICS (note:
Parameter Positive supply voltage Input logic voltage Input logic voltage Reference current Reference voltage Digital input current Off-state digital output current Average power supply current DACs power down mode Sense logic Sense logic Clock logic Clock logic Logic Logic input clock rise time input clock fall time Frequency change CLK0 CLK1 over supply temperature Symbol IREF VREF IDACOFF VOHS VOLS VOHC VOLC XCLKr* XCLKf* Min. 4.75 -7.0 1.10 Max. 5.25 VDD+0.5 1.35 0.05 Units Test Conditions
VDD=max, VDDVINGND max, VDDVINGND max, Digital outputs unloaded palette access -0.4mA 0.4mA -12.0mA 12.0mA -3.2mA, note 3.2mA, note levels levels with respect typical frequency
ICS5342 GENDAC
Characteristics
Parameter Maximum output voltage Maximum output current Full scale error correlation Integral Linearity, 6-bit Integral Linearity, 8-bit Full scale settling time*, 6-bit Full scale settling time*, 8-bit Rise time (10% 90%)* Glitch energy* Symbol (max) (max) ±0.5 Units pV.s Test Conditions note note note note note note note note
Characteristics
Parameter Clock operating range Clock operating range Output clocks rise time* Output clocks fall time* Duty Cycle* Jitter, sigma* Jitter, absolute* Input reference frequency* Characterized values only Symbol jabs fref 60/40 Units Test Conditions
load, levels load, levels
40/60 -300
Typically 14.318
Electrical Characteristics (note:
Parameter PCLK period PCLK jitter PCLK width PCLK width high Pixel word setup time Pixel word hold time BLANK* setup time BLANK* hold time PCLK valid output Symbol tCHCH tCHCH* tCLCH tCHCL tPVCH tCHPX tBVCH tCHBX tCHAV* 12.5 ±2.5 110MHz 9.09 +2.5 135Mhz Units Test Conditions note
note note note note note
ICS5342 GENDAC
Electrical Characteristics (note:
Parameter Differential output delay pulse width pulse width Register select setup time Register select setup time Register select hold time Register select hold time data setup time data hold time Output turn-on delay enable access time Output hold time Output turn-off delay Successive write interval followed read interval Successive read interval followed write interval after color write after color write after color read after color read after read address write SENSE* output delay input clock rise time Symbol tCHAV tWLWH tRLRH tSVWL tSVRL tWLSX tRLSX tDVWH tWHDX tRLQX tRLQV tRHQX tRHQZ tWHWL1 tWHRL1 tRHRL1 tRHWL1 tWHWL2 tWHRL2 tRHRL2 tRHWL2 tWHRL3 tSOD tXCLKR* (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) (tCHCH) 110MHz 135Mhz Units cycle cycle cycle cycle cycle cycle cycle cycle cycle Test Conditions note
write cycle read cycle write cycle read cycle
note note note note note note note note note note
levels
ICS5342 GENDAC
Electrical Characteristics (note:
Parameter input clock fall time Characterized values only Symbol tXCLKF* 110MHz 135Mhz Units Test Conditions levels
Notes: Full scale error derived from design equation: {[(F.S.IOUT)RL 2.1(IREF)RL] [2.1(IREF)RL]} 100% VBLACK LEVEL= F.S.IOUT Actual full scale measured output 37.5 IREF 8.88 37.5 IREF 8.88 This parameter allowed Pixel Clock frequency variation. does permit Pixel Clock period vary outside minimum values Pixel Clock (tCHCH) period. color palette's pixel address required valid logic level with appropriate setup hold times each rising edge PCLK (this requirement includes blanking period). output delay measured from point rising edge CLOCK valid analog output. valid analog output defined when analog signal halfway between successive values.
Input rise fall times (10% 90%) Digital input timing reference level Digital output timing reference level .0.8
Capacitance
Digital input. Digital output. Analog output
1.4V
5342_03
Clock Load
This applies different analog outputs same device. Measured from steady state output voltage. This parameter allows synchronization between operations microprocessor interface pixel stream being processed color palette. following specifications apply +5V± 0.5V, GND=0. Operating Temperature 70°C.
General Operation
ICS5342 GENDAC intended analog output stage raster scan video systems. contains highspeed Random Access Memory 18-bit words, three 6/8-bit high-speed DACs, microprocessor/graphic controller interface, pixel word mask, on-chip comparators, user programmable frequency generators. externally generated BLANK* signal applied ICS5342. This signal acts three analog outputs. BLANK* signal delayed internally that appears with correct relationship pixel stream analog outputs. pixel word mask included allow incoming pixel address masked. This permits rapid changes effec-
Except SENSE pin.
Test Conditions
Input pulse levels.VDD
ICS5342 GENDAC
tive contents color palette facilitate such operations animation flashing objects. Operations contents mask register also totally asynchronous pixel stream. ICS5342 also includes dual frequency generators providing video clock (CLK0) memory clock (CLK1), both generated from single 14.318 crystal. There eight selectable CLK0 frequencies. eight programmable. There selectable programmable CLK1 frequencies (fA, fB). Default values (Shown tables: "Video Clock Default Frequency Registers," "Memory Clock Default Frequency Registers") loaded into appropriate registers power
Outputs
outputs DACs designed capable producing peak white amplitude with IREF 8.88 when driving doubly-terminated load. This corresponds effective output load (REFFECTIVE) 37.5 formula calculating IREF with various peak white voltage/output loading combinations given below:
PEAKWHITE -2.1 EFFECTIVE
Note that values IREF output loading:
BLACKLEVEL
Video Path
GENDAC supports nine different video modes determined bits command register. default mode 8-bit Pseudo Color mode. other modes bypass 15-bit, 16-bit True Color modes 8-bit 16-bit interface, 16-bit Pseudo Color (2:1) mode with Clock. 24-bit True Color sparse packed modes.
reference current IREF determined reference voltage VREF value resistor connected RSET pin. VREF internal band reference voltage overridden external voltage. both cases:
VREF
IREF
IREF
Pseudo Color
8-bit Interface this mode, Pixel Address, P7-P0 BLANK* inputs sampled rising edge clock (PCLK) change appears analog outputs after three succeeding rising edges PCLK. output depends data color palette RAM. 16-bit Interface this mode, Pixel Address, P15-P0 BLANK* inputs sampled rising edge clock (PCLK) change appears analog outputs after three succeeding rising edges ICLK. ICLK frequency twice PCLK input frequency. output depends data color palette RAM.
(INT)
VREF
(EXT)
RSET
REFF
5342_04
Setup BLANK* input GENDAC acts three outputs. When BLANK* input low, DACs powered down. connection between outputs ICS5342 inputs monitor should regarded transmission line. Impedance changes along transmission line will result reflection part video signal back along line. These reflections result degradation picture displayed monitor. techniques should observed ensure good fidelity. trace connecting GENDAC off-board connector should sized form transmission line correct impedance. Correctly matched connectors should used connection from monitor coaxial cable from that cable monitor. There recommended methods termination: double termination buffered signal. Each described below with relative merits.
Bypass Mode
GENDAC supports seven different bypass modes: three byte transfers four word transfers. these modes, address pins P0-P15 represent Color Data that applied directly DAC. internal look-up table ignored. During byte transfers, P8-P15 inputs are"don't care." Data always latched rising edge PCLK. Byte word framing internally synchronized with rising edge BLANK*.
ICS5342 GENDAC
Double Termination (Figure this termination scheme, load resistor placed both output monitor input. resistor values should equal characteristic impedance line. Double termination output allows both ends transmission line between outputs monitor inputs correctly matched.The result should ideal reflection-free system. This arrangement relatively tolerant variations transmission line impedance (e.g. mismatched connector) since reflections occur from either line. doubly terminated output will rise faster than singly terminated output because rise time outputs dependent time constant load. comparators proportional VREF (internal external) typically 0.330 VREF=1.235 Volts. SENSE* will driven when analog video output above 0.385 SENSE* output will high when analog outputs below This signal used detect type lack monitor connected system.
Clock
ICS5342 dual frequency generators generating video clock (CLK0) memory clock (CLK1) needed graphics subsystems. Both these clocks generated from single 14.318 crystal they driven from external clock source. chip includes capacitors crystal components needed loop filters, minimizing board component count. There eight possible video clock, CLK0, frequencies (f0f7) which selected external pins CS1-CS0. clocks software selectable setting control register. Frequencies f0-f7 programmed frequency writing appropriate parameter values parameter registers. default frequencies power commonly used video frequencies (see table "Video Clock Default Frequency Registers"). power frequencies selected pins CS2-CS0. There programmable memory clock frequencies (fA, fB). power this frequency defaults frequency given table: "MemoryClock Default Frequency Registers." memory clock transition between frequencies smooth glitch free parameter changed from previous setting. Video Clock (CLK0) Default Frequency Register Comments VCLK Code (MHz) 25.175 VGA0 (VGA Graphics) 28.322 VGA1 (VGA Text) 31.500 VESA 36.00 VESA 40.00 VESA 44.889 1024 Interlaced 65.00 1024 Hi-Color 75.00 VESA 1024 True Color With 14.318 input.
ICS5342
MONITOR
RLOAD
RLOAD
Ground
Ground
5342_05
Double Termination GENDAC drives large capacitive loads (for instance long cable runs), necessary buffer outputs. buffer will have relatively high input impedance. connection between outputs buffer inputs should also considered transmission line. buffer output will have relatively impedance. should matched transmission line between monitor with series terminating resistor. transmission line should terminated monitor.
ICS5342 MONITOR
RLOAD
Ground
Ground
5342_06
Buffered Signal
SENSE Output
GENDAC contains three comparators, each output lines. reference voltage
ICS5342 GENDAC
Memory Clock (CLK1) Default Frequency Register MCLK (MHz) 45.00 55.00 Code Comments Memory subsystem clock Memory subsystem clock Writing color definitions consecutive locations made easy this auto-incrementing feature. First, start address locations written write mode Pixel Address register, followed color definition that location. Since address incremented after each color definition written, color definition next location written immediately. Thus, color definitions consecutive locations written sequentially Color Value register without re-writing Pixel Address register each time. Reading from read color definition, value specifying location palette read written read mode Pixel Address register. After this value been written, contents location specified copied Color Value register, Pixel Address register automatically increments. red, green blue intensity values read sequence three reads from Color Value register. After blue value been read, location currently specified Pixel Address register copied Color Value register Pixel Address again automatically increments. color values consecutive locations read simply writing start address read mode Pixel Address register then sequentially reading color values each location set. Whenever Pixel Address register updated, unfinished color definition read write aborted begin. Pixel Mask Register pixel address used access through pixel interface result bitwise AND-ing incoming pixel address contents Pixel Mask register. This pixel masking process used alter displayed colors without altering video memory contents. partitioning color definitions more bits pixel address, such effects rapid animation, overlays, flashing objects produced. Pixel Mask register independent Pixel Address Color Value registers. Command Register Command register used select various GENDAC color modes power down mode. power this register defaults 8-bit Pseudo Color mode. This register accessed control pins RS2-RS0, special sequence events graphics subsystems that have control signal RS2. graphic systems that have RS2, this tied internal flag (HF: Hidden Flag) when pixel mask register read four times
Microprocessor Interface
Below listed microprocessor interface registers within ICS5342, register addresses through which they accessed. Microprocessor Interface Registers 0/HF Register Name Pixel Address (write mode) Pixel Address (read mode) Color Value Pixel Mask Address (write mode) Parameter Command Address (read mode) Command Register accessed (hidden) flag after special sequence events.
Asynchronous Access Microprocessor Interface Accesses registers occur without reference high speed timing pixel stream being processed GENDAC. Data transfers between color palette Color Value register, well modifications Pixel Mask register, synchronized Pixel Clock internal logic. This done period between microprocessor interface accesses. Thus, various minimum periods specified between microprocessor interface accesses allow appropriate transfers modifications take place. Access address, parameter command register asynchronous pixel clock. contents palette accessed Color Value register Pixel Address registers. Writing color palette color definition, value specifying location color palette first written Write mode Pixel Address register. values red, green blue intensities then written succession Color Value register. After blue data written Color Value register, color definition transferred RAM, Pixel Address register automatically incremented.
ICS5342 GENDAC
consecutively. Once flag set, following Read Write pixel mask register directed command register. flag reset read write register other than Pixel Mask register. sequence repeated subsequent access command register. Parameter Register CLK0 CLK1 ICS5342 programmed different frequencies writing different values parameter register bank. There eight registers parameter register; seven bytes long (0E) byte long. Writing parameter register write parameter data, corresponding address location first written address register. software compatibility with other chips, address registers defined: write mode address register read mode address register. These actually single Read/ Write register ICS5342. next parameter write will directed first byte address location specified address register. next write parameter register will automatically second byte this register. second write address automatically incremented. byte "0E" register address location incremented after first byte write. this frequency selected while programming, output frequency will change second write. Reading parameter register read registers parameter register address value corresponding location first written address register. next parameter read will directed first byte address location pointed this index register. next read parameter register will automatically second byte this register. second read, address location automatically incremented. address register (0E) incremented after first byte read.
ICS5342 GENDAC
Functional Description
This section describes register address definition RAMDAC Frequency Synthesizer sections. Color Mode Select These three bits select Color Mode RAMDAC operation shown following table "Color Mode Select" (default power up). (Reserved) future compatibility. Test Mode When checksum accumulation enabled. also oscillator synthesizers turned minimum noise. Power Down Mode RAMDAC When this (default device operates normally. this power clock Color Palette DACs turned off. data Color Palette still preserved. access without loss data internal automatic clock start/stop control. outputs become same BLANK* (sync) level output during power down mode. This does affect clock synthesizer function unless test mode enabled.
Color Palette
Command Register (RS0-RS2 011) (RS0-RS1 with hidden flag) setting bits command register ICS5342 programmed different color modes DACs turned power operation. Command Registers Reserved Test mode Snooze
Color Mode Select
8-BIT INTERFACE Mode Number (CR4) (CR7) (CR6) (CR5) Color Mode 8-bit Pseudo Color With Palette (default) 15-bit Direct Color With Bypass (Hi-Color) 24-Bit True Color With Bypass (True Color) 16-bit Direct Color With Bypass (XGA) 15-bit Direct Color With Bypass (hi-color) 15-bit Direct Color With Bypass (Hi-Color) 15-bit Direct Color With Bypass (Hi-Color) 24-bit True Color With Bypass (True Color) Clock Cycles/ Pixel Bits
16-BIT INTERFACE Mode Number (CR4) (CR7) (CR6) (CR5) Color Mode Multiplexed 16-bit Pseudo Color With Palette 15-bit Direct Color With Bypass (Hi-Color) 16-bit Direct Color With Bypass (XGA 24-bit True Color With Bypass (True Color) 24-bit Packed True Color With Bypass (true-color) Reserved Reserved Reserved Clock Cycles/ Pixel Bits
ICS5342 GENDAC
Color Modes
nine selectable color modes described here. Four eight-bit five 16-bit wide pixel input. Color Modes 8-bit interfaces with bits P0-P7; P8-P15 "don't care" bits. Mode 8-bit Pseudo Color (one clock pixel). This mode 8-bit pixel Pseudo Color mode. this mode, inputs P0-P7 pixel address color palette latched rising edge every PCLK. This default mode power selected setting bits CR7-CR4 0000. 8-bit Pseudo Color Mode PIXEL BYTE ADDRESS Mode (15-bit color bypass Hi-Color mode). This mode 15-bit pixel bypass mode. this mode, inputs P0-P7 color DATA input directly DAC, bypassing color palette. bytes data latched successive PCLK rising edges. ICS5342 supports only clock mode does support mode where data latched rising falling edges. compatibility, 15/16 clock modes selected clock modes this chip. low-byte, high byte synchronization internally done rising edge BLANK*. Each color 5-bit wide packed into bytes shown below. This mode selected setting bits CR7-CR4 0010, 1000 1010. 15-Bit Color Mode SECOND BYTE FIRST BYTE GREEN BLUE 3LSB zero Mode (16-bit pixel bypass mode). This mode 16-bit pixel bypass mode P0-P7 inputs directly, bypassing color palette. bytes data latched successive rising edges lowbyte, high-byte synchronization internally done rising edge BLANK*. this mode, blue colors bits wide green bits wide. bytes data packed shown below. This mode selected setting bits CR7-CR4 0110 1100. 16-Bit Color Mode SECOND BYTE FIRST BYTE GREEN BLUE 2LSB zero (green) 3LSB zero (blue, red) Mode (24-bit pixel True Color Mode). This mode 24-bit pixel bypass mode. three bytes data latched three successive PCLK edges first byte synchronized rising edge BLANK*. this mode, each colors 8-bit wide 8-bit wide DAC. first byte blue followed green red. This mode selected setting bits CR7-CR4 0100 1110. outputs changes every three cycles pipeline delay from first byte output five cycles. 24-bit Color Mode THIRD BYTE SECOND BYTE GREEN FIRST BYTE BLUE
Color Modes
Modes 16-bit pixel interface. Mode (8-bit Pseudo Color pixels clock) this mode, inputs P0-P15 latched rising edge every PCLK. P0-7 P8-P15 used successive addresses palette using internal clock (ICLK) that runs twice PCLK frequency. outputs change twice every PCLK pipeline delay from first word output half cycles. This mode selected setting bits CR7-CR4 0001. Multiplexed 8-bit Pseudo Color Word Mode PIXEL WORD PIXEL PIXEL ADDRESS ADDRESS Mode (16-bit pixel interface, 15-bit color bypass HiColor Mode) this mode inputs P0-P15 color data input directly DAC, bypassing color palette. data latched rising edge PCLK pipe-
ICS5342 GENDAC
lined DAC. pipeline delay from input output three PCLK cycles. Each color 5-bit wide shown below. This mode selected setting bits CR7-CR4 0011. 15-Bit Color Word Mode PIXEL WORD GREEN BLUE 3LSB zero Mode (16-bit pixel interface, 16-bit color bypass mode) this mode input P0-P15 color data input directly bypassing color palette. data latched rising edge PCLK pipelined DAC. pipeline delay, from input output, three PCLK cycles. this mode Blue colors bits wide, Green bits wide. This mode selected setting bits CR7-CR4 0101. 16-Bit Color Word Mode PIXEL WORD GREEN BLUE 2LSB zero (GREEN) 3LSB zero (BLUE, RED) Mode (16-bit pixel interface, 24-bit color bypass TRUE color mode) this mode inputs P0-P15 color data input directly bypassing color palette. words latched successive rising edge PCLK form 24-bit input. first word lower byte second word form 24-bit pixel input DAC. higher byte second word ignored. high word synchronization internally done rising edge BLANK*. pipeline delay from latching first word output cycles each pixel pixel clocks wide. this mode, each colors 8-bits wide 8-bit wide DAC. first byte Blue followed Green Red. This mode selected setting bits CR7-CR4 0111. 24-Bit Direct Color Word Mode FIRST WORD GREEN BLUE SECOND WORD XXXXXXXX7 IGNORED Mode (16-bit pixel interface packed 24-bit color bypass TRUE color mode) this mode inputs P0-P15 color data input directly bypassing color palette. Three words latched three successive rising edges PCLK form successive 24-bit inputs. 16bit first word lower byte second word from first 24-bit pixel input second byte second word with bits third word from second 24-bit pixel input. This cycle repeats every three cycles. three-word synchronization internally done rising edge BLANK*. pipeline delay from latching first word output cycles each colors 8-bits wide 8-bit wide DAC. first byte Blue followed Green Red. This mode selected setting bits CR7-CR4 1001. Packed 24-bit Word Mode Cycle SECOND WORD FIRST WORD GREEN BLUE Cycle THIRD WORD GREEN
SECOND WORD BLUE
ICS5342 GENDAC
Frequency Generators
ICS5342 clock synthesizer reprogrammed through microprocessor interface frequencies. This done writing appropriate values Parameter Register Bank (See following table: "PLL Parameter Registers").
Control Register
Bits this register determine internal external CLK0 select. Control Register (RV)= (RV)= ENBL CLK1 (RV)= Internal Select INCS 7,6, Reserved, future compatibility. Enable Internal Clock Select (INCS) CLK0. When this CLK0 output frequency selected bits this register. External pins CS0-CS2 ignored. Clk1 Select when this selected. When selected. default selected power Internal Clock Select CLK0 (INCS). These three bits select CLK0 output frequency this register They interpreted octal number, that selects Default selects
Address Registers
address parameter register written address registers before accessing parameter register. This register accessed register select pins RS2-RS0 111. Address Register Register Adr.
Parameters Registers
There sixteen registers parameter register (table Registers CLK0 selectable frequency list, Register CLK1 programmable frequency register control register. Parameter Registers Index R/R/W R/R/R/W R/Register CLK0 Parameters CLK0 Parameters CLK0 Parameters CLK0 Parameters CLK0 Parameters CLK0 Parameters CLK0 Parameters CLK0 Parameters (Reserved) CLK1 CLK1 (Reserved) (Reserved) (Reserved) Control Register (Reserved) bytes) bytes) bytes) bytes) bytes) bytes) bytes) bytes) bytes bytes) bytes) bytes bytes) bytes) (1-byte) bytes)
Data Registers
CLK0 CLK1 output frequency determined parameter values this register. These two-byte registers; first byte M-byte second N-byte. M-Byte Parameter Input M-byte 7-bit value (1-127) which feedback divider PLL. M-Byte Reserved M-Divider Value
N-Byte Parameter Input N-byte contains parameter values. sets 5-bit value (1-31) input scalar 2-bit code selecting post divide clock output. N-Byte Parameter Input Reserved Code N1-Divider Value
ICS5342 GENDAC
Post Divide Code mode command register, CR7-CR4 bits equal 0001, code must Post Divide Code Code Divider
Additional Information Programming Frequency Generator section GENDAC
When programming GENDAC parameter registers, there many possible combinations parameters which will give correct output frequency. Some combinations better than others, however. Here method determine registers need set: guidelines come from operation phase locked loop, which following restrictions:
This refers input refer-
block diagram clock synthesizer shown figure Based values, output frequency clocks given following equation:
ence frequency. Most users simply connect 14.318 crystal crystal inputs, this problem.
600KHz 8MHz This frequency input
values should programmed such that frequency within optimum range duty cycle, jitter glitch free transition. Optimum duty cycle achieved programming values greater than unity. next section programming example.
phase detector.
60MHz
This
Programming Example
Suppose output frequency 25.175 desired. reference crystal 14.318 MHz. should targeted range, choosing post divide gives frequency
25.175 101.021
frequency. general, should fast possible, because lower jitter higher frequencies. Also, running multiples desired frequency allows output divides, which tends improve duty cycle.
This output fre-
quency. These rules lead following procedure determining parameters, assuming rules satisfied. Determine value (either selecting highest value which satisfies condition fCLK Mhz.
From table previous section, find Substituting FREF 14.318 into clock frequency equation previous section:
25.175 -14.318
Calculate:
trial error: registers are: 125d code N=01010000b
(M+2) (N1+2) must found trial error. With 14.318 reference frequency, there will generally small output frequency error resolution limit (M+2) (N1+2). given frequency tolerance, several different (M+2) (N1+2) combinations usually found. Usually, minutes trying
ICS5342 GENDAC
numbers with calculator will produce workable combination. Multiplying possible values (N1+2) desired ratio will indicate approximately value This method shown example below. program could written possible combinations (M+2) (N1+2) (3937 possible combinations). Discard those outside error band, select from those remaining giving preference ratios which lower values (M+2). Lower values (M+2) (N1+2) provide better noise rejection phase locked loop. Example: Suppose have 14.318 reference crystal want output frequency MHz. want limit frequency have error greater than 0.5%. What values data registers? 66*8 speed high 66*4 speed high 66*2 speed code from Post Divide Code table Data Registers section. 132/14.31818 9.219 This desired frequency multiplication ratio. Setting (N1+2) 3,4, .12, performing some simple calculations yields following table: (Note that cannot ratio 83/9 closest. Thus: (N2+2) N2=7 (M+2) M-byte parameter word simply binary, plus (which must 01010001. N-byte parameter word code (01) concatenated with bits binary (00111), 00100111. Once again, must zero. combination with least frequency error chosen, several other combinations within 0.5% tolerance. Because lowest value (M+2) offers best damping, 37/4 combination will have best power supply rejection. This results lower jitter external noise.
Example Calculation Data Register Values *9.219 27.657 36.876 46.095 55.314 64.533 73.752 82.971 92.19 101.409 110.628 119.847 rounded Actual Ratio 9.33 9.25 9.20 9.17 9.29 9.25 9.22 9.20 9.18 9.25 9.23 Percent Error -1.23 -0.34 0.21 0.57 -0.72 -0.34 -0.03 0.21 0.40 -0.34 -0.13
ICS5342 GENDAC
Fref
1/(N1+2)
PHASE DETECT
CHARGE PUMP
LOOP FILTER
COUNTER
1/(M1+2)
5342_07
Clock Synthesizer Block Diagram Video Clock Selection Table
External Select (Internal Select Control Register) Frequency
ICS5342 GENDAC
PCLK P0-P7
BLANK
BLANK
BLANK
GREEN
BLANK
5342_8
BLUE
System Timing Pseudo Color, Mode
tCHCL
tCHCH
tCLCH
PLCK
tPVCH tCLPX
tBVCH
tCHBX
BLANK
tCHAV
tCHAV
BLANK
BLUE
tCHAV
BLANK
BLANK
5342_09
Detailed Timing Specifications Pseudo Color, Mode
ICS5342 GENDAC
PCLK
BLANK
P0-P7
BYTE
HIGH BYTE
BYTE
HIGH BYTE
DAC-RD
DAC-GR
5342_10
DAC-BL
System Timing Bypass- 15(5/6/5) Modes
PCLK
25ns
50ns
75ns
100ns
125ns
150ns
BLANK
P0-P7
DAC-BL DAC-GR
5342_11
DAC-RD
System Timing Bypass True Color (8,8,8) Mode
ICS5342 GENDAC
PCLK ICLK
P0-P7 P8-P15 BLANK
GREEN BLUE
BLANK
BLANK
BLANK
5342_12
System Timing 8-bit Pseudo Color, Mode
PCLK
P0-P7
BLANK
BLANK
BLANK
GREEN
BLUE
BLANK
5342_13
System Timing 16-bit Color, Mode 5(5,5,5) 6((5,6,5)
ICS5342 GENDAC
PCLK
P0-P7
BLANK
BLANK
GREEN
BLANK
BLUE
BLANK
5342_14
System Timing 16-bit Direct True Color, Mode
PCLK P0-P7
BLANK
BLANK
BLANK
GREEN
BLANK
BLANK
BLUE
BLANK
BLANK
5342_15
System Timing 24-bit Packed Color, Mode
ICS5342 GENDAC
tWLWH tSVWL RS0-RS1 tDVWH D0-D7 tWHDX tWLSX
Basic Write Cycle Timing
tRLRH tSVRL RS0-RS1 tRLQV D0-D7 tRLQX tRHQZ tRHQX tRLSX
Basic Read Cycle Timing
5342_16
tWHWL1
tWHRL1
Write Pixel Mask Register Followed Write
tRHRL1
Write Pixel Mask Register Followed Read
tRHWL1
Read from Pixel Pixel Address Register (Read Write) followed Read
Read from Pixel Pixel Address Register (Read Write) followed Write
5342_17
Read-Write Timing
ICS5342 GENDAC
tWHRL1
D0-D7
ADDRESS
ADDRESS+1
5342_18
Back Write ReadR BPixel Address Register (Read Mode)
tWHRL3
D0-D7
ADDRESS
ADDRESS
5342_19
Write Read Back Pixel Address Register (Write Mode)
ICS5342 GENDAC
tWHRL3
tRHRL1
tRHRL1
tRHRL2
D0-D7
ADDRESS
GREEN
BLUE
ADDRESS+2
5342_20
Read Color Value then Pixel Address Register (Read Mode)
tWHWL1 tWHRL2 tWHWL1 tWHWL1
D0-D7
ADDRESS
GREEN
BLUE
5342_21
Color Value Write Followed Read
ICS5342 GENDAC
tWHWL1 tWHWL1 tWHWL1 tWHWL2
D0-D7
ADDRESS
GREEN
BLUE
5342_22
Color Value Write Followed Write
tWHRL3
tRHRL1
tRHRL1
tRHRL2
D0-D7
ADDRESS
GREEN
BLUE
5342_23
Color Value Read Followed Read
ICS5342 GENDAC
tWHRL3
tRHRL1
tRHRL1
tRHWL2
D0-D7
ADDRESS
GREEN
BLUE
5342_24
Color Value Read Followed Write
tWHRL3
D0-D7
ADDRESS
ADDRESS
5342_25
Write Read back Address Register (Write Mode)
ICS5342 GENDAC
tWHRL3
D0-D7
ADDRESS
ADDRESS+1
5342_26
Write Read back Address Register (Read Mode)
tWHRL3
tRHRL1
tRHRL1
tRHRL2
D0-D7
ADDRESS
HIGH
ADR+1
5342_27
ReadR PLLPLL then AddressR bytes Register Register
ICS5342 GENDAC
tWHRL3
tRHRL1
tRHRL1
tRHRL2
D0-D7
ADDRESS
ADR+1
5342_28
Read Byte Register then Address Register
GREEN BLUE 0.335V tS0D SENSE
5342_29
Monitor SENSE Signal
ICS5342 GENDAC
Recommended Layout
LOCATE NEAR CONTROLLER
LOCATE NEAR CONTROLLER
CGND
CVDD
CLK1
CVDD AGND
DGND
BLUE AVDD RSET DVDD
CLK0
CGND
GENDAC ICS5342
XVDD XOUT XGND VREF
PCLK
DGND
5342_30
Board Layout Analog Signal Considerations
high performance GENDAC dependent careful board layout. four layer board (internal power ground planes, signals surface layers) recommended. ground plane layer should closest component side board. layout following this section shows suggested configuration.
power plane ground plane 0.047 chip capacitor chip capacitor tantalum capacitor ferrite bead, Fair-Rite 2743019447 ohm, parallel resonant crystal
Power Supply
high speed CMOS device, GENDAC draw large transient currents from power supply. necessary adopt high-frequency board-layout power-distribution techniques assure proper operation GENDAC. This will also minimize radio frequency interference (RFI). crosstalk also attributed high impedance power supply.
ICS5342 GENDAC
Note power plane separated into analog digital supply regions. power ground planes continuous, split. Power supplied analog power pins through ferrite bead, bypassed power entry point tantalum capacitor. Analog power connections should routed shown diagram. They routed back side analog signals routed without vias. Power pins should connected digital power. Power pins connected analog power (VAA). Ceramic decoupling capacitors (indicated should placed close GENDAC possible. power traces should routed through capacitor pads ground vias should shared. rule pad, via. GENDAC analog ground pins should have multiple vias ground plane, possible. supply transient currents required, impedance decoupling path should kept minimum. just important that connection between capacitor ground ground plane short direct. recommended that decoupling capacitance between should 0.047 high frequency capacitor. Chip capacitors have lowest lead inductance highly recommended. 0.047 chip capacitors more effective frequencies above than other values range 0.022 supply pins must have ceramic capacitor connected. tantalum capacitor with value between recommended decouple frequencies. further reduce power-supply noise, ferrite bead added series with positive supply form pass filter, shown layout example. Power ground traces GENDAC should mils wide whenever possible. GENDAC. effect this will have compromise time duty cycle output clocks. traces between outputs devices driving GENDAC input GENDAC behave like impedance transmission lines. trace driven from impedance source terminated with high impedance. accordance with transmission line principles, signal transitions will reflected from high impedance input device. Similarly, signal transitions will inverted reflected from impedance output. Termination necessary reduce eliminate ringing; particularly undershoot caused reflections. Termination either series parallel. Series parallel termination recommended technique use. This accomplished placing resistor series with signal output clock driver. resistor matches output buffer impedance that transmission line. line another resistor added terminate transmission line VCC. minimize reflections, some experimentation necessary find proper value series termination. Generally, series resistor with value around parallel resistor will satisfactory. Since each design will result different trace impedance, resistor predetermined value properly match signal path impedance. proper value resistance should found empirically.
Analog Signals
analog digital lines shown. Analog signals (DAC outputs, VREF, RSET) should only routed side board. output termination resistors should located close possible GENDAC best signal quality. Doing this will also reduce RFI.
Digital Input Information
minimize differential ground noise between components board, impedance ground supply between GENDAC digital devices driving should minimized. This high impedance ground trace controller cause false signals GENDAC. This appear glitches edge sensitive inputs such RD*, WR*, STRB. Splitting ground plane exacerbates this problem. combination series impedance ground supply GENDAC transients current drawn device, will appear voltage differences across pins
ICS5342 GENDAC
ICS5342 GENDAC
ICS5342 GENDAC
Package Outline
IDENTIFIER
0.045
0.045
0.985 0.995 (25.02 25.27)
0.950 0.958 (24.13 24.33)
GENDAC ICS5342
0.890 0.930 (22.61 23.62)
0.013 0.021 (0.33 0.53)
0.985 0.995 (25.02 25.27) 0.950 0.958 (24.13 24.33)
0.020 (0.51) 0.102 (2.59) 0.165 0.180 (4.20 4.57) LEAD PITCH 0.050 TYPICAL DIMENSIONS: INCHES (MILLIMETERS)
5342_31
PLCC
Package Detail

ICS5342 GENDAC combination dual programmable clock generators, 18-bit

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