High Speed w/16-Bit Resolution MSPS Monolithic 16-Bit Oversampled

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High Speed w/16-Bit Resolution MSPS Monolithic 16-Bit Oversampled

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AK2711
High Speed w/16-Bit Resolution MSPS
Monolithic 16-Bit Oversampled Oversampling, MSPS Clock Internal jitter allows clock input speeds sample clock. 1.25 Input Word Rate Specifications Signal Passband Signal-to-Noise: Signal-to-(Noise plus Distortion): 82.5 Dynamic range: Out-of-band Mhz): Digital Filter Passband Ripple: 0.05dB Stopband Attentuation: 70dB Power Dissipation Power Supply Analog Supply Digital Supply differential glitch free output Edge triggered input latch parallel data input LQFP package
Block Diagram
AVDD AVSS AVDD AVDD AVSS AVSS DVDD DVSS
ORDER SWITCHED CAPACITOR
MULTIBIT SIGMA-DELTA MODULATOR
OUTN
OUTPUT BUFFER
ORDER CONTINUOUS
STAGE INTERPOLATION FILTER
INPUT REGISTER
OUTP
BIT1-BIT16
AK2711
REFP REFN VCOM REFERENCE BUFFER
STAGE INTERPOLATION FILTER
PRELIMINARY
STAGE INTERPOLATION FILTER
RBIAS
BANDGAP REFERENCE
Description
AK2711 16-bit, high speed oversampled digital-to-analog converter optimized waveform reconstruction applications requiring high dynamic range. Glitches that characteristic Nyquist rate DACs avoided over-sampled, multibit sigma-delta architecture. AK2711 manufactured advanced submicron analog process. High dynamic range achieved proprietary multi delta sigma techniques. AK2711 switched capacitor DAC, with nominal full scale differential output with common-mode output level 2.5V.
on-chip interpolation filter suppresses original
MCEN
MCLK
inband images eliminating need complex external analog smoothing filters. Additional out-ofband filtering provided after sigma-delta on-chip reference reference buffer amplifier configured maximum accuracy flexibility. Phase-Lock-Loop clock multiplier provides necessary synchronized 16fs clock support over-sampled DAC. external synchronous clock also used. AK2711 operates single analog supply digital supply, typically consuming 200mW. AK2711 available 44-lead LQFP package specified operate from 85C.
MCBP
SCLK
PERFORMANCE SPECIFICATION
SPECIFICATION
AVDD 5.0V, DVDD AGND DGND fMCLK MSPS, TMAX=85C, TMIN=-40C Parameter Resolution Accuracy Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Monotonicity Offset Error Gain Error Temperature Drift Offset Error Gain Error Power Supply Rejection AVDD,DVDD,SVDD Analog Output Output Full Scale Output Common Mode Voltage Output Load Resistance Output Load Capacitance Internal Voltage Reference Output Voltage Power Supplies AVDD SVDD DVDD Supply Currents I(AVDD SVDD) I(DVDD) Power Consumption Power VREF 2.5V supply ripple(500kHz) ppm/C ppm/C Bits Guaranteed Note Note
Conditions/Comments
Min.
Typ.
Max.
Units Bits
+0.8 -3.5
Bits
4.75
100kHz Input, -2.2dBFS1
100kHz Input, -2.2dBFS
100kHz Input, -2.2dBFS1
2.43 2.43 5.25 5.25
Vp-p Diff ohms
12/1999
ASAHI KASEI
AK2711
PERFORMANCE SPECIFICATION[continued]
SPECIFICATION
AVDD +5V, DVDD= +3V, fMCLK MSPS, TMAX=85C, TMIN=-40C Parameter DYNAMIC PERFORMANCE Input Test Frequency: Signal Noise (SNR) Distortion (SINAD) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Input Test Frequency: Signal Noise (SNR) Spurious Free Dynamic Range (SFDR) INTERMODULATION DISTORTION fIN1 kHz, fIN2 DYNAMIC CHARACTERISTICS Settling Time Output Propagation Delay Output Noise Voltage 0.003% Input Amplitude: -0.5dBFS Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS Input Amplitude: -0.5dBFS1 Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS Input Amplitude: -0.5 dBFS1 Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS
Conditions/Comments
Min.
Typ.
Max.
Units
82.5
Min.
DIGITAL FILTER CHARACTERISTICS
Parameter Filter Passband Ripple Stopband Attenuation
Conditions/Comments
0.596
12/1999
dBFS Clocks Typ. Max. ±0.05 Units
PERFORMANCE SPECIFICATION[continued]
DIGITAL SPECIFICATION
AVDD +5V, DVDD +5V, MAX=85C, TMIN=-40C Parameter RPULLDOWN High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Pull Down Resistance Conditions/Comments Clock Clock other pins other pins MCEN, MCBP, TST, DITHEN, DEMEN, SCAN pins except internal pulldown pins 0.7*DVDD 0.3*DVDD Ohms Min. Units
Input Leakage Current
Notes 100% production tested sample tested specified temperatures.
Absolute Maximum Ratings
AGND, SGND,RGND DGND voltages with respect ground.
Parameter
Power Supplies VIND Temperature Tstg Storage Temperature Analog Power Supply Digital Power Supply Difference between AGND, SGND, AGND2 DGND Input Current-All pins except supply pins Digital Input Voltage Ambient Operating Temperature (Power Applied)
Min. -0.3 -0.3
-0.3 Min. 4.75 Typ.
Recommended Operation Conditions
Parameter
Power Supplies
AGND, SGND, AGND2, DGND voltages with respect ground. Max. 5.25 Units
Analog Power Supply (AVDD SVDD) Digital Power Supply (DVDD)
Max. Units
12/1999
ASAHI KASEI
AK2711
Digital Switching Characteristics
AVDD +5V, DVDD=5V, CL=20pF, TMAX=85C, TMIN=-40C Parameter tMCLK tSCLK tMCLKL tSCLKH tSCLKL Master Clock Period Sample Clock Period Master Clock Pulse Width Sample Clock Pulse Width High Sample Clock Pulse Width Input Setup Time SCLK Input Hold Time after SCLK Conditions/Comments Min. Typ. Max. Units
tMCLKH Master Clock Pulse Width High
LAYOUT
LQFP AK2711
SVDD AVSS REFH REFL
DEMEN DVDD SCAN DVSS AVSS
12/1999
RBIAS AVDD AVSS VCOM OUTP OUTN DITHEN
MCEN
MCBP
MCLK
SVSS
SCLK
TCLK
DESCIPTION
1-16 Name D0-D15 DVDD DVSS AVSS SCAN DEMEN DITHEN OUTN Function Description Data Input. (MSB Pin1) Digital Supply. DVDD 3/5V Digital Ground. DVSS Analog Ground. AVSS=0V Test Mode Test Mode Test Mode Dither Enable (Active low) Differential Analog Output Differential Analog Output Internal Common mode voltage Analog Ground. AVSS=0V Resistor Connected Ground (4.99K ohms) output derived from internal bandgap voltage output derived from internal bandgap voltage Analog Ground. AVSS=0V Analog Supply SVDD Analog Ground. SVSS Master Clock Chip Enable (Active High) Analog Supply. AVDD
OUTP
VCOM AVSS AVDD RBIAS REFL REFH AVSS SVDD SVSS MCLK MCBP MCEN TCLK SCLK
Mode Pins. M1,M0 MCLK SCLK; MCLK 2SCLK, MCLK 4SCLK; MCLK 16SCLK. Connected Connected Bypass Clock Output
Sample Clock (Data latched positive edge clock)
Enables Clock Output
12/1999
ASAHI KASEI
AK2711
THEORY OPERATION
AK2711 bit, 2.5MSPS Digital Analog converter intended xDSL high speed instrumentation, medical imaging high resolution, high speed signal generation. novel delta-sigma modulator operating 20Mhz employing multibit quantization dynamic element matching techniques achieves 86dB signal noise performance, with 86dB spurious free dynamic range power dissipation 200mW. on-chip interpolation filter continuos time filter provides excellent stop-band rejection suppress stray signal greater than 0.745MHz, substantially easing requirements anti-imaging filter analog output path. AK2711 features internal digital provide flexibility clock input. MODE allow different clocking options. digital supply 5.25 2.7V used, though supply recommended minimize digital noise board. provided reset internal filters, case overflow condition correct initialization during power up.An on-chip reference reference buffer included AK2711. 2.5V reference provides pk-pk differential output full scale. intended further reduce quantization noise introduced multibit DAC. This dithering externally turned using test mode pin, DITHEN.
Analog Filtering
AK2711 includes order switched capacitor discrete time pass filter followed order analog continuos time pass filter. These filters eliminate need additional chip external reconstruction filtering. continuos time filtering results glitch free output waveforms.
Phase Lock Loop
digital phase lock loop integrated chip provide flexibility clocking. Mode pins allow MCLK times SCLK frequency. Range pins allow different ranges SCLK from 625KHz 2.5MHz. best performance achieved when bypassed.
Analog Output Reference Overview
value defines maximum output voltage AK2711. internal reference buffer scales 2.5V create REFH REFL. scale factor these buffers 0.8. Thus maximum output voltage defined +0.8 -0.8 -2V.
Digital Inputs
parallel data interface uses sample clock (SCLK) clock input data. positive edge SCLK strobes complement data into input registers AK2711. SCLK asynchronous master clock (MCLK).
Digital Interpolation Filter
Multibit Sigma Delta Modulator
purpose interpolator oversample input data, i.e. increase sample rate that attentuation requirements analog filters relaxed. interpolation performed using multistage digital filters.The filtering introduces +0.05dB passband ripple stopband attentuation -70dB.
Output Drive, Buffering Loading
AK2711 analog output stage able drive load ohms. single ended output required, differential single ended instrument circuit required. Level scaling also achieved easily using this circuit. DIFFERENTIAL SINGLE ENDED DRIVER
AK2711 employs multi sigma delta using proprietary dynamic element matching techniques provide excellent linearity.
Dither Generator
AK2711 includes chip dither generator, which
Figure Coupled Differential Buffer with Level Shifting
12/1999
AK2711
ASAHI KASEI
REFERENCE OPERATION
AK2711 contains integrated bandgap reference internal reference buffer amplifier. This reference generates 2.5V. actual voltages used internal circuitry AK2711 appear REFH REFL pins. proper operation, necessary capacitive network decoupled pins. digital switching lines must drawn away from these pins. BIAS connected 4.99k ohms. This sets bias currents analog circuitry. Minimization capacitance this recommended order prevent instability bias amplifier.
SCLK TCLK MCEN MCBP MCLK SVSS
SVDD
DATA
AK2711
CLOCK INPUT CONSIDERATION
clock input should treated analog signal cases where aperture jitter affect dynamic range AK2711. input buffer powered analog supply requires high levels 3.5V respectively. jitter crystal controlled oscillators make best clock source
Figure2: Decoupling Bias Connection AK2711
GROUNDING DECOUPLING
Analog Digital Grounding Multi layer printed circuit boards (PCBs) recommended provide optimal grounding power schemes. ground power planes results both reduction electromagnetic interference (EMI) overall improvement performance. important design layout that prevents noise from coupling onto input signal. Digital signals should parallel with input signal traces should routed away from input circuitry. While AK2711 features separate analog digital pins, should treated analog component.
Analog Digital Supply Decoupling
analog digital supplies should decoupled close chip physically possible. combination 0.1uF 10uF should connected between each pair power supplies: AVDD AVSS, DVDD DVSS, SVDD SVSS. external decoupling bias network shown figure
12/1999
DVDD DVSS AVSS SCAN DEMEN
AVSS REFH REFL RBIAS AVDD AVSS VCOM OUTP OUTN DITHEN
DATA
ASAHI KASEI
AK2711
MARKING SPEC
Marking Spec
AK2711 XXXXXXX JAPAN
XXXXXXX Date Production Code
12/1999
JAPAN Country Origin
AK2711
ASAHI KASEI
OUTLINE DIMENSIONS
12.8 10.0
12.8+
10.0
+0.2 0.37
0.1+0.1
44-Lead LQFP
1.7MAX
0.17
Dimensions shown millimeters
Important Notice
These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonable expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product contributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
12/1999
0~10

High Speed w/16-Bit Resolution MSPS Monolithic 16-Bit Oversampled

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