MK2049-02 MK2049-03 PhaseLocked Loop (PLL) based clock synthesizers th
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MK2049-02/03 Communications Clock PLLs
MK2049-02 MK2049-03 PhaseLocked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With clock input reference, MK2049-02/03 generate ISDN, xDSL, other communications frequencies. This allows generation clocks frequency-locked phaselocked backplane clock, simplifying clock synchronization communications systems. MK2049-02/03 also accept input clock provide same output loop timing. outputs frequency-locked together input. These parts also have jitter-attenuated buffer capability. this mode, MK2049-02/03 ideal filtering jitter from video clocks other clocks with high jitter. ICS/MicroClock customize these devices many other different frequencies. Contact your ICS/MicroClock representative more details.
Packaged SOIC Fixed input-output phase relationship most clock selections Meets TR62411, ETS300 011, GR-1244 specification MTIE, Pull-in/Hold-in Range, Phase Transients, Jitter Generation Stratum Accept multiple inputs: backplane clock, Loop Timing frequencies, 10-28 Lock ±100 (External mode) Buffer Mode allows jitter attenuation 10-28 input x1/x0.5 x2/x4 outputs Exact internal ratios enable zero error Output clock rates include ISDN, xDSL, submultiples operation. Refer MK2049-34
Block Diagram
RESET FS3:0 Clock Synthesis, Control, Jitter Attenuation Circuitry Output Buffer Output Buffer Output Buffer CAP1 CLK1
Clock Input Reference Crystal Crystal Oscillator
External/ Loop Timing
CLK2
CAP2
CLK3 (External Mode only)
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
Assignment
CLK2 CLK1 CLK3 RESET CAP2 CAP1 ICLK
(300 mil) SOIC Descriptions
Number Name CLK2 CLK1 CLK3 ICLK CAP1 CAP2 RESET Type Description Frequency Select Determines input/outputs tables pages Crystal connection. Connect crystal shown tables pages Crystal connection. Connect crystal shown tables pages Connect +5V. Connect +5V. Connect +5V. Connect ground. Clock output determined status FS3:0 tables pages Clock output determined status FS3:0 tables pages Always CLK2. Clock shown tables pages typically recovered clock output. Frequency Select Determines input/outputs tables pages Frequency Select Determines input/outputs tables pages Input clock connection. Connect backplane clock. Connect ground. Connect +5V. Connect loop filter ceramic capacitors resistor between this CAP2. Connect ground. Connect loop filter ceramic capacitors resistor between this CAP1. Reset pin. Resets internal when low. Outputs will stop low. Internal pull-up resistor. Frequency Select Determines input/outputs tables pages
Type: crystal connections, Input, output, power supply connection, loop filter connections Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
Electrical Specifications
Parameter Supply Voltage, Inputs Clock Outputs Ambient Operating Temperature Soldering Temperature Storage Temperature Operating Voltage, Input High Voltage, Input Voltage, Input High Voltage, Input Voltage, Output High Voltage Output High Voltage Output Voltage Operating Supply Current, Short Circuit Current Input Capacitance, FS3:0 Input Frequency, External Mode Input Clock Pulse Width Propagation Delay Output-Output Skew, Zero Delay Selections Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle, High Time Actual mean frequency error versus target Conditions Referenced MK2049-0xS MK2049-0xSI seconds -0.5 4.75 only only IOH=-4 IOH=-8 IOL=8 Load, VDD=5.0V Each output VDD-0.5 VDD-0.4 ±100 8.000 ICLK CLK2 CLK1 CLK2, Note VDD/2 clock selection Minimum Typical Maximum VDD+0.5 5.25 Units
ABSOLUTE MAXIMUM RATINGS (Note
CHARACTERISTICS (VDD unless noted)
CHARACTERISTICS (VDD unless noted)
ICLK
Notes: Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage device. Prolonged exposure levels above operating limits below Absolute Maximums affect device reliability. CLK1 MK2049-02 have rising falling edge aligned with rising edge CLK2. INPUT OUTPUT SYNCHRONIZATION section more details.
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
MK2049-02 Output Decoding Table External Mode (MHz)
ICLK CLK1 (Note 1.544 2.048 22.368 17.184 19.44 16.384 24.576 25.92 10.24 4.096 CLK2 3.088 4.096 44.736 34.368 38.88 32.768 49.152 51.84 20.48 8.192 Crystal 12.352 12.288 11.184 11.456 12.96 8.192 12.288 12.96 10.24 12.288 CLK3
MK2049-02 Output Decoding Table Loop Timing Mode (MHz)
ICLK 1.544 2.048 44.736 34.368 CLK1 (Note 1.544 2.048 22.368 17.184 CLK2 3.088 4.096 44.736 34.368 Crystal 12.352 12.288 11.184 11.456 CLK3
MK2049-02 Output Decoding Table Buffer Mode (MHz)
ICLK CLK1 (Note ICLK/2 2*ICLK CLK2 ICLK 4*ICLK Crystal ICLK/2 ICLK CLK3
connect directly ground, connect directly VDD. Crystal connected pins clock input applied
Zero (Fixed) Delay these selections shown shaded boxes. Note CLK1 rising falling edge align with input clock. Figure page more details.
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
MK2049-03 Output Decoding Table External Mode (MHz)
ICLK CLK1 1.544 2.048 18.688 7.68 19.44 16.384 24.576 8.64 12.416 18.528 10.24 4.096 CLK2 3.088 4.096 37.376 15.36 38.88 32.768 49.152 17.28 24.832 37.056 20.48 8.192 CLK3 1.544 Crystal 12.352 12.288 9.344 10.24 9.72 8.192 12.288 11.52 12.416 12.352 10.24 8.192
Zero (Fixed) Delay these selections shown shaded boxes. MK2049-03 Output Decoding Table Loop Timing Mode (MHz) T1/E1
ICLK 1.544 2.048 CLK1 1.544 2.048 CLK2 3.088 4.096 Crystal 12.352 12.288 CLK3
MK2049-03 Output Decoding Table Buffer Mode (MHz)
ICLK CLK1 ICLK/2 2*ICLK CLK2 ICLK 4*ICLK Crystal ICLK/2 ICLK CLK3
connect directly ground, connect directly VDD. Crystal connected pins clock input applied
OPERATING MODES
MK2049-02/03 have three operating modes: External, Loop Timing, Buffer. Although each mode uses input clock generate various output clocks, there important differences their input crystal requirements. External Mode MK2049-02/03 accept external clock will produce number common communication clock frequencies. input clock does need have duty cycle; "high" "on" pulse narrow acceptable. MK2049-02, rising edge CLK2 aligned with rising edge ICLK; refer Figure more details. MK2049-03, rising edges CLK1 CLK2 both aligned with rising edge ICLK (unless noted shaded area table); refer Figure more details.
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
OPERATING MODES (continued)
Loop Timing Mode This mode used remove jitter from standard high-frequency communication clocks. inputs, CLK1 output will same input frequency, with CLK2 twice input frequency. inputs, CLK1 will input frequency CLK2 will same input frequency. Buffer Mode Unlike other modes that accept only single specified input frequency, Buffer Mode will accept wider range input clocks. input jitter attenuated, outputs CLK1 CLK2 also provide option getting input frequency. example, this mode used remove jitter from clock, generating low-jitter 13.5 outputs.
INPUT OUTPUT SYNCHRONIZATION
shown tables pages MK2049-02/03 offer Zero Delay feature most selections. these selections, there internal feedback path between ICLK CLK2 output clock. This provides fixed phase relationship between input output, requirement many communications systems. MK2049-02 illustrated diagram below, when using MK2049-02 Zero Delay selections, rising edge ICLK will aligned with rising edge CLK2. However, CLK1 edge these cases will either rising falling. used this illustration, same true Zero Delay selections Loop Timing Buffer modes.)
ICLK kHz)
CLK2 (MHz)
CLK1 (MHz)
Figure MK2049-02 Input Output Clock Waveforms Zero Delay Selections
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
INPUT OUTPUT SYNCHRONIZATION (continued)
MK2049-03 illustrated diagram below, when using MK2049-03 Zero Delay selections, rising edge ICLK will aligned with rising edges CLK1 CLK2.
ICLK kHz)
CLK2 (MHz)
CLK1 (MHz)
Figure MK2049-03 Input Output Clock Waveforms Zero Delay Selections
MK2049-02 MK2049-03 selections that Zero Delay, phase relationship between input output clocks predictable. Although will change once MK2049-02/03 running, this relationship likely change when power interrupted.
Measuring Zero Delay MK2049
MK2049-02/03 both produce low-jitter output clocks. addition, both parts have very bandwidth-on order Hertz. Since most input clocks will have high jitter, this make measuring input-to-output skew (zero delay feature) very difficult. MK2049 designed reject input jitter; when input output clocks both displayed oscilloscope, they appear locked because scope trigger point constantly changing with input jitter. fact, input output clocks probably locked, MK2049 will have zero delay average position input clock. order this clearly, jitter input clock necessary. Most frequency sources SUITABLE this since they have high jitter frequencies.
Frequency Locking Input
modes, output clocks frequency-locked input. output will remain specified output frequency long combined variation input frequency crystal does exceed ppm. example, crystal vary (initial accuracy temperature aging), then input frequency vary still have output clock remain frequency-locked. Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
LAYOUT EXTERNAL COMPONENTS
MK2049-02/03 require minimum number external components proper operation. Decoupling capacitors 0.01µF must connected between pins close chip (especially pins 17), terminating resistors should used clock outputs with traces longer than inch (assuming traces).
Board Layout
proper board layout critical successful MK2049. particular, CAP1 CAP2 pins very sensitive noise leakage (CAP2 most sensitive). Traces must short possible capacitors resistor must mounted next device shown below. capacitor shown between pins between pins power supply decoupling capacitors. high frequency output clocks pins should have series termination connected close pin. Additional improvements will come from keeping components same side board, minimizing vias through other signal layers, routing other signals away from MK2049. also refer MAN05 additional suggestions layout crystal section. crystal traces should include pads small capacitors from ground; these used adjust stray capacitance board match crystal load capacitance. typical telecom reference frequency accurate much less than ppm, MK2049 lock properly even board capacitance adjusted with these fixed capacitors. However, MicroClock recommends that adjustment capacitors included minimize effects variation individual crystals, temperature, aging. value these capacitors (typically determined once given board layout, using procedure described section titled "Determining Crystal Frequency Adjustment Capacitors". Cutout ground power plane.
Optional; text
Route traces away from this area.
resist. resist.
resist.
=connect =connect
Figure Typical MK2049-02/03 Layout
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
LAYOUT EXTERNAL COMPONENTS (continued) External Components Selection
external loop filter should connected between CAP1 CAP2 shown Figure below, close chip possible. High quality ceramic capacitors recommended. type polarized electrolytic capacitor. Ceramic capacitors should have dielectric. Another alternative Panasonic polymer dielectric series; their part number ECHU1C104JB5. Avoid high-K dielectrics like X7R; these other ceramics which have piezolectric properties allow mechanical vibration system increase output jitter because mechanical energy converted directly voltage noise input. CAP2
0.015
CAP1
Figure Loop Filter Component Values
Typical component values shown. Contact MicroClock applications department (408)297-1201 recommended values your application.
Crystal Operation
MK2049 operates phase locking input signal VCXO which consists special recommended crystal integrated VCXO oscillator circuit MK2049. achieve best performance reliability, layout guidelines shown previous page must closely followed. frequency oscillation quartz crystal determined load capacitors connected MK2049 variable load capacitors on-chip which "pull", change frequency crystal. External stray capacitance must kept minimum ensure maximum pullability crystal. achieve this, layout should short traces between MK2049 crystal.
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
LAYOUT EXTERNAL COMPONENTS (continued) Crystal Specifications
Parameter Operating Temperature Range Initial Accuracy Temperature stability Aging, first year Aging, years Load Capacitance Shunt Capacitance, Motional Capacitance, C0/C1 ratio Equivalent Series Resistance Minimum Typical Maximum none Units none Ohms
Note none
*This ratio decreases lower crystal frequencies. Note Nominal crystal load capacitance specification varies with frequency. Contact MicroClock applications department (408)297-1201. Note third overtone mode crystal spurs must >200 away from fundamental resonance shown table below.
recommended crystal devices, please contact MicroClock application department 408-297-1201.
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
LAYOUT EXTERNAL COMPONENTS (continued) Determining Crystal Frequency Adjustment Capacitors
determine crystal adjustment capacitor values, will need board your final layout, frequency counter capable less than resolution accuracy, power supplies, some samples crystals which plan production, along with measured initial accuracy each crystal specified load capacitance, determine value crystal capacitors: Connect MK2049 Connect MK2049 second power supply. Adjust voltage Measure record frequency CLK1 CLK2 output Adjust voltage Measure record frequency same output. calculate centering error: Centering error 3.0V target) 0.0V target) target error xtal
Where ftarget 44.736000 MHz, example, errorxtal actual initial accuracy ppm) crystal being measured. centering error less than ppm, adjustment needed. centering error more than negative, board much stray capacitance will need redone with layout reduce stray capacitance. (The crystal re-specified lower load capacitance instead. Contact MicroClock details.) centering error more than positive, identical fixed centering capacitors from each crystal ground. value each these caps given External Capacitor 2*(centering error)/(trim sensitivity) Trim sensitivity parameter which supplied your crystal vendor. know value, assume ppm/pF. After changes, repeat measurement verify that remaining error acceptably (less than ppm). MicroClock Applications department perform this procedure your board. Call 408-2959800, will arrange send board (stuffed unstuffed) your crystals. will calculate value capacitors needed.
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
MK2049-02/03 Communications Clock PLLs
Package Outline Package Dimensions (For current dimensional specifications, JEDEC Publication 95.)
SOIC
Inches Symbol -0.104 0.0040 0.013 0.020 0.007 0.013 0.496 0.512 0.291 0.299 .050 0.394 0.419 0.01 0.029 0.016 0.050 Millimeters -2.65 0.10 -0.33 0.51 0.18 0.33 12.60 13.00 7.40 7.60 1.27 10.01 10.64 0.25 0.74 0.41 1.27
INDEX AREA
Ordering Information
Part/Order Number MK2049-02S MK2049-02STR MK2049-02SI MK2049-02SITR MK2049-03S MK2049-03STR MK2049-03SI MK2049-03SITR Marking MK2049-02S MK2049-02S MK2049-02SI MK2049-02SI MK2049-03S MK2049-03S MK2049-03SI MK2049-03SI Package SOIC Tape Reel SOIC Tape Reel SOIC Tape Reel SOIC Tape Reel Temperature
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
Revision 040601 Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
2049-02/03
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