0.8mm single poly, double metal CMOS technology gate architecture Oper

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0.8mm single poly, double metal CMOS technology gate architecture Oper

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HT5D 0.8mm CMOS High Speed Gate Array
0.8mm single poly, double metal CMOS technology gate architecture Operating voltage: Propagation delay 0.3ns 2-input NAND with fanout=2 Output driving capability 2mA, 4mA, 8mA, 12mA, 16mA, 20mA, 24mA, 30mA, 48mA
array bases Under usable gates Maximum (not including power pads)
HT5D Series
Part Number HT5D028 HT5D048 Usable Gates 1285 Maximum
HT5D 0.8mm CMOS High Speed Gate Array
Cell Libraries
Buffers Inverting, noninverting, tri-state, clock buffer Input buffers CMOS, CMOS Schmitt TTL, Schmitt NAND/AND gates NOR/OR gates AOI/OAI gates XNOR/XOR gates Flip-Flops Flip-Flops Multiplexed Flip-Flops Flip-Flops Latches with set, with clear, with clear, NOR-latch, NAND-latch, scannable latch
Adders 1-bit full, 2-bit full Adders/Subtractors 1-bit, 2-bit Decoders 2-to-4, 3-to-8 Multiplexers 2-to-1, 4-to-1, 8-to-1 Synchronous counters with clear, with clear Miscellaneous DLY, CLOAD1, MAXCAP, NETWTH, RP01D1, WEIGHT
Libraries
Input pads Input only, with pull-up/pull-down resistor Clock input pads Inverting/noninverting with CMOS level Inverting/noninverting with Schmitt Trigger Inverting/noninverting with level Output pads 2mA, 4mA, 8mA, 12mA, 16mA, 20mA, 24mA, 30mA, 48mA driving capability Output only, 3-state output, with pull-up/pull-down resistor CMOS level, level with limited slew rate control
Pads 2mA, 4mA, 8mA, 12mA, 16mA, 20mA, 24mA, 30mA, 48mA driving capability 3-state output, with pull-up/pull-down resistor CMOS level, level with limited slew rate control Power pads Core only, padding only, padding Crystal oscillator pads frequency (1kHz~10MHz) Intermediate frequency (10MHz~25MHz) High frequency (25MHz~60MHz)
HT5F/5G 0.5mm CMOS High Speed Gate Array
0.5mm single poly double/triple metal CMOS technology gate architecture Operating voltage: 5V/3V Propagation delay 120ps 2-input NAND with fanout=2 Output driving capability 4mA, 8mA, 12mA, 16mA, 24mA
Maximum usable gates Maximum I/O: Megacells metallized SRAM blocks available integration Supports scan test ability Array Bases
HT5F/5G Series
Part Number HT5F068 HT5F084 HT5F100 HT5F128 HT5F164 HT5F208 HT5G100 HT5G128 Max. Usable Gates (40% 7198 11096 15444 25216 41172 66008 Usable Gates (80% 30888 50433
HT5F/5G 0.5mm CMOS High Speed Gate Array
Cell Library
Buffers Inverting, noninverting, tri-state, clock buffer NAND/AND gates NOR/OR gates AOI/OAI gates XNOR/XOR gates Delay cells 2ns, 4ns, 7ns, 10ns Parity generator bits even, bits Flip-flops D-type, T-type, JK-type Multiplexed flip-flops
Latches with set, with clear, with clear, Nor-Latch NAND-latch, scannable latch Adders 1-bit Half, 1-bit Full Decoders 2-to-4, 3-to-8 Multiplexers 2-to-1, 3-to-1, 4-to-1, 5-to-1, 8-to-1 Comparator Miscellaneous Internal pull-up/pull-down, holder, cell
Library
Input pads Inverting, noninverting CMOS, Clock driver with CMOS buffer Clock driver with buffer Output pads 2mA, 4mA, 8mA, 12mA, 16mA, 24mA driving capability Output only, 3-state output, with pull-up/pull-down resistor CMOS level, level with limited slew rate control
Bidirectional pads 2mA, 4mA, 8mA, 12mA, 16mA, 24mA driving capability 3-state output, with pull-up/pull-down resistor CMOS level, level with limited slew rate control
3.3V Library
Input pads Inverting, noninverting CMOS, Clock driver with CMOS buffer Clock driver with buffer Output pads 2mA, 4mA, 8mA, 12mA, 16mA, 24mA driving capability Output only, 3-state output, with pull-up/pull-down resistor CMOS level, level with limited slew rate control
Bidirectional pads 2mA, 4mA, 8mA, 12mA, 16mA, 24mA driving capability 3-state output, with pull-up/pull-down resistor CMOS level, level with limited slew rate control

0.8mm single poly, double metal CMOS technology gate architecture Oper

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