Programmable Serial Interface(Frequency Agile Devices) Mbps-1.5 G
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CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Programmable Serial Interface(Frequency Agile Devices)
Mbps-1.5 Gbps, Gbps serial signaling rate Flexible parallel-to-serial conversion transmit path Flexible serial-to-parallel conversion receive path Multiple selectable loopback/loop-through modes 100k 200k usable gates CPLD logic 240k 480k bits integrated memory 192k 384k bits synchronous asynchronous SRAM bits true Dual-Port FIFO Internal transmit receive PLLs Logic dedicated Spread Aware Transmit FIFO flexible variable phase clocking Differential serial input with internal termination DC-restoration Differential serial output with source matched impedance 160-240 user programmable I/Os AnyVoltI/O interface Programmable 1.8V, 2.5V, 3.3V Multiple standards LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II), HSTL(I-IV), GTL+ Direct interface standard fiber-optic modules Designed drive: fiberoptic modules copper cables circuit board traces backplane links box-to-box links chip-to-chip communication Supported standards: Fibre Channel Gigabit Ethernet ESCON SMPTE Extremely flexible clocking options Four global clocks additional product term clocks Clock polarity every register Carry chain logic fast efficient arithmetic operations compliant (Rev. 2.2)
Note: detailed data sheet "High-Speed data sheet."
JTAG programming interface with boundary scan support High-Speed (HS) Frequency Agile (FA) Programmable Serial Interface(PSITM) versions available
Frequency Agile Mbps-1.5 Gbps serial signaling rate channel eight serial channels available allow: Frequency Agile Redundancy Selectable input output clocking options MultiFramereceive framer provides alignment Bit, byte, half-word, word, multi-word COMMA Full K28.5 detect Single Multi-byte framer byte alignment Low-latency option Skew alignment support multiple bytes offset Serial Built-In-Self-Test (BIST) at-speed link testing Per-channel Link Quality Indicator Analog signal detect Digital signal detect Frequency range detect
High-Speed Features[1]
Gbps/channel serial signaling rate Full Bellcore jitter compliance Power-saving mode serial channels available allow: High-Bandwidth
Redundancy Supported standards: InfiniBand- SONET/SDH OC-48
Development Software
Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog context sensitive editing Active-HDL graphical finite state machine editor Active-HDL post-synthesis timing simulator Architecture Explorer detailed design analysis Static Timing Analyzer critical path analysis Available Windows Supports Cypress programmable logic products
Cypress Semiconductor Corporation Document 38-02044 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised January 2002
Table Quick Reference Selection Guide
High-Speed/SONET/SDH Serial Bandwidth Logic Gate Density 100K 200K Gbps S25G01K100 Gbps S25G02K100 S25G02K200
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Frequency-Agile Serial Bandwidth 0.2-1.5 Gbps P15G04K100 P15G04K200 P15G08K200 0.2-1.5 Gbps
Family Standards Supported
Device SONET/SDH High Speed Frequency Agile S25G01K100 P25G01K100 P15G04K100 P15G04K200 P15G08K200 SONET/SDH (OC-48) Infiniband Fibre Channel Gigabit Ethernet ESCON SMPTE SMPTE
Family General Selection Guide
Device 25G01K100 15G04K100 15G04K200 15G08K200 Typical Gates 46K-144K 46K-144K 92K-288K 92K-288K Macrocells 1536 1536 3072 3072 Cluster memory (Kbits) Channel memory (Kbits) Maximum User Programmable Package Offering 456-BGA (35x35 1.27-mm pitch) 456-BGA (35x35 1.27-mm pitch) 700-BGA (40x40 1.27-mm pitch) (40x40 1.27-mm pitch)
Family Performance Selection Guide
Device 25G01K100 15G04K100 15G04K200 15G08K200 Channels Link Speed Gbps Gbps Gbps Gbps Total Bandwidth Gbps Gbps Gbps 12.0 Gbps fMAX2 (MHz) Logic Speed Pin-to-Pin (ns) Standby ICC[2]
Note: Standby values with utilized, output load, stable inputs.
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GCLK[1:0]
Clock
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
GCTL[3:0]
GCLK[1:0]
Bank
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Serial Signal Bank
Figure Frequency Agile Block Diagram (CYP15G04K100) with Bank Structure
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XCVR CNTRL
Phase Align Buffer
Phase Align Buffer
Phase Align Buffer
Phase Align Buffer
Deserializer
Deserializer
Deserializer
Serializer
Serializer
Serializer
Serializer
Deserializer
Bank
Bank
PSI15G04K100V1 Configuration (Top View)
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
OUTB2- INB2-
OUTB1- INB1OUTB1 INB1+ RXLE LFIAn VCCO VCCO VCCO VCCO VCCP LPEN TXMO DE_0
OUTA2- INA2OUTA2 INA2+ TXCLK RFEN TXMO RXMO DE_1 DE_0 RXCLK
OUTA1- INA1OUTA1 INA1+ MAST SPDS RXMO TXRAT DE_1 REFCL REFCL
OUTD2- IND2OUTD2 IND2+ SDAS BOE_6 INSEL INSEL TXCLK
OUTD1- IND1OUTD1 IND1+ BOE_7 BOE_4 RXCLK INSEL
OUTC2- INC2VCC OUTC2 INC2+ TRSTZ BOE_5 INSEL RFMO
OUTC1- INC1VCC VCCO OUTC1 INC1+ RXCK BOND _ALL LFICn
OUTB2 INB2+ CONFI BOND RXRAT G_DO _INHn DATA BOE_1 BOE_0 RECO BOE_3 BOE_2 NFIG
TXRST BOND TXCKS ST_0 IO6/Lo IO/VR
RXCLK BOND LFIDn ST_1 IO/VR IO/VR IO/VR IO/VR IO/VR
VCCC BISTL FRAM RESET CHAR CCLK IO/VR IO/VR IO/VR MSEL IO/VR IO/VR IO/VR OELE DECM
RXCLK LFIBn
VCCO
VCCO GCLK0
VCCO IO/VR GCTL0 VCCor VCCO VCCO VCCO VCCO VCCO GCTL3 GCLK3 IO/VR GCTL2
IO/VR VCCO VCCO VCCO VCCO VCCO
IO/VR VCCor IO/VR VCCO
VCCPL IO/VR VCCO
VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCor VCCor VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCJT GCTL1 GCLK2 IO/VR IO/VR IO/VR IO/VR IO/VR IO/VR IO/VR IO/VR IO/VR IO/VR GCLK1 IO/VR
Note: Signals appended active signals.
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Functional Description
Programmable Serial Interface (PSI) family point-topoint point-to-multipoint programmable communications building block allowing manipulation transfer data over high-speed serial links signaling speeds ranging from Mbps Gbps serial link. family designed combine high speed, predictable timing, high density, power, ease-of-use complex programmable logic devices (CPLDs) with serializing/deserializing (SERDES) capability high-speed serial transceivers. family divided into groups: High-Speed Frequency Agile PSI. Both groups have unique transceiver characteristics that define specific transceiver block operation given device. architecture device based logic block clusters (LBC) serial transceiver blocks that connected horizontal vertical routing channels. Each features eight individual logic blocks (LB) macrocells cluster memory blocks. Adjacent each channel memory block, which externally accessible through interface. Each transmit channel transceiver accepts parallel characters, encodes each character transport converts serial data. Each receive channel accepts serial data converts parallel data, decoding data into characters presents these characters routing channels unit. Frequency Agile Devices transceiver operation Frequency Agile Programmable Serial Interface devices self-contained single block. separate transmit receive PLLs clock data recovery (CDR) unit flexible clocking. transmit channel accepts 8-bit unencoded 10-bit encoded input character from routing channels passes character elasticity buffer. This character then serialized output dual differential transmission-line drivers required bit-rate. receive channel accepts serial bit-stream from differential line receivers. This bit-stream deserialized 8-bit unencoded 10-bit encoded character presented routing channels device. block also features Built-In Self Test (BIST) mode simplified design debugging. Global Routing Description routing architecture block device made horizontal vertical (H&V) routing channels.
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
These routing channels allow signals move among I/Os, logic blocks memories. addition horizontal vertical routing channels that interconnect banks, channel memory blocks, transceiver blocks logic block clusters, each contains Programmable Interconnect Matrix (PIMTM), which used route signals among logic blocks cluster memory blocks LBC. Figure block diagram routing channels that interface within architecture. exactly same every member family. Transceiver Block Each transceiver block given device will have serializer transmit path deserializer receive path operating speed from Mbps Gbps. transceiver block interfaces routing channels device through highly configurable datapath cells. specific architecture operation transceiver blocks please refer Serial Transceiver Operation section (page 17). Frequency Agile Transceiver Blocks Frequency Agile devices include four eight transceiver blocks operating Gbps channel. They same reference clock. internal interfacing transceiver blocks device occur through port definition transceiver block. internal signals their definition described Signal Description section (page 62). Standard Datapath Cell Figure block diagram datapath cell. datapath cell contains three-state transmit buffer, receive buffer, register that configured transmit receive register. transceiver enable (TE) selected from four global control signals from Output Control Channel (OCC) signals. transmit enable configured always enabled always disabled controlled remaining inputs mux. selection done that includes inputs. global clocks selected clock datapath cell register. clock output input clock polarity that allows transmit/receive register clocked either edge clock.
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CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Registered
From Output
Receive
Routing Channel
Output Control Channel
Global Control Signals
Global Clock Signals
Register Receive
Transmit
Register Enable Clock Polarity
Signal
Clock
Register Reset
Figure Block Diagram Standard Datapath Cell Logic Block Cluster (LBC) architecture consists several logic block clusters, each which have Logic Blocks (LB) cluster memory blocks connected Programmable Interconnect Matrix (PIM) shown Figure Each cluster memory block consists 8-Kbit single-port RAM, which configurable synchronous asynchronous. cluster memory blocks cascaded with other cluster memory blocks within same well other LBCs implement larger memory functions. cluster memory block specifically utilized designer, Cypress's Warp® software automatically implement large blocks logic. LBCs interface with each other horizontal vertical routing channels.
Block
Cluster Memory Block
Cluster
Cluster Memory Block
Channel Memory Block
Channel memory outputs drive dedicated tracks horizontal vertical routing channels
Block
H-to-V V-to-H
inputs from cells drive dedicated tracks horizontal vertical routing channels
Figure Routing Interface
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Clock Inputs GCLK[3:0]
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Cluster Memory
Cluster Memory
Carry Chain
Inputs From Horizontal Routing Channel
Inputs From Vertical Routing Channel
Outputs Horizontal Vertical cluster-to-channel PIMs
Figure Logic Block Cluster Diagram Logic Block (LB) logic block basic building block architecture. consists product term array, intelligent productterm allocator, macrocells. Product Term Array Each logic block features programmable product term array. This array accepts inputs from PIM. These inputs originate from device pins macrocell feedbacks well cluster memory channel memory feedbacks. Active active HIGH versions each these inputs generated create full 72-input field. product terms array created from inputs. product terms, general-purpose macrocells logic block. remaining three product terms logic block used asynchronous asynchronous reset product terms. final product term Product Term clock (PTCLK) shared macrocells within logic block. Product Term Allocator Through product term allocator, Warp software automatically distributes product terms needed among macrocells logic block. product term allocator provides important capabilities without affecting performance: product term steering product term sharing. Product Term Steering Product term steering process assigning product terms macrocells needed. example, macrocell requires product terms while another needs just three, product term allocator will "steer" product terms macrocell three other. devices, product terms steered individual basis. number between product terms steered macrocell. Product Term Sharing Product term sharing process using same product term among multiple macrocells. example, more than function more product terms equation that common other functions, those product terms only created once. product term allocator allows sharing across groups four macrocells variable fashion. software automatically takes advantage this capability that user does have intervene. Note that neither product term sharing product term steering have effect speed product. steering sharing configurations have been incorporated timing specifications devices.
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Macrocell Within each logic block there macrocells. Each macrocell accepts product terms from product term array. these product terms output either registered combinatorial mode. Figure displays block diagram macrocell. register asynchronously preset asynchronously reset macrocell level with separate preset reset product terms. Each these product terms features programmable polarity. This allows registers preset reset based expression expression. gate macrocell allows many different types equations realized. used polarity implement true complement form equation product term array toggle turn flip-flop into flip-flop. carry-chain input allows additional flexibility implementation different types logic. macrocell utilize carry chain logic implement adders, subtractors, magnitude comparators, parity tree, even generic logic. output macrocell either registered combinatorial. Carry Chain Logic macrocell features carry chain logic, which used fast efficient implementation arithmetic operations. carry logic connects macrocells logic blocks total macrocells. Effective data path operations imCarry (from macrocell n-1)
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plemented through carry-in arithmetic, which drives through circuit quickly. Figure shows that carry chain logic within macrocell consists product terms (CPT0 CPT1) from input carry-in carry logic. inputs carry chain connected directly product terms PTA. output carry chain generates carry-out next macrocell logic block well local carry input that connected input input mux. Carry-in configuration inputs gate. This gate provides method segmenting carry chain macrocell logic block. Macrocell Clocks Clocking register highly flexible. Four global synchronous clocks (GCLK[3:0]) Product Term clock (PTCLK) available each macrocell register. Furthermore, clock polarity within each macrocell allows register clocked rising falling edge (see macrocell diagram Figure PRESET/RESET Configurations macrocell register asynchronously preset reset using PRESET RESET mux. Both signals active high controlled either Preset/Reset product terms (PRC[1:0] Figure GND. situations where PRESET RESET active same time, RESET takes priority over PRESET.
PRESET
Carry Chain CPT0 CPT1
Input
Output
PSET
FROM Clock GCLK[3:0] PTCLK Clock Polarity
PRC[1:0]
Carry macrocell n+1)
RESET
Figure Macrocell
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Embedded Memory Each member family contains types embedded memory blocks. channel memory block placed intersection horizontal vertical routing channels. Each channel memory block 4096 bits size configured asynchronous synchronous Dual-Port RAM, Single-Port RAM, Read-Only memory (ROM), synchronous FIFO memory. memory organization configurable 4Kx1, 2Kx2, 1Kx4 512x8. second type memory block located within each referred cluster memory block. Each contains cluster memory blocks that 8192 bits size. Similar channel memory blocks, cluster memory blocks configured 8Kx1, 4Kx2, 2Kx4 1Kx8 configured either asynchronous synchronous Single-Port ROM. Cluster Memory Each logic block cluster device contains 8192bit cluster memory blocks. Figure block diagram cluster memory block interface cluster memory block cluster PIM. output cluster memory block optionally registered perform synchronous pipelining register asynchronous read write operations. output registers contain asynchronous RESET, which used type sequential logic circuits (e.g., state machines) There four global clocks (GCLK[3:0]) local clock available input output registers. local clock input registers independent used output registers. local clock generated user-design macrocell comes from
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Cluster Memory Initialization cluster memory powers undefined state, user-defined known state during configuration. facilitate look-up-table (LUT) logic applications, cluster memory blocks initialized with given data when device configured power-up. applications, user cannot write memory blocks. Channel Memory architecture includes embedded memory block each crossing point horizontal vertical routing channels. channel memory 4096-bit embedded memory block that configured asynchronous synchronous Single-Port RAM, Dual-Port RAM, ROM, synchronous FIFO memory. Data, address, control inputs channel memory driven from horizontal vertical routing channels. data FIFO logic outputs drive dedicated tracks horizontal vertical routing channels. clocks channel memory block selected from four global clocks inputs from horizontal vertical channels. clock muxes also include polarity each clock that user choose inverted clock. Dual-Port (Channel Memory) Configuration Each port distinct address inputs, well separate data control inputs that accessed simultaneously. inputs Dual-Port memory driven from horizontal vertical routing channels. data outputs drive dedicated tracks routing channels. interface routing such that Port Dual-Port interfaces primarily with horizontal routing channel Port interfaces primarily with vertical routing channel.
DIN[7:0]
Write Control Logic
ADDR[12:0]
Decode (1024 Rows)
Write Pulse
Cluster
GCLK[3:0] Local
1024x8 Asynchronous SRAM
DOUT[7:0]
Read Control Logic
RESET GCLK[3:0] Local
Figure Block Diagram Cluster Memory Block
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clocks each port Dual-Port configuration selected from four global clocks local clocks. local clock sourced from horizontal channel other from vertical channel. data outputs dual-port memory also registered. Clocks output registers also selected from four global clocks local clocks. clock polarity port allows true complement polarity input output clocking purposes. Arbitration Dual-Port configuration Channel Memory Block provides arbitration when both ports access same address same time. Depending memory operation being attempted, port always gets priority. Table details which port gets priority read write operations. active-LOW `Address Match' signal generated when address collision occurs. Table Arbitration Result: Address Match Signal Becomes Active Result Port Port Arbitration Read Write Read Read arbitration required Port gets priority Comment Both ports read same time Port requests first then will read current data. output will then change newly written data Port Port requests first then will read current data. output will then change newly written data Port Port blocked until Port finished writing
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
local clock sourced from horizontal channel other from vertical channel. data outputs from read port FIFO also registered. clock polarity port allows using true complement polarity read write operations. write operation controlled clock write enable pin. read operation controlled clock read enable pin. enable pins sourced from horizontal vertical channels. Channel Memory Initialization channel memory powers undefined state, user-defined known state during configuration. facilitate look-up-table (LUT) logic applications, channel memory blocks initialized with given data when device configured power applications, user cannot write memory blocks. Channel Memory Routing Interface Similar outputs, channel memory blocks feature dedicated tracks horizontal vertical routing channels data outputs flag outputs, shown Figure This allows channel memory blocks expanded easily. These dedicated lines routed pins chip outputs other logic block clusters used logic equations.
channel memory inputs driven from routing channels
Read
Write
Port gets priority
4096-bit Dual-Port Array
Configurable Async/Sync Dual-Port Sync FIFO Configurable 4Kx1, 2Kx2, 1Kx4 512x8 block sizes
Global Clock Signals
Write
Write
Port gets priority
GCLK[3:0]
Vertical Channel
FIFO (Channel Memory) Configuration channel memory blocks also configurable synchronous FIFO RAM. FIFO mode operation, channel memory block supports normal FIFO operations without general-purpose logic resources device. FIFO block contains necessary FIFO flag logic, including read write address pointers. FIFO flags include empty/full flag (EF), half-full flag (HF), programmable almost-empty/full (PAEF) flag output. FIFO configuration ability perform simultaneous read write operations using separate clocks. These clocks tied together single operation independently asynchronous read/write (w.r.t. each other) applications. data control inputs FIFO block driven from horizontal vertical routing channels. data flag outputs driven onto dedicated routing tracks both horizontal vertical routing channels. This allows FIFO blocks expanded using multiple FIFO blocks same horizontal vertical routing channel without speed penalty. FIFO mode, write read ports controlled separate clock enable signals. clocks each port selected from four global clocks local clocks.
channel memory outputs drive dedicated tracks routing channels
Horizontal Channel
Figure Block Diagram Channel Memory Block Banks interfaces horizontal vertical routing channels pins through banks. There several banks device shown Figure I/Os from bank located same section package layout convenience. There kinds banks; fixed-signal banks user-programmable banks. first fixed-signal bank Serial Signal Bank. This bank includes differential serial data transmission receive signals. second bank Transceiver Control Bank. This bank includes static signal pins required configuration operation transceiver blocks each devices.
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Each device several types user-programmable banks. Table indicates availability each type programmable bank device. Supported standards each bank addressed appropriate VREF VCCIO voltages. VREF VCCIO pins bank must connected same VREF VCCIO voltage respectively. This requirement restricts number standards supported bank given time. also dictates standard used GCTL[3:0] pins. architecture defining each programmable bank consists several cells, where each cell contains input/output register, output enable register, programmable slew rate control, programmable hold control logic. Each cell drives output device; cell also supplies input device that connects dedicated track associated routing channel. There four dedicated inputs (GCTL[3:0]) that used Global Control Signals available every cell. These global control signals used output enables, register resets register clock enables shown Figure
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Table Standards Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL 1.15 1.15 0.68 0.68 0.68 0.68 1.35 1.35 VREF Min. Max. VCCIO 3.3V 3.3V 3.0V 2.5V 1.8V 3.3V 3.3V 3.3V 2.5V 2.5V 1.5V 1.5V 1.5V 1.5V Termination Voltage (VTT) 1.25 1.25 0.75 0.75
Bank
Bank
Bank
Serial Bank
HSTL
Bank
Bank
Bank
Figure Bank Block Diagram
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XCVR CNTL
Page
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Registered
From Output
Input
Routing Channel
Output Control Channel
Global Control Signals
Global Clock Signals
Register Input
Output
Register Enable Clock Polarity
Hold
Clock
Slew Rate Control
Register Reset
Figure Block Diagram Cell Cell Figure block diagram cell. cell contains three-state input buffer, output buffer, register that configured input output register. output buffer slew rate control option that used configure output slower slew rate. input device output each configured registered combinatorial, however only path configured registered given design. output enable selected from four global control signals from Output Control Channel (OCC) signals. output enable configured always enabled always disabled, controlled remaining inputs mux. selection done that includes inputs. global clocks selected clock cell register. clock output input clock polarity that allows input/output register clocked either edge clock. Slew Rate Control output buffer slew rate control option. This allows ouput buffer slew fast rate V/ns) slow rate V/ns). I/Os default fast slew rate. designs concerned with meeting emissions standards slow edge provides lower system noise. designs requiring very high performance fast edge rate provides maximum system performance. Programmable Hold each pin, user-programmable bus-hold included. Bus-hold, which improved version popular internal Document 38-02044 Page pull-up resistor, weak latch connected that does degrade device's performance. latch, bus-hold maintains last state when placed high-impedance state, thus reducing system noise bus-interface applications. Bus-hold additionally allows unused device pins remain unconnected board, which particularly useful during prototyping designers route signals device without cutting trace connections GND. more information, application note "Understanding Bus-Hold Feature Cypress CPLDs." Clocks Frequency Agile devices have four dedicated clock input pins (GCLK[3:0]) accept system clocks. these clocks (GCLK[0]) selected drive on-chip Phase-Locked Loop (PLL) frequency modulation (see Figure details). global clock tree Frequency Agile devices driven combination dedicated clock pins and/or PLL-derived clocks. global clock tree consists four global clocks that every macrocell, memory block, cell. Clock Tree Distribution global clock tree performs primary functions. First, clock tree generates four global clocks multiplexing four dedicated clocks from package pins four driven clocks. Second, clock tree distributes four global clocks every cluster, channel memory, block die. global clock tree designed such that clock skew minimized while maintaining acceptable clock delay.
Spread AwarePLL Each device family features on-chip designed using Spread Awaretechnology applications. general, PLLs used implement time-divisionmultiplex circuits achieve higher performance with fewer device resources. example, system that operates 32-bit data path that runs implemented with 16-bit circuitry that runs internally MHz. PLLs also used take advantage positioning internally generated clock edges shift performance towards improved setup, hold clock-to-out times. There several frequency multiply (X1, divide (/1, /16) options available create wide range clock frequencies from single clock input (GCLK[0]). increased flexibility, there seven phase shifting options which allow clock skew/de-skew 45°, 90°, 135°, 180°, 225°, 270° 315°. Spread Aware feature refers ability track spread-spectrum input clock such that spread seen output clock with staying locked. total amount spread input clock should limited 0.6%
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fundamental frequency. Spread Aware feature supported only with multiply options. Voltage Controlled Oscillator (VCO), core designed operate within frequency range MHz. Hence, multiply option combined with input (GCLK[0]) frequency should selected such that this operating frequency requirement met. This demonstrated Table (columns Another feature this ability drive output clock (INTCLK) chip clock other devices board, shown Figure below. This off-chip clock half frequency output clock through register (I/O register macrocell register). This also used board deskewing purpose driving output clock off-chip, routing other devices board feeding back PLL's external feedback input (GCLK[1]). When this feature used, only limited multiply, divide phase shift options used. Table describes valid multiply divide options that used without external feedback. Table describes valid multiply divide options that used with external feedback.
off-chip signal (external feedback) INTCLK0, INTCLK1, INTCLK2, INTCLK3
Register
Send global clock chip GCLK1
Normal signal path Lock Detect/IO Clock Tree Delay
Phase selection
Divide 1-6,8,16 INTCLK0 GCLK0
Lock
Phase selection
Divide 1-6,8,16 INTCLK1 GCLK1
GCLK0
Source Clock
Phase selection
1350 1800 2250 2700
Divide 1-6,8,16 INTCLK2 TXCLK
3150
Phase selection
Divide 1-6,8,16 INTCLK3 RXCLK
GCLK[1:0]
Figure Block Diagram Spread Aware CYS25G01K100
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INTCLK0, INTCLK1, INTCLK2, INTCLK3
Register
Send global clock chip INTCLK1
Normal signal path Lock Detect/IO Clock Tree Delay
Phase selection
Divide 1-6,8,16 INTCLK0 GCLK0
Lock
Phase selection
Divide 1-6,8,16 INTCLK1 RXCLK
Source Clock
Phase selection
1350 1800 2250 2700 3150
Divide 1-6,8,16 INTCLK2 TXCLK
Phase selection
Divide 1-6,8,16 INTCLK3 RXCLK_B
GCLK[0]
Figure Block Diagram Spread Aware CYS25G02K100
Table Multiply Divide Options-without INTCLK1 Feedback Input Frequency (GCLK[0]) fPLLI (MHz) 12.5-25 25-33 33-50 50-66 66-100 100-133 Valid Multiply Options Value Output Frequency (MHz) 100-200 200-266 100-133 133-200 200-266 100-133 133-200 200-266 100-133 Value 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, Valid Divide Options Output Frequency (INTCLK[3:0]) fPLLO (MHz) 6.25-200 12.5-266 6.25-133 8.33-200 12.5-266 6.25-133 8.3-200 12.5-266 6.25-133 Off-chip Clock Frequency 3.12-100 6.25-133 3.12-66 4.16-100 6.25-133 3.12-66 4.16-100 6.25-133 3.12-66
Table Multiply Divide Options-with External Feedback Valid Multiply Options Input (GCLK) Frequency fPLLI (MHz) 50-66 66-100 100-133 Value Output Frequency (MHz) 100-133 133-200 200-266 Value Valid Divide Options Output (INTCLK) Frequency fPLLO (MHz) 100-133 133-200 200-266 Off-chip Clock Frequency 50-66 66-100 100-133
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Table describes valid phase shift options that used with without external feedback. Table Phase Shift Options- with without INTCLK1 Feedback Without External Feedback 0°,45°, 90°, 135°, 180°, 225°, 270°, 315° With External Feedback
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Table example effect available divide phase shift options output MHz. also shows effect division duty cycle resultant clock. Note that duty cycle 50-50 when output divided even number. Also note that phase shift applies output divided output
Table Timing Clock Phases Divide Options Output Frequency Divide Factor Period (ns) Duty Cycle% 40-60 33-67 40-60 (ns) (ns) (ns) 135° (ns) 180° (ns) 225° (ns) 270° (ns) 315° (ns)
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Timing Model important feature family simplicity timing. combinatorial registered/synchronous delays worst case system performance static shown specs section) long data routed through same horizontal vertical channels. Figure illustrates true timing model 200-MHz devices. synchronous clocking macrocells, delay incurred from macrocell clock macrocell clock separate Logic Blocks within same cluster, well separate Logic Blocks within different clusters. This shown tSCS tSCS2 Figure combinatorial paths, input output (from corner corner device), incurs worst-case delay 100K gate regardless amount logic which horizontal vertical channels used. This shown Figure
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synchronous systems, input set-up time output macrocell register clock-to-output time shown parameters tMCS tMCCO shown Figure These measurements output synchronous clock, regardless logic placement. features: dedicated delays penalty using 0-16 product terms added delay steering product terms added delay sharing product terms output bypass delays simple timing model family eliminates unexpected performance penalties.
tSCS
GCLK[3:0]
Channel
Channel
Channel
Channel
Cluster
Cluster
SRAM
tMCS
Cluster
Cluster
Cluster
Cluster
SRAM
GCLK[3:0]
tSCS2
Channel
Channel
Channel
Channel
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
GCLK[3:0]
Channel
Channel
Channel
Channel
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
tMCCO
Figure Timing Model 100K gate Devices
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Serial Transceiver Operation
transceiver block highly configurable device designed support reliable transfer large quantities data, using high-speed serial links, from multiple sources multiple destinations. This device supports four singlebyte single-character channels that combined support transfer wider buses. Frequency Agile Transmit Data Path Operating Modes transmit path transceiver block supports four character-wide data paths. These data paths used multiple operating modes controlled TXMODE[1:0] inputs. Input Register Within these operating modes, bits Input Register each channel support different assignments, based whether character unencoded, encoded with control bits, encoded with three control bits. These assignments shown Table Table Input Register Assignments Encoded Signal Name TXDx[0] (LSB) TXDx[1] TXDx[2] TXDx[3] TXDx[4] TXDx[5] TXDx[6] TXDx[7] TXCTx[0] TXCTx[1] (MSB) Unencoded DINx[0] DINx[1] DINx[2] DINx[3] DINx[4] DINx[5] DINx[6] DINx[7] DINx[8] DINx[9] 2-bit Control TXDx[0] TXDx[1] TXDx[2] TXDx[3] TXDx[4] TXDx[5] TXDx[6] TXDx[7] TXCTx[0] TXCTx[1]
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
absorb clock phase differences between presently selected input clock internal character clock. Initialization these phase-align buffers takes place when TXRST input sampled TXCLKA. When TXRST returned HIGH, present input clock phase relative REFCLK set. TXRST asynchronous input, sampled internally synchronize internal transmit path state machines. TXRST must sampled minimum consecutive TXCLKA clocks ensure reset operation initiated correctly channels. Once set, TXCLKA allowed skew time half character period either direction relative REFCLK; i.e., ±180°. This time shift allows delay paths character clocks (relative REFLCK) change operating voltage temperature, while affecting design operation. phase offset, between initialized location input clock REFCLK, exceeds skew-handling capabilities Phase-Align Buffer, error reported associated TXPERx output. This output will indicate continuous error until Phase-Align Buffer reset. While error remains active, transmitter associated channel will output continuous C0.7 character indicate remote receiver that error condition present link. specific transmit modes also possible reset Phase-Align Buffers individually with minimal disruption serial data stream. When transmit interface configured generation atomic Word Sync Sequences (TXMODE[1] Phase-Align Buffer error present, transmission Word Sync Sequence will re-center buffer clear error condition. NOTE: more K28.5 characters added lost from data stream during this reset operation. When used with non-Cypress devices that require complete 16character Word Sync Sequence proper receive Elasticity Buffer alignment, recommend that sequence followed second Word Sync Sequence ensure proper operation. Encoder character, received from input register phase-align buffer then passed Encoder logic. This block interprets each character associated control bits, outputs 10-bit transmission character. Depending configured operating mode, generated transmission character 10-bit pre-encoded character accepted input register 10-bit equivalent 8-bit Data character accepted input register 10-bit equivalent 8-bit Special Character code accepted input register 10-bit equivalent C0.7 character PhaseAlign Buffer overflow underflow error present character that part 511-character BIST sequence K28.5 character generated individual character part 16-character Word Sync Sequence. selection specific characters generated controlled TXMODE[1:0], TXCTx[1:0], TXDx[7:0] inputs each character.
Each input register captures minimum eight data bits control bits each input clock cycle. When encoder bypassed, control bits part pre-encoded 10-bit character. When Encoder enabled (TXMODE[1] TXCTx[1:0] bits interpreted along with associated TXDx[7:0] character generate specific 10-bit transmission character. Phase-Align Buffer Data from input registers passed either encoder associated Phase-Align buffer. When transmit paths operated synchronous REFCLK (TXCKSEL TXRATE LOW), Phase-Align Buffers bypassed data passed directly encoder blocks reduce latency. When Input-Register clock with uncontrolled phase relationship REFCLK selected (TXCLSEL data captured both edges REFCLK (TXRATE HIGH), Phase-Align Buffers enabled. These buffers used
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Data Encoding data, received directly from Transmit Input Register, seldom form suitable transmission across serial link. characters must usually processed transformed guarantee minimum transition density allow serial receive extract clock from data stream) DC-balance signaling prevent baseline wander) run-length limits serial data limit bandwidth link) remote receiver determining correct character boundaries (framing). When Encoder enabled (TXMODE[1] characters transmitted converted from Data Special Character codes 10-bit transmission characters selected their respective TXCTx[1:0] SCSEL inputs), using integrated 8B/10B encoder. When directed encode character Special Character code, encoded using Special Character encoding rules listed Table When directed encode character Data character, encoded using Data Character encoding rules Table 8B/10B encoder standards compliant with ANSI/NCITS X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit Ethernet), IBM® ESCON® FICONchannels, AForum standards data transport. Many Special Character codes listed Table generated more than input character. transceiver block designed support independent (but nonoverlapping) Special Character code tables. This allows transceiver block operate mixed environments with other transceiver blocks using enhanced Cypress command code reduced command sets other non-Cypress devices. Even when used environment that normally uses non-Cypress Special Character codes, selective Cypress command codes permit operation where running disparity error handling must managed. Following conversion each input character from bits 10-bit transmission character, passed Transmit Shifter shifted first, required ANSI IEEE standards 8B/10B coded serial data streams. Transmit Modes operating mode transmit path through TXMODE[1:0] inputs. These three-level select inputs allow nine transmit modes selected. Within each these operating modes, actual characters generated Encoder logic block also controlled both these other static dynamic control signals. transmit modes listed Table encoded modes Modes through support multiple encoding tables. These encoding tables vary specific combinations TXCTx[1] TXCTx[0] that used control generation data control characters. These multiple encoding forms allow maximum flexibility interfacing legacy applications, while also supporting numerous extensions capabilities. Mode TXMODE [1:0] Mode Number
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Table Transmit Operating Modes Operating Mode
Word Sync Sequence Support None None None Atomic None None None Word Sync Special Character Word Sync Special Character Word Sync Special Character Word Sync Special Character
TXCTx Function Encoder Bypass Reserved test Reserved test Encoder Control Encoder Control Encoder Control
Atomic Atomic
Interruptible
Encoder Control Encoder Control Encoder Control
Interruptible Interruptible
Mode 0-Encoder Bypass When Encoder bypassed, character captured TXDx[7:0] TXCTx[1:0] inputs passed directly transmit shifter without modification. With encoder bypassed, TXCTx[1:0] inputs considered part data character perform control function that would otherwise modify interpretation TXDx[7:0] bits. usage mapping these control bits when Encoder bypassed shown Table Table Encoder Bypass Mode (TXMODE[1:0] Signal Name TXDx[0] (LSB) TXDx[1] TXDx[2] TXDx[3] TXDx[4] TXDx[5] TXDx[6] TXDx[7] TXCTx[0] TXCTx[1] (MSB) Weight
Name a[4]
this mode SCSEL input interpreted. clocking modes interpret data same, with internal linking between channels. Modes 2-Factory Test Modes These modes enable specific factory test configurations. They considered normal operating modes device.
Note: shifted first.
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configuration into these test modes will damage device. Mode 3-Atomic Word Sync Control Special Codes When configured Mode TXCTx[1:0] data control inputs captured. These bits combine control interpretation TXDx[7:0] bits characters generated them. These bits interpreted listed Table Table Modes Encoding TXCTx[1] TXCTx[0]
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Mode 4-Atomic Word Sync Control Word Sync Sequence Generation When configured Mode TXCTx[1:0] data control inputs captured. These bits combine control interpretation TXDx[7:0] bits characters generated them. These bits interpreted listed Table Table Modes Encoding TXCTx[1] TXCTx[0]
Characters Generated Encoded data character K28.5 fill character Special character code
Characters Generated Encoded data character K28.5 fill character 16-character Word Sync Sequence
Mode 5-Atomic Word Sync addition standard character encodings, both with without atomic Word Sync Sequence generation, additional encoding mappings controlled Channel Bonding selection made through RXMODE[1:0] inputs. non-bonded operation, TXCTx[1:0] inputs each channel control characters generated that channel. specific characters generated these bits listed Table Table Modes Encoding, Non-Bonded TXCTx[1] TXCTx[0]
Word Sync Sequence When TXCTx[1:0] 16-character sequence K28.5 characters, known Word Sync Sequence, generated associated channel. This sequence K28.5 characters start with either positive negative disparity K28.5 determined current running disparity 8B/10B coding rules). disparity second third K28.5 characters this sequence reversed from what normal 8B/10B coding rules would generate. remaining K28.5 characters sequence follow 8B/10B coding rules. disparity generated K28.5 characters this sequence would follow pattern either ++--+-+-+-+-+-+- --++-+-+-+-+-+-+. When TXMODE[1] (open, modes generation this character sequence atomic (non-interruptible) operation. Once been successfully started, cannot stopped until characters have been generated. content associated input register(s) ignored duration this 16-character sequence. this sequence, TXCTx[1:0] condition sampled again, sequence restarts remains uninterruptible following character clocks. When TXMODE[1] modes generation Word Sync Sequence becomes interruptible operation. Mode this sequence started soon TXCTx[1:0] condition detected channel. order sequence continue that channel, TXCTx[1:0] inputs must sampled remaining characters sequence. time sample period exists where TXCTx[1:0] Word Sync Sequence terminated, character representing associated data control bits generated Encoder. This resets Word Sync Sequence state machine such that will start beginning sequence next occurrence TXCTx[1:0] When TXCKSEL input registers four transmit channels clocked REFCLK [36]. When TXCKSEL input registers four transmit channels clocked with TXCLKA. NOTE: When operated configuration where receive channels bonded together, TXCKSEL must either HIGH (not MID) ensure that associated characters transmitted same character cycle. Document 38-02044
Characters Generated Encoded data character K28.5 fill character Special character code 16-character Word Sync Sequence
Mode also capability generating Atomic Word Sync Sequence. sequence started, TXCTx[1:0] inputs must both sampled HIGH. With exception combination control bits used initiate sequence, generation operation this Word Sync Sequence same that documented Mode additional encoding maps provided when receive channel bonding enabled. When dual-channel bonding enabled (RXMODE[1] transceiver block configured such that channels bonded together form two-character-wide path, channels bonded together form second two-character-wide path. When operated this two-channel bonded mode, TXCTA[0] TXCTB[0] inputs control interpretation data both channels, while TXCTC[0] TXCTD[0] inputs control interpretation data both channels. characters each half these bonded channels controlled associated TXCTx[1] bit. specific characters generated these control combinations listed Table Note especially that time TXCTB[0] sampled HIGH, both channels start generating Atomic Word Sync Sequence, regardless Page
Table Modes Dual-Channel Bonded TXCTA[1] TXCTA[0] TXCTA[1] TXCTA[0]
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Table Modes Quad-Channel Bonded
Characters Generated Encoded data character channel K28.5 fill character channel Special character code channel 16-character word sync channel Encoded data character channel K28.5 fill character channel Special character code channel 16-character word sync channel
Characters Generated Encoded data character channel K28.5 fill character channel Special character code channel 16-character word sync channel Encoded data character channel K28.5 fill character channel Special character code channel 16-character word sync channel Encoded data character channel K28.5 fill character channel Special character code channel 16-character word sync channel Encoded data character channel K28.5 fill character channel Special character code channel 16-character word sync channel
state other bits input registers. similar fashion, anytime TXCTD[0] sampled HIGH, both channels start generation Atomic Word Sync Sequence. When RXMODE[1] transceiver block configured quad-channel bonding, such that channels bonded together form four-character-wide path. When operated this mode, TXCTA[0] TXCTB[0] inputs control interpretation data four channels. characters generated these bonded channels controlled associated TXCTx[1] bit. specific characters generated these bits listed Table Unlike dual-channel modes, when four channels bonded together, TXCTC[0] TXCTD[0] inputs interpreted. Transmit BIST transmitter interfaces contain internal pattern generators that used validate both device link operation. These generators enabled associated BOE[x] signals listed Table (when BISTLE latch enable input HIGH). When enabled, register associated transmit channel becomes signature pattern generator logically converting Linear Feedback Shift Register (LFSR). This LFSR generates 511-character sequence that includes Data Special Character codes, including explicit violation symbols. This provides predictable pseudo-random sequence that matched identical LFSR attached Receiver(s).
When BISTLE signal HIGH, BOE[x] input that enables BIST generator associated transmit channel BIST checker associated receive channel). When BISTLE returns LOW, values BOE[x] signals captured BIST Enable Latch. These values remain BIST Enable Latch until BISTLE returned high open latch again. captured signals BIST Enable Latch HIGH (i.e., BIST disabled) following device reset (TRSTZ sampled LOW). data data-control information present associated TXDx[7:0] TXCTx[1:0] inputs ignored when BIST active that channel. receive channels configured common clock operation (RXCKSEL MID) each pass preceded 16-character Word Sync Sequence allow Elasticity Buffer alignment management clock-frequency variations.
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Serial Output Drivers serial interface Output Drivers make high-performance differential (Current Mode Logic) provide source-matched driver transmission lines. These drivers accept data from Transmit Shifters. These outputs have signal swings equivalent that standard PECL drivers, capable driving AC-coupled optical modules AC-coupled transmission lines. When configured local loopback (LPEN HIGH), output drivers enabled ports configured drive static differential logic-1. Each output enabled disabled separately through BOE[7:0] inputs, controlled OELE latch-enable signal. When OELE HIGH, signals present BOE[7:0] inputs passed through Serial Output Enable latch control serial output drivers. BOE[7:0] input associated with specific OUTxy± driver listed Table Table Output Enable, BIST, Receive Channel Enable Signal Output Controlled (OELE) OUTD2± OUTD1± OUTC2± OUTC1± OUTB2± OUTB1± OUTA2± OUTA1± BIST Channel Enable (BISTLE) Transmit Receive Transmit Receive Transmit Receive Transmit Receive Receive Channel Enable (RXLE) Receive Receive Receive Receive
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SPDSEL three-level select (ternary) input that selects three operating ranges serial data outputs inputs. operating serial signaling-rate allowable range REFCLK frequencies listed Table Table Operating Speed Settings REFCLK Frequency (MHz) 10-20 20-40 20-40 40-80 40-75 80-150 800-1500 400-800 Signaling Rate (MBaud) 200-400
SPDSEL (Open) HIGH
TXRATE
Input BOE[7] BOE[6] BOE[5] BOE[4] BOE[3] BOE[2] BOE[1] BOE[0]
REFCLK± input non-standard input. implemented differential input with each input internally biased VCC/2. REFCLK+ input connected TTL, LVTTL, LVCMOS clock source, input signal recognized when passes through internally biased reference point. When both REFCLK+ REFCLK- inputs connected, clock source must differential clock. This either differential LVPECL clock that AC-coupled, differential LVTTL LVCMOS clock. connecting REFCLK- input external voltage source resistive voltage divider, possible adjust reference point REFCLK+ input alternate logic levels. When doing necessary ensure that 0V-differential crossing point remain within parametric range supported input.
Frequency Agile Receive Data Path
Serial Line Receivers differential line receivers, INx1± INx2±, available each channel accepting serial data streams. active line receiver channel selected using associated INSELx input. serial line receiver inputs differential, accommodate wire interconnect filtering losses transmission line attenuation greater than (VDIF peak-to-peak differential) AC-coupled +3.3V powered fiber-optic interface modules (any ECL/PECL logic family, limited 100K PECL) AC-coupled powered optical modules. common-mode tolerance these line receivers accommodates wide range signal termination voltages. Each receiver provides internal DC-restoration, center receiver's common mode range, AC-coupled signals. local loopback input (LPEN) allows serial transmit data outputs routed internally back Clock Data Recovery circuit associated with each channel. When configured local loopback, transmit serial driver outputs forced output differential logic-1. This prevents local diagnostic patterns from being broadcast attached remote receivers. Signal Detect Link Fault Each selected Line Receiver (i.e., that routed Clock Data Recovery PLL) simultaneously monitored analog amplitude Page
When OELE HIGH BOE[x] HIGH, associated serial driver enabled drive attached transmission line. When OELE HIGH BOE[x] LOW, associated driver disabled internally configured minimum power dissipation. both outputs channel this disabled state, associated internal logic that channel also configured lowest power operation. When OELE returns LOW, values present BOE[7:0] inputs latched Output Enable Latch, remain there until OELE returns HIGH opened latch again. Note: When disabled transmit channel (i.e., both outputs disabled) re-enabled, data serial outputs meet timing specifications Transmit Clock Multiplier Transmit Clock Multiplier accepts character-rate half-character-rate external clock REFCLK input, multiples that clock selected TXRATE) generate bit-rate clock transmit shifter. also provides character-rate clock used transmit paths. clock multiplier accept REFCLK input between MHz, however, this clock range limited operating mode transceiver block clock multiplier (controlled TXRATE) level SPDSEL input.
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transition density range controls report received data stream inside normal frequency range (±200 ppm) receive channel enabled these conditions must valid Signal Detect block indicate valid signal present. This status presented LFIx (Link Fault Indicator) output associated with each receive channel, which changes synchronous selected receive interface clock. Table Analog Amplitude Detect Valid Signal Levels SDASEL (Open) HIGH Typical signal with peak amplitudes above differential differential differential
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specific trip points this compare function listed Table Because compare function operates with asynchronous clocks, there small uncertainty measurement. switch points asymmetric provide hysteresis operation. Table Receive Signaling Rate Range Control criteria Frequency Difference Between Transmit Character Clock <1708 1708-1953 >1953 <488 488-732 >732 Receive Channel Enabled Frequency Agile device contains four receive channels that independently enabled disabled. Each channel enabled disabled separately through BOE[7:0] inputs, controlled RXLE latch-enable signal. When RXLE HIGH, signals present BOE[7:0] inputs passed through Receive Channel Enable latch control PLLs logic associated receive channel. BOE[7:0] input associated with specific receive channel listed Table When RXLE HIGH BOE[x] HIGH, associated receive channel enabled receive decode serial stream from selected line receiver. When RXLE HIGH BOE[x] LOW, associated receive channel disabled internally configured minimum power dissipation. single channel bonded-pair bonded-quad disabled, this will impact ability receive channels bond correctly. addition, disabled channel selected master channel insert/delete functions, recovered clock select, these functions will work correctly. disabled channel will indicate constant /LFIx output. When RXLE returns LOW, values present BOE[7:0] inputs latched Receive Channel Enable Latch, remain there until RXLE returns HIGH opened latch again. Note: When disabled receive channel re-enabled, status associated LFIx output data parallel outputs associated channel indeterminate 10ms. Clock/Data Recovery extraction bit-rate clock recovery bits from each received serial stream performed separate Clock/Data Recovery (CDR) block within each receive channel. clock extraction function performed high-performance embedded phase-locked loops (PLLs) that track frequency transitions incoming streams align phase their internal bit-rate clocks transitions selected serial data streams. Each accepts character-rate (bit-rate halfcharacter-rate (bit-rate reference clock from REFCLK input. This REFCLK input used Page
Current Tracking Source Selected data stream (LFIx HIGH) REFCLK (LFIx LOW)
Next Tracking Source Data Stream Indeterminate REFCLK Data Stream Indeterminate REFCLK
Analog Amplitude While majority these signal monitors based fixed constants, analog amplitude level detection adjustable allow operation with highly attenuated signals, highnoise environments. This adjustment made through SDASEL signal, three-level select (ternary) input, which sets trip point detection valid signal three levels, listed Table This control input effects analog monitors receive channels. Signal Detect monitors active present line receiver, selected associated INSELx input. When configured local loopback (LPEN HIGH), line receivers selected, output each channel reports only receive frequency out-of-range transition density status associated transmit signal. When local loopback active, analog amplitude monitors disabled. Transition Density transition detection logic checks absence transitions spanning greater than transmission characters bits). transitions present data received channel (within referenced period), transition detection logic that channel will assert LFIx. LFIx output remains asserted until least transition detected each three adjacent received characters. Range Controls receive-VCO range-control monitors more than just report frequency status received signal. They also determine receive Clock/Data Recovery circuits (CDR) should align receive clock data stream local REFCLK input. This function prevents receive from tracking out-of-specification received signal. When range-control monitor channel indicates that signaling rate within specification, phase detector receive configured track transitions received data stream. this mode LFIx output associated channel HIGH (unless other status monitors indicates that received signal specification). range-control monitor indicates that received data stream signaling-rate specification, phase detector configured track local REFCLK input, associated LFIx output asserted LOW.
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ensure that (within each CDR) operating correct frequency (rather than some harmonic bitrate) improve acquisition time limit unlocked frequency excursions when data present selected serial inputs. Regardless type signal present, will attempt recover data stream from frequency recovered data stream outside limits range control monitors, will track REFCLK instead data stream. When frequency selected data stream returns valid frequency, allowed track received data stream. frequency REFCLK required within ±200 frequency clock that drives REFCLK input remote transmitter ensure lock incoming data stream. systems using multiple redundant connections, LFIx output used select alternate data stream. When LFIx indication detected, external logic toggle selection associated INx1± INx2± inputs through associated INSELx input. When port switch takes place, necessary receive that channel reacquire serial stream frame incoming character boundaries. channel bonding also enabled, channel alignment event also required before output data considered usable. Deserializer/Framer Each circuit extracts bits from associated serial data stream clocks these bits into Shifter/Framer bitclock rate. When enabled, Framer examines data stream looking more COMMA K28.5 characters possible positions. location this character data stream used determine character boundaries following characters. Framing Character transceiver block allows selection three combinations framing characters support requirements different interfaces. selection framing character made through FRAMCHAR input. FRAMCHAR 3-level select input that allows selection three different framing characters character combinations. specific combinations these framing characters listed Table When specific combination selected framing character detected framer, boundaries characters present received data stream known. Table Framing Character Selector Bits detected framer FRAMCHAR (Open) HIGH Character Name COMMA+ COMMA+ COMMA- -K28.5 +K28.5 Bits Detected 00111110XX 00111110XX 11000001XX 0011111010 1100000101 Framer
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framer each channel operates three different modes, selected RFMODE input. addition, framer itself enabled disabled through RFEN input. When RFEN LOW, framers four receive paths disabled, combination bits received data stream will alter character boundaries. When RFEN HIGH, framer selected RFMODE enabled four channels. When RFMODE LOW, low-latency framer selected. This framer operates stretching recovered character clock until aligns with received character boundaries. this mode framer starts alignment process first detection selected framing character. reduce impact external circuits that make recovered clock, clock period stretched more than bit-periods clock cycle. When operated with character-rate output clock (RXRATE LOW), output properly framed characters delayed nine character-clock cycles from detection selected framing character. When operated with half-character-rate output clock (RXRATE HIGH), output properly framed characters delayed character-clock cycles from detection selected framing character. When RFMODE (open) Cypress-mode multi-byte framer selected. required detection multiple framing characters makes associated link much more robust incorrect framing aliased SYNC characters data stream. this mode, framer does adjust character clock boundary, instead aligns character already recovered character clock. This ensures that recovered clock will contain significant phase changes hops during normal operation framing, allows recovered clock replicated distributed other external circuits components using PLL-based clock distribution elements. this framing mode character boundaries only adjusted selected framing character detected least twice within span bits, with both instances identical 10-bit character boundaries. When RFMODE HIGH, alternate-mode multi-byte framer enabled. Like Cypress-mode multi-byte framer, multiple framing characters must detected before character boundary adjusted. this mode, data stream must contain minimum four selected framing characters, received consecutive characters, identical 10-bit boundaries, before character framing adjusted. Note: Except K29.7 character, 8B/10B running disparity rules prohibit presence multiple COMMA+ characters consecutive characters. Because this, combination FRAMCHAR RFMODE HIGH recommended. While framing still take place while following 8B/10B coding rules, this configuration prevents framing K28.5 character. Note: receive Elasticity Buffers require detection four selected framing character enable buffer alignment centering. Because these characters must occur consecutive characters, combination FRAMCHAR RFMODE HIGH recommended receive modes that Elasticity Buffers. Framing channels enabled when RFEN HIGH. RFEN LOW, framer each channel disabled. When framers disabled, changes made recovPage
Note: standard definition COMMA contains only seven bits. However, since valid COMMA characters within 8B/10B character also have inversion bit, compare pattern extended full eight bits reduce possibility framing error.
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ered character boundaries channel, regardless presence framing characters data stream. 10B/8B Decoder Block decoder logic block performs primary functions: decoding received transmission characters back into Data Special Character codes, comparing generated BIST patterns with received characters permit at-speed link device testing, 10B/8B Decoder framed parallel output each deserializer shifter passed 10B/8B Decoder where, Decoder enabled (DECMODE LOW), transformed from 10-bit transmission character back original Data Special Character codes. This block uses 10B/8B decoder patterns Tables this data sheet. Valid data characters indicated 000b bit-combination associated RXSTx[2:0] status bits, Special Character codes indicated 001b bit-combination these same status outputs. Framing characters, Invalid patterns, disparity errors, synchronization status presented alternate combinations these status bits. 10B/8B decoder operates normal modes, also bypassed. operating mode decoder controlled DECMODE input. When DECMODE LOW, decoder bypassed 10-bit characters passed output register. this mode, channel bonding possible, receive Elasticity Buffers bypassed, RXCKSEL must MID. This clock mode generates separate RXCLKx+ outputs each receive channel. When DECMODE open), 10-bit transmission characters decoded using Tables Received Special Code characters decoded using Cypress column Table When DECMODE HIGH, 10-bit transmission characters decoded using Tables Received Special Code characters decoded using Alternate column Table settings where decoder enabled, receive paths operated separate channels bonded form various multi-channel buses. Receive BIST Operation receiver interfaces contain internal pattern generators that used validate both device link operation. These generators enabled associated BOE[x] signals listed Table (when BISTLE latch enable input HIGH). When enabled, register associated receive channel becomes signature pattern generator checker logically converting Linear Feedback Shift Register (LFSR). This LFSR generates 511-character sequence that includes Data Special Character codes, including explicit violation symbols. This provides predictable pseudo-random sequence that matched identical LFSR attached Transmitter(s). When synchronized with received data stream, associated receiver checks each character Decoder with each character generated LFSR indicates compare errors BIST status RXSTx[2:0] bits output register.
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When BISTLE signal HIGH, BOE[x] input that enables BIST generator/checker associated receive channel BIST generator associated transmit channel). When BISTLE returns LOW, values BOE[x] signals captured BIST Enable Latch. These values remain BIST Enable Latch until BISTLE returned high open latch again. captured signals BIST Enable Latch HIGH (i.e., BIST disabled) following device reset (TRSTZ sampled LOW). LFSR initialized BIST hardware once BIST enable that receive channel present output BIST Enable Latch, recognized. This sets BIST LFSR BIST-loop start-code D0.0 (D0.0 sent only once BIST loop). status BIST progress character mismatches presented RXSTx[2:0] status outputs. Code rule violations running disparity errors that occur part BIST loop cause error indication. RXSTx[2:0] indicates 010b 100b character period BIST loop indicate loop completion. This status used check test pattern progress. These same status values presented when decoder bypassed BIST enabled receive channel. specific status reported BIST state machine listed Table These same codes reported receive status outputs regardless state DECMODE. specific patterns checked each receiver described detail Cypress application note "HOTLink Built-In SelfTest." sequence compared transceiver block identical that CY7B933 CY7C924DX, allowing interoperable systems built when used compatible serial signaling rates. number invalid characters received ever exceeds number valid characters receive BIST state machine aborts compare operations resets LFSR D0.0 state look start BIST sequence again. When receive paths configured common clock operation (RXCKSEL MID) each pass must preceded 16-character Word Sync Sequence allow output buffer alignment management clock frequency variations. This automatically generated transmitter when local RXCKSEL MID. BIST state machine requires characters correctly framed detect BIST sequence. framer enabled configured low-latency operation (RFMODE LOW), framer align characters within BIST sequence. either multi-byte framers enabled (RFMODE LOW), generally necessary frame receiver before BIST enabled. receive outputs clocked relative REFCLK (RXCKSEL LOW), transmitter precedes every character BIST sequence with 16character Word Sync Sequence. This sequence will frame receiver regardless setting RFMODE. Receive Elasticity Buffer Each receive channel contains Elasticity Buffer that designed support multiple clocking modes. These buffers allow data read using Elasticity Buffer read-clock that asynchronous both frequency phase from Elasticity Buffer write clock, read clock that frequency coherent with uncontrolled phase relative Elasticity Buffer write clock. Page
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Each Elasticity Buffer minimum 10-characters deep, supports 11-bit wide data path. capable supporting decoded character three status bits each character present buffer. write clock these buffers always recovered clock associated read channel. read clock Elasticity Buffers come from three selectable sources. character-rate REFCLK recovered clock from same receive channel recovered clock from alternate receive channel These Elasticity Buffers also used align output data streams when multiple channels bonded together. Receive Modes operating mode receive path through RXMODE[1:0] inputs. These RXMODE[1:0] inputs only interpreted when decoder enabled (DECMODE LOW). These modes determine type any) channel bonding status reporting. different receive modes listed Table Table Receive Operating Modes Mode RXMODE [1:0] Mode Number Operating Mode
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density framing characters must present received data streams. Prior reception valid data, least Word Sync Sequence that portion necessary align receive buffers) must received allow receive Elasticity Buffer centered. Elasticity buffer also device reset operation initiated through TRSTZ input, however, following such event Frequency Agile device will normally require framing event before will correctly decode characters. When RXCKSEL open), each received channel output register clocked recovered clock that channel. Since characters added deleted, receiver Elasticity Buffer bypassed. When RXCKSEL HIGH, channels clocked selected recovered clock. This selection made using RXCLKB+ RXCLKD+ signals inputs Table This selected clock always output RXCLKA+ RXCLKC+. this mode receive Elasticity Buffers enabled. When data output using recovered clock (RXCKSEL HIGH), receive channels allowed insert delete characters, except necessary Elasticity Buffer alignment. Table Independent Quad Channel Bonded Recovered Clock Select RXCLKB+ RXCLKD+ RXCLKA+/RXCLKC+ Clock Source RXCLKA RXCLKB RXCLKC RXCLKD
Channel Bonding Independent Independent Dual Dual Quad Quad
RXSTx Status Reporting Status Reserved test Status Status Reserved test Status Status Reserved test Status
Independent Channel Modes independent channel modes Modes where RXMODE[1] LOW), four receive paths clocked clock mode selected RXCKSEL. When RXCKSEL LOW, four receive channels clocked REFCLK. RXCLKB+ RXCLKD+ outputs disabled (High-Z), RXCLKA+ RXCLKC+ outputs present buffered delayed form REFCLK. this mode, receive Elasticity Buffers enabled. REFCLK clocking, Elasticity Buffers must able insert K28.5 characters delete framing characters appropriate. insertion K28.5 deletion framing character occur time channel, however, actual timing these insertions deletions controlled part transmitter sends data. Insertion K28.5 character only occur when receiver framing character Elasticity Buffer. Likewise, delete framing character, must also Elasticity Buffer. prevent receive buffer overflow underflow receive channel, minimum
Prior reception valid data, least Word Sync Sequence that portion necessary align receive buffers) must received allow receive Elasticity Buffers centered. Elasticity buffer also device reset operation initiated through TRSTZ input, however, following such event Frequency Agile device will normally require framing event before will correctly decode characters. Since Elasticity buffer allowed insert delete framing characters, transmit clocks channels must from common source. Dual-Channel Bonded Modes dual-channel bonded modes Modes where RXMODE[1] open), associated receive channel pair output registers must clocked common clock. This mode does operate when RXCKSEL MID. Proper operation this mode requires that associated transmit data streams clocked from common reference with long-term character slippage between bonded channels. dual-channel mode this means that channels must clocked from common reference, channels must clocked from common reference (all four transmit channels clocked from same source, that requirement). Prior reception valid characters, least Word Sync Sequence that portion necessary align receive buffers) must received bonded channels (within allowable inter-channel skew window) allow
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ceive Elasticity Buffers centered. While normal characters output prior this alignment event, they necessarily aligned within same boundaries that they were transmitted. When RXCKSEL LOW, four receive channels clocked REFCLK. RXCLKB+ RXCLKD+ outputs disabled (High-Z), RXCLKA+ RXCLKC+ present buffered delayed form REFCLK. this mode, receive Elasticity Buffers enabled. REFCLK clocking, Elasticity Buffers must able insert K28.5 characters delete framing characters appropriate. While these insertions deletions take place time, they must occur same time both channels that bonded together. This necessary keep data bonded channel-pairs properly aligned. This insert delete process controlled channel selected using RXCLKB+ RXCLKD+ inputs using decodes listed Table When RXCKSEL HIGH, channels clocked selected recovered clock, channels clocked selected recovered clock, shown Table output clock channel bonded-pair output continuously RXCLKA+. clock source this output selected from recovered clock channel channel using RXCLKB+ input. output clock channel bonded-pair output continuously RXCLKC+. clock source this output selected from recovered clock channel channel using RXCLKD+ input. Table Dual-Channel Bonded Recovered Clock Select Clock Source RXCLKB+ RXCLKD+ RXCLKA+ RXCLKA RXCLKB RXCLKC RXCLKD RXCLKC+
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
this mode receive Elasticity Buffers enabled. REFCLK clocking, Elasticity Buffers must able insert K28.5 characters delete framing characters appropriate. While these insertions deletions take place time, they must occur same time four channels. This necessary keep data four bonded channels properly aligned. This insert delete process controlled channel selected using RXCLKB+ RXCLKD+ inputs using decode listed Table When RXCKSEL HIGH, four receive-channel output registers clocked selected recovered clock. clock select quad channel mode same that independent channel operation. This selection made using RXCLKB+ RXCLKD+ inputs, shown Table output clock four bonded channels output continuously RXCLKA+ RXCLKC+. When data output using recovered clock (RXCKSEL HIGH), receive channels allowed insert delete characters, except necessary Elasticity Buffer alignment. Multi-Device Bonding When configured quad-channel bonding (RXMODE[1] HIGH) also possible bond channels across multiple devices. This form channel bonding only possible when RXCKSEL LOW, selecting REFCLK output clock channels devices. this mode, BONDST[1:0] signals used pass channel bonding status between different devices. This necessary keep data bonded devices common alignment. device must selected controlling device driving MASTER that device LOW. other devices must have their MASTER HIGH prevent having multiple active drivers BONDST bus. Within master device, single receive channel selected controlling channel generation different BONDST[1:0] status. This selection made using RXCLKB+ RXCLKD+ inputs, shown Table This allows master channel selection dynamically changed through external control MASTER, RXCLKB+, RXCLKD+ inputs. Note: change master device channel should followed assertion TRSTZ properly initialize devices. Output Each receive channel presents 11-signal output consisting 8-bit data 3-bit status signals present this output modified present operating mode transceiver block selected DECMODE. This mapping shown Table When 10B/8B decoder bypassed (DECMODE LOW), framed 10-bit value presented associated output register, along with status output (COMDETx) indicating character output register selected framing characters. usage mapping external signals coded character shown Table COMDETx status outputs operate same regardless combination selected character framing FRAMCHAR input. They HIGH when character Page
When data output using recovered clock (RXCKSEL HIGH), receive channels allowed insert delete characters, except necessary Elasticity Buffer alignment. Quad-Channel Modes quad-channel modes modes where RXMODE[1] HIGH), four receive channel output registers must clocked common clock. This mode does operate when RXCKSEL MID. Proper operation this mode requires that four transmit data streams clocked from common reference with long-term character slippage between bonded channels. quad-channel modes this means that transmit channels must clocked from common reference. Prior reception valid data, least Word Sync Sequence that portion necessary align receive buffers) must received four bonded channels (within allowable inter-channel skew window) allow receive Elasticity Buffers centered aligned. When RXCKSEL LOW, four receive channels clocked internal derivative REFCLK. RXCLKB+ RXCLKD+ outputs disabled (High-Z), RXCLKA+ RXCLKC+ present buffered delayed form REFCLK. Document 38-02044
Table Output Register Assignments Signal Name RXSTx[2] (LSB) RXSTx[1] RXSTx[0] RXDx[0] RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7] (MSB) DECMODE COMDETx DOUTx[0] DOUTx[1] DOUTx[2] DOUTx[3] DOUTx[4] DOUTx[5] DOUTx[6] DOUTx[7] DOUTx[8] DOUTx[9] DECMODE HIGH RXSTx[2] RXSTx[1] RXSTx[0] RXDx[0] RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7]
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
output register contains selected framing character proper character boundary, other combinations. When low-latency framer half-rate receive port clocking also enabled (RFMODE LOW, RXRATE HIGH, RXCKSEL LOW), framer will stretch recovered clock nearest 20-bit boundary such that rising edge RXCLKx+ occurs when COMDETx present associated output bus. When standard framer enabled half-rate receive port clocking also enabled (RFMODE RXRATE HIGH), output clock modified when framing detected, single pipeline stage added subtracted from data stream framer logic such that rising edge RXCLKx+ occurs when COMDET present associated output bus. This adjustment only occurs when framer enabled (RFEN HIGH). When framer disabled, clock boundaries adjusted, COMDETx active during rising edge RXCLKx- number characters were received following initial framing). Receive Status Bits When 10B/8B decoder enabled (DECMODE LOW), each character presented output register includes three associated status bits. These bits used identify contents data valid, type character present, state receive BIST operations (regardless state DECMODE), character violations, channel bonding status These conditions normally overlap; i.e., valid data character received with incorrect running disparity reported valid data character. instead reported decoder violation some specific type. This implies hierarchy priority level various status combinations. hierarchy value each status listed Table
Table Decoder Bypass Mode (DECMODE LOW) Signal Name RXSTx[2] (LSB) RXSTx[1] RXSTx[0] RXDx[0] RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7] (MSB) Weight COMDETx
Name
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Table Receive Character Status Bits Description RXSTx[2:0] Priority Type-A Status Type-B Status
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Receive BIST Status (Receive BIST Enabled)
Normal Character Received. valid Data character output BIST Data Compare. Characbus meets formatting requirements Data characters listed compared correctly Table Special Code Detected. valid special character output BIST Command Compare. meets formatting requirements Special Code characters listed Character compared correctly Table presently selected framing character decoder violation indication. Receive Elasticity Buffer Underrun/Overrun Error. receive buffer able add/drop K28.5 framing character. Channel Lock Detected. Asserts BIST Last Good. Last Characwhen bonded channels have BIST sequence detected detected RESYNC within allot- valid. window. Presented only last cycle before aligned data presented.
Framing Character detected. This indicates that character matching patterns identified framing character selected FRAMCHAR) detected. decoded value this character present associated output bus. Codeword Violation. character output C0.7. This BIST Last Bad. Last Character indicates that received character cannot decoded into valid BIST sequence detected incharacter. valid. Loss Sync. character invalid, event that caused receive channels lose synchronization. When channel bonding enabled, this indicates that more channels have either lost synchronization (loss character framing), that bonded channels longer proper character alignment. When channels operated independently (with decoder enabled), this indicates Lock condition. Loss Sync. character invalid, event that caused receive channels lose synchronization. When channel bonding enabled, this indicates that more channels have either lost synchronization (loss character framing), that bonded channels longer proper character alignment. When channels operated independently (with decoder enabled), this indicates loss character framing. Also used indicate receive Elasticity Buffer underflow/overflow errors. BIST Start. Receive BIST enabled this channel, character compares have commenced. This also indicates Lock condition, Elasticity Buffer overflow/underflow conditions.
Running Disparity Error. character output C4.7, BIST Error. While comparing C1.7, C2.7. characters, mismatch found more decoded character bits. Resync. receiver state machine Resynchronization state. BIST Wait. receiver comIn this state data output reflects presently decoded paring characters. FRAMCHAR. found start BIST character enable LFSR. Receive Synchronization State Machine Each receive channel contains Receive Synchronization state machine. This machine handles loss recovery bit, channel, word framing, part control channel bonding. This state machine enabled whenever receive channels configured channel bonding (RXMODE[1] LOW). Separate forms state machine exist different types status reporting. When operated without channel bonding (RXMODE[1] LOW, Modes these state machines disabled Page
Within these status decodes, there three forms status reporting. normal data status reporting modes (Type Type selectable through RXMODE[0] input. These status types allow compability with legacy systems, while allowing full reporting systems. third status type used reporting receive BIST status progress. These status values generated part Receive Synchronization State Machine, listed Table
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CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Reset
IN_SYNC
NO_SYNC
RXSTx=101
COULD_NOT_BOND
RXSTx=101
RESYNC
RXSTx=111
FRAMCHAR Detected (Elasticity Buffer Under/Overrun) Loss Lock) (Any Decoder Error) Four Consecutive FRAMCHAR Detected (Elasticity Buffer Under/Overrun) Loss Lock) (Four Consecutive Decoder Errors) (Invalid Minus Valid Valid Character other than FRAMCHAR Figure Status Type-A Receive State Machine characters decoded directly. Mode RESYNC (111b) status never reported. Mode neither RESYNC (111b) Channel Lock Detected (010b) status reported. Status Type-A Receive State Machine This machine four primary states: NO_SYNC, RESYNC, COULD_NOT_BOND, IN_SYNC, shown Figure IN_SYNC state respond with multiple status types, while others respond with only type. Status Type-B Receive State Machine This machine four primary states: NO_SYNC, RESYNC, IN_SYNC, COULD_NOT_BOND, shown Figure Some these state respond with only status value, while others respond with multiple status types. BIST Status State Machine When receive path enabled look compare received data stream with BIST pattern, RXSTx[2:0] bits identify present state BIST compare operation. BIST state machine multiple states, shown Table When receive detects out-of-lock condition, BIST state forced Start-of-BIST state, regardless present state BIST state machine. number detected errors ever exceeds number valid matches greater than state machine forced WAIT_FOR_BIST state where monitors interface first character next BIST sequence (D0.0). Also, Elasticity Buffer ever hits overflow/underflow condition, status forced BIST_START until buffer recentered (approximately nine character periods). ensure compatibility between source destination BIST operating modes, sending receiving ends BIST sequence must both have RXCKSEL both have RXCKSEL MID. Page State Transition Conditions (BOND_INH LOW) (Deskew Window Expired)
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CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Reset
RXSTx
IN_SYNC
NO_SYNC
RXSTx RXSTx RXSTx RXSTx
RESYNC_IN_SYNC
RXSTx=011
RESYNC
RXSTx=111
Condition
FRAMCHAR Detected
(BOND_INH Master Channel Bond) Deskew Window Expired (Elasticity Buffer Under/Overrun) Loss Lock) (Any Decoder Error) ((BOND_INH Master Channel Bond) (Deskew Window Expired)) Four Consecutive FRAMCHAR Detected (Elasticity Buffer Under/Overrun) Loss Lock) (Four Consecutive Decoder Errors) (Invalid Minus Valid Last FRAMCHAR Before Valid Character Bonded Master Channel (Elasticity Buffer Under/Overrun) Loss Lock) Decoder Error Figure Status Type-B Receive State Machine
IEEE 1149.1 Compliant JTAG Operation family IEEE 1149.1 JTAG interface both Boundary Scan operations. Four dedicated pins reserved each device Test Access Port (TAP). Boundary Scan family supports Bypass, Sample/Preload, Extest, Intest, Idcode Usercode boundary scan instructions. JTAG interface shown Figure Frequency Agile devices also allow system-level diagnosis transceiver interface interconnect. Boundary scan supported LVCMOS signals, inputs outputs. highspeed serial inputs part JTAG test chain.
In-System Reprogramming (ISR) In-System Reprogramming combination capability program reprogram device on-board, ability support design changes without changing system timing device pinout. This combination means design changes during debug field upgrades cause board respins. family implements providing JTAG compliant interface on-board programming, robust routing resources pinout flexibility, simple timing model consistent system performance. Configuration CPLD block each device family designed with Self-Boot capability. embedded on-chip EEPROM used store configuration data. devices, programming defined loading user's design into inter-
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Instruction Register
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
software assists this method converting device file into serial stream that contains instruction information addresses data locations configured. controller/processor then simply directs this stream chain devices complete desired reconfiguration diagnostic operations. Contact your local sales office information availability this option. Programming on-chip EEPROM device CPLD block programmed issuing appropriate IEEE 1149.1 JTAG instruction. This done automatically using ISR/STAPL software. configuration bits sent from through JTAG port into programming cable. data then passed internal EEPROM through NonVolatile (NV) port CPLD block. more information program through ISR/STAPL, please refer ISR/STAPL User Guide. Third-Party Programmers Cypress support available wide variety third-party programmers. major programmers (including Micro, System General, Hi-Lo) support family.
TCLK
JTAG CONTROLLER
Bypass Reg. Boundary Scan idcode Usercode Prog.
Data Registers
Figure JTAG Interface EEPROM. Configuration, other hand, defined loading user's design into volatile CPLD block. Configuration begin ways. initiated toggling Reconfig from HIGH, issuing appropriate IEEE 1149.1 JTAG instruction device JTAG interface. There IEEE 1149.1 JTAG instructions that initiate configuration PSI. Self Config instruction causes (re)configure with data store internal EEPROM. Load Config instruction causes (re)configure with data provided other sources such automatic test equipment (ATE), embedded microcontroller/processor JTAG port. There multiple configuration options available issuing IEEE 1149.1 JTAG instructions PSI. first method with programming cable software. With this method, pins devices system routed connector edge printed circuit board. programming cable then connected between this connector. simple configuration file instructs software programming operations performed devices system. software then automatically completes necessary data manipulations required accomplish configuration, reading, verifying, other functions. more information Cypress interface, Programming/ISR application notes systems with embedded controllers/processors, controller/processor used configure PSI.
Development Software Support
Warp Warp state-of-the-art design environment designing with Cypress programmable logic. Warp utilizes subset IEEE 1076/1164 VHDL IEEE 1364 Hardware Description Language (HDL) design entry. Warp accepts VHDL Verilog input, synthesizes optimizes entered design, outputs configuration bitstream desired Delta39K device. simulation, Warp provides graphical waveform simulator well VHDL Verilog Timing Models. VHDL Verilog open, powerful, non-proprietary Hardware Description Languages (HDLs) that standards behavioral design entry simulation. allows designers learn single language that useful facets design process. Third-Party Software Cypress products supported number third-party design entry simulation tools. Refer third-party software data sheet contact your local sales office list currently supported third party vendors.
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Transmit Path Block Diagram
REFCLK+ REFCLK-
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Internal Signal Character-Rate Clock
TXRATE SPDSEL
TXCLKO
Transmit Clock Multiplier Character-Rate Clock
Bit-Rate Clock BISTLE BIST Enable Latch BOE[7:0] RBIST[D:A] Output Enable Latch Phase-Align Buffer BIST LFSR 8B/10B OELE
TXMODE[1:0] TXCKSEL TXPERA
Transmit Mode
Input Register
TXDA[7:0]
Shifter
OUTA1+ OUTA1- OUTA2+ OUTA2- TXLBA
TXCTA[1:0]
TXCLKA TXPERB Phase-Align Buffer BIST LFSR 8B/10B Input Register Shifter TXDB[7:0]
OUTB1+ OUTB1- OUTB2+ OUTB2- TXLBB
TXCTB[1:0]
TXPERC Phase-Align Buffer BIST LFSR 8B/10B Input Register Shifter
OUTC1+ OUTC1- OUTC2+ OUTC2- TXLBC
TXDC[7:0]
TXCTC[1:0]
TXPERD Phase-Align Buffer BIST LFSR 8B/10B Input Register Shifter TXDD[7:0]
OUTD1+ OUTD1- OUTD2+ OUTD2- TXLBD
TXCTD[1:0]
TXRST
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Receive Path Block Diagram
RXLE BOE[7:0] Enable Latch
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Internal Signal TRSTZ TCLK LFIA
Character-Rate Clock
SDASEL LPEN INSELA INA1+ INA1- INA2+ INA2- TXLBA
JTAG Boundary Scan Controller
Framer
Elasticity Buffer
10B/8B BIST
Receive Signal Monitor Clock Data Recovery Shifter
Output Register
RXDA[7:0]
RXSTA[2:0]
Clock Select INSELB INB1+ INB1- INB2+ INB2- TXLBB
RXCLKA+
Framer
Shifter
Elasticity Buffer
10B/8B BIST
Receive Signal Monitor Clock Data Recovery
LFIB Output Register RXDB[7:0]
RXSTB[2:0]
Clock Select INSELC INC1+ INC1- INC2+ INC2- TXLBC
RXCLKB+
Framer
Elasticity Buffer
10B/8B BIST
Receive Signal Monitor Clock Data Recovery Shifter
LFIC Output Register RXDC[7:0]
RXSTC[2:0]
Clock Select INSELD IND1+ IND1- IND2+ IND2- TXLBD
RXCLKC+
Elasticity Buffer
10B/8B BIST
Receive Signal Monitor Clock Data Recovery RBIST[D:A] Framer Shifter
LFID Output Register RXDD[7:0]
RXSTD[2:0]
FRAMCHAR RXRATE RFEN RFMODE RXCKSEL DECMODE RXMODE[1:0]
Clock Select
Bonding Control
RXCLKD+
BONDST BOND_ALL BOND_INH MASTER
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Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature .-65°C +150°C Soldering Temperature.220°C Ambient Temperature with Power Applied. -40°C +85°C Junction Temperature.135°C relative Ground Potential. -0.5V 4.2V VCCIO relative Ground Potential. -0.5V 4.6V Voltage Applied Outputs High State -0.5V 4.5V Range Commercial
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Output Current into LVCMOS Outputs (LOW). Input voltage. .-0.5V 4.5V Current into Outputs. mA[6] Static Discharge Voltage.> 2001 (per MIL-STD-883, Method 3015) Latch-Up Current.> Operating Range Ambient Temperature +70°C VDDQ
3.3V 1.4V 1.6V
Operating Range Range Commercial Ambient Temperature +70°C Junction Temperature +85°C Output Condition 3.3V 2.5V 1.8V 1.5V
Notes: current into outputs with HSTL with HSTL
VCCIO 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V
3.3V 0.3V
VCCJTAG/ VCCCNFG Same VCCIO
VCCPLL Same
VCCPRG 3.3V 0.3V
Test Loads Waveforms
3.3V OUTPUT R1=365 R2=267 (Includes fixture probe capacitance)
=100 (Includes fixture probe capacitance)
LVTTL Test Load
3.0V Vth=1.4V 3.0V 2.0V 0.8V 2.0V 0.8V
Test Load
VIHE VILE
VIHE VILE
Vth=1.4V
LVTTL Input Test Waveform
PECL Input Test Waveform
Notes: Cypress uses constant current (ATE) load configurations forcing functions. This figure reference only. LVTTL switching threshold 1.4V. timing references made relative point where respective rising falling signal edge crosses this threshold voltage.
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Electrical Characteristics Over Operating Range
Characteristics
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
VCCIO 3.3V VCCIO 2.5V VCCIO 1.8V Parameter Description VDRINT VDRIO IOS[9] IBHL IBHH IBHLO IBHHO Data Retention Voltage (config data lost below this) Data Retention VCCIO Voltage (config data lost below this) Input Leakage Current Output Leakage Current Output Short Circuit Current Input Hold Sustaining Current Input Hold HIGH Sustaining Current Input Hold Overdrive Current Input Hold HIGH Overdrive Current 3.6V VCCIO VCCIO Max., VOUT 0.5V Min., VPIN Min., VPIN Max. Max. +250 -250 Test Conditions Min. -160 +200 -200 Max. Min. -160 +150 -150 Max. Min. -160 Max. Unit
Capacitance[10] Parameter CI/O CPCI CCLK CINPECL CSD1 CINTTL Description Input/Output Capacitance compliant Capacitance Clock Signal Capacitance PECL Input Capacitance Input Capacitance Input Capacitance Test Conditions VCCIO 25°C VCCIO 25°C VCCIO 25°C 3.3V 25°C 3.3V 25°C 3.3V 25°C Min. Max. Unit
Specifications Power Parameter ICC2[11] Device Description Test Conditions Frequency Commercial Frequency Commercial Frequency Commercial Standby Typical 1800 2000 3000 Unit
P15G04K100 Active Power Supply Current P15G04K200 Active Power Supply Current P15G08K200 Active Power Supply Current
Notes: more than output should tested time. Duration short circuit should exceed second. VOUT=0.5V been chosen avoid test problems caused tester ground degradation. Tested initially after design process changes that affect these parameters. Tested initially after design process changes that affect these parameters, 100% tested. Typical measured with 3.3V, 25°C, RFEN LOW, outputs unloaded.
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Characteristics (I/O) Max. Input/ Output Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL Note -7.6 -15.2 VCCIO-1.1V VCCIO-0.9V VCCIO- 0.62V VCCIO- 0.43V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VREF Min. VCCIO -0.1 -0.1 -0.1 -1.0 -2.0 -0.1 -0.5 (min.) VCCIO-0.2V VCCIO-0.2V VCCIO-0.2V VCCIO- 0.45V 0.9VCCIO (max.) 0.45
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Min. 2.0V 2.0V 2.0V 1.7V Max. Min. Max. 0.8V 0.8V 0.8V 0.7V
VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V
0.65VCCIO VCCIO+0.3 -0.3V
0.35VCCIO
0.1VCCIO Note 15.2 0.54 0.35
0.5VCCIO VREF+0.2
VCCIO+0.5 -0.5V
0.3VCCIO VREF-0.2 VREF-0.2 VREF-0.2 VREF-0.18 VREF-0.18 VREF-0.1 VREF-0.1 VREF-0.1 VREF-0.1
VREF+0.2 VCCIO+0.3 -0.3V VREF+0.2 VCCIO+0.3 -0.3V VREF+1.8 VCCIO+0.3 -0.3V VREF+1.8 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V
1.15 1.35 1.15 1.35 0.68 0.68 0.68 0.68
Notes: "Power-up Sequence Requirements" VCCIO requirement. resistor terminated termination voltage 1.5V.
Parameter VOHT VOLT IOST IOZL VIHT VILT IIHT IILT IIHPDT IILPUT
Description Output HIGH Voltage Output Voltage Output Short Circuit Current High-Z Output Leakage Current Input HIGH Voltage Input Voltage Input HIGH Current Input Current Input HIGH Current with internal pull-down Input Current with internal pull-up
Test Conditions Min. Min. VOUT
[14]
Min. -0.5
Max. -100 VCC+0.3 -500 +200 -200
Unit
LVTTL Compatible Outputs
LVTTL Compatible Inputs
REFCLK Input, Other Inputs, REFCLK Input, 0.0V Other Inputs, 0.0V 0.0V
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Parameter VDIFF [15] VIHHP VILLP VCOM VIHH VIMM VILL IIHH IIMM IILL VOHC VOLC VODIF
[16]
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Min. 0.87 0.47 Max. VCC-0.4V VCC-1.2V 0.53 0.13 -200 VCC-0.85 VCC-0.85 VCC-1.1 VCC-1.1 VCC-1.2 VCC-2.0 VCC-0.2 VCC-0.2 VCC-0.7 VCC-0.7 1200 1200 VCC-1.45 1300 -600 Typ. Max. 2000 Commercial 1800 Unit
Description Input Differential Voltage Highest Input HIGH Voltage Lowest Input voltage Common Mode Range
Test Conditions
LVDIFF Inputs: REFCLK±
3-Level Inputs Three-Level Input HIGH Voltage Min. Max. Three-Level Input Voltage Three-Level Input Voltage Input HIGH Current Input current Input current Output HIGH Voltage (VCC referenced) Output Voltage (VCC referenced) Output Differential Voltage |(OUT+) (OUT-)| Input Differential Voltage |(IN+) (IN-)| Highest Input HIGH Voltage Lowest Input Voltage Input HIGH Current Input Current Power Supply Current VIHE Max. VILE Min. Freq. Max. Min. Max. Min. Max. VCC/2 differential load differential load differential load differential load differential load differential load
Differential Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2± VDIFF VIHE VILE IIHE IILE [17]
Miscellaneous
Notes: Tested output time, output shorted less than second, less than duty cycle. This minimum difference voltage between true complement inputs required ensure detection logic-1 logic-0. common mode range defines allowable range REFCLK+ REFCLK- (relative associated power rail) when |(REFCLK+) (REFCLK-)| This marks zero-crossing between true complement inputs signal switches between HIGH LOW. Maximum measured with MAX, RFEN LOW, with serial channels sending constant alternating pattern, outputs unloaded. Typical measured under similar conditions except with 3.3V, 25°C.
Configuration Parameters
Parameter tRECONFIG Description Reconfig time before goes HIGH Min. Units.
Power-up Sequence Requirements Upon power-up, outputs remain three-stated until pins have powered-up nominal voltage part completed configuration. part will start configuration until VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCCPRG have reached nominal voltage.
pins powered order. This includes VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCCPRG. VCCIOs bank should tied same potential powered together. VCCIOs (even unused banks) need powered least 1.5V before configuration completed. Maximum ramp time VCCs should nominal voltage
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Switching Characteristics
Timing Parameter Values
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Parameter Combinatorial Mode Parameters tPRR tPRO Delay from input, through cluster channel associated with that input, output horizontal vertical channel associated with that cluster Global control output enable Global control output disable Asynchronous macrocell RESET PRESET recovery time from input horizontal vertical channel associated with cluster macrocell Asynchronous macrocell RESET PRESET from input horizontal vertical channel associated with cluster that macrocell output those same channels Asynchronous macrocell RESET PRESET minimum pulse width, from input macrocell farthest cluster horizontal vertical channel associated with Set-up time input macrocell cluster channel associated with that input pin, relative global clock Hold time input macrocell cluster channel associated with that input pin, relative global clock Global clock output macrocell output horizontal vertical channel associated with cluster that macrocell Set-up time input cell register associated with that pin, relative global clock Hold time input cell register associated with that pin, relative global clock Clock output cell register output associated with that register Macrocell clock macrocell clock through array logic within same cluster Macrocell clock macrocell clock through array logic different clusters same channel register clock macrocell clock cluster channel register associated with Macrocell clock register clock horizontal vertical channel associated with cluster that macrocell Clock output disable (high-impedance) Clock output enable (low-impedance) Maximum frequency with internal feedback-within same cluster Maximum frequency with internal feedback-within different clusters opposite ends horizontal vertical channel Set-up time macrocell used input register, from input product term clock Hold time macrocell used input register Product term clock output delay from input Register register delay through array logic different clusters same channel using product term clock Description Min. Max. Unit
tPRW
Synchronous Clocking Parameters tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2
Product Term Clocking Parameters tMCSPT tMCHPT tMCCOPT tSCS2PT
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Switching Characteristics
Timing Parameter Values (continued)
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Parameter Channel Interconnect Parameters tCHSW tCL2CL tCPLD Adder signal switch from horizontal vertical channel vice-versa Cluster Cluster delay adder (through channels channel PIM) Delay from input cluster PIM, through macrocell cluster, back cluster input. This parameter added tSCS parameters each extra pass through AND/OR array required given signal path Adder carry chain logic macrocell Maximum cycle cycle jitter time delay with skew adjustment delay without skew adjustment Lock time Output frequency Input frequency Description Min. Max. Unit
Miscellaneous Parameters
tMCCD tMCCJ tDWSA tDWOSA tLOCK fPLLO fPLLI
[18] [18]
0.25 0.50 0.35 0.35
Parameters
Note: Tested initially after design process changes that affect these parameters, 100% tested.
Cluster Memory Timing Parameter Values Parameter Asynchronous Mode Parameters tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 tCLMCLAA Cluster memory access time. Delay from address change read data Write enable pulse width Address set-up beginning write enable Address hold after write enable with both signals from same block Data set-up write enable Data hold after write enable Clock cycle time flow-through read write operations (from macrocell register through cluster memory back macrocell register same cluster) Clock cycle time pipelined read write operations (from cluster memory input register through memory cluster memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data Cluster memory input clock macrocell clock same cluster Cluster memory output clock macrocell clock same cluster Macrocell clock cluster memory input clock same cluster Macrocell clock cluster memory output clock same cluster Asynchronous cluster memory access time from input cluster output cluster Page Description Min. Max. Unit
Synchronous Mode Parameters
Document 38-02044
Channel Memory Timing Parameter Values
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Parameter Dual-Port Asynchronous Mode Parameters tCHMAA tCHMPWE tCHMSA tCHMHA tCHMSD tCHMHD tCHMBA Channel memory access time. Delay from address change read data Write enable pulse width Address set-up beginning write enable Address hold after write enable with both signals from same block Data set-up write enable Data hold after write enable Channel memory asynchronous dual port address match (busy access time) Clock cycle time flow through read write operations (from macrocell register through channel memory back macrocell register same cluster) Clock cycle time pipelined read write operations (from channel memory input register through memory channel memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data Channel memory synchronous dual-port address match (busy, clock data valid) Channel memory input clock macrocell clock same cluster Channel memory output clock macrocell clock same cluster Macrocell clock channel memory input clock same cluster Macrocell clock channel memory output clock same cluster Read write minimum clock cycle time Data, read enable, write enable set-up time relative inputs Data, read enable, write enable hold time relative inputs Data access time output pins from rising edge read clock (read clock data valid) Channel memory FIFO read clock macrocell clock read data Macrocell clock channel memory FIFO write clock write data Read write clock respective flag output output pins Read write clock macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recovery Time Master Reset Flag Data Output Time Read/Write Clock Skew Time Full Flag Read/Write Clock Skew Time Empty Flag Read/Write Clock Skew Time Boundary Flags Asynchronous channel memory access time from input channel memory output channel memory 10.0 Description Min. Max. Unit
Dual-Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 tCHMCHAA
Synchronous FIFO Data Parameters
Internal Parameters
Document 38-02044
Page
Transmitter LVTTL Switching Characteristics Parameter tTXCLK tTXCLKH tTXCLKL tTXCLKR tTXCLKF tTXDS tTXDH fTOS tTXCLKO tTXCLKOD tTXOH tTXOL
[19, [19,
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Min. 6.66 6.66 Unit
Description TXCLKx Clock Cycle Frequency TXCLKx Period TXCLKx HIGH Time TXCLKx Time TXCLKx Rise Time TXCLKx Fall Time Transmit Data Set-Up Time TXCLKx (TXCKSEL LOW) Transmit Data Hold Time from TXCLKx (TXCKSEL LOW) TXCLKO Clock Cycle Frequency (=1x REFCLK Frequency) TXCLKO Period TXCLKO Duty Cycle TXCLKO HIGH Time TXCLKO Time
Receiver LVTTL Switching Characteristics Parameter tRXCLKP tRXCLKH tRXCLKL tRXCLKD tRXCLKR tRXCLKF tRXDS
[19] [19]
Description RXCLKx Clock Output Frequency RXCLKx Period RXCLKx HIGH Time (RXRATE LOW) RXCLKx HIGH Time (RXRATE HIGH) RXCLKx Time (RXRATE LOW) RXCLKx HIGH Time (RXRATE HIGH) RXCLKx Duty Cycle RXCLKx Rise Time RXCLKx Fall Time Status Data Set-up Time From RXCLKx Status Data Hold Time From RXCLKx
Min. 6.66
Max.
Unit
[22]
tRXDH[22]
Notes: Parallel data output specifications only valid outputs loaded with similar loads. given operating frequency, neither rise fall specification greater than clock-cycle period data sheet maximum time. duty cycle specification simultaneous condition with tREFH tREFL parameters. This means that faster character rates REFCLK duty cycle cannot large 30%-70%. ratio rise time falling time must vary greater than 2:1.
Document 38-02044
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REFCLK Switching Characteristics Parameter fREF tREFCLK tREFH tREFL tREFD[23] REFCLK Clock Frequency REFCLK Period REFCLK HIGH Time (TXRATE HIGH) REFCLK HIGH Time (TXRATE LOW) REFCLK Time (TXRATE HIGH) REFCLK Time (TXRATE LOW) REFCLK Duty Cycle tREFR[19, REFCLK Rise Time (20%-80%) tREFF[19, REFCLK Fall Time (20%-80%) tTREFDS tTREFDH tRREFDA tRREFDH tREFADS tREFADH tREFCDS tREFCDH tREFRX Description
CYP15G04K100V1-MGC CYP15G04K200V2-MGC
Min. -0.02 +0.02 Max. Unit
Transmit Data TXRST Setup Time REFCLK (TXCKSEL LOW) Transmit Data TXRST Hold Time from REFCLK (TXCKSEL LOW) Receive Data Access Time from REFCLK (RXCKSEL LOW) Receive Data Hold Time from REFCLK (RXCKSEL LOW) Received Data Setup Time RXCLKA (RXCKSEL LOW) Received Data Hold Time from RXCLKA (RXCKSEL LOW) Received Data Setup Time RXCLKC (RXCKSEL LOW) Received Da
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