SINGLE CHANNEL LINE INTERFACE UNIT REV. 1.0.6 GENERAL DESCRI

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SINGLE CHANNEL LINE INTERFACE UNIT REV. 1.0.6 GENERAL DESCRI

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XRT82D20
SINGLE CHANNEL LINE INTERFACE UNIT
REV. 1.0.6
GENERAL DESCRIPTION
XRT82D20 fully integrated, single channel, line interface Transceiver (2.048 Mbps) applications. consists receiver with adaptive data slicer accurate data clock recoveries transmitter which accepts either single dual-rail digital input signal transmission line using low- impedance differential line driver. device also includes crystal-less jitter attenuator clock data smoothing which, depending system requirements, selected either transmit receive path. Coupling XRT82D20 line requires transformers both Receiver Transmitter sides, supports both balanced unbalanced interfaces. FEATURES Complete (CEPT) line interface unit Compatible with XRT7288 Generates transmit output pulses that compliant with ITU-T G.703 Pulse Template 2.048Mbps (E1) rates On-Chip Pulse Shaping both Line Drivers FIGURE BLOCK DIAGRAM XRT82D20
Clock Recovery Selectable Crystal-less Jitter attenuator Compliant with ETS300166 Return Loss Compliant with ITU-T G.823 Jitter Tolerance Requirements Supports Remote, Local Digital Loop back Operations Declares Clears ITU-T G.775 Logic Inputs accept either 3.3V 5.0V levels Operates over -400C 850C Temperature Range Ultra Power Dissipation +3.3V Supply Operation APPLICATIONS Multiplexers Multiplexers Digital Cross-Connect Systems DECT (Digital European Cordless Telephone) Base Stations CSU/DSU Equipment. Test Equipment
TClk TPOS TNEG
TTIP HDB3 Encoder Pulse Shaper Line Driver TRing Jitter Attenuator Digital Loopback Remote Loopback Data Timing Recovery Local Loopback Detect RLOS
RClk RPOS RNEG
HDB3 Decoder
Data Slicer
Peak Detector
RTIP RRing
Timing Generator
MClk
Exar Corporation 48720 Kato Road, Fremont 94538 (510) 668-7000 (510) 668-7017 www.exar.com
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
FIGURE PINOUT XRT82D20
RLOS ClkLOS TNEG/CODE RNEG/LCV RClk RPOS/RData TClk TPOS/TData LLoop RLoop DLoop ARAOS TAOS
RTIP RRing MuteRx AGND AVDD TxLEV TTIP TVDD TRing TGND JAEN DIGI JATx/Rx MClk
ORDERING INFORMATION
PART XRT82D20IW PACKAGE Lead Jedec OPERATING TEMPERATURE RANGE -40oC 85oC
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
TABLE CONTENTS
GENERAL DESCRIPTION
FEATURES APPLICATIONS Figure Block Diagram XRT82D20 Figure Pinout XRT82D20 ORDERING INFORMATION
DESCRIPTIONS
Figure Interface Timing Diagram Both Single-Rail Dual-Rail Mode, with DIGI (Pin Figure Interface Timing Diagram Dual-Rail Mode only, with DIGI (Pin
ELECTRICAL CHARACTERISTICS
TABLE RECEIVER CHARACTERISTICS 25°C, 3.3V± UNLESS OTHERWISE SPECIFIED) TABLE TRANSMITTER CHARACTERISTICS: 25°C, 3.3V± UNLESS OTHERWISE SPECIFIED) TABLE POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION RECEIVE PATHS ACTIVE -40° 85°C, 3.3V± UNLESS OTHERWISE SPECIFIED) TABLE POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION RECEIVE PATHS ACTIVE -40° 85°C, UNLESS OTHERWISE SPECIFIED) TABLE ELECTRICAL CHARACTERISTICS TABLE ELECTRICAL CHARACTERISTICS; 25°C, VDD=3.3V UNLESS OTHERWISE SPECIFIED) ABSOLUTE MAXIMUM RATINGS Figure Receiver Maximum Jitter Tolerance, Test Conditions: Test Patterrn 2^15-1, (-6dB) Cable Loss Figure Receiver Jitter Transfer Function (Jitter Attenuator Disabled, Test Conditions: Test Pattern 2^15-1, Input Jitter 0.5UIp-p Figure Receiver Jitter Transfer Function (Jitter Attenuator enabled) Test Conditions: Test Pattern 2^15-1, Input Jitter Maximum Jitter Tolerance
SYSTEM DESCRIPTION
Receive Section
JITTER ATTENUATOR TRANSMIT SECTION
Figure Illustration XRT82D20 Samples data TPOS TNEG input pins
PULSE SHAPING CIRCUIT
Figure Illustration ITU-T G.703 Pulse Template Application
INTERFACING TRANSMIT SECTION XRT82D20 LINE
Figure Illustration interface XRT82D20 Line Applications 3.3V operation only Figure Illustration interface XRT82D20 Line Applications 3.3V operation only
INTERFACING RECEIVE SECTION LINE
Figure Recommended Schematic Transformer-Coupling XRT82D20 Line Applications operation only Figure Recommended Schematic Transformer-Coupling XRT82D20 Line Applications operation only Diagnostic Features
LOCAL LOOP-BACK MODE
Figure Illustration Analog Local Loop-Back within XRT82D20
REMOTE LOOP BACK MODE
Figure Illustration Remote Loop-Back path, within XRT82D20
PACKAGE OUTLINE DRAWING
.REVISION HISTORY
DESCRIPTIONS
SYMBOL RLOS ClkLOS TYPE
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
DESCRIPTION Receiver Loss Signal: This toggles indicate loss signal receive inputs. Receiver Loss Clock: With MuteRx=1, this will toggle indicate loss clock occurred when receive signal lost (RLOS=0). When RLOS=0, transitions occur RClk, RPOS/RData RNEG outputs. Transmitter Negative Data Input/Coding Select.With Jitter Attenuator enabled (pin 18=1), input activity this determines whether device configured operate single-rail dual-rail mode. With n-rail transmit data applied this pin, device automatically configured operate dual-rail mode both transmit input receive output. this tied high more than clock cycles, device configured operate single-rail mode with HDB3 encoding decoding functions enabled. this tied more than clock cycles, device configured operate single-rail mode with encoding decoding functions enabled. (internal pull-down). Receive Negative Data/Line Code Violation Output. device configured Dual-rail mode with n-rail data applied then receive negative data will output through this pin. device configured Single-rail mode operate with HDB3 coding enabled, HDB3 code violation will detected cause this high. device configured Single-rail mode with coding selected, every bipolar violation will reported this pin. Receive Clock: Output receive clock signal terminal equipment. Receive Positive/ Data Output: Dual-rail mode, this signal p-rail receive output data. Singlerail mode, this signal receive output data. Transmitter Clock Input: Input clock signal (2.048 50ppm) Transmit Positive Data Input. Dual-rail mode, this signal p-rail transmit input data. Single-rail mode, this signal transmit input data. Local Loop back enable (active low): this enable analog Local Loop-back.In local loop-back mode, transmit output data looped back input receiver.Input signal RTIP RRing ignored. Local Loop-back priority over Remote Digital Loop-back mode. Section more details. (internal pull-down). Remote Loop Back Enable (active low): Connect this ground enable Remote Loop-back. Remote Loop-back mode, transmit data TPOS/TData TNEG ignored. Section more details. (internal pull-down). Digital Loop Back enable (active low): Connect this ground enable Digital Local Loop-back.In Digital loop-back mode, transmit input data after encoder looped back jitter attenuator selected) receive decoder. Input data RTIP RRing ignored this mode. (internal pull-up). this mode, XRT82D20 operate only jitter attenuator.
TNEG/CODE
RNEG/LCV
RClk RPOS/RData
TClk TPOS/TData
LLoop
RLoop
DLoop
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
DESCRIPTION
SYMBOL A
TYPE
Alarm Test Mode (Active-Low): Connect this ground force ClkLOS, RLOS testing without affecting data transmission. (internal pull-up) Receive Ones: With this tied High, "1's" signal inserted receiver output RPOS RNEG/RData using MCLK timing reference. This control priority over Digital Loop-back both enabled. (internal pull-down). Transmit Ones: With this tied High, encoded "1's" signal sent transmit output using MCLK timing reference. This control priority over Remote Loop-back both enabled. (internal pull-down). Master Clock Input: This signal independent 2.048 clock with accuracy better than duty cycle within 60%. function MClk provide timing source clock recovery circuit, reference clock insert "1's" data transmit well receive paths. This signal must available device operate. Jitter Attenuator Path Select. With jitter attenuator enabled, (pin ="1"), this "High" select jitter attenuator transmit path "Low" select receive path. Data input/output format then controlled automatically status TNEG input. TNEG data present device operates Dual-rail data mode. Dual-Rail/Single-Rail Select: With jitter attenuator disabled, (pin ="0"), this "High" select Dual-Rail data format "Low" select Single-Rail data format. (internal pull-down) Digital Interface: With this tied Low, input data TPOS/TData TNEG/CODE active-high will sampled TClk falling edge, while activehigh RPOS/RData RNEG output data updated falling edge RClk. Figure details. With tied high Dual-rail mode, transmit input accepts active-low TPOS/TData TNEG/CODE data will sampled TClk falling edge, while RPOS/RData RNEG/LCV activelow, data updated rising edge RClk. (internal pull-down). Jitter Attenuator Enable (active high): Connect this high enable jitter attenuation function.Jitter Attenuator Path select determined setting. (internal pull-down) Transmitter Supply Ground Transmitter Ring Output. Negative bipolar data output line. Transmit Positive Supply. Transmitter Output. Positive bipolar data output line. Transmit Level. this high twisted pair cable operation coaxial cable operation (internal pull-down). This only active 5.0V operation.
RAOS
TAOS
MClk
JATx/Rx (DR/SR)
DIGI
JAEN
TGND TRing TVDD TTIP TxLEV
SYMBOL AVDD AGND MuteRx TYPE
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
DESCRIPTION Analog Positive Supply. Analog Supply Ground Mute Receive Output. With this tied high, loss receive input signal (RLOS=0) will cause ClkLOS generate following. Dual-rail mode operation: With DIGI RClk RPOS RNEG/RData fWith DIGI RClk RPOS RNEG/RData Single-rail mode: RClk RData=0 (internal pull-down) Receive Bipolar Negative Input. Bipolar line signal input receiver. Receiver Bipolar Positive Input. Bipolar line signal input receiver.
RRing RTIP
FIGURE INTERFACE TIMING DIAGRAM BOTH SINGLE-RAIL DUAL-RAIL MODE, WITH DIGI (PIN
ctive
ctive
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
FIGURE INTERFACE TIMING DIAGRAM DUAL-RAIL MODE ONLY, WITH DIGI (PIN
TClk TClk
TPOS/TData
Active
RClk RPOS/RData
Active
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
ELECTRICAL CHARACTERISTICS
TABLE RECEIVER CHARACTERISTICS 25°C, 3.3V± UNLESS OTHERWISE SPECIFIED)
PARAMETER Receiver Sensitivity Interference Margin with -6db Cable Loss Input Impedance measured between RTIP RRing ground Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency (-3dB curve) Return Loss 51kHz-102kHz 102kHz-2048kHz 2048kHz-3072kHz MIN. TYP. UNIT
TABLE TRANSMITTER CHARACTERISTICS: 25°C, 3.3V± UNLESS OTHERWISE SPECIFIED)
PARAMETER Output Pulse Amplitude Application Application Output Pulse Width Output Pulse Amplitude Ratio Jitter Added Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz MIN. 2.14 2.70 TYP. 2.37 3.00 0.025 2.60 3.30 0.050 UIpp UNIT
TABLE POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION RECEIVE PATHS ACTIVE -40° 85°C, 3.3V± UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER Power Consumption Power Consumption Power Consumption Power Consumption MIN. TYP. UNIT CONDITIONS load, operating Mark Density load, operating Mark Density load, operating 100% Mark Density load, operating 100% Mark Density
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
TABLE POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION RECEIVE PATHS ACTIVE -40° 85°C, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER Power Consumption Power Consumption Power Consumption Power Consumption MIN. TYP. UNIT CONDITIONS load, operating Mark Density load, operating Mark Density load, operating 100% Mark Density load, operating 100% Mark Density
TABLE ELECTRICAL CHARACTERISTICS 3.3V± UNLESS OTHERWISE SPECIFIED)
PARAMETER Clock Frequency Clock Duty Cycle Clock Period TClk Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TClk Rise Time (10% /90%) TClk Fall Time (90% 10%) RClk Duty Cycle Receive Data Setup Time Receive Data Hold Time RClk Data Delay RClk Rise Time (10%/90%) RClk Fall Time (90%/10%) SYMBOL MClk MClk TClk TCDU tTSU tTHO RCDU tRSU tRHO tRCD MIN. 2.048 +50ppm
UNITS
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
TABLE ELECTRICAL CHARACTERISTICS; 25°C, VDD=3.3V UNLESS OTHERWISE SPECIFIED)
PARAMETER Input High Voltage Input Voltage Output High Voltage @IOH=5mA (See Note) VDD=3.3V VDD=5.0v Output Voltage IOL=5mA (See Note) VDD=3.3V VDD=5.0v Input Leakage Current (except input pins with pull-up resistors) Input Capacitance Output Load Capacitance SYMBOL UNIT
NOTE: Digital output pins except which typically source 20µA sink -4mA
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Operating Temperature Supply Voltage 150°C 85°C -0.5V +6.0V
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
FIGURE RECEIVER MAXIMUM JITTER TOLERANCE, TEST CONDITIONS: TEST PATTERRN 2^15-1, (-6DB) CABLE LOSS
isabled
Input Jitter (UIp-p)
.823
(Freq.(MHz))
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
FIGURE RECEIVER JITTER TRANSFER FUNCTION (JITTER ATTENUATOR DISABLED, TEST CONDITIONS: TEST PAT15 TERN INPUT JITTER 0.5UIP-P
.735-G pecification
20log(Jout/Jin) (dB)
erform ance
(Freq.(MHz))
FIGURE RECEIVER JITTER TRANSFER FUNCTION (JITTER ATTENUATOR ENABLED) TEST CONDITIONS: TEST PATTERN 2^15-1, INPUT JITTER MAXIMUM JITTER TOLERANCE
.736
Jitter Attenuation (dB)
erform ance
(Freq.(MHz))
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
SYSTEM DESCRIPTION
XRT82D20 single channel transceiver that provides electrical interface 2.048Mbps applications. XRT82D20 includes receive circuit that converts ITU-T G.703 compliant bipolar signal into compatible logic levels. receiver also includes (Loss Signal) detection circuit. Similarly, Transmit Direction, Transmitter converts compatible logic levels into G.703 compatible bipolar signal. XRT82D20 consists both Receive Section, Jitter Attenuator Transmit Section; each these sections will discussed below. RECEIVE SECTION receiver input, cable attenuated signal coupled receiver using capacitor transformer. receive data first goes through peak detector data slicer accurate data recovery.The digital representation signals clock recovery circuit timing recovery subsequently decoder selected) HDB3 decoding before being output RPOS/RData RNEG/LCV pins. digital data output format depending mode operation selected with option dual-rail single rail mode.Clock timing recovery line interface accomplished means digital scheme which high input jitter tolerance. purpose Receive Output Interface block interface directly with Receiving Terminal Equipment. Receive Output Interface block outputs data (which been recovered from
coming line signal) Receive Terminal Equipment RPOS RNEG output pins. Receive Section XRT82D20 received Positive-Polarity pulse, RTIP RRing input pins, then Receive Output Interface will output pulse RPOS output pin. Similarly, Receive Section XRT82D20 received Negative-Polarity pulse, RTIP RRing input pins, then Receive Output Interface will output pulse RNEG output pin. JITTER ATTENUATOR reduce frequency jitter transmit clock receive clock, crystal-less jitter attenuator provided.The jitter attenuator selected either transmit receive path disabled. TRANSMIT SECTION general, purpose Transmit Section (within XRT82D20) accept TTL/CMOS level digital data (from Terminal Equipment), encode into format such that can: efficiently transmitted over coaxial- twisted pair cable data rate; reliably received Remote Terminal Equipment other data link. Comply with ITU-T G.703 pulse template requirements, applications 2.048 clock applied TClk input data TPOS TNEG input pins. Transmit Input Interface circuit will sample data, TPOS TNEG input pins, upon falling edge TClk, illustrated Figure 8below.
FIGURE ILLUSTRATION XRT82D20 SAMPLES DATA TPOS TNEG INPUT PINS
TPOS
TNEG TClk
general, XRT82D20 samples TPOS input pin, then Transmit Section will ultimately generate positive polarity pulse TTIP TRing output pins (across transformer). Conversely, XRT82D20 samples TNEG input pin, then Transmit Section
vice will ultimately generate negative polarity pulse TTIP TRing output pins (across transformer). PULSE SHAPING CIRCUIT purpose Transmit Pulse Shaping circuit generate Transmit Output pulses that comply with
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
ITU-T G.703 Pulse Template Requirements Applications.
illustration ITU-T G.703 Pulse Template Requirements presented below Figure
FIGURE ILLUSTRATION ITU-T G.703 PULSE TEMPLATE APPLICATION
269ns (244
100%
194ns
Nominal Pulse
244ns 219ns (244
With input signal described above, XRT82D20 will take each mark (which provided Transmit Input Interface block, will generate pulse that complies with pulse template, presented Figure (when measured secondary side Transmit Output Transformer). INTERFACING TRANSMIT SECTION XRT82D20 LINE
ITU-T G.703 specifies that line signal transmitted over coaxial cable terminated with transmitted over twisted-pair terminated with 120. both applications (e.g., 120, user advised interface Transmitter Line, manner depicted Figure 10and Figure respectively.
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
FIGURE ILLUSTRATION INTERFACE XRT82D20 LINE APPLICATIONS 3.3V
OPERATION ONLY
RPOS/RData RTIP RNEG/LCV RClk
RRING TxLEV TTIP TGND AGND TVDD +3.3 AVDD
TNEG/CODE TRING TClk TPOS/TData
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
FIGURE ILLUSTRATION INTERFACE XRT82D20 LINE APPLICATIONS 3.3V OPERATION ONLY
RPOS/RData RTIP RNEG/LCV RClk
RRING TxLEV TTIP TGND AGND TVDD +3.3 AVDD
TNEG/CODE TRING TClk TPOS/TData
NOTES: Figure Figure 11indicate that operation, both applications, user should connect resistor series between TTIP/TRing outputs transformer. Figure Figure 11indicate that user should STEP-UP Transformer.
INTERFACING RECEIVE SECTION LINE design XRT82D20 permits user transformer-couple Receive Section line. Additionally, mentioned earlier, specification documents specify termination loads, when transmitting over coaxial cable, loads, when transmitting over twisted-pair. Figure Figure present various methods that user employ interface Receiver XRT82D20 line.
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
FIGURE RECOMMENDED SCHEMATIC TRANSFORMER-COUPLING XRT82D20 LINE APPLICATIONS OPERATION ONLY
RPOS/RData RTIP RNEG/LCV RClk
RRING TxLEV 1.36 TTIP 15.4 TGND AGND 0.11 TVDD AVDD
TNEG/CODE 15.4 TRING TClk TPOS/TData
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
FIGURE RECOMMENDED SCHEMATIC TRANSFORMER-COUPLING XRT82D20 LINE APPLICATIONS OPERATION ONLY
RPOS/RData RTIP RNEG/LCV RClk
RRING TxLEV 1.36 TTIP 26.1 TGND AGND TVDD AVDD
TNEG/CODE 26.1 TRING TClk TPOS/TData
NOTE: Figure Figure 13indicate that user should 1.36 STEP-UP transformer, when interfacing receiver line.
DIAGNOSTIC FEATURES order support diagnostic operations, XRT82D20 supports following loop-back modes: Local Loopback Remote Loopback Digital Loopback Each these loop-back modes will discussed below. LOCAL LOOP-BACK MODE When XRT82D20 configured operate Local Loop-Back Mode, XRT82D20 will ignore signals that input RTIP RRing input pins. Transmitting Terminal Equipment will trans-
data into XRT82D20 TPOS, TNEG TClk input pins. This data will processed through Transmit Terminal Input Interface Pulse Shaping circuit. Finally, this data will output line TTIP TRing output pins. Additionally, this data (which being output TTIP TRing output pins) will looped back into Receiver block. consequence, this data will also processed through entire Receive Section XRT82D20. After this post-loop-back data been processed through Receive Section will output, Near-End Receiving Terminal Equipment RPOS RNEG output pins. Figure illustrates path that data takes (within XRT82D20), when chip configured operate Local Loop-Back Mode.
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
FIGURE ILLUSTRATION ANALOG LOCAL LOOP-BACK WITHIN XRT82D20
TClk TPOS TNEG
TTIP HDB3 Encoder Pulse Shaper Line Driver TRing Jitter Attenuator Local Loopback Detect Data Timing Recovery RLOS
RClk RPOS RNEG
HDB3 Decoder
Data Slicer
Peak Detector
RTIP RRing
Timing Generator
MClk
user configure XRT82D20 operate Local Loop-Back Mode, pulling LLoop input (pin GND. REMOTE LOOP BACK MODE When XRT82D20 configured operate Remote Loop-Back Mode, XRT82D20 will ignore signals that input TPOS TNEG input pins. XRT82D20 will receive incoming line signals, RTIP RRing input pins. This data will processed through entire Receive Section (within XRT82D20) will output
Receive Terminal Equipment RPOS RNEG output pins. Additionally, this data will also internally looped back Transmit Input Interface block within Transmit Section. this point, this data will routed through remainder Transmit Section XRT82D20 will transmitted onto line TTIP TRing output pins. Figure illustrates path that data takes (within XRT82D20) when chip configured operate Remote Loop-Back Mode.
SINGLE CHANNEL LINE INTERFACE UNIT
XRT82D20
REV. 1.0.6
FIGURE ILLUSTRATION REMOTE LOOP-BACK PATH, WITHIN XRT82D20
TClk TPOS TNEG
TTIP HDB3 Encoder Pulse Shaper Line Driver TRing Jitter Attenuator Remote Loopback Data Timing Recovery
Detect
RLOS
RClk RPOS RNEG
HDB3 Decoder
Data Slicer
Peak Detector
RTIP RRing
Timing Generator
MClk
should noted that during Remote Loop-Back operation, data which input RTIP
RRING input pins, will also output Terminal Equipment, RPOS RNEG output pins.
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
PACKAGE OUTLINE DRAWING
XRT82D20
REV. 1.0.6
SINGLE CHANNEL LINE INTERFACE UNIT
REVISION HISTORY Rev. 1.0.6 corrections figures, remove values from pull-up/down resistors, correct formating
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed inaccuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 2000 EXAR Corporation Datasheet October 2000 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.

SINGLE CHANNEL LINE INTERFACE UNIT REV. 1.0.6 GENERAL DESCRI

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