The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

WFP7151 output segment/common driver suitable driving matrix panels. T


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



Preliminary WFP7151 OUTPUT SEGMENT/COMMON DRIVER
WFP7151 output segment/common driver suitable driving matrix panels. Through (Super Slim TCP) technology. ideal substantially decreasing size frame section module. WFP7151 good both segment driver common driver power consuming, highprecision panel display assembled.
FEATURES BENEFITS
(Segment mode) Shift clock frequency Adopts data system 4-bit/8-bit parallel input modes selectable with pin. Automatic transfer function enable signal. Automatic counting function which chip select mode causes internal clock stopped automatically counting input data. (Common model)
Shift clock frequency Built-in 160-bits bi-directional shift register (divisible into 80-bits
(80-bits shift register Y160 single mode Y160 Y80, Y160 Dual mode Y160 Y81, above shift directions pin-selectable (Others) Supply voltage drive +30V Number drive outputs output impedance power consumption Supply voltage logic system +2.5 +5.5V CMOS silicon gate process (P-type silicon substrate) Packaged
Publication Release Date: July 2001 Revision
Preliminary WFP7151
BLOCK DIAGRAM
WFP7151
WFP7151
Driver
WFP7151 Data Control
Driver
Control
ASIC
Reference generator
MATRIX PANEL
WFP7151
CONFIGURATION
Y160 Y159 Y158
Chip Surface
V12L V43L LorR SorC EIO2 DISPOFF EIO1 V43R V12R
Preliminary WFP7151
CONFIGURATION
Y147
Y140
Y148
Y160
Pin1
thers
Note: Dummy
PARAMETER Chip Size Pitch Pitch Bumped Size Bumped Size Bumped Size Bumped High Wafer Thickness
SIZE (X.) 12317
SIZE (Y.) 1481
UNIT
256, 256, pads
(min.) (min.)
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Coordinates
NAME Y<1> Y<2> Y<3> Y<4> Y<5> Y<6> Y<7> Y<8> Y<9> Y<10> Y<11> Y<12> Y<13> DUMR<3> DUMR<4> DUMT<28> DUMT<27> DUMT<26> DUMT<25> DUMT<24> DUMT<23> DUMT<22> DUMT<21> DUMT<20> DUMT<19> DUMT<18> DUMT<17> DUMT<16> DUMT<15> Y<14> Y<15> Y<16> NAME 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5940.000 5635.000 5565.000 5495.000 5425.000 5355.000 5285.000 5215.000 5145.000 5075.000 5005.000 4935.000 4865.000 4795.000 4725.000 4655.000 4585.000 4515.000 -429.000 -359.000 -289.000 -219.000 -149.000 -79.000 -9.000 61.000 131.000 201.000 271.000 341.000 411.000 481.000 551.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000
Preliminary WFP7151
Coordinates, continued
NAME Y<17> Y<18> Y<19> Y<20> Y<21> Y<22> Y<23> Y<24> Y<25> Y<26> Y<27> Y<28> Y<29> Y<30> Y<31> Y<32> Y<33> Y<34> Y<35> Y<36> Y<37> Y<38> Y<39> Y<40> Y<41> Y<42> Y<43> Y<44> Y<45> Y<46> Y<47> Y<48>
NAME
4445.000 4375.000 4305.000 4235.000 4165.000 4095.000 4025.000 3955.000 3885.000 3815.000 3745.000 3675.000 3605.000 3535.000 3465.000 3395.000 3325.000 3255.000 3185.000 3115.000 3045.000 2975.000 2905.000 2835.000 2765.000 2695.000 2625.000 2555.000 2485.000 2415.000 2345.000 2275.000
547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Coordinates, continued
NAME Y<49> Y<50> Y<51> Y<52> Y<53> Y<54> Y<55> Y<56> Y<57> Y<58> Y<59> Y<60> Y<61> Y<62> Y<63> <64> Y<65> Y<66> Y<67> Y<68> Y<69> Y<70> Y<71> Y<72> Y<73> Y<74> Y<75> Y<76> Y<77> Y<78> Y<79> Y<80>
NAME
2205.000 2135.000 2065.000 1995.000 1925.000 1855.000 1785.000 1715.000 1645.000 1575.000 1505.000 1435.000 1365.000 1295.000 1225.000 1155.000 1085.000 1015.000 945.000 875.000 805.000 735.000 665.000 595.000 525.000 455.000 385.000 315.000 245.000 175.000 105.000 35.000
547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000
Preliminary WFP7151
Coordinates, continued
NAME Y<81> Y<82> Y<83> Y<84> Y<85> Y<86> Y<87> Y<88> Y<89> Y<90> Y<91> Y<92> Y<93> Y<94> Y<95> Y<96> Y<97> Y<98> Y<99> Y<100> Y<101> Y<102> Y<103> Y<104> Y<105> Y<106> Y<107> Y<108> Y<109> Y<110> Y<111> Y<112>
NAME
-35.000 -105.000 -175.000 -245.000 -315.000 -385.000 -455.000 -525.000 -595.000 -665.000 -735.000 -805.000 -875.000 -945.000 -1015.000 -1085.000 -1155.000 -1225.000 -1295.000 -1365.000 -1435.000 -1505.000 -1575.000 -1645.000 -1715.000 -1785.000 -1855.000 -1925.000 -1995.000 -2065.000 -2135.000 -2205.000
547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Coordinates, continued
NAME Y<113> Y<114> Y<115> Y<116> Y<117> Y<118> Y<119> Y<120> Y<121> Y<122> Y<123> Y<124> Y<125> Y<126> Y<127> Y<128> Y<129> Y<130> Y<131> Y<132> Y<133> Y<134> Y<135> Y<136> Y<137> Y<138> Y<139> Y<140> Y<141> Y<142> Y<143> Y<144>
NAME
-2275.000 -2345.000 -2415.000 -2485.000 -2555.000 -2625.000 -2695.000 -2765.000 -2835.000 -2905.000 -2975.000 -3045.000 -3115.000 -3185.000 -3255.000 -3325.000 -3395.000 -3465.000 -3535.000 -3605.000 -3675.000 -3745.000 -3815.000 -3885.000 -3955.000 -4025.000 -4095.000 -4165.000 -4235.000 -4305.000 -4375.000 -4445.000
547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000
Preliminary WFP7151
Coordinates, continued
NAME Y<145> Y<146> Y<147> DUMT<14> DUMT<13> DUMT<12> DUMT<11> DUMT<10> DUMT<9> DUMT<8> DUMT<7> DUMT<6> DUMT<5> DUMT<4> DUMT<3> DUMT<2> DUMT<1> DUML<4> DUML<3> Y<148> Y<149> Y<150> Y<151> Y<152> Y<153> Y<154> Y<155> Y<156> Y<157> Y<158> Y<159> Y<160>
NAME
-4515.000 -4585.000 -4655.000 -4725.000 -4795.000 -4865.000 -4935.000 -5005.000 -5075.000 -5145.000 -5215.000 -5285.000 -5355.000 -5425.000 -5495.000 -5565.000 -5635.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000 -5940.000
547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 547.000 551.000 481.000 411.000 341.000 271.000 201.000 131.000 61.000 -9.000 -79.000 -149.000 -219.000 -289.000 -359.000 -429.000
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Coordinates, continued
NAME DUML<2> DUML<1> DUMB<1> DUMB<2> DUMB<3> LorR DUMB<4> DUMB<5> DUMB<10> DUMB<11> SorC DUMB<14> DUMB<15> EIO2 DUMB<18> DI<0> DUMB<21> DI<1> DUMB<24> DI<2> DUMB<28> DI<3> DUMB<32> DUMB<33> DI<4> DUMB<36> DI<5> DUMB<40>
NAME
-5940.000 -5940.000 -5634.400 -5479.400 -5339.400 -5199.400 -5058.700 -4809.700 -4669.700 -4529.700 -4389.700 -4249.700 -3999.200 -3859.200 -3719.200 -3579.200 -3439.200 -3299.200 -2815.800 -2675.800 -2535.800 -2176.300 -2036.300 -1676.800 -1536.800 -1177.300 -1037.300 -677.800 -537.800 -397.800 -38.300 101.700 461.200
-499.000 -569.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000
Preliminary WFP7151
Coordinates, continued
NAME DI<6> DUMB<44> DI<7> DUMB<45> DUMB<46> DUMB<47> DUMB<48> DISPOFF DUMB<49> DUMB<50> DUMB<51> EIO1 DUMB<52> DUMB<53> DUMB<54> DUMB<55> DUMB<56> DUMB<57> DUMB<58> DUMB<59> DUMB<60> DUMB<79> DUMR<2> DUMR<1>
NAME
601.200 960.700 1100.700 1460.200 1600.200 1740.200 1880.200 2020.200 2160.200 2300.200 2440.200 2580.200 2720.200 2860.200 3343.600 3483.600 3623.600 3763.600 3903.600 4113.100 4253.100 4393.100 4533.100 4673.100 4919.100 5063.600 5203.600 5343.600 5483.600 5623.600 5940.000 5940.000
-565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -565.000 -499.000 -569.000
Publication Release Date: July 2001 Revision
Preliminary WFP7151
DESCRIPTION
Functions
(Segment mode) CLASSIFICATION Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply SYM. V0R, V12R, V12L V43R, V43L LorR NAME INPUT/ OUTPUT Input Input Input Input Input Input FUNCTION Logic power supply (+2.5 +5.5V) Ground Power supply driver voltage Power supply driver voltage Power supply driver voltage Direction selection reading display data Vss, data read sequentially from Y160 VDD, data read sequentially from Y160 Control Signal Clock1 Input Clock input taking display data Data read falling edge clock pulse Control Signal Clock2 Input Latch pulse input display data Data latched falling edge clock pulse Control Signal Mode Input Mode selection When Vss, 4-bit parallel input mode When VDD, 8-bit parallel input mode Control Signal DI0~DI7 Data Data Input Input display data 4-bit mode, input data into DI0~DI3 DI4~DI7 connect 8-bit mode, input data into DI0~DI7
Preliminary WFP7151
Functions (Segment mode), continued
CLASSIFICATION
SYM.
NAME
INPUT/ OUTPUT
FUNCTION
Control Signal
control
Input
Control Signal
DISPOFF
Display
Input
Control Signal
EIO1 EIO2
Enable
Input/ Output
Control Signal Driver Output
SorC Y1-Y160
Mode select Y160
Input Output
signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit Normally inputs frame inversion signal (3)The driver output pin's output voltage level using line latch output signal signal. Trueth table shown Table Control input output deselect level (1)The input signal level-shifted from logic voltage level drive voltage level controls drive circuit Vss, drive output pins Vss, contents line latch reset, read display data data latch regardless condition DISPLAY, When DISPLAY function cancelled, driver outputs deselect level (V12 V34), then outputs contents data latch next falling edge That time DISPLAY removal time keep regulation what shown characteristics, output reading data correctly. Chip selecting enable providing chip selecting signal Vss, EIO1 output, EIO2 input VDD, EIO1 input, EIO2 output During output "H", while LP*XCK after 160-bits data have been read, cycle (from falling edge falling edge XCK). after which return "H". During input, after signal input, chip selected while "L", After 160-bits data have been read, chip deselected. Segment mode/common mode selection SorC VDD, segment mode segment driver output pins
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Functions, continued
(Common mode)
CLASSIFICATION SYMBOL NAME INPUT/ OUTPUT FUNCTION
Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply
V0R, V12R, V12L V43R, V43L LorR
Input Input Input Input Input Input
Logic power supply (+2.5 +5.5V) Ground Power supply driver voltage Power supply driver voltage Power supply driver voltage Bidirection shift register shift bidirection selection Data shifted left when Vss, data shifted right when "H". used pull-down common mode, connect Bidirectional shift register shift clock pulse input Data shifted falling edge clock pulse Mode selection When Vss, single mode operation selected When VDD, dual mode operation selected Dual mode data input According data shift direction data shift register, data input starting from 8lst bit. When chip used Dual mode, will pull-down. When chip used Single mode won't pull-down used Connect signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit Normally inputs frame inversion signal driver output pin's output voltage level using line latch output signal signal. Trueth table shown Table
Control Signal
Input
Control Signal Control Signal
Clock2 Mode
Input Input
Control Signal
Data
Input
Control Signal
DI0~DI6
Control Signal
Data Data control
Input
Input
Preliminary WFP7151
Functions (Common mode), continued
CLASSIFICATION
SYMBOL
NAME Display
INPUT/ OUTPUT
FUNCTION
Control Signal
DISPOFF
Input
Control Signal
EIO1
Enable
Input/ Output
Control Signal
EIO2
Enable
Input/ Output
Control Signal driver output
SorC Y1-Y160
Mode Select Y160
Input Output
Control input output deselect level input signal level-shifted from logic voltage level drive voltage level controls drive circuit Vss, drive output pins Vss, contents line latch reset, read display data data latch regardless condition DISPLAY, When DISPLAY function cancelled, driver outputs deselect level (V12 V34), then outputs contents data latch next falling edge That time DISPLAY removal time keep regulation what shown characteristics, output reading data correctly. Bidirectional shift register shift data input/output Input right shift, output left shift When EIO1 used input right shift, will pull-down When EIO1 used output left shift, won't pull-down Bidirectional shift register shift data input/output Input left shift, output right shift When EIO2 used input left shift, will pull-down When EIO2 used output right shift, won't pull-down Segment mode/common mode selection SorC Vss, "L", common mode segment driver output pins
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Functional Operations
6.2.1 Truth Table Table (Segment mode) LATCH DATA DISPOFF DRIVER OUTPUT VOLTAGE LEVEL (Y1-Y160)
Here, (+2.5 +5.5V), Vss(0V), Don't care
Note: There kinds power supply (logic level voltage, drive voltage) driver, Please supply regular voltage which assigned specification each power pin. should Vss, avoiding floating
Table (Common mode) LATCH DATA DISPOFF DRIVER OUTPUT VOLTAGE LEVEL (Y1-Y160)
Here, (+2.5 +5.5V), (0V), Don't care
Note: There kinds power supply (logic level voltage, drive voltage) driver, Please supply regular voltage which assigned specification each power pin. should Vss, avoiding floating
Table (Segment Mode) 4-bit parallel mode
LorR EIO1 EIO2 Data Input 40clock Y160 Y159 Y158 Y157 Figure Clock 39clock Y156 Y155 Y154 Y153 38clock Y152 Y151 Y150 Y149 -3clock 2clock 1clock Y149 Y153 Y157 Y150 Y154 Y158 Y151 Y155 Y159 Y152 Y156 Y160
Output
Input
Input
Output
Preliminary WFP7151
8-bit parallel mode
LorR EIO1 EIO2 Data Input 20clock Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 Figure Clock 19clock Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 18clock Y144 Y143 Y142 Y141 Y140 Y139 Y138 Y137 -3clock 2clock 1clock Y137 Y145 Y153 Y138 Y146 Y154 Y139 Y147 Y155 Y140 Y148 Y156 Y141 Y149 Y157 Y142 Y150 Y158 Y143 Y151 Y159 Y144 Y152 Y160
Output
Input
Input
Output
(Common Mode)
(Single) LorR L(shift left) H(shift right) L(shift left) H(shift right) Data Transfer Direction Y160 Y160 Y160 Y160 EIO1 Output Input Output Input EI02 Input Output Input Output Input Input
(Dual)
Here: (0V), (+2.5 +5.5V), don't care
Note: Don' care means fixed "L", avoiding floating.
Publication Release Date: July 2001 Revision
Preliminary WFP7151
6.2.2 Connection Examples Plural Segment Drivers Case LorR
first data
last data
Y160 EI02
EI01 LorR DI0~DI7
Y160 EI02
EI01 LorR DI0~DI7
Y160 EI02
EI01 LorR DI0~DI7
DI0~DI7
Case LorR
DI0~DI7 DI0~DI7 DI0~DI7 DI0~DI7 LorR EI01 EI02 Y160 last data
LorR EI01 EI02 Y160 EI01
LorR EI02 Y160
first data
Preliminary WFP7151
6.2.3 Timing Chart 4-Device Cascade Connection Segment Drivers
first data DI0~DI7 device (device (device (device (device Note: 4-bit parallel mode 8-bit parallel mode device device device lastdata
6.2.4 Connection Examples Plural Common Drivers Single Mode (Shifting toward left)
First
Last
Y160 EI02 DISPOFF
EI01 LorR
Y160 EI02 DISPOFF
EI01 LorR
Y160 EI02 DISPOFF
EI01 LorR
DISPOFF Vss(VDD)
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Single Mode (Shifting toward right)
Vss(VDD) DISPOFF DISPOFF DISPOFF DISPOFF LorR EI01 EI02 Y160 Last
LorR EI01 EI02 Y160 EI01
LorR EI02 Y160
First
Dual Mode (Shifting toward left)
First1
Last1
First2
Last2
Y160 EI02 DISPOFF
EI01 LorR
Y160 EI02 DISPOFF
EI01 LorR
Y160 EI02 DISPOFF
EI01 LorR
DISPOFF Vss(VDD)
Preliminary WFP7151
Dual Mode (Shifting toward right)
Vss(VDD) DISPOFF DISPOFF DISPOFF DISPOFF LorR EI01 EI02 Y160 Last2
LorR EI01 EI02 Y160 EI01
LorR EI02 Y160
First1
Last1 First2
ABSOLUTE MAXIMUM RATINGS
PARAMETER Logical Circuit Voltage drive Circuit Voltage Input Logic Voltage Input Drive Voltage Input logic Voltage Storage Temperature SYMBOL TSTG RATINGS -0.3 +7.0 -0.3 -0.3 V0+0.3 -0.3 V0+0.3 -0.3 +0.3 +125 UNIT NOTES
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
Publication Release Date: July 2001 Revision
Preliminary WFP7151
RECOMMENDED OPERATING CONDITIONS
PARAMETR Supply Voltage Supply Voltage Operating Temperature
Note: Ensure that voltage
SYMBOL TOPT
MIN. +2.5
TYP.
MAX. +5.5
UNIT
ELECTRICAL CHARACTERISTICS
Characteristics
2.5V 5.5V, +10V 30V;
(Segment Mode)
PARAMETER SYM. APPLICABLE MIN. TYP. MAX. UNIT CONDITION NOTES
Input Voltage
DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF EIO1, EIO2 EIO1, EIO2 DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF Y160 Y160
Input Voltage
Output Voltage Output Voltage Input Leagake Current
ILIH
-0.4 +0.4
-0.4
Input Leakage Current
ILIL
Output Resistance Output Resistance Stand-by Current Consumed Current (deselect) Consumed Current (select) Current Consumption
ISTA IDD1 IDD2
0.5V +30V 0.5V +20V
Notes: +5.0V, +30V, VDD, Vss. +5.0V, +30V, Fxck MHz, No-load, VDD. input data turned over data taking clock (4-bit parallel input mode) +5.0V, +30V, Fxck MHz, No-load, input data turned over data taking clock (4-bit parallel input mode) +5.0V, +30V, Fxck MHz, 19.2K, No-load input data turned over data taking clock (4-bit parallel input mode)
Preliminary WFP7151
(Common Mode)
PARAMETER Input Voltage SYM. APPLICABLE DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF EIO1, EIO2 EIO1, EIO2 DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF DI0~DI7, XCK, LorR, EI01, EI02, DISPOFF DI7, XCK, EI01, EI02 Y160 -0.4 +0.4 MIN. TYP. MAX. UNIT CONDITION
NOTES
Input Voltage
Output Voltage Output Voltage Input Leagake Current
ILIH
-0.4
Input Leakage Current
ILIL
Input Pull-down Current Output Resistance
0.5V =+30V 0.5V =+20V
Output Resistance
Y160
Stand-by Current Consumed Current (deselect) Current Consumption
ISTA
Notes: +5.0V, +30V, +5.0V, +30V, 19.2 KHz, case 1/240 duty operation, No-load
Publication Release Date: July 2001 Revision
Preliminary WFP7151
Characteristics
(Segment Mode)
+2.5 +5.5V, +10V +30V, 70°C
PARAMETER Shift Clock Period Shift Clock Pulse Width Shift Clock Pulse Width Data Setup Time Data Hold Time Latch Pulse Pulse Width Shift Clock Rise Latch Pulse Rise Time Shift Clock fall Latch Pulse Fall Time Latch Pulse Rise Shift Clock Rise Time Latch Pulse Fall Shift Clock Fall Time Input Signal Rise Time Input Signal Fall Time Enable Setup Time DISPLAYOFF Removal Time DISPOFF Pulse Width Output Delay Time Output Delay Time Output Delay Time
Notes:
SYMBOL twck twckH twckL tWLPH tWDL tpd1, tpd2 tpd3
CONDITION
MIN.
MAX.
UNIT
Take cascade connection into consideration. (twck-twckH-twckL)/2 maximum case high speed operation
Preliminary WFP7151
(Timing Characteristics Segment Mode)
tWLPH
tWCK DI0~DI7 Last Data tWDL DISPOFF First Data tWCKH tWCKL
Note: 4-bit parallel mode 8-bit parallel mode
tpd1 tpd2 DISPOFF tpd3 Y1~Y160
Publication Release Date: July 2001 Revision
Preliminary WFP7151
(Common Mode)
+2.5 +5.5V, +10V +30V, 70°C
PARAMETER Shift Clock Period Shift Clock Pulse Width Shift Clock Pulse Width Data Setup Time Data Hold Time Input Signal Rise Time Input Signal Fall Time DISPLAYOFF Removal Time DISPOFF Pulse Width Output Delay Time Output Delay Time Output Delay Time
SYMBOL twlp twlpH twlpH tWDL tpd1, tpd2 tpd3
CONDITION +5.0V 10%) +2.5V +4.5V
MIN.
MAX.
UNIT
tWLP
tWLPH
EIO2 (DI7) EIO1 tWDL DISPOFF
Preliminary WFP7151
tpd1 tpd2 DISPOFF tpd3 Y160
Note: LorR
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, Creation III, Kwun Tong Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: -27513100 TEL: 886-3-5770066 FAX: -27552064 FAX: -3-5792766 http://www.winbond.com.tw/ Voice Fax-on-demand: -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 First Street, Jose, 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, 115, Sec. -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: -2-27197502
Note: data specifications subject change without notice.
Publication Release Date: July 2001 Revision

Other recent searches


uPD16602 - uPD16602   uPD16602 Datasheet
TC7MBD3244AFK - TC7MBD3244AFK   TC7MBD3244AFK Datasheet
STTA3006CW - STTA3006CW   STTA3006CW Datasheet
ISL5440XEVAL1Z - ISL5440XEVAL1Z   ISL5440XEVAL1Z Datasheet
HSCH-5500 - HSCH-5500   HSCH-5500 Datasheet
DP8390 - DP8390   DP8390 Datasheet
DP83910 - DP83910   DP83910 Datasheet
DP8392 - DP8392   DP8392 Datasheet
app097 - app097   app097 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive