EBD51RC4AAFA (64M words bits, Bank) EBD51RC4AAFA words bits bank
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512MB Registered SDRAM DIMM
EBD51RC4AAFA (64M words bits, Bank)
EBD51RC4AAFA words bits bank Double Data Rate (DDR) SDRAM Module, mounting pieces 256Mbits SDRAM sealed TSOP package. Read write operations performed cross points /CK. This high-speed data transfer realized 2-bit prefetch-pipelined architecture. Data strobe (DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors mounted beside each TSOP module board.
Features
184-pin socket type dual line memory module (DIMM) height: 30.48mm Lead pitch: 1.27mm 2.5V power supply Data rate: 266Mbps (max.) (SSTL_2 compatible) Double Data Rate architecture; data transfers clock cycle Bi-directional, data strobe (DQS) transmitted /received with data, used capturing data receiver Data inputs outputs synchronized with internal banks concurrent operation (Component) edge aligned with data READs; center aligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data referenced both edges Auto precharge option each burst access Programmable burst length: Programmable /CAS latency (CL): Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval variations refresh Auto refresh Self refresh piece clock driver, pieces register driver piece serial EEPROM bits) Presence Detect (SPD) PCB.
Document E0335E10 (Ver. 1.0) Date Published January 2003 Japan URL: http://www.elpida.com Elpida Memory,Inc. 2003
EBD51RC4AAFA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed bin*1 (CL-tRCD-tRP) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact Gold
Part number EBD51RC4AAFA-7A EBD51RC4AAFA-7B
Package 184-pin DIMM
Mounted devices M2S56D20ATP-75A M2S56D20ATP-75A,
Note: Module /CAS latency component
Configurations
Front side
Back side
name VREF DQS0 /RESET DQS1 VDDQ DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 DQ18
name DQS8 DQ32 VDDQ DQ33 DQS4 DQ34 DQ35 DQ40 VDDQ DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49
name VDDQ DM0/DQS9 VDDQ DQ12 DQ13 DM1/DQS10 DQ14 DQ15 VDDQ DQ20 DQ21 DM2/DQS11 DQ22
name DM8/DQS17 VDDQ DQ36 DQ37 DM4/DQS13 DQ38 DQ39 DQ44 /RAS DQ45 VDDQ /CS0 DM5/DQS14 DQ46 DQ47 VDDQ DQ52 DQ53
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
name VDDQ DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 name VDDQ DQS6 DQ50 DQ51 VDDID DQ56 DQ57 DQS7 DQ58 DQ59 name DQ23 DQ28 DQ29 VDDQ DM3/DQS12 DQ30 DQ31 VDDQ /CK0 name DM6/DQS15 DQ54 DQ55 VDDQ DQ60 DQ61 DM7/DQS16 DQ62 DQ63 VDDQ VDDSPD
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
name BA0, DQ63 /RAS /CAS /CS0 CKE0 /CK0 DQS0 DQS8 DM8/DQS9 DQS17 VDDQ VDDSPD VREF VDDID /RESET Function Address input address Column address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input output data strobe Clock input serial Data input/output serial Serial address input Power internal circuit Power circuit Power serial EEPROM Input reference voltage Ground identification flag Reset (forces register inputs low) connection
Bank select address
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Serial Matrix*
Byte
Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM banks Module data width Module data width continuation SDRAM cycle time, SDRAM access from clock (tAC) DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: latency SDRAM device attributes: latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments byte SDRAM bits SSTL 2.5V 2.5*3
Voltage interface level this assembly
0.75ns*3 Self refresh 2/2.5 Registered 0.2V
Maximum data access time (tAC) from clock Minimum clock cycle time Maximum data access time (tAC) from clock Minimum precharge time (tRP) Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD) Minimum active precharge time (tRAS)
0.75ns*3
20ns 15ns 20ns 45ns
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Byte Function described Module bank density Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value (ASCII-8bit code) (Space) Initial (Space) Year code (BCD) Comments bank 512MB 0.9ns*3 0.9ns*3 0.5ns*3 0.5ns*3 Future 65ns*3 75ns*3 12ns*3 500ps*3 750ps*3 Future Initial Continuation code Elpida Memory
Address command setup time before clock (tIS) Address command hold time after clock (tIH) Data input setup time before clock (tDS) Data input hold time after clock (tDH) Superset information Active command period (tRC) Auto refresh active/ Auto refresh command cycle (tRFC) SDRAM cycle max. (tCK max.) Dout skew Data hold skew (tQHS) Superset information revision Checksum bytes
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Manufacturer's JEDEC code Module part number Module part number Revision code Revision code Manufacturing date
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Byte Function described Manufacturing date Module serial number Manufacturer specific data Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments Week code (BCD)
Notes: serial data protected. Serial data, "driven Low", Serial data, "driven High". Bytes through assembly serial number. These specifications defined based component specification, module.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Block Diagram
/RCS0 DQS0 DQS1 DQ11 DQS2 DQ16 DQ19 DQS3 DQ24 DQ27 DQS4 DQ32 DQ35 DQS5 DQ40 DQ43 DQS6 DQ48 DQ51 DQS7 DQ56 DQ59 DQS8
DM0/DQS9 DM1/DQS10 DQ12 DQ15 DM2/DQS11 DQ20 DQ23 DM3/DQS12 DQ28 DQ31 DM4/DQS13 DQ36 DQ39 DM5/DQS14 DQ44 DQ47 DM6/DQS15 DQ52 DQ55 DM7/DQS16 DQ60 DQ63 DM8/DQS17
/CS0 /RAS /CAS CKE0
/RCS0 /CS: SDRAMs RBA0 RBA1 BA1: SDRAMs RA12 A12: SDRAMs /RRAS /RAS: SDRAMs /RCAS /CAS: SDRAMs RCKE0A CKE: SDRAMs /RWE /WE: SDRAMs /RESET
D17: 256M bits SDRAM bits EEPROM PLL: CDCV857 Register: SSTV16857 Serial
/PCK VDDQ VREF VDDID open
CK0, /CK0 PLL* Note: Wire Clock loading table/Wiring diagrams.
Notes: pull-up resistor required open-drain/open-collector output. pull-up resistor recommended because normal line inacitve "high" state.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Differential Clock Wiring (CK0, /CK0)
(nominal) SDRAM stack
OUT1
SDRAM stack Register1
/CK0
OUT'N'
(Typically registers DIMM)
Feedback
Register2
Notes: clock delay from input clock input SDRAM register willl (nominal). Input, output feedback clock lines terminated from line line shown, from line ground. Only output shown output type. additional outputs will wired similar manner. Termination resistors feedback path clocks located after pins PLL.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Electrical Specifications
voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VDD, VDDQ IOUT Topr Tstg Value -1.0 +3.6 -1.0 +3.6 +125 Unit Note
Note: SDRAM component specification. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Operating Conditions +70°C) (DDR SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ Input reference voltage Termination voltage Input high voltage Input voltage Input signal voltage Input differential voltage, inputs VREF (DC) (DC) (DC) (DC) min. 0.49 VDDQ VREF 0.04 VREF 0.15 -0.3 -0.3 0.36 max. Unit Notes
0.50 VDDQ 0.51 VDDQ VREF VREF 0.04 VDDQ VREF 0.15 VDDQ VDDQ
Notes:
parameters referred VSS, when measured. VDDQ must lower than equal VDD. allowed exceed 3.6V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (DC) specifies allowable execution each differential input. (DC) specifies input differential voltage required switching.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Characteristics 70°C, VDD, VDDQ 2.5V 0.2V,
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Symbol IDD0 IDD1 Grade max. 2194 2096 3184 2996 1114 1016 1294 1196 4444 4256 4084 3896 4084 3986 6326 6146 Unit Test condition VIH, (min.) VIH, 3.5, (min.) VIH, Notes
Idle power down standby current IDD2P Floating idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current Random read current banks interleaving) IDD2F IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
VIH, VIH, tRAS tRAS (max.) VIH, VIH, tRFC tRFC (min.), Input Input 0.2V Input 0.2V.
Notes.
These data measured under condition that pins connected. bank operation. bank active. banks idle. Command/Address transition once cycle. Data/Data mask transition twice cycle. data this table measured with regard min. general. banks active. Only bank running (min.)
Characteristics 70°C, VDD, VDDQ 2.5V 0.2V, (DDR SDRAM Component Specification)
Parameter Input leakage current Output leakage current Output high current Output current Symbol min. -16.8 16.8 max. Unit Test condition VOUT VOUT 0.84V VOUT 0.84V Notes
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Capacitance 25°C, VDD, VDDQ 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins Address, /RAS, /CAS, /WE, /CS, DQS, max. Unit Notes
Notes: These parameters measured conditions: 100MHz, VOUT VDDQ/2, VOUT 0.2V. Dout circuits disabled. This parameter sampled 100% tested. Characteristics +70°C, VDD, VDDQ 2.5V 0.2V, (DDR SDRAM Component Specification)
Parameter Clock cycle time 2.5) high-level width low-level width half period output access time from output access time from skew DQ/DQS output hold time from Symbol tDQSCK tDQSQ min. 0.45 0.45 (tCH, tCL) -0.75 -0.75 0.75 -0.75 -0.75 1.75 0.25 0.75 0.35 0.35 0.55 0.55 0.75 0.75 0.75 0.75 1.25 120000 min. 0.45 0.45 (tCH, tCL) -0.75 -0.75 0.75 -0.75 -0.75 1.75 0.25 0.75 0.35 0.35 0.55 0.55 0.75 0.75 0.75 0.75 1.25 120000 Unit Notes
Data-out high-impedance time from Data-out low-impedance time from Read preamble Read postamble input setup time input hold time input pulse width Write preamble setup time Write preamble Write postamble Write command first latching transition falling edge setup time falling edge hold time from input high pulse width input pulse width Address control input setup time Address control input hold time tRPRE tRPST tDIPW tWPRES tWPRE tWPST tDQSS tDSS tDSH tDQSH tDQSL
Mode register command cycle time tMRD Active Precharge command period tRAS
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Parameter Symbol min. min. Unit Notes
Active Active/Auto refresh command period Auto refresh Active/Auto refresh tRFC command period Active Read/Write delay Precharge active command period Active active command period Write recovery time Auto precharge write recovery precharge time Internal write Read command delay Exit self refresh non-read command Exit self refresh read command Exit power down non-read command Exit precharge power down read command Average periodic refresh interval tRCD tRRD tDAL tWTR tXSNR tXSRD tXPNR tXPRD tREF
Notes:
transitions occur same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device will operate with greater value this parameter, system performance (bus turnaround) will degrade accordingly. specific requirement that valid (High, Low, some point valid transition) before this edge. valid transition defined monotonic, meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from High-Z logic Low. previous write progress, could High, Low, transitioning from High this time, depending tDQSS. maximum eight auto refresh commands posted given SDRAM device. tXPRD should condition unstable operation during power down mode. command/address slew rate 1.0V/ns.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Functions
(CLK), (/CLK) (input pin): master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (/CS) (input pin): When Low, commands data input. When High, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins): These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins): address (AX0 AX12) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9, AY11) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin): defines precharge mode when precharge command, read command write command issued. High when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. High when read write command, auto-precharge function enabled. While Low, auto-precharge function disabled. BA0, (input pin): BA0/BA1 bank select signals. memory array divided into bank bank bank bank Low, bank selected. High Low, bank selected. High, bank selected. High High, bank selected. (input pin): controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes High. level must kept cycle ICKEPW) least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH.
Functions
(input output pins): Data input output from these pins. (input output pin): provide read data strobes output) write data strobes input). VDDQ (power supply pins): 2.5V applied. (VDD internal circuit VDDQ output buffer.) VDDSPD (power supply pin): 2.5V applied (For serial EEPROM). (power supply pin): Ground connected. /RESET (input pin): LVCMOS reset input. When /RESET low, registers reset outputs low.
Detailed Operation Part Timing Waveforms
Refer M2S56D20/30/40ATP datasheet. pins component device fixed level module board. DIMM /CAS latency Device registered type.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
Physical Outline
Unit: 128.95 4.00 (64.48) (DATUM -A-)
2.30
64.77 133.35 0.15 49.53
1.27 0.10
2.50 0.10
10.00
17.80
4.00
Component area (Front)
Component area (Back)
4.00 0.10
2.00
3.00 Detail 1.27 6.62
0.20 0.15
Detail
2.50 0.20
(DATUM -A-) 2.175 0.90
6.35
3.80
1.00 0.05
1.80 0.10
Note: Tolerance dimensions 0.13 unless otherwise specified.
ECA-TS2-0050-01
Preliminary Data Sheet E0335E10 (Ver. 1.0)
30.48 0.15
EBD51RC4AAFA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E0335E10 (Ver. 1.0)
EBD51RC4AAFA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E0335E10 (Ver. 1.0)
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