EBD52UC8AKDA (64M words bits, Ranks) EBD52UC8AKDA words bits, ran
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512MB SDRAM DIMM
EBD52UC8AKDA (64M words bits, Ranks)
EBD52UC8AKDA words bits, ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting pieces 256M bits SDRAM sealed package. Read write operations performed cross points /CK. This high-speed data transfer realized bits prefetch-pipelined architecture. Data strobe (DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors mounted beside each module board. Note: push cover drop modules order avoid mechanical defects, which result electrical defects.
Features
200-pin socket type small outline dual line memory module DIMM) height: 31.75mm Lead pitch: 0.6mm 2.5V power supply Data rate: 333Mbps/266Mbps (max.) (SSTL_2 compatible) Double Data Rate architecture; data transfers clock cycle Bi-directional, data strobe (DQS) transmitted /received with data, used capturing data receiver Data inputs, outputs synchronized with internal banks concurrent operation (Component) edge aligned with data READs; center aligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data referenced both edges Data mask (DM) write data Auto precharge option each burst access Programmable burst length: Programmable /CAS latency (CL): Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval variations refresh Auto refresh Self refresh
Document E0367E20 (Ver. 2.0) Date Published March 2003 Japan URL: http://www.elpida.com Elpida Memory Inc. 2003
EBD52UC8AKDA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact Mounted devices 256M bits SDRAM TCP*1
Part number EBD52UC8AKDA-6B EBD52UC8AKDA-7A EBD52UC8AKDA-7B
Package
200-pin DIMM Gold
Note:
Please refer 256Mb TSOP product datasheet electrical characteristics.
Configurations
Front side
Back side
name VREF DQS0 DQS1 DQ10 DQ11 /CK0 DQ16 DQ17 DQS2 DQ18
name DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 /CK2 CKE1
name VREF DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22
name DQ23 DQ28 DQ29 DQ30 DQ31 CKE0
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
name A10/AP /CS0 DQ32 DQ33 DQS4 DQ34 DQ35 DQ40 DQ41 DQS5
name DQ42 DQ43 DQ48 DQ49 DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQ58 DQ59 VDDSPD VDDID
name /RAS /CAS /CS1 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45
name DQ46 DQ47 /CK1 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
name BA0, DQ63 /RAS /CAS /CS0, /CS1 CKE0, CKE1 /CK0 /CK2 DQS0 DQS7 VDDSPD VREF VDDID Function Address input address Column address Data input/output address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Input reference voltage Ground identification flag connection
Bank select address
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Serial Matrix
Byte Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation SDRAM cycle time, -7A, SDRAM access from clock (tAC) -7A, DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: latency SDRAM device attributes: latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time -0.5 -6B, Maximum data access time (tAC) from clock -0.5 -7A, Minimum precharge time (tRP) -7A, Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value 18ns 20ns 12ns 15ns 0.7ns*1 0.75ns*1 0.7ns*1 0.75ns*1 None 7.8µs Self refresh used 2,4,8 Unbuffered 0.2V Comments bytes bytes SDRAM bits SSTL2 2.5*1
Voltage interface level this assembly
SDRAM device attributes: /CAS latency
Minimum active active delay (tRRD) -7A,
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Byte Function described Minimum /RAS /CAS delay (tRCD) -7A, Minimum active precharge time (tRAS) -7A, Module rank density Address command setup time before clock (tIS) -7A, Address command hold time after clock (tIH) -7A, Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value (ASCII-8bit code) Continuation code Elpida Memory Comments 18ns 20ns 42ns 45ns ranks 256MB 0.75ns*1 0.9ns*1 0.75ns*1 0.9ns*1 0.45ns*1 0.5ns*1 0.45ns*1 0.5ns*1 Future 60ns*1 65ns*1 72ns*1 75ns*1 12ns*1 0.45ns*1 0.5ns*1 0.55ns*1 0.75ns*1 Future
Data input setup time before clock (tDS) -7A, Data input hold time after clock (tDH) -7A, Superset information Active command period (tRC) -7A, Auto refresh active/ Auto refresh command cycle (tRFC) -7A, SDRAM cycle max. (tCK max.) Dout skew -7A, Data hold skew (tQHS) -7A, Superset information Revision Checksum bytes
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Byte Function described Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -7A, Module part number -6B, Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments (Space) Initial (Space) Year code (HEX) Week code (HEX)
Manufacture specific data
Note:
These specifications defined based component specification, module.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Block Diagram
/CS1 /CS0 DQS0 DQS1 DQ15 DQS5 DQ40 DQ47 I/O0 I/O7 I/O0 I/O7 DQ32 DQ39 DQS4 I/O0 I/O7 I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
DQS2 DQ16 DQ23 DQS3 DQ24 DQ31
DQS6 DQ48 DQ55 DQS7 DQ56 DQ63
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
Serial /RAS /CAS CKE0 CKE1 VDDSPD VREF SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs SDRAMs D15) SDRAMs D15) SDRAMs D15), VDDQ Notes VDDID Open 256M bits SDRAM bits EEPROM SDRAMs D15), SDRAMs D15), wiring differ from that described this drawing; however DQ/DM/DQS relationships maintained shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap (open): VDDQ Strap (closed): VDDQ pull-up registor reguired open-drain/open-collector output. pull-up registor recommended, because normal lime inactive "high" state. /CK0 /CK1 /CK2 loads loads loads
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Logical Clock Structure
4DRAM loads DRAM1
DIMM connector
DRAM2
DRAM3
DRAM4
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Electrical Specifications
voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol Tstg Value -1.0 +3.6 -1.0 +3.6 +125 Unit Note
Note: SDRAM component specification. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Conditions +70°C) (DDR SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ Input reference voltage Termination voltage Input high voltage Input voltage Input voltage level, inputs Input differential cross point voltage, inputs Input differential voltage, inputs VREF (DC) (DC) (DC) (DC) (DC) 0.49 VDDQ VREF 0.04 VREF 0.15 -0.3 -0.3 VDDQ 0.2V 0.36 0.50 VDDQ VREF VDDQ 0.51 VDDQ VREF 0.04 VDDQ VREF 0.15 VDDQ Unit Notes
VDDQ 0.2V VDDQ
Notes:
VDDQ must lower than equal VDD. allowed exceed 3.6V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (DC) specifies allowable execution each differential input. (DC) specifies input differential voltage required switching. (CK) assumed over VREF 0.18V, (CK) assumed under VREF 0.18V measurement.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Characteristics +70°C, 2.5V 0.2V,
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Idle power down standby current Floating idle standby current Quiet idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current Operating current banks interleaving) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A -7A, -7A, -7A, -7A, -7A, -7A, -7A, Grade -7A, -7A, max. 1320 1200 1560 1440 2080 1840 2080 1840 3200 2800 3240 2800 Unit Test condition VIH, (min.) VIH, 2.5, (min.) Notes
VIH, VIH, DQS, VREF VIH, VIH, DQS, VREF VIH, tRAS tRAS (max.) VIH, VIH, tRFC tRFC (min.), Input Input Input
Notes. These data measured under condition that pins connected. bank operation. bank active. banks idle. Command/Address transition once cycle. Data/Data mask transition twice cycle. banks active. Only bank running (min.) data this table measured with regard (min.) general. Command/Address transition once every clock cycles. Command/Address stable VIL.
Characteristics +70°C, VDD, VDDQ 2.5V 0.2V,
Parameter Input leakage current Output leakage current Output high current Output current Symbol min. -15.2 15.2 max. Unit Test condition VOUT VOUT 1.95V VOUT 0.35V Notes
Note: SDRAM component specification.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Capacitance 25°C, 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins Address, /RAS, /CAS, /CK, CKE, DQS, max. Unit Notes
Characteristics +70°C, VDD, VDDQ 2.5V 0.2V, (DDR SDRAM Component Specification)
Parameter Clock cycle time 2.5) high-level width low-level width half period output access time from output access time from skew DQ/DQS output hold time from Data hold skew factor Symbol tDQSCK tDQSQ tQHS min. 0.45 0.45 (tCH, tCL) -0.7 -0.6 max. 0.55 0.55 0.45 min. 0.45 0.45 (tCH, tCL) -0.75 -0.75 max. 0.55 0.55 0.75 0.75 min. 0.45 0.45 (tCH, tCL) -0.75 -0.75 0.55 0.55 0.75 0.75 Unit Notes
tQHS -0.7 -0.7 0.45 0.45 1.75 0.55 1.25
tQHS -0.75 -0.75 1.75 0.25 0.75 0.35 0.35 0.75 0.75 0.75 1.25
tQHS -0.75 -0.75 1.75 0.25 0.75 0.35 0.35 0.75 0.75 0.75 1.25
Data-out high-impedance time from Data-out low-impedance time from Read preamble Read postamble input setup time input hold time input pulse width Write preamble setup time Write preamble Write postamble Write command first latching transition falling edge hold time from input high pulse width input pulse width Address control input setup time Address control input pulse width tRPRE tRPST tDIPW
tWPRES tWPRE tWPST tDQSS 0.25 0.75 0.35 0.35 0.75 0.75
falling edge setup time tDSS tDSH tDQSH tDQSL
Address control input hold time tIPW
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Parameter Mode register command cycle time Active Precharge command period Active Active/Auto refresh command period Auto refresh Active/Auto refresh command period Active Read/Write delay Precharge active command period Active Autoprecharge delay Active active command period Write recovery time Symbol tMRD tRAS tRFC tRCD tRAP tRRD min. tRCD min. max. 120000 min. tRCD min. max. 120000 min. tRCD min. 120000 Unit Notes
Auto precharge write recovery tDAL precharge time Internal write Read command tWTR delay Average periodic refresh interval tREF
(tWR/tCK)+ (tRP/tCK)
(tWR/tCK)+ (tRP/tCK)
(tWR/tCK)+ (tRP/tCK)
Notes: parameters listed this data sheet component specifications. testing conditions, refer corresponding component data sheet. This parameter defines signal transition delay from cross point /CK. signal transition defined occur when signal level crossing VTT. timing reference level VTT. Output valid window defined period between successive transition data (read) signals. signal transition defined occur when signal level crossing VTT. defined DOUT transition delay from Low-Z High-Z read burst operation. timing reference cross point /CK. This parameter referred specific DOUT voltage level, specify when device output stops driving. defined DOUT transition delay from High-Z Low-Z beginning read operation. This parameter referred specific DOUT voltage level, specify when device output begins driving. Input valid windows defined period between successive transition data input (write) signals. signal transition defined occur when signal level crossing VREF. timing reference level VREF. transition from Low-Z High-Z defined occur when device output stops driving. specific reference voltage judge this transition given. (max.) determined lock range DLL. Beyond this lock range, operation assured. (min.) when these parameters measured. Otherwise, absolute minimum values these values tCK. assumed 2.5V 0.2V. power supply variation cycle expected less than 0.4V/400 cycle. tDAL (tWR/tCK)+(tRP/tCK) each terms above, already integer, round next highest integer. Example: Speed 2.5, 7.5ns, 15ns tRP= 20ns, tDAL (15ns/7.5ns) (20ns/7.5ns) tDAL clocks
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Timing Parameter Measured Clock Cycle unbuffered DIMM
Number clock cycle Parameter Write pre-charge command delay (same bank) Read pre-charge command delay (same bank) Write read command delay input data) Burst stop command write command delay 2.5) Burst stop command High-Z 2.5) Read command write command delay output data) 2.5) Pre-charge command High-Z 2.5) Write command data latency Write recovery data latency Mode register command cycle time Self refresh exit non-read command Self refresh exit read command Power down entry Power down exit command input Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tDMD tMRD tSNR tSRD tPDEN tPDEX min. BL/2 BL/2 BL/2 BL/2 BL/2 max. 7.5ns min. BL/2 BL/2 BL/2 BL/2 BL/2 max. Unit
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Functions
(input pin) master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (input pin) When low, commands data input. When high, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins) These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins) address (AX0 AX12) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin) defines precharge mode when precharge command, read command write command issued. high when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. high when read write command, auto-precharge function enabled. While low, auto-precharge function disabled. BA0, (input pin) BA0, bank select signals (BA). memory array divided into bank bank bank bank (See Bank Select Signal Table) [Bank Select Signal Table]
Bank Bank Bank Bank
Remark: VIH. VIL. (input pin) controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes high. level must kept cycle least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH. (input output pins) Data input output from these pins. (input output pin) provide read data strobes output) write data strobes input).
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
(input pins): reference signal data input mask function. sampled cross point VREF (power supply pins) 2.5V applied. (VDD internal circuit VDDQ output buffer.) VDDSPD (power supply pin) 2.5V applied (For serial EEPROM). (power supply pin) Ground connected.
Detailed Operation Part Timing Waveforms
Refer EDD2508AKTA datasheet.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
Physical Outline
Unit:
Front side
11.55 18.45 (DATUM -A-) 3.80
Full
2.15
11.40
67.60
47.40 2.45 1.00 0.10
Back side 2.45 R0.50 0.20
2.15 R0.50 0.20
20.00
4.00
Component area (Back)
(DATUM -A-) Detail 0.60
2.55
Detail FULL 1.80
Detail
4.20
0.25
4.20
4.00 0.10
1.50
1.00 0.10
0.45 0.03
ECA-TS2-0085-01
Preliminary Data Sheet E0367E20 (Ver. 2.0)
31.75
4.00
Component area (Front)
EBD52UC8AKDA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E0367E20 (Ver. 2.0)
EBD52UC8AKDA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E0367E20 (Ver. 2.0)
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