UXART Serial/Parallel Controller CD1400 flexible asynchronous rec
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CD1400
UXART Serial/Parallel Controller
CD1400 flexible asynchronous receiver/transmitter with four full-duplex serial channels, three full-duplex serial channels high-speed bidirectional parallel channel. With optional special character processing capabilities, especially well-suited UNIX applications. CD1400 fabricated advanced-CMOS process operates system clock MHz. Packaged 100-pin MQFP, high throughput, low-power consumption high level integration permit system designs with minimum part-count, maximum performance maximum reliability. Note: Note: This document applies CD1400 Revision later device. CD1400 only offered 100-pin MQFP package.
Figure Functional Block Diagram
User-Configurable Channel Serial Parallel RISC Processor
Host Interface
Serial/Parallel Interface Channels
Firmware User-Configurable Channel Serial
Host Interface Logic
User-Configurable Channel Serial
User-Configurable Channel Serial
A8661-01
2001, this document replaces Basis Corp. document CD1400 Data Book.
2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. CD1400 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
UXART Serial/Parallel Controller CD1400
Contents
Features
Asynchronous Features Parallel Features
Configuration Examples Design Considerations
Differences Abbreviations.11 Acronyms Functions Major Operational Modes List.16 CD1400 Register Map.23 Register Definitions Device Architecture Host Interface 7.2.1 Host Read Cycles.31 7.2.2 Host Write Cycles.31 7.2.3 Host Service Acknowledge Cycles.32 Service Requests 7.3.1 Interrupt 7.3.2 Polling.36 7.3.3 Service Requests Multiple CD1400s.37 Serial Data Reception Transmission 7.4.1 Receiver Operation 7.4.2 Receiver Timer Operations 7.4.3 Receive Exceptions.41 7.4.4 Transmitter Operation 7.4.5 Transmitter Timer Operations Flow Control 7.5.1 In-Band Flow Control.45 7.5.2 Out-of-Band Flow Control.47 7.5.3 Modem Signals General-Purpose Receive Special Character Processing 7.6.1 UNIX Character Processing 7.6.2 Non-UNIX Receive Special Character Processing.52 Transmit Special Character Processing 7.7.1 Line Terminating Characters 7.7.2 Embedded Transmit Commands.56
Conventions
Information
Registers
Functional Description.29
CD1400 UXART Serial/Parallel Controller
7.10
7.11
7.7.3 Send Special Character Command. Baud Rate Generation Diagnostic Facilities Loopback Parallel Channel Operations 7.10.1 Transmit Operation 7.10.2 Receive Operation 7.10.3 Programming Considerations. Hardware Configurations 7.11.1 Interfacing Intel Microprocessor-Based System. 7.11.2 Interfacing Motorola* Microprocessor-Based System 7.11.3 Interfacing National Semiconductor* Microprocessor-Based System Overview Initialization 8.2.1 Chip Initialization 8.2.2 Global Function Initialization 8.2.3 Individual Channel Initialization. Poll Mode Examples 8.3.1 Polling Routine Examples Hardware-Activated Service Examples. 8.4.1 Receive Service 8.4.2 Transmit Service 8.4.3 Modem Service 8.4.4 Baud Rate Derivation Baud Rate Tables ASCII Code Table 8.6.1 Hexadecimal Character 8.6.2 Decimal Character Global Registers. 9.1.1 Global Firmware Revision Code (GFRCR) 9.1.2 Channel Access Register (CAR) 9.1.3 Global Configuration Register (GCR). 9.1.4 Service Request Register (SVRR) 9.1.5 Receive Interrupting Channel Register (RICR) 9.1.6 Transmit Interrupting Channel Register (TICR). 9.1.7 Modem Interrupting Channel Register (MICR). 9.1.8 Receive Interrupt Register (RIR) 9.1.9 Transmit Interrupt Register (TIR) 9.1.10 Modem Interrupt Register (MIR). 9.1.11 Prescaler Period Register (PPR). Virtual Registers. 9.2.1 Receive Interrupt Vector Register (RIVR) 9.2.2 Transmit Interrupt Vector Register (TIVR). 9.2.3 Modem Interrupt Vector Register (MIVR). 9.2.4 Transmit Data Register (TDR). 9.2.5 Receive Data/Status Register (RDSR).
Programming
Detailed Register Descriptions.
UXART Serial/Parallel Controller CD1400
9.2.6 Receive Data/Status Register (RDSR).96 9.2.7 Modem Interrupt Status Register (MISR) 9.2.8 Service Request Register (EOSRR) Channel Registers.99 9.3.1 Local Interrupt Vector Register (LIVR) 9.3.2 Channel Command Register (CCR) 9.3.3 Service Request Enable Register (SRER) .104 Channel Option Registers .105 9.4.1 Channel Option Register (COR1).105 9.4.2 Channel Option Register (COR2).107 9.4.3 Channel Option Register (COR3) Serial Format .108 9.4.4 Channel Option Register (COR3) Parallel Format .108 9.4.5 Channel Option Register (COR4).110 9.4.6 Channel Option Register (COR5).111 9.4.7 Channel Control Status Register (CCSR) Serial Format.112 9.4.8 Channel Control Status Register (CCSR) Parallel Format.112 9.4.9 Received Data Count Register (RDCR) Serial Format .114 9.4.10 Received Data Count Register (RDCR) Parallel Format.114 Special Character Registers.116 9.5.1 Special Character Register (SCHR1) .116 9.5.2 Special Character Register (SCHR2) .116 9.5.3 Special Character Register (SCHR3) .116 9.5.4 Special Character Register (SCHR4) .117 9.5.5 Special Character Range (SCRL).117 9.5.6 Special Character Range High (SCRH) .117 9.5.7 LNext Character (LNC).118 Modem Change Option Registers .118 9.6.1 Modem Change Option Register (MCOR1) Serial Format .118 9.6.2 Modem Change Option Register (MCOR1) Parallel Format .119 9.6.3 Modem Change Option Register (MCOR2) Serial Format .120 9.6.4 Modem Change Option Register (MCOR2) Parallel Format .120 9.6.5 Receive Time-out Period Register (RTPR) .121 9.6.6 Modem Signal Value Register (MSVR1 .122 9.6.7 Modem Signal Value Register (MSVR2) .122 9.6.8 Printer Signal Value Register (PSVR) .122 9.6.9 Receive Baud Rate Period Register (RBPR) .123 9.6.10 Receive Clock Option Register (RCOR) .124 9.6.11 Transmit Baud Rate Period Register (TBPR).124 9.6.12 Transmit Clock Option Register (TCOR) .125 Absolute Maximum Ratings.126 Recommended Operating Conditions .126 Electrical Characteristics.126 Electrical Characteristics .128 10.4.1 Index Timing Information.128 10.4.2 Asynchronous Timing.128 10.4.3 Synchronous Timing.132 10.4.4 Parallel Port Timing Specifications.135
10.0
Electrical Specifications .126
10.1 10.2 10.3 10.4
CD1400 UXART Serial/Parallel Controller
11.0 12.0 13.0
Package Specifications
11.1 12.1 13.1 100-Pin MQFP (JEDEC) Package Diagram 100-Pin MQFP CD1400 Register Map.
Ordering Information Quick Reference
Figures
Workstation: Printer, Keyboard, Mouse Modem Ports Three Serial Ports Bidirectional Parallel Port Four Full-Modem Ports Diagram CD1400. Functions Four Serial Channel Mode. Functions Three Serial/One Parallel Channel Mode CD1400 Functional Block Diagram Internal Address Generation Control Signal Generation. CD1400 Daisy-Chain Connections FIFO Timer Processing CD1400 Receive Character Processing CD1400 Transmit Character Processing CD1400 Parallel Data Transmit Connections CD1400 Parallel Data Receive Connections Relationship between RCOR/RBPR PACK* Pulse Intel, 80x86 Family Interface Motorola* 68020 Interface. National* 32000 Interface. CD1400 Master Initialization Sequence Reset Timing Clock Timing Asynchronous Read Cycle Timing Asynchronous Write Cycle Timing Asynchronous Service Acknowledge Cycle Timing Synchronous Read Cycle Timing. Synchronous Write Cycle Timing Synchronous Service Acknowledge Cycle Timing Parallel Port Transmit Timing. Parallel Port Receive Timing. Diagram 100-Pin MQFP
UXART Serial/Parallel Controller CD1400
Tables
General.16 Microprocessor Interface.17 Service Request Interface Communication Interface Miscellaneous.18 Descriptions Global Registers.23 Virtual Registers Channel Registers.23 Global Registers.24 Virtual Registers Channel Registers.26 Modem Registers Baud Rate Constants, MHz.84 Baud Rate Constants, MHz.84 Baud Rate Constants, 20.2752 MHz.85 Receive/Transmit/Modem Interrupting Channel Registers.91 Receive/Transmit/Modem Interrupt Vector Registers Receive Data/Status Register Global Registers.141 Virtual Registers .141 Channel Registers.141 Definitions .142
CD1400 UXART Serial/Parallel Controller
Revision History
Revision Date 2001 Initial release. Description
UXART Serial/Parallel Controller CD1400
Features
Asynchronous Features
Software-programmable serial data rates 230.4 kbps, full-duplex
Note: minimum clock frequency required four serial channels 230.4-kbps data rate. Refer characteristics ("Electrical Specifications" page 126) complete information device timing.
Twelve bytes FIFO each transmitter each receiver, with programmable threshold
receive-FIFO-interrupt generation
Improved interrupt schemes: Good Data interrupts eliminate need character status
check
Independent rate selection transmit receive each channel User-programmable automatic flow control modes serial channels:
In-band (software) flow control single character (XON/XOFF) Out-of-band (hardware) flow control RTS/CTS DTR/DSR
Special character recognition generation Special character processing, particularly useful UNIX-line-driver applications, optionally
handled automatically CD1400 Automatic expansion CR-NL Supports LNEXT ISTRIP Ignore Break UNIX parity handling options: Character removed from stream Passed Good Data Replaced with null hex) Preceded with FF-00 Passed with exception flagged
Line break detection (start end) generation, with programmable choice response
data pattern host
Insertion transmit delays data stream timer channel receive data time-out interrupt modem control signals-per-channel (DTRDSR, RTS, CTS, RI); Signals
available using parallel channel
Local Remote Maintenance Loopback Modes Five eight data bits character plus optional parity Odd, even, forced parity 1.5, Stop bits
CD1400 UXART Serial/Parallel Controller
Parallel Features
Parallel data rates 105-Kbytes/sec. receive 32-Kbytes/sec. transmit Thirty-byte FIFO Programmable strobe pulse widths Automatic generation recognition handshake control signals (STROBE, ACK, BUSY) Compatible with Centronics-interface specifications bits provided increase parallel signal width
Configuration Examples
Figure page through Figure page functional block diagrams three possible configurations that implemented with CD1400. first typical workstation with printer, mouse, keyboard modem ports, mode that includes single parallel port three serial channels with modem control; Figure illustrates channel with complete bidirectional modem control three channels with partial modem control; Figure shows quad serial mode four channels with complete modem control. modes operation softwareprogrammable through Control registers within CD1400.
Design Considerations
CD1400 Revision higher speed version CD1400 Revision CD1400 Revision only available 100-pin MQFP package. recommended that CD1400 Revision used designs. Please note that achieve high data rates, 60-MHz clock required. Please refer differences between CD1400 Revision
Differences
Feature Package System clock Maximum rates Ground pins pins No-connect pins CD1400 Revision 100-pin MQFP 230.4 kbps CD1400 Revision 100-pin MQFP 115.2 kbps
UXART Serial/Parallel Controller CD1400
Notes: Some no-connect pins CD1400 Revision (100-pin MQFP) were converted additional ground pins CD1400 Revision (please refer "Pin List" page details). CD1400 Revision part does work Revision layout. Revision noconnect pins must left true no-connect pins cannot connected Ground. achieve high data rates, 60-MHz system clock required. However, possible achieve some rates based 60-MHz clock lower system clock required). Refer "Baud Rate Tables" page bit-rate programming constraints. Higher clock rates produce shorter PSTROBE* signal pulse widths, when Channel programmed parallel port, similar limitations must also considered (see Parallel Channel Operations" page PSTROBE* pulse-width programming constraints).
Conventions
Abbreviations
Symbol Units measure degree Celsius microfarad microsecond (1,000 nanoseconds) hertz (cycle second) kilobit (1,024 bits) kilobit (1,000 bits) second kilobyte (1,024 bytes) kilobyte (1,000 bytes) second kilohertz kilohm megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) milliampere millisecond (1,000 microseconds) nanosecond picovolt volt watt
Kbit kbps kbits/second Kbyte Kbytes/sec. Mbyte
`tbd' indicates values that determined', `n/a' designates `not available', `n/c' indicates that connect'.
CD1400 UXART Serial/Parallel Controller
Acronyms
Acronym CMOS DRAM FIFO MQFP SDLC Definition alternating current complementary metal-oxide semiconductor direct current dynamic random-access memory first in/first industry standard architecture least-significant most-significant metric quad-flat pack random-access memory read/write synchronous data link control transistor-transistor logic
Figure Workstation: Printer, Keyboard, Mouse Modem Ports
RESET* A[6:0] DB[7:0] R/W* DTACK* SVCREQR* SVCREQT* SVCREQM* DGRANT* DPASS* SVCACKR* SVCACKT* SVCACKM*
PARALLEL FIFOS HOST INTERFACE LOGIC RISC PROCESSOR SERIAL CHANNEL SERIAL CHANNEL FIRMWARE SERIAL CHANNEL CHANNEL
PSTROBE* PACK* PSLIN* PSLCT* PRINTER PBUSY PINIT* SCANNER PERROR* PPE* PAUTOFD* PD[7:0] TXD1 RXD1
MOUSE
TXD2 RXD2 TXD3 RXD3 RTS3* CTS3* DTR3* DSR3* GPO[3:0] GPI[3:0]
KEYBOARD
MODEM
UXART Serial/Parallel Controller CD1400
Figure Three Serial Ports Bidirectional Parallel Port
PSTROBE* PACK* PSLIN* PSLCT* PRINTER PBUSY PINIT* PERROR* SCANNER PPE* PAUTOFD* PD[7:0] TXD1 RXD1 RTS1* CTS1* DTR1* DSR1* SAME CHANNEL
RESET* A[6:0] DB[7:0] R/W* DTACK* SVCREQR* SVCREQT* SVCREQM* DGRANT* DPASS* SVCACKR* SVCACKT* SVCACKM*
PARALLEL FIFOS HOST INTERFACE LOGIC RISC PROCESSOR FIRMWARE SERIAL CHANNEL CHANNEL
SERIAL CHANNEL
SERIAL CHANNEL
SAME CHANNEL
Figure Four Full-Modem Ports
RESET* A[6:0] DB[7:0] R/W* DTACK* SVCREQR* SVCREQT* SVCREQM* DGRANT* DPASS* SVCACKR* SVCACKT* SVCACKM* HOST INTERFACE LOGIC SERIAL CHANNEL SERIAL CHANNEL FIFOS SERIAL CHANNEL
TXD0 RXD0 RTS0* CTS0* DTR0* DSR0* CD0* RI0* SAME CHANNEL
RISC PROCESSOR
FIRMWARE
SAME CHANNEL
SERIAL CHANNEL
SAME CHANNEL
CD1400 UXART Serial/Parallel Controller
Information
Figure Diagram CD1400
DB[3] DB[5] DB[6] DB[7] DB[2] DB[4] A[0] A[2] A[3] A[4] A[5] A[1]
DB[1] DB[0] TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 DTR3* RTS3* CTS3* DSR3* RI3* CD3* DTR2* RTS2* CTS2*
A[6] RESET* R/W* DTACK* DPASS* DGRANT* SVCREQM* SVCREQT* SVCREQR* SVCACKM* SVCACKT* SVCACKR* PD[1] PD[0] PAUTOFD*
CD1400
100-Pin MQFP
DSR1*
RTS1*
DTR1*
DSR2*
DTR0* RTS0*
CTS1*
CTS0* DSR0*
RI2* CD2*
CD1*
CD0*
Note:
means connection (make connections these pins).
RI0*
RI1*
UXART Serial/Parallel Controller CD1400
Functions Major Operational Modes
Figure Functions Four Serial Channel Mode
A[6:0] DB[7:0] Channel Interface Host R/W* RESET* DTACK* Daisy Chain DGRANT* DPASS* SVCREQR* SVCREQT* SVCREQM* SVCACKR* SVCACKT* SVCACKM* Chan.
Request
Service
Chan.
Service
Chan.
CD1400 UXART Serial/Parallel Controller
Figure Functions Three Serial/One Parallel Channel Mode
PD[7:0] A[6:0] DB[7:0] Interface R/W* RESET* DTACK* Channel PSTROBE* PACK* PSLCT* PBUSY PPE* PERROR* PSLIN* PINIT* PAUTOFD* Chan. Daisy Chain
SVCREQM*
Service
SVCACKT* SVCACKM*
SVCACKR*
Request
Service
SVCREQR* SVCREQT*
Chan.
DGRANT* DPASS*
Host
List
following naming conventions used assignment tables: after name denotes active-low signal. Signal names parentheses parallel channel. input; input/output; output; open drain.
Table
General
Symbol RESET* Pins Type
Chan.
UXART Serial/Parallel Controller CD1400
Table
Microprocessor Interface
Symbol R/W* DTACK* A[6:0] DB[7:0] 80-83, 97-100, Pins Type
Table
Service Request Interface
Symbol SVCREQR* SVCREQT* SVCREQM* SVCACKR* SVCACKT* SVCACKM* DGRANT* DPASS* Pins Type
Table
Communication Interface (Sheet
Symbol TXD0 (PSTROBE*) RXD0 (PACK*) RTS0* (PSLIN*) CTS0* (PSLCT*) DSR0* (PBUSY) DTR0* (PINIT*) CD0* (PERROR*) RI0* (PPE*) PAUTOFD* TXD1 RXD1 RTS1* CTS1* DSR1* DTR1* Pins Type
CD1400 UXART Serial/Parallel Controller
Table
Communication Interface (Sheet
CD1* (PD[2]) RI1* (PD[3]) TXD2 RXD2 RTS2* CTS2* DSR2* DTR2* CD2* (PD[4]) RI2* (PD[5]) TXD3 RXD3 RTS3* CTS3* DSR3* DTR3* CD3* (PD[16]) RI3* (PD[7]) PD[0] PD[1]
Table
Miscellaneous
Symbol Pins Type
UXART Serial/Parallel Controller CD1400
Table
Symbol
Descriptions (Sheet
Type Description ACTIVE-LOW RESET: This synchronously resets CD1400. RESET* must active minimum system clock cycles. When RESET* removed, CD1400 will perform software initialization registers, disable transmitters receivers, when complete, place firmware revision number GFRCR. CLOCK SYSTEM CLOCK: CD1400 requires nominal 60-MHz clock proper operation. system clock divided two, internally, generate onchip timing clocks. CHIP SELECT: When active, CS*, conjunction with DS*, initiates host cycle with CD1400. DATA STROBE: During active cycle, strobes data into on-chip registers during write cycle enables data onto data during read cycles. READ/WRITE: R/W* sets direction data transfer between host CD1400. When high, cycle read, when low, cycle write. DATA TRANSFER ACKNOWLEDGE: When CD1400 completed internal operations associated with host cycle, activates DTACK* indicate cycle. host terminate cycle soon DTACK becomes active. ADDRESS [6:0]: These signals select on-chip register being accessed during host cycle. DATA [7:0]: These eight bidirectional signals data interface between host internal CD1400 registers. SERVICE REQUEST RECEIVE: When CD1400 needs host service receivers, activates this signal. SERVICE REQUEST TRANSMIT: When CD1400 needs host service transmitters, activates this signal. SERVICE REQUEST MODEM: CD1400 activates this signal when enabled change occurs. SERVICE ACKNOWLEDGE RECEIVE: host activates this signal start receive interrupt service. This special-case read cycle, during which CD1400 places contents Receive Interrupt Vector register data bus. SERVICE ACKNOWLEDGE TRANSMIT: host activates this signal start transmit interrupt service. This special-case read cycle, during which CD1400 places contents Transmit Interrupt Vector register data bus. SERVICE ACKNOWLEDGE MODEM: host activates this signal start modem interrupt service. This special-case read cycle, during which CD1400 places contents Modem Interrupt Vector register data bus. DAISY GRANT: This input, qualified with valid service acknowledge (SVCACKR*, SVCACKT*, SVCACKM*), activates CD1400 service acknowledge cycle. DAISY PASS: This output driven when valid service request exists type service acknowledge active. multiple-CD1400 designs, this signal normally connected following CD1400 DGRANT* input, forming service acknowledge daisy chain. TRANSMIT DATA [3:0]: These output signals provide serial transmit data stream four channels. When Channel operating Parallel Mode, TxD0 becomes PSTROBE* (See PSTROBE*).
RESET*
R/W*
DTACK*
80-83, 97-100,
A[6:0]
DB[7:0]
SVCREQR* SVCREQT* SVCREQM*
SVCACKR*
SVCACKT*
SVCACKM*
DGRANT*
DPASS*
TxD[3:0]
CD1400 UXART Serial/Parallel Controller
Table
Symbol RxD[3:0]
Descriptions (Sheet
Type Description RECEIVE DATA [3:0]: These input signals carry serial streams into CD1400. When Channel programmed parallel operation, RxD0 becomes PACK* (See PACK*). REQUEST SEND [3:0]: request send output from each channel. These signals controlled Modem Signal Value register inside CD1400. RTS0* serves dual-purpose based mode operation Channel (see PSLIN*). CLEAR SEND [3:0]: These clear-to-send inputs each channels. enabled, this signal control transmitter, enabling transmission when active, disabling transmission when inactive. CTS0* serves dual-purpose based mode operation Channel (see PSLCT*). DATA READY [3:0]: Data Ready each channel. DSR0* serves dualpurpose based mode operation Channel (see PBUSY). DATA TERMINAL READY [3:0]: Data Terminal Ready each channel. These signals controlled Modem Signal Value register DTR0* serves dualpurpose based mode operation Channel (see PINIT*). CARRIER DETECT [3:0]: These Carrier Detects each PD[6] PD[4] channel monitored Modem Signal Value registers. CD0* serves dual-purpose based mode operation Channel (see PERROR*). CD1*, CD2* CD3* serve dual purposes Parallel Data bits (PD[2], PD[4] PD[6]) when Channel operating Parallel mode. RING INDICATOR [3:0]: These Ring Indicators each channel monitored Modem Signal Value registers. RI0* serves dual purpose based mode operation Channel (see PPE*). RI1*, RI2*, RI3* serve dual purposes Parallel Data bits (PD[3], PD[5], PD[7]) when Channel operating Parallel mode. PRINTER STROBE: This alternate function TxD0 when Channel programmed parallel port. When port selected output (printer), PSTROBE* driven active CD1400 after proper data setup time. Data held proper hold time after PSTROBE* deactivated. When Channel programmed input (scanner) port, PSTROBE* acts acknowledge signal completion data reception. PRINTER ACKNOWLEDGE: This alternate function RxD0 when Channel programmed parallel port. When port selected output (printer), this signal used CD1400 indicate completion data reception printer, that next cycle begin. When Channel selected input (scanner), PACK* treated strobe input. Proper data setup hold times required. PRINTER SELECT PRINTER INITIALIZE PRINTER AUTOFEED: These three signals general-purpose outputs. Their state controlled lower three bits PSVR (see register descriptions detailed information register assignments). PSLIN* PINIT* alternate functions RTS0* DTR0*, depending mode operation Channel PAUTOFD* singlefunction output pin. PRINTER SELECT latch, buffer PRINTER PAPER EMPTY
RTS[3:0]*
CTS[3:0]*
DSR[3:0]*
DTR[3:0]*
CD[3:0]* PD[6],PD[4], PD[2] PERROR* RI[3:0]* PD[7],PD[5], PD[3], PPE*
PSTROBE*
PACK*
PSLIN* PINIT*
PAUTOFD*
PSLCT* PPE*
UXART Serial/Parallel Controller CD1400
Table
Symbol
Descriptions (Sheet
Type PRINTER ERROR: These three signals general-purpose inputs. Their state monitored upper four bits PSVR. with their modem input counterparts (CTS0*, RI0*, CD0*), change state programmed generate SVCREQM*. function these signals selected automatically based mode operation programmed Channel PSLCT* input logic `0', parallel port operates latch. falling edge strobe input latches data. PSLCT* logic `1', input port buffer. PRINTER BUSY: PBUSY bidirectional signal; input when transmit enabled output when receive enabled. During receive data operations, CD1400 drives PBUSY active after receiving strobe from remote. When device taken data, deasserts PBUSY activates PACK*. During transmit data operations, state PBUSY made available host PSVR; however, does affect transfer operation handshake signal this direction. PARALLEL DATA BIT: When Channel operating Parallel mode, this provides Parallel Data PARALLEL DATA BIT: When Channel operating Parallel mode, this provides Parallel Data Description
PERROR*
PBUSY
PD[0] PD[1]
CD1400 UXART Serial/Parallel Controller
Registers
communication with CD1400 occurs through large array registers. Registers divided into three types:
Global affect channels within device always available host access; access
local registers particular channel requires selecting register that channel.
Virtual only available host during context service routine. Per-channel pertain only channel being referenced.
There four sets per-channel registers, each channel. Selection register accomplished writing Channel Number through into Channel Access Register (CAR). This causes `bank switch' action, allowing registers selected channel accessed. given time, only registers single channel available. Once selected, this register remains available until changed host. tables following pages define register symbols, names, read write access modes, internal offset address each register CD1400. offset address applied address (A[6:0]) during host cycle select particular register. detailed description host interface presented "Host Interface" page register definitions immediately following register tables, some registers shown with functions. these cases, first definition applies Serial Operation Mode Channel second Parallel Mode. Channels through only function labeled `Serial' applies. "Programming" page presents detailed description register programming. Note that addresses shown relative CD1400 definition address lines. 32-bit systems, common practice connect 8-bit peripherals only byte lane. Thus, 16-bit systems, CD1400 appears every other address; example, CD1400 connected host 32-bit systems, CD1400 appears every fourth address; (the CD1400 connected host A2). either these cases, addresses used programmer will different than what shown. instance, 16-bit Motorola 68000-based system, CD1400 placed data lines D0-D7, which addresses Motorola manner addressing. CD1400 connected 68000 Thus, CD1400 address x'40 becomes x'81 programmer. `leftshifted' bit, must low-byte (D0-D7) accesses.
UXART Serial/Parallel Controller CD1400
Table
Name GFRCR SVRR RICR TICR MICR
CD1400 Register
Global Registers
Description Global Firmware Revision Code Register Channel Access Register Global Configuration Register Service Request Register Receive Interrupting Channel Register Transmit Interrupting Channel Register Modem Interrupting Channel Register Receive Interrupt Register Transmit Interrupt Register Modem Interrupt Register Prescaler Period Register Addr. Mode Size Access Page
Table
Name RIVR TIVR MIVR RDSR MISR EOSRR
Virtual Registers
Description Receive Interrupt Vector Register Transmit Interrupt Vector Register Modem Interrupt Vector Register Transmit Data Register Receive Data/Status Register Modem Interrupt Status Register Service Request Register Addr. Mode Size Access Page
NOTE: page numbers shown these tables indicate detailed register description locations "Detailed Register Descriptions" page
Table
Symbol LIVR SRER COR1 COR2 COR3
Channel Registers (Sheet
Register Name Local Interrupt Vector Register Channel Command Register Service Request Enable Register Channel Option Register Channel Option Register Channel Option Register Addr. Mode Size Access Page
CD1400 UXART Serial/Parallel Controller
Table
Symbol COR4 COR5 CCSR RDCR SCHR1 SCHR2 SCHR3 SCHR4 SCRL SCRH MCOR1 MCOR2 RTPR MSVR1 MSVR2 PSVR RBPR RCOR TBPR TCOR
Channel Registers (Sheet
Register Name Channel Option Register Channel Option Register Channel Control Status Register Received Data Count Register Special Character Register Special Character Register Special Character Register Special Character Register Special Character Range, Special Character Range, High LNext Character Modem Change Option Register Modem Change Option Register Receive Time-out Period Register Modem Signal Value Register Modem Signal Value Register Printer Signal Value Register Receive Baud Rate Period Register Receive Clock Option Register Transmit Baud Rate Period Register Transmit Clock Option Register Addr. Mode Size Access Page
Register Definitions
Table Global Registers (Sheet
Global Registers Global Firmware Revision Code Register (GFRCR) Firmware Revision Code Channel Access Register (CAR) Poll Poll Poll Poll Poll
Global Configuration Register (GCR) P/S*
Service Request Register (SVRR)
Receive Interrupting Channel Register (RICR)
UXART Serial/Parallel Controller CD1400
Table Global Registers (Sheet
Global Registers runfair tunfair munfair Binary Value ch[1] ch[1] ch[1] ch[0] ch[0] ch[0]
Transmit Interrupting Channel Register (TICR)
Modem Interrupting Channel Register (MICR)
Receive Interrupt Register (RIR) rxireq rbusy
Transmit Interrupt Register (TIR) txireq tbusy
Modem Interrupt Register (MIR) mdireq mbusy
Prescaler Period (PPR)
Table Virtual Registers
Virtual Registers Receive Interrupt Vector Register (RIVR) Transmit Character Receive Data/Status Register (RDSR) Data Received Character Status Time-out Det2 Det1 Det0 Break CDch
Transmit Interrupt Vector Register (TIVR)
Modem Interrupt Vector Register (MIVR)
Transmit Data Register (TDR)
Modem Interrupt Status Register (MISR) DSRch CTSch Rich
Service Request Register (EOSRR)
CD1400 UXART Serial/Parallel Controller
Table Channel Registers (Sheet
Channel Registers Local Interrupt Vector Register (LIVR) Chan
Channel Command Register (CCR) Chan Send
Format Reset Channel Command Chan Type
Format Channel Option Register Change Command COR3 COR2 COR1
Format Send Special Character Command Send SSPC2 SSPC1 SSPC0
Format Channel Control Command Chan RxData TxRdy Ignore Stop1 Stop0 RtsAO CtsAE ChL1 TxMpty NNDT ChL0 DsrAE
Service Request Enable Register (SRER) MdmCh
Channel Option Register (COR1) Parity ParM1 ParM0
Channel Option Register (COR2) TxIBE
Channel Option Register (COR3) Serial SCDRNG Parallel RxTh4 RxTh3 SCD34 SCD12 RxTh3
RxTh2
RxTh1
RxTh0
RxTh2
RxTh1 PEH[1] ONLCR
RxTh0 PEH[0] OCRNL
Channel Option Register (COR4) IGNCR ICRNL INLCR IGNBRK -BRKINT
PEH[2]
Channel Option Register (COR5) ISTRIP CMOE
Channel Control Status Register (CCSR) Serial RxEn Parallel RxEn TxEn RxFloff RxFlon TxEn
TxFloff
TxFlon
Received Data Count Register (RDCR) Serial Parallel
UXART Serial/Parallel Controller CD1400
Table Channel Registers (Sheet
Channel Registers Special Character Register (SCHR1) Special Character Special Character Register (SCHR2) Special Character Special Character Register (SCHR3) Special Character Special Character Register (SCHR4) Special Character Special Character Range (SCRL) Character Range Special Character Range HIgh (SCRH) Character Range High LNext Character (LNC) LNext Character 117) R//W
Table Modem Registers (Sheet
Modem Registers Modem Change Option Register (MCOR1) Serial DSRzd Parallel PBUSYzd PSLCTzd PPEzd PERRORzd CTSzd Rlzd CDzd DTRth3 DTRth2 DTRth1 DTRth0
Modem Change Option Register (MCOR2) Serial DSRod Parallel PBUSYod PSLCTod PPEod PERRORod CTSod Rlod CDod
Receive Time-out Period Register (RTPR) Binary Count Value Modem Signal Value Register (MSVR1) PSTROBE*
PSTROBE*
PINIT*
fModem Signal Value Register (MSVR2)
Printer Signal Value Register (PSVR) PBUSY PSLCT* PPE* PERROR* PACK*
PSLIN*
PAUTOFD
Receive Baud Rate Period Register (RBPR) NOTE:
MSVR1 MSVR2 show state PSTROBE* output only Channel
CD1400 UXART Serial/Parallel Controller
Table Modem Registers (Sheet
Modem Registers Binary Divisor Value Receive Clock Option Register (RCOR) ClkSel2 Binary Divisor Value Transmit Clock Option Register (TCOR) NOTE:
ClkSel1
ClkSel0
Transmit Baud Rate Period Register (TBPR)
ClkSel2
ClkSel1
ClkSel0
MSVR1 MSVR2 show state PSTROBE* output only Channel
UXART Serial/Parallel Controller CD1400
Functional Description
Device Architecture
CD1400 described small computer system tailored function sending receiving serial parallel data. made RISC processor (MPU), RAM, ROM, host interface logic serial data channels (one which function parallel port). contains special instructions hardware facilitate serial data manipulation. true RISC processor. addition having compact, efficient instructions, `windowed' architecture that allows handle channel registers time. Before beginning operations given channel, loads internal Index Register that forces accesses appropriate registers. Index Register becomes part internal address allows direct addressing register bank hardware resources selected channel. address computation required select proper channel. This same windowed scheme provided host interface (see Figure page 31). channel-specific accesses, host first loads Channel Access Register (CAR) with pointer channel accessed. read write operations will occur with proper channel. Host software need only define register address once, will valid channels because used part internal addressing.
Figure CD1400 Functional Block Diagram CHANNEL LOGIC TIMING CHANNEL LOGIC TIMING
INTERFACE LOGIC
CHANNEL LOGIC TIMING
CHANNEL LOGIC TIMING serial data channels made `bit engines' that off-load task receiving transmitting each from MPU. engines, after processing complete bit, interrupt that perform whatever task required next. example, when receiving data, will take character that being assembled. When transmitting, will
CD1400 UXART Serial/Parallel Controller
give engine next character being transmitted. Thus, does need concern itself with basic timing; this task handled engines, freeing perform higher-level processing, such detecting special characters. When Channel programmed parallel port, engines used timing handshake signals (PSTROBE*, PACK*).
Host Interface
host interface CD1400 comprises 8-bit bidirectional data bus, 7-bit address various strobes that identify type cycle occurring. most system designs, cycles will normal host read write cycles that activate appropriate strobes. Although strobe names basic timing match that Motorola 68000 family, CD1400 easily fits into environment. most cases, when host reads writes internal CD1400 location, actually accesses location array that serves bank registers. Some locations, however, mapped actual hardware resources; example, when hard output signal required, such Service Request Output SVRR), when necessary read actual state input, such modem input. CD1400 design, synchronous device. internal operations take place edges levels (phases) internal clock. Note that internal clock generated dividing external (system) clock two. When host performs cycle with CD1400, strobes, address data sampled falling edges internal clock. seen timing diagrams "Electrical Specifications" page 126, external control signals must meet setup times with respect clock edges. Once cycle started, sequence events locked CD1400 clock, with events (address setup, write data setup read data available) occurring predictable times.
UXART Serial/Parallel Controller CD1400
Figure Internal Address Generation
Register Array Channel Registers Host Address Address Generation Channel Registers Channel Registers
Channel Registers
necessary, however, design synchronous interface CD1400. asynchronous design, Data Transfer Acknowledge (DTACK*) Signal used indication that CD1400 completed requested data transfer. Thus DTACK* input wait-state generation logic that will hold host until operation complete. strobes (Chip Select Data Strobe DS*) meet minimum setup time with respect clock edge, CD1400 will detect request, cycle will delayed fullsystem clock cycles, thus meeting setup time. cycle will then commence follow predictable timing, with DTACK* signaling end.
7.2.1
Host Read Cycles
Read cycles initiated when CD1400 senses that both Inputs active Read/Write (R/W*) Input high. strobes address inputs must meet setup times specified timing specifications "Electrical Specifications" page 126. important note that both Signals must valid cycle start, thus cycle times measured from whichever signals goes active last. CD1400 signals that completed read cycle (placing data from addressed register data pins), activating DTACK* Signal. read cycle terminated when host removes DS*.
7.2.2
Host Write Cycles
Write cycle timing strobe activity nearly identical read cycles except that R/W* Signal must held low. Write data, strobes address inputs must meet setup hold times specified timing diagrams "Electrical Specifications" page 126. Again, DTACK* Signal used indicate that cycle complete CD1400 taken data. Removing both terminates cycle.
CD1400 UXART Serial/Parallel Controller
7.2.3
Host Service Acknowledge Cycles
Service acknowledge cycles special-case read cycles. Timing basically same normal read cycle, SVCACK* Inputs activated instead Input slightly longer setup time required SVCACK* Input than Input). data that CD1400 provides during read cycle contents Interrupt Vector Register associated with type request being acknowledged (RIVR receive, TIVR transmit MIVR modem) channel that requesting service (see description service request procedures later this section). with read write cycles, DTACK* will indicate cycle removing SVCACK* terminates cycle. important fact note about timing service acknowledge cycles: When host completed service routine writes EOSRR, subsequent cycle, started immediately, will delayed approximately This time required internal processor complete housekeeping activities associated with switch service acknowledge context. These activities primarily FIFO-pointer updates restoration environment prior service request/service acknowledge procedure, must completed before internal registers modified host. situation occurs that host attempts access before internal procedures complete, CD1400 will delay cycle until ready. system designs that monitor DTACK*, this will cause problem; cycle extended until DTACK* becomes active, delay will automatically met. system design does monitor DTACK*, mechanism must provided introduce required delay.
Service Requests
From host point view, CD1400 operates modes: normal operation service request/acknowledge. normal mode operation allows host system make changes obtain current operating status global per-channel basis. Service Request/Acknowledge Mode used when particular channel needs service; example, used when receive FIFO reached programmed threshold requires emptying. unique behavior CD1400 that service request only responded after been placed service acknowledge `context'. This context switch takes place when request acknowledged, either activating appropriate SVCACK* Input Pin, proper manipulation internal registers. When internal processor (MPU) detects condition channel that requires host attention, posts service request internally externally. external request activation SVCREQ* Output Pins, depending whether type service needed receive, transmit modem signal change. Included with internal request channel pointer that points channel requiring service. When host service acknowledge begins, this pointer loaded into CAR, thus request automatically services proper channel. This purpose context switch; prepares CD1400 servicing proper channel. completion acknowledge procedure, CD1400 must taken acknowledge context indicating that procedure complete, thus restoring internal state what before context switched. important remember that several registers within CD1400 only accessed when context switch been made referred `virtual' registers. example, host cannot directly place data transmit FIFO arbitrary time. must wait transmit service request indicating that FIFO empty, then acknowledge Once acknowledge procedure started, transmit FIFO available loading.
UXART Serial/Parallel Controller CD1400
CD1400 requests service when required. basic ways host informed these service requests through hardware (interrupt), software (polling internal CD1400 registers). method used will dependent hardware/software design system; CD1400 functions well both environments. following section discusses trade-offs choosing other basic methods, combined maximum performance.
7.3.1
Interrupt
term `interrupt' used generalized description method which CD1400 gains attention host CPU. used interchangeably with `service request' because really same function. `Interrupt' often used describe unconditional response part host. Whether this case, source still same service request from CD1400. hardware signals generated CD1400 (SVCREQR*, SVCREQT* SVCREQM*) connected host interrupt generation/control facility cause invoke interrupt service routine. service routine then begin servicing request CD1400 starting acknowledge sequence. SVCREQ* Outputs connected host interrupt circuitry individually, thus using three unique interrupt-level inputs; they logically OR'ed together into single interrupt applied interrupt-level input. latter case, host examine SVRR determine which service requests active. method (single multiple interrupts) chosen designer will dependent system requirements hardware and/or board space limitations; CD1400 places restrictions likely that interrupt latency will slightly shorter with first method, since individual interrupt levels cause software vector directly correct service routine without first checking source interrupt. matter which interrupt method used, result same. Once host recognized that service request active, service acknowledge routine must executed satisfy request. There ways which start acknowledge force context switch: through four hardware input pins, making specific modifications internal registers.
7.3.1.1
Hardware-Activated Context Switch
internal register manipulation that involved context switch forced through Service Acknowledge (SVCACK*) Input Pins CD1400. There SVCACK* each service request type: SVCACKR* receive service requests, SVCACKT* transmit service requests SVCACKM* modem signal change service requests. Each these inputs special-case chip select that causes CD1400 servicing that particular service request type requesting channel. Note that Input activated service acknowledge cycles. Instead, appropriate SVCACK* Input DGRANT* Inputs used. DGRANT* will discussed description daisy-chaining multiple CD1400s "Service Requests Multiple CD1400s" page Figure shows generalized logic diagram hardware interface SVCACK* Inputs. service acknowledge, SVCACK* address locations will accessed instead location. host, service acknowledge cycle read cycle. data that CD1400 places during read cycle contents Interrupt Vector Register (RIVR, TIVR MIVR) associated with service acknowledge input that active (SVCACKR*, SVCACKT* SVCACKM*). upper five bits Vector Register whatever previously loaded into LIVR host; lower three bits will supplied CD1400, indicating type interrupt (vector).
CD1400 UXART Serial/Parallel Controller
Figure Control Signal Generation
AD[6:0]
CD1400 ADDRESS HOST ADDRESS DECODE LOGIC SVCACKR* SVCACKT* SVCACKM*
DB[7:0]
DGRANT* HOST CONTROL R/W*
HOST DATA
time CD1400 ready post service request, copies upper five bits LIVR into appropriate Vector Register (RIVR, TIVR, MIVR) then places request type vector lower three bits. table below shows assignment request type bits. transmit modem service acknowledge cycles, data lower three bits will redundant host, since this information known because corresponding acknowledge taken place. However, these bits will important receive data service acknowledge because they provide indication whether request Good Data exception data. value contained upper five bits LIVR used number purposes. primary purpose LIVR source software vector that used host system index interrupt dispatch table. However, systems that cannot this require these bits purpose. multiple-CD1400 daisy-chained designs, logical value place these bits chip identification number. This discussed more detail daisychaining description "Service Requests Multiple CD1400s" page single-CD1400 design that does daisy-chaining (unique address range each device) does need value LIVR vector hardware interrupt response, convenient these bits channel encoding. Since each channel LIVR, these five bits have unique value identifying channel. doing this, there need read RICR, TICR MICR determine channel number; thus single operation, host determines both type interrupt number channel requesting service. fact, with five bits available, systems with small numbers CD1400s encode both channel number chip identification number LIVR. Once above been completed, CD1400 ready serviced type interrupt that been acknowledged. example, interrupt receive Good Data, host would read RDCR determine number characters available receive FIFO, then read that many characters successive reads from RDSR. Other work, such disabling future interrupts changing channel parameters could also performed this time. Once tasks involved servicing interrupt have been completed, further operation must performed. order inform CD1400 that service acknowledge complete, host must
UXART Serial/Parallel Controller CD1400
write dummy value EOSRR. data written does matter; value will What important write operation itself. This write forces internal context switch back normal Operating Mode.
used Group Modem signal change service request Group Transmit data service request Group Received Good Data service request used used used Group Received exception data service request Request Type
Summary Interrupt-Driven Service Requests
summary, actions that take place during interrupt request/service are: Host senses service request through interrupt request input from CD1400 service request outputs. Host responds performing read cycle that activates appropriate SVCACK* Input Pin. Host decodes value read from Vector Register during Step making decision type service request necessary). Host reads M)ICR determine channel number. Host services request (load transmit FIFO, read receive FIFO, Host writes dummy value EOSRR terminate service routine.
7.3.1.2
Software-Activated Context Switch
possible through host manipulation some internal registers cause context switch without activating SVCACK* Hardware Inputs. method used same that which used Poll-Mode-CD1400 design. Once host detected service request through interrupt response circuitry, then follow same procedures that polling method would once detected active service request. Refer context switching description following section. reason design might make this method that there limited board space available provide additional hardware address decoding required generate three SVCACK* DGRANT* Control Signals. system gains advantage having constantly check active service requests polling CD1400; will interrupted when request posted then examine internal CD1400 Registers determine source channel number generating that request. this method chosen, three SVCACK* DGRANT* Input Pins should tied inactive (logic `1') prevent false activation service acknowledge cycle noise. They should terminated with resistor, hard-wired VCC.
CD1400 UXART Serial/Parallel Controller
7.3.2
Polling
Poll Mode, hosts periodically checks CD1400 there active service requests. detects any, proceeds service them through software-driven technique. There several registers within CD1400 provided specifically facilitate Poll Mode service request detection acknowledgment. These SVRR, RIR, TIR, MIR, RIVR, TIVR MIVR. "Detailed Register Descriptions" page provides detailed definitions these registers. SVRR (Service Request Register) Master Service Request Register. least-significant three bits (Bits 2:0, SRM, SRT, SRR) reflect inverse state three Service Request Output Pins (SVCREQM*, SVCREQT* SVCREQR*). example, (SRR) `one', indicates there active receive data service request pending, that SVCREQR* Output active (low). Thus, with single read, host determine CD1400 needs service and, which ones active. Each service request type Interrupt Request Register; receive, transmit modem. These special-purpose registers that used with force context switch start service acknowledge procedure. When service request particular type pending, corresponding Interrupt Request Register with appropriate data cause context switch requested type requesting channel. When host ready service request, reads contents Request Register copies into CAR. action writing this value into forces context switch, CD1400 ready serviced. This same result service acknowledge cycle been performed with SVCACK* Pin. Each Interrupt Request Registers provides channel number that requesting service least significant bits. most-significant three bits provide status control over internal interrupt sequencing. middle three bits contain code that used hardware service acknowledge cycles (write EOSRR) tell which type acknowledge cycle ending. Each three registers unique code these three bits that select proper service acknowledge type; however, they meaningless Poll Mode operation. service request operation, host must inform CD1400 that request been satisfied take service request context. This done writing value that Interrupt Request Register back into after first clearing upper bits. with hardware-driven request/acknowledge procedure, virtual registers should only accessed after context switch been made. Their contents undefined until this time.
Summary Poll Mode Service Requests
summarize, major steps involved Poll Mode service request/service acknowledge sequence are: Host scans SVRR periodically, checking three least-significant bits. them true (`1'), service request active. Depending which service request bits active, read appropriate Interrupt Request Register (RIR, MIR) copy contents into CAR. Perform service routine. Write original contents interrupt request register back with most-significant bits cleared.
UXART Serial/Parallel Controller CD1400
7.3.3
Service Requests Multiple CD1400s
Multiple CD1400s combined form systems with more than four channels. There number ways that more connected, provides more efficient service request/service acknowledge sequence allowing CD1400s arbitrate between themselves. This mode only works hardware-activated service acknowledges being utilized. CD1400 provides means `daisy-chaining' service request service acknowledgments more devices together. This allows them arbitrate priorities between themselves regarding which post particular type service request. This Fair Share interrupt scheme. Figure page shows that CD1400s would connected enable Fair Share function. open-drain request outputs CD1400s (SVCREQR*, SVCREQT* SVCREQM*) wire OR'ed together form request each type. This allows each monitor state others' outputs. Each Service Acknowledge Inputs (SVCACKR*, SVCACKT* SVCACKM*) also connected together form acknowledge each type. DGRANT* Input first CD1400 connected logical three SVCACK* Inputs; DPASS* Output first CD1400 drives DGRANT* Input second. Before request service particular type posted, checks current state `fair bit' internal interrupt register that type. inactive, indicating that fair post interrupt that type, request posted; otherwise, will wait. This guarantees that each CD1400 will have opportunity have this request type serviced when needed. When host acknowledges request, both CD1400s will receive acknowledge through SVCACK* Input. However, only first will receive DGRANT*. active request this type pending, will take acknowledge drive Vector Register (RIVR, TIVR, MIVR) onto data bus. does have request pending, will pass DGRANT* Input second CD1400 through DPASS* Output. Assuming that second active request pending, will take acknowledge drive Vector Register onto data bus. mentioned earlier, upper five bits LIVR will reflect whatever host loaded into them during initialization CD1400s. These bits must used unique chip identification number host will know which CD1400 responded service acknowledge. These five bits could binary zero LIVR first CD1400, binary second. host easily test determine which device responded. Some examples host service acknowledge software routines that show performing this task provided "Programming" page
Caution:
neither CD1400 pending request, DGRANT* will passed second neither will respond, thus causing cycle hang. only time this could happen would error condition outside CD1400s that caused host respond request that made. mechanism should provided terminate abort cycle this error should occur. This accomplished with time-out circuitry DPASS* output second CD1400 activate abort condition. Other devices share daisy-chain mechanism could connected DPASS* output second whichever last) CD1400 chain. actual
CD1400 UXART Serial/Parallel Controller
implementation system-dependent, important provide some host know that cycle complete normally device exists chain. Figure CD1400 Daisy-Chain Connections
ADDRESS DECODE LOGIC
SVCACKR* SVCACKT* SVCACKM*
SVCACKR* SVCACKT* SVCACKM*
DGRANT* DPASS* SVCREQR* SVCREQT* SVCREQM*
DGRANT* DPASS* SVCREQR* SVCREQT* SVCREQM* CYCLE ERROR
Serial Data Reception Transmission
CD1400 four channels, each with receiver transmitter. Although receiver transmitter pair associated with each channel, many respects they operate independently, sharing only parameter settings regarding character format such length, parity type, any, number stop bits. Each receiver transmitter baud-rate generation function, allowing channel send rate receive another. Shared independent parameters shown diagram below:
UXART Serial/Parallel Controller CD1400
Receiver
Baud Rate
Transmitter
Baud Rate
Parity Character Length Stop Bits Prescale Period Register FIFO Thresh Time-out Channel service requirements, such empty transmit FIFO, indicated host three service request indicators: receivers, transmitters modem signal changes. internal processor (MPU) scans each channel sequentially service needs, posting request when detects particular type. continues Fair Share scheme used external daisy-chain configuration allowing channel post another request type until other channels have posted their requests that type, any. example, Channel currently being serviced transmit request Channel pending, request from Channel will posted before Channel able make another request transmit service. Each receiver transmitter 12-character FIFO. receiver additional character holding locations, Receive Character Holding Register Receiver Shift Register. transmitter also additional locations, Transmitter Holding Register Transmitter Shift Register. receive FIFO programmable threshold that sets level which service request will posted. When data reaches this `high water' mark, request will made host empty FIFO. More details this provided following section. Receive FIFOs also have programmable threshold that, when reached, cause Output deasserted (see flow-control description). asynchronous serial data protocol, message consists `character', made bits, either high low, representing zero value. character made from five eight bits, plus optional parity bracketed Start least Stop Bit. Each time duration that sets data transmission rate, baud rate. Start indicates beginning character stream indicated transition from logic logic (mark space) transmission media. Start lasts `bit time' immediately followed Data Bits parity, any, Stop Bit(s). previously discussed, CD1400 incorporates special hardware receive transmit each bit. These `bit engines'. They perform timing associated with sending receiving serial data bit. engine behaves differently depending whether sending receiving. When complete been received, engine interrupts that handle character level. This usually entails addition character being assembled. transmitting, transmit-bit-engine interrupt causes give next transmitted. bit-engine interrupt happens time, which been timed engine, thus removing that duty from MPU.
CD1400 UXART Serial/Parallel Controller
7.4.1
Receiver Operation
Each channel programmed receive characters with several different parameters, such character length, parity, number stop bits, FIFO threshold baud rate. Each receiver independent other receiver. also different baud rate from corresponding transmitter. Before valid data received, host must each channel programming desired operational parameters Channel Option Registers (COR1-COR5) Baud Rate Generator Registers (Receiver Clock Option Register Receiver Baud Rate Period Register RCOR RBPR). Once these set, channel enabled issuing receiver enable command through enabling service requests Service Request Enable Register (SRER). Once receiver enabled, engine begins scanning Input valid Start Bit. does this detecting falling-edge transition input. When transition detected, engine delays until middle programmed time checks input again. input still low, then start considered valid character assembly begins. each subsequent full time, input checked level recorded value next bit. center time, Input returned mark state, then Start considered invalid engine goes back Start Detect Mode. Following valid Start Bit, engine begins receiving data bits. programmed number bits, following bits checked parity enabled) valid Stop Bit. valid Stop defined mark logic input. valid Stop detected, framing error will noted character. After properly assembled framing error) character been received, checked several special conditions, overflow condition before placed receive FIFO. (See "Transmit Special Character Processing" page special character handling "Flow Control" page 45.) errors special character processing required, character considered Good Data placed directly FIFO. errors exist, placed FIFO `exception' data along with status indicating type error. each good character placed FIFO, Receive Data Count Register (RDCR) updated reflect number good characters currently FIFO. receive FIFO programmable threshold that determines level which CD1400 will request receive data service. This level programmed through RxTh3-RxTh0 Bits Channel Option Register host place threshold number characters from Note that this only sets level which CD1400 will post service request, depth FIFO. When host responds receive Good Data service request, read number characters FIFO, from zero number indicated RDCR before exiting service routine. number read zero, CD1400 will post another request service almost immediately. number characters read less than number indicated RDCR enough such that number FIFO falls below threshold, request will made until threshold once again exceeded. term `almost immediately' used above because, since scans channels `round-robin' fashion, another channel post receive service request before this channel again opportunity.
7.4.2
Receiver Timer Operations
Also associated with each receiver FIFO timer whose duration Receive Time-out Period Register (RTPR). This timer provides services relation receive FIFO operation: time-out prevent `stale' data FIFO time-out after last character taken
UXART Serial/Parallel Controller CD1400
FIFO. first type, Type will occur receive FIFO does reach threshold before programmed time period expires second, Type will occur timer expires data been placed FIFO after last character removed; this called Data Time-out (NNDT) service request. timer driven prescaled clock generated Prescale Period Register (PPR) global register set. timer loaded with value contained RTPR each time character placed receive FIFO when last character removed from FIFO. Each `tick' prescaler decrements timer. timer reaches zero receiver interrupts enabled, will generate receive data service request time-out conditions, depending which valid.
Type
there characters FIFO threshold level been reached, Good Data service request will posted when timer expires. This function provided prevent data from remaining FIFO long (potentially infinite) periods time because remote send enough data fill FIFO threshold level. This time-out cannot disabled.
Type
there data FIFO when timer expires Data Time-out (NNDT) service request enabled SRER, receive exception service request will posted with status indicating time-out condition. This time-out optional, provided that host driver software detect possible block data allows buffers flushed higher, operating system level. NNDT will posted only first occurrence timeout after FIFO becomes empty. Also note that NNDT timer started last character removed from FIFO exception character, such break parity error. flow chart Figure page shows timer process evaluation performed when timer reaches zero.
7.4.3
Receive Exceptions
Several conditions cause CD1400 evoke receive exception service request. exception condition occurs, bytes placed receive FIFO. first status indicating type error second data itself. Exception data given host event time. That there will separate service request each character that received with some special condition. when exception condition occurs, receive FIFO Good Data Good Data receive service request will posted immediately upon receipt data, regardless number characters FIFO programmed threshold. This allows host remove data FIFO ahead exception data that CD1400 post service request error condition. Once host terminates service acknowledge procedure Good Data, service request will posted exception data. When host acknowledges receive exception service request, reads Receive Data/ Status Register (RDSR) first status second data. Reading data optional: host does read FIFO twice during service routine, CD1400 will update internal FIFO pointers appropriately discard second byte. (Actually, host
CD1400 UXART Serial/Parallel Controller
need read data from FIFO during exception service acknowledge FIFO pointers will update correctly service routine, discarding both status data. Thus, host must read least status, will lost forever.) Another special case exception data handling received-line-break conditions. line break character with zero data parity Stop Bit. this case, null (zero) character placed FIFO with break condition indicated accompanying status receive exception service request will posted. However, regardless length break, only character will placed FIFO. `end-of-break' option enabled, another null character placed FIFO with status indicating end-of-break condition, once detected receive data stream. This option enabled (Bit COR5 "Channel Registers" page details. Resumption normal character reception will cause data again placed FIFO. Refer register definitions "Detailed Register Descriptions" page description status bits RDSR.
7.4.4
Transmitter Operation
Each four channels CD1400 capable transmitting characters with number programmable characteristics such length, parity baud rate. channels operate independently settings have effect operation another. After being reset, from either hardware (RESET* Input Pin) software (through master reset command CCR), transmitters disabled with Output held logic condition. This off, mark, condition asynchronous protocol. Before operation transmitter begin, host must program appropriate parameters Channel Option Registers (COR), Clock Option Register (TCOR) Transmit Baud Rate Period Register (TBPR). Once these registers set, channel enabled issuing transmit enable command through enabling service requests setting appropriate transmit enable request bit(s) Service Request Enable Register (SRER). channel will immediately post transmit service request since FIFO empty. host responds request loading characters into transmit FIFO through Transmit Data Register (TDR) after places CD1400 Service Request Acknowledge Mode (see description service request/service acknowledge procedures "Poll Mode Examples" page 75). transmitter does begin transmitting characters until host terminates service routine writes EOSRR. Transmission begins sending Start (logic '0') followed five eight data bits (depending programmed value), least-significant first. last data followed appropriate parity bit, enabled, minimum stop bit. transmission handled transmit engine with giving each required. there still characters FIFO, next will transmitted immediately after last stop previous character. This process continues until characters FIFO have been transmitted. CD1400 will then post service request more data. There actually transmit character holding locations each channel: FIFO, Transmitter Holding Register, Transmitter Shift Register itself. CD1400 programmed, per-channel basis, request transmit data when conditions exist: when last character FIFO transferred Holding Register when last data last character shifted Transmitter Shift Register. first option allows host character transmit times which reload FIFO prevent transmit data underrun. This normal mode operation. second mode used make sure transmitter empty before reconfiguring channel. likely that transmitter will underrun second option chosen unless host sufficiently fast enough respond transmit service request reload FIFO during transmission stop bit(s) last character. transmitter
UXART Serial/Parallel Controller CD1400
underruns, will continue send stop bits (mark) until more data placed FIFO. Normally, when string characters greater than being transmitted, host software will program CD1400 transmitter post service request when FIFO becomes empty. When last data send been placed FIFO, service request enable changed that requests made after last character sent. This allows host know that data been transmitted before disabling channel. channel disabled, characters other than currently being transmitted will held transmitter will enter marking state. channel subsequently re-enabled, remaining data will transmitted. transmitter capable performing several special functions such break generation, intercharacter delays automatic flow control. These functions discussed sections describing special character handling (embedded transmit commands) flow control.
7.4.5
Transmitter Timer Operations
with receiver, transmitter timer associated with This timer used generate timing embedded transmit commands that send line breaks inter-character delays. Whenever detects embedded transmit command specifying delay command, loads timer with value contained parameter byte. This timer decremented each `tick' prescaler timer (PPR) until reaches zero. that time, delay terminated unless next character FIFO beginning another delay-command sequence.
CD1400 UXART Serial/Parallel Controller
Figure FIFO Timer Processing
from other background processing
background scanning detects character arrived
TIMER
character FIFO reload timer FIFO empty resume background scanning loop
post receive Good Data service request
Data Time-out Enabled
Data internal flag armed clear NoNewData internal flag
post receive exception service request
resume background scanning loop
UXART Serial/Parallel Controller CD1400
Flow Control
data communications applications, data sent from system another through some protocol. Most systems have some method buffering data transmission reception. asynchronous protocol, there way, protocol level, determine length data transmission; therefore, normally possible aside buffer area that known handle entire length transmission. Also, hardware receiving data generally limited amount buffer area, usually FIFO, host does unload data fast enough pace, buffer FIFO overflow. these reasons, methods provided that used stop remote from sending data until room once again available receive data. This known flow control. Flow control in-band out-of-band. In-band flow control makes special characters that sent host stop data transmission. Out-of-band flow control signals outside serial data channel that perform same function. These Request Send (RTS), Clear Send (CTS) pair Data Ready (DSR) Data Terminal Ready (DTR) pair. CD1400 make either kind built-in capabilities automatically and/or semi-automatically (depending direction options chosen) without host intervention knowledge, desired).
7.5.1
In-Band Flow Control
mentioned, in-band flow control implemented special characters that imbedded serial data stream, request that transmission stop request resumption. characters chosen characters although conventionally (x'11) XOFF (x'13) characters used ASCII character being used. XOFF value designates character that used stop data transmission character determines character that used resume transmission. Whether ASCII XOFF Characters used, CD1400 allows characters value that appropriate system design value programmed Special Character Registers (SCHR1 SCHR2). SCHR1 defines Character SCHR2 defines XOFF Character.
7.5.1.1
Receiver In-Band Flow Control
When host senses need flow control sender, receive buffer filling fast service, request that remote stop transmission sending XOFF character through transmitter. This accomplished issuing Send Special Character command through Channel Command Register (CCR). CD1400 will then transmit whatever character programmed SCHR2. discussed earlier, send special character command preemptive data currently transmit FIFO, thus XOFF character will transmitted after currently transmitting character character Transmitter Holding Register have been sent, maximum delay character times. When host again ready start receiving characters, sends Character, also through send special character command. This time, CD1400 issued command send whatever programmed SCHR1. Send special character commands will override remotes' flow-controlling CD1400; other words, even CD1400 transmitter been shut remote, still send flow control characters. current state flow control condition always made available host through Channel Control Status Register (CCSR). addition enabled/disabled status receiver transmitter, CCSR displays flow control status. bits CCSR pertain receiver flow control, RxFloff RxFlon. Whenever host issues send Special Character (send XOFF), CD1400 sets RxFloff Bit, indicating that requested remote stop
CD1400 UXART Serial/Parallel Controller
transmission. When host issues send Special Character (send XON) command, RxFlon RxFloff reset. RxFlon remains until first character received after transmitted. table below shows encoding RxFloff RxFlon. RxFloff/RxFlon Bits cleared whenever receiver disabled enabled, regardless state flow control when disable/enable occurred.
RxFloff RxFlon Encoded Status Transmission resumed, receiver been enabled/disabled receiver default reset state been sent, transmission restarted XOFF been sent Used
Note:
Regardless current state RxFloff, CD1400 continues receive characters. remote ignores slow respond XOFF Character, there possibility overruns.
7.5.1.2
Transmitter In-Band Flow Control
CD1400 ability automatically flow control transmitter when receives XOFF Characters, programmed SCHR1 SCHR2. Control Bits Channel Option Registers (COR2 COR3) enable disable various aspects automatic flow control. order flow control characters acted upon, special character detection must enabled through (Special Character Detect SCD12) COR3 (TxIBE) COR2. When these bits set, CD1400 will scan received characters match with special characters programmed SCHR1-SCHR2. enabled, received character matching contents SCHR2 (the XOFF Character), CD1400 will then check automatic transmit in-band flow control enabled through COR2. this function enabled, CD1400 will cease transmission after currently transmitting character character transmitter holding register, any. enabled, CD1400 will also attempt match against erroneous characters. This function enabled through CMOE COR5. other Control COR2 involved flow control activities. This Implied Mode, IXM. This determines what character will restart transmission after automatic flow control caused stop. zero, only programmed Character (SCHR1) will restart transmitter; other characters will received placed FIFO normally. set, character received will restart data transmission. with receiver flow control, host always determine current state transmitter through bits CCSR: TXFloff TxFlon. When automatic in-band flow control enabled CD1400 receives XOFF character, sets TxFloff. When character received, TxFlon set. Once transmission actually resumes, TxFlon cleared. encoding shown table below. TxFloff/TxFlon Bits cleared whenever transmitter disabled enabled, regardless state flow control when disable/enable occurred. This feature used force resumption transmission regardless remote initiated flow control.
UXART Serial/Parallel Controller CD1400
TxFloff
TxFlon
Encoded Status Transmission resumed, transmitter been enabled/disabled transmitter default reset state been received, transmission restarted XOFF been received, transmission stopped Used
There final aspect automatic in-band flow control: Flow Control Transparency (FCT) which enabled/disabled COR3. determines whether remote flow control will transparent host. this set, addition stopping transmission when XOFF received, CD1400 will place received XOFF Character receive FIFO inform host reception through receive exception service request. When Character received, will given host through exception service request well restarting data transmission. enabled, received flow control characters will control transmission they will discarded rather than placed FIFO. host system software doesn't need informed when transmit data been stopped, this reduce number service requests that must handled. table below summarizes Control Bits Channel Option Registers that enable various modes in-band flow control.
7.5.2
Out-of-Band Flow Control
Flow control also accomplished through modem handshake signal pairs RTS/CTS DSR/DTR. These called out-of-band flow control because they external data channel. CD1400 programmed automatically respond generate out-of-band flow control through these signals.
7.5.2.1
Receiver Out-of-Band Flow Control
Along with receiver FIFO threshold that sets level which CD1400 will post service request, another threshold that determines when will automatically assert/deassert DTR* Output enabled. This threshold enabled through DTRth3-DTRth0 Bits Modem Change Option Register (MCOR1). level number characters from with threshold disabling function. function receiver enabled, CD1400 will automatically assert DTR* Output whenever number characters receive FIFO less than programmed number. Once level reaches threshold, DTR* will deasserted. DTR* will held deasserted state until host removes enough characters from FIFO lower level below threshold. order receiver operate properly, threshold must value equal higher than receiver service request threshold. levels were reversed, normal character reception could completed because DTR* would always deasserted before receive FIFO threshold reached, thus host would receive data service request until receive FIFO time-out reached. serial data transmission performance limitation would result. DTR* Output also controlled manually through Modem Signal Value Register (MSVR2). Setting this will assert DTR* Output.
CD1400 UXART Serial/Parallel Controller
DSR* Input also used flow-control receiver. this mode enabled through COR2 (DSR Automatic Enable DsrAE), characters received while DSR* deasserted will discarded.
Name SCD12 TxIBE Register COR3 COR3 COR2 COR2 Function Enables recognition Special Characters Enables transparent flow control Enables automatic transmitter in-band flow control Enables implied Mode
7.5.2.2
Transmitter Out-of-Band Flow Control
Transmitter out-of-band flow control implemented with three Modem Control Signals: RTS* Output CTS* DSR* Inputs. RTS* Output programmed automatically asserted whenever there data transmit FIFO transmitter cleared send. CTS* DSR* enabled automatically control transmitter. Automatic Output (RtsAO) enabled through COR2. this set, CD1400 will automatically assert RTS* Output when there data FIFO send. When data been sent FIFO empty, RTS* will deasserted until host inserts more data. RtsAO set, host software must control RTS* output manually through Modem Signal Value Register (MSVR1) required remote. CTS* Input also monitored CD1400 used transmitter enable. function enabled setting (CTS Automatic Enable CtsAE) COR2. function enabled, character transmission will occur only when CTS* Input Signal asserted. signal deasserted during active transmission, current character plus character Transmitter Holding Register, any, will transmitted then transmission will cease. Thus, minimum maximum characters transmitted after control signal deasserted. Transmission will resume when signal(s) reasserted. send special character command does not, however, sample CTS* Input. host chooses send special characters, character will transmitted regardless state this input. most cases, this desirable that host `flow-control' remote even host itself flow-controlled. state CTS* important, should tested through MSVR1 before special character send command issued.
7.5.3
Modem Signals General-Purpose
Each channel CD1400 four pins that used either modem-control generalpurpose input/output pins. modem signal names assigned these four pins have been chosen provide easy reference systems designers. fact, they simply general purpose inputs outputs automatic out-of-band flow-control used) that individually controlled through modem signal value register(s). Since they general purpose, system designers choose connect pins that suits application. However, when system software design chooses make automatic out-of-band flow control with pins, then signal naming convention longer holds true some cases, depending whether device used DTE. this case, best think pins terms their actual uses within CD1400 connect them accordingly, without regard
UXART Serial/Parallel Controller CD1400
their names. RTS* CTS* Pins associated with transmitter DTR* DSR* Pins associated with receiver. table below shows recommended signal hook-up automatic, out-of-band flow control desired.
CD1400 Pins Out-of-Band Flow Control Signal remote transmit implemented this direction Request remote permission transmit Enable transmitter
example, CD1400 designed automatic out-of-band flow control desired, labeled should connected remote input. CD1400 used side, then CD1400 output would connected remote input. Note that automatic out-of-band flow control implemented, activity Pins implement function assigned those signal names signalling conventions CCITT other standards organization. These names would only apply these pins they under program control under automatic CD1400 control. fact, `DTR' function, defined, enables modem off-line, depending state pin. automatic control used, then would inactive when receive FIFO reached programmed threshold thus causing modem drop connection (carrier) remote, which would correct function.
Modem Control Pins RTS* CTS* DTR* DSR* Function Request Send (general-purpose output). Clear Send (general-purpose input). Data Terminal Ready (carrier detect/general-purpose input/output). Data Ready (general-purpose input). Carrier Detect (general-purpose input). Ring Indicator (general-purpose input).
Modem pins implemented ports accessible either CD1400 processor host. modem pins connected directly transmit receive hardware. When user programs out-of-band modem functions active, CD1400 processor will read from write these pins. Specifically, when RTS* CTS* being used transmit flow control, CD1400 processor will assert RTS* sense CTS*, required. Likewise, when configured Receive FIFO will negate DTR* when full. host should allowed re-assert inadvertently. host `locked out' accessing these bits; care should taken that these bits written causing system malfunction. user direct control over RTS* DTR* Outputs sense state CTS*, CD*, DSR* Inputs through Modem Signal Value Register (MSVR). Since host accessing these pins directly, there delay host's ability detect level change. DTR* depend state DTRSEL input. When CD1400 programmed detect level changes generate service requests when level changes occur, does firmware reading pins comparing previously stored value. This function performed main timing loop firmware; maximum time required detect level change under worst-case conditions approximately milliseconds.
CD1400 UXART Serial/Parallel Controller
When CD1400 performing this function, modem pins periodically sampled rather than continuously monitored; such they have very little sensitivity noise, which desirable data communication applications. However, extremely noisy applications, re-read modem line which caused Modem Signal Change Service Request verify that indeed changed merely malfunctioning. This will eliminate even slight possibility noise pulse causing erratic operation. When CD1400 monitoring modem pins control transmit receive functions, does rely previously stored value, checks pins appropriate time. Thus, there very little delay this response. example, before deciding transmit another character, will examine CTS* that time. (The CD1400 makes this decision when moving characters from FIFO Holding Register, from Holding Register Shift Register.) Note that logical sense modem bits inverted; that writing MSVR1 MSVR2 causes output nominal zero volts. Likewise, low-voltage input will sensed `1'.
7.5.3.1
Generating Service Requests with Modem Pins
CD1400 generate service requests when input pins changes state. Either both edges detected setting bits Modem Change Option Registers (MCOR1 MCOR2). each pin, user individually enable on-to-off off-to-on transition detection inputs. When CD1400 detects such transition, sets corresponding Modem Change Register. corresponding channel's Interrupt Enable Register set, CD1400 will assert IREQ1* Output. user must clear Modem Change Register during service request service routine before writing EOIR. CD1400 performs this task reading modem input signals comparing current value with value read last pass through outer scanning loop. Because this lowest-priority event CD1400 scanning loop, changes detected unless they several hundred microseconds long. Modem Input Pins used purposes such detecting closing switch. However, relatively slow speed response should taken into account when using Modem Input Pins this purpose. CD1400 does latch Modem Input Signals.
7.5.3.2
Using Modem Pins General-Purpose
Since modem pins directly accessed host, they used general-purpose pins they needed flow control modem interfacing. Simply read from write them port.
Receive Special Character Processing
CD1400 several means sending special characters ways which processes these characters when receives them. Some special characters have fixed definitions some user-defined. flow-chart this section defines processing that CD1400 performs receive data. chart understanding special character handling process.
UXART Serial/Parallel Controller CD1400
7.6.1
UNIX Character Processing
CD1400 incorporates special character processing that particular benefit systems designed UNIX operating system. processing performs some functions normally handled `line discipline' part serial device driver program. effect this higher overall performance serial communication than would otherwise obtained because character manipulation takes place hardware level without host action. This processing includes carriage return (CR) line (NL) substitution, programmable response errored characters (framing, parity overrun errors), LNext function ISTRIP. Each types processing optional; any, none them enabled/disabled through control bits Channel Option Registers two, four five (see detailed register descriptions format COR2, COR4 COR5). This section gives detailed descriptions each functions. Channel programmed parallel channel, only transmit special character processing occurs, such repeat space carriage return line translation.
7.6.1.1
Line-Terminating Characters
CD1400 programmed perform automatic substitution carriage return (CR) line (NL) characters both received transmitted data. Received character processing five unique substitutions based value three bits COR4 IGNCR, ICRNL INLCR (some combinations cause identical actions): nothing function enabled Received changed Received changed Received change received changed Received discarded Received discarded received changed Received discarded Received discarded received changed
7.6.1.2
Errored Character Processing
CD1400 provides number ways handle characters that received with errors (parity, framing overrun errors). none special processing functions enabled, errored characters delivered host through receive exception service request. Alternatively, these characters handled following ways, defined PE[2:0] Bits COR4:
Parity errors ignored character placed FIFO Good Data given
host other received Good Data.
errored character replaced with NULL (x'00) character FIFO. errored character replaced FIFO with three byte string x'FF character. this mode enabled actual good x'FF character received, replaced FIFO x'FF characters.
CD1400 UXART Serial/Parallel Controller
errored character discarded.
Received breaks handled little differently from other errored characters. They processed, based settings IGNBRK -BRKINT Bits COR4,
Reported errored character through received exception service request. Replaced with good NULL (x'00) character FIFO. Discarded
7.6.1.3 LNext
This function provides means `escaping' ignoring special meaning special characters treats them normal data. escape character defined value Register. CD1400 receives this character, will next character FIFO without further processing. This allows, example, flow-control character received without actually causing flow-control activity. LNext enabled operate even characters that received with errors (parity, framing, overrun), otherwise errored characters handled normally next character escaped.
7.6.1.4
ISTRIP
ISTRIP simple function that, enabled, resets most-significant (Bit received good characters. character parity framing error, ISTRIP function does nothing character given host through normal receive exception service request.
7.6.2
Non-UNIX Receive Special Character Processing
addition UNIX special character processing, CD1400 provides other special character recognition capabilities. CD1400 four registers that define special characters, SCHR1SCHR4. these, SCHR1 SCHR2 used flow control activities were discussed flow control section. SCHR3 SCHR4 define additional special characters that CD1400 scan receive data stream. Recognition Special Characters enabled SCD34 COR3 (Bit either these received, cause special character detect (receive exception) service request. should noted that automatic in-band flow control enabled, SCHR1 SCHR2 still used special characters. They will detected reported receive exceptions, will cause flow control activities invoked. Another special character function range detect function. this mode enabled (through SCDRNG COR3), CD1400 will compare received characters against values Special Character Range (SCRL) Special Character Range High (SCHL). character received falls between these values (inclusive), special character detect service request will posted. status shown RDSR indicates which special character recognition conditions were that caused receive exception service request. RDSR description register definitions in"Detailed Register Descriptions" page encoding.
UXART Serial/Parallel Controller CD1400
Figure CD1400 Receive Character Processing
Character Received
Parity, Framing, Overrun error
Errored Char Flag
Break
Break Flag
ISTRIP Enabled
Char Match Error Enabled
SCHR12 Enabled
LNext flag
Clear LNext Flag
LNext Mode Enabled
Char LNext
LNext Flag
(Continued next page)
CD1400 UXART Serial/Parallel Controller
XOFF Character
Character
Toggle Flow State
Flow
Character
Clear Flow
Implied Mode
Clear Flow Flow Control Transparency
SCHR34 Enabled
Character Match
Done
Enabled
Character Range
Special Character Exception
Done (Continued next page)
UXART Serial/Parallel Controller CD1400
CASE: Nothing Discard Discard Discard Discard
CR/NL Processing Enabled
Char
Parity Error Handling `100'
Parity Error Flag
Char x'FF
char FIFO
Parity Error Flag
FF,00, char FIFO
char FIFO
Parity Error
Handling
`011'
Parity Error Handling `010'
Parity Error Handling `001'
Post Exception Service Request
FIFO
Discard Char
Char FIFO
Break Flag
Break Processing Mode `11'
Break Processing Mode `10'
Post Exception Service Request
Char FIFO
Discard Char
FIFO
Done
CD1400 UXART Serial/Parallel Controller
Transmit Special Character Processing
CD1400 also provides some special character handling transmit side; embedded
transmit commands direct commands that cause transmission predefined special characters. flow chart (Figure page included this section help describe process special character handling.
7.7.1
Line Terminating Characters
transmit, there four possible substitutions based setting flags COR5 (Bits ONLCR OCRNL): nothing function enabled Change <CR> characters <NL> Change <NL> characters <CR> <NL> characters changed changed <CR> <NL>
last case, where both flags set, only translations will take place. other words, that been changed will then changed into CRNL.
7.7.2
Embedded Transmit Commands
CD1400 special feature that optionally allows specific `escape' character sequences transmit data stream interpreted commands. These called Embedded Transmit Commands (ETC) enabled Channel Option Register They used insert programmed time delays between characters generate line break transmit data output. enabled, detected when two- three-character `escape' sequence detected transmit FIFO. escape-character sequence made special escape character followed command character optional count delay period. escape character all-zero (null) character. should confused with ASCII character, which hex; this discussion, refers null character. Five commands supported command set:
ESC:
Send character. This command sequence provided allow character sent alone. Thus, this `escapes' escape when actually desired send null character.
x'81:
Send BREAK. This causes transmitter enter line-break condition least character time. Several conditions control continuation and/or termination line break. there more data FIFO following send break command, break will continue indefinitely until terminated stop break command. there insert delay command (see next command) immediately following send break command, break duration will
UXART Serial/Parallel Controller CD1400
value programmed delay command. other character FIFO immediately following send break command carries `implied' break condition, causing break terminated next character sent.
x'82 x'xx:
Insert delay. This command will cause delay between previous character transmitted next character transmitted. value contained third byte sequence determines time delay based basic time period Prescale Period Register (PPR). value treated unsigned binary value that loaded into internal counter. counter decremented once each `tick' prescale period timer. Thus, sets basic timing period value command (x'64), then delay second will generated. Multiple insert delay commands placed FIFO time delays longer than that generated single delay period needed. This command useful when delay required after sending carriage return. printer example this type situation. Often, carriage return causes printer start print cycle sending device must wait print complete before sending next line text (unbuffered input). Using insert delay command allows delay performed automatically without need host time delay command placed FIFO directly following carriage return preceding first data next line. CD1400 will automatically execute delay following carriage return then start sending characters again. Another useful application delay command built-in timer that host interrupt source causing periodically check internal buffers data transmit. This assumes that channel currently transmitting data. When host services transmit FIFO service request after delay time-out, delay value, start transmission buffer data available re-send insert delay command wait next service request. This removes necessity host setting internal timer interrupt perform same function.
x'83:
Stop BREAK. This command will terminate break progress regardless other conditions. This command preceded insert delay commands specific, programmed break period more than character time needed. character FIFO will cause break terminate. x'83 needed only necessary stop break there more data sent. break will continue until another character sent x'83 encountered FIFO.
x'01- x'3F:
Send Repeat Space. This command will cause CD1400 send repeated space characters. character following interpreted binary count specifying number ASCII space (x'20) characters send. count must range x'01 through x'3F (1-63 decimal), inclusive.
7.7.3
Send Special Character Command
CD1400 has, host commands, method transmitting four special characters programmed Special Character Registers SCHR1-SCHR4. command issued through with least significant three bits encoding selection
CD1400 UXART Serial/Parallel Controller
four characters (see "Detailed Register Descriptions" page details bitencoding). function preemptive, meaning that selected character will transmitted immediately following currently transmitting character character transmitter holding register, any. This preempts characters transmit FIFO. there characters transmit FIFO, transmission those will resume after special character sent. ignored CtsAE set. important this command that allows host flow-control remote without having wait transmit FIFO empty before flow control character This special case normal transmitter operation CD1400 that character sent without waiting transmit service request. only requirement that transmitter enabled (interrupts need enabled).
UXART Serial/Parallel Controller CD1400
Figure CD1400 Transmit Character Processing
Ready Next Character
Delay Time
Repeat Char Mode Active
Decrement count, send `space'
Embedded Command Progress Reset Embedded Command Progress
Count Clear repeat Char Mode
Char x'81
Send Break
Char x'82
Delay Time
(Continued next page)
CD1400 UXART Serial/Parallel Controller
Char x'83
Stop Break
Char x'00 Char x'01 x'3F
Send `00' char
Initialize repeat char count repeat char `space' repeat Char Mode
Illegal Condition: Send this char
Char
Enabled
Embedded Command progress flag
(Continued next page)
UXART Serial/Parallel Controller CD1400
Char Translation Enabled
Perform processing specified
Send Char
Exit
Baud Rate Generation
CD1400 provides separate baud rate generator each direction each channel. Each receive transmit baud rate generator driven from five available clock sources. source being used selected value Receive Clock Option Register (RCOR) Transmit Clock Option Register (TCOR). selected clock divided value Receive Baud Rate Period Register (RBPR) Transmit Baud Rate Period Register (TBPR) yield desired rate. five clock sources are: Clk0 Clk1 Clk2 Clk3 Clk4 System clock divided RCOR/TCOR System clock divided RCOR/TCOR System clock divided 128, RCOR/TCOR System clock divided 512, RCOR/TCOR System clock divided 2048, RCOR/TCOR
CD1400 UXART Serial/Parallel Controller
system clock external clock driving Input CD1400. Four example baud rate tables provided "Programming" page
Diagnostic Facilities Loopback
CD1400 provides capability perform loopback testing internally both local remote loopback modes. Loopback Mode enabled through Local Loopback Mode (LLM) Remote Loopback Mode (RLM) Bits COR2. local loopback, output transmitter engine connected directly input receiver engine input output pins (TxD RxD) disconnected. Output left mark condition that remote equipment does sense line activity. Input conditions ignored. channel parameters service request functions effect operate normally. enabled, special characters detected acted upon UNIX translations occur. Remote Loopback Mode causes CD1400 echo received data immediately back Transmit Output. This done character-by-character rather than bit-by-bit; other words, characters echoed once they have been completely received assembled. Received data will placed FIFO, thus data given host. received character will retransmitted with parity Stop options defined COR1. important note that, transmit baud rate lower than receive baud rate, overrun errors loss data likely occur.
7.10
Parallel Channel Operations
Channel user-configurable either serial parallel port. selection operating modes made value P/S* (Bit Global Configuration Register (GCR). After reset, Channel configured serial port default. Host software reconfigures port parallel mode setting this `1'. port capable bi-directional operation, direction being enabled mode: transmit receive. receive mode, CD1400 drives PBUSY well PSTROBE* automatically. PBUSY, however, bi-directional handshake control: Transmit Mode, monitored CD1400. PACK* used acknowledge that transfer been completed. important note that when Channel configured parallel operation, several modem input signals other three channels taken over parallel channel provide necessary data control/status signals required support parallel interface definition Centronics parallel specifications. These Inputs (since they used bidirectional data transfer, they actually Input/Output Signals). These signals (RI[3:1]* CD[3:1]*) separate Parallel Data Input/Output Signals (PD[0] PD[1]) form bi-directional parallel data port. Other modem input/output signals Channel provide control status signals. data transfer handshake provided PSTROBE* Output PACK* Input. Note also that these signals never change direction; PSTROBE* always output PACK* always input. This normal signal name convention parallel data transmit. receive, PSTROBE* Output effectively becomes Transfer Acknowledge (ACK) Output function PACK* becomes Data Strobe (STROBE) Input function.
UXART Serial/Parallel Controller CD1400
Unlike some parallel interface devices which require host control generate timing handshake signals directly, CD1400 automatically generates PSTROBE* PBUSY Outputs monitors PACK* Input. This removes nearly host overhead data transmission reception other than putting data taking data FIFO. Since parallel data movement inherently half-duplex, CD1400 combines serial receive transmit FIFOs, plus some other registers needed Parallel Mode, into large, 30-byte FIFO. This further reduces host overhead providing larger buffering thus reduced service request activity. width PSTROBE* pulse value programmed least-significant five bits TBPR (the TCOR used Parallel Mode) multiplied system clock divided two. Thus, width duration range 33.3 1.03 (based 60-MHz system clock, values TBPR). best overall performance, RCOR/RBPR pair should generate bit-time slightly more than twice width expected pulse PACK* Input. PBUSY pulse width dependent duration between Strobe Input CD1400 Acknowledge Output (PACK* PSTROBE* delay; "Electrical Specifications" page 126). General operation parallel port same serial port. When channel Transmit Mode transmitter transmit service requests enabled, CD1400 will request service whenever FIFO empty. host responds writing bytes into FIFO. Carriage return line mapping occur transmit data same manner Serial Mode, enabled. Only send repeated space command embedded transmit command operative. receiver also works same Parallel Mode does serial. FIFO threshold trigger level between inclusive. However, interest highest possible performance, receive special character processing occurs.
7.10.1
Transmit Operation
When channel enabled transmit operation service requests enabled, CD1400 will transmit data whenever characters FIFO. Service requests programmed occur when FIFO becomes empty. There equivalent Serial Transmitter Empty Interrupt Parallel Mode, thus only TxRDY Interrupt SRER operational. Characters taken directly from FIFO placed parallel data pins transmission. Therefore, when FIFO empty indicated TxRDY SRER), there more data send `transmitter' empty. Data transmission controlled CD1400 through handshake signals PSTROBE* PACK*. When FIFO byte send, CD1400 puts eight bits data parallel port. After setup time, PSTROBE* Signal driven active (low) remains active time specified value programmed TBPR. PSTROBE* then deactivated data held until PACK* Input driven active (low) receiving device. PACK* only signal monitored automatically CD1400 flow-control purposes. state PBUSY, however, made available host through PSVR. Host software detect busy condition disable transmitter, necessary. Once PACK* becomes inactive, CD1400 will place next data byte port FIFO empty), cycle repeats. receiving device able accept data, hold cycle indefinitely activating PACK*. This provides parallel version flow control. Figure shows typical connection CD1400 parallel transmit interface, which printer this example.
CD1400 UXART Serial/Parallel Controller
Figure CD1400 Parallel Data Transmit Connections
CD1400
PRINTER
PACK*
PSTROBE* PD[7:0]
STROBE DATA
7.10.2
Receive Operation
receive operation Parallel Mode also very much like Serial Mode. receive FIFO threshold setting that determines level data required cause receive service request. threshold anywhere from characters. When number characters FIFO equals value threshold, CD1400 will post receive service request. sequence events receiving byte reverse sending, sending device places data parallel data port; after appropriate setup time, activates strobe out. strobe connected PACK* Input CD1400. When CD1400 senses active level PACK* Input, activates PBUSY indicate that taking data done. Once taken data, will activate PSTROBE* Output, which should connected sender acknowledge input. programmed pulse width duration (set TBPR), PSTROBE* PBUSY deactivated. Flow control happens automatically receive direction. FIFO full when next data byte being received, CD1400 will maintain PBUSY active (high) state will activate PACK*. Once host serviced receive FIFO removed least byte, thus providing space current byte, CD1400 will complete receive cycle acknowledging byte (activate PSTROBE*) deactivating PBUSY. Figure shows connections between CD1400 sending device such scanner. This connection might also seen application where CD1400 receiving device printer application.
UXART Serial/Parallel Controller CD1400
Figure CD1400 Parallel Data Receive Connections
CD1400
SCANNER
PACK* PBUSY PSTROBE* PD[7:0]
STROBE BUSY DATA
7.10.3
Programming Considerations
There guidelines that should followed optimum parallel port data transfer performance. These primarily related programming RCOR/RBPR pair, although programming TBPR properly also affects performance. Only TBPR used determining pulse width PSTROBE* Output when Channel programmed parallel port; TCOR used value `don't care'. Parallel Mode, transmit engine used PSTROBE* generation. Instead, PSTROBE* Output produced five-bit hardware counter that loaded with value contained least significant five bits register that itself loaded from TBPR each time channel enabled re-enabled). This five-bit counter loaded each time strobe generation cycle started. This happens simultaneously with activation PSTROBE* Output. counter decremented once each cycle internal clock (CLK divided when count reaches zero, PSTROBE* deactivated. general, TBPR should programmed produce shortest pulse width which receiving device reliably respond. Depending upon operating frequency clock (CLK), pulse width short (TBPR MHz) long (TBPR MHz). important note that time strobe width PSTROBE* changed (that value loaded into TBPR), change will reflected until channel re-enable, either receive transmit, performed through CCR. far, programming RCOR/RBPR pair will have most significant impact parallel port performance. explanation device works internally Parallel Mode will help make this apparent. same engine that used receive serial data used detect PACK* Signal. When CD1400 waiting active PACK* Signal, engine running `Start-Bit Detect' Mode. this mode, once detected leading edge PACK* Signal, times middle `bit' (one-half time, based programmed baud rate determined RCOR/RBPR pair) then generates interrupt MPU. This would normally time that start-bit validation would take place serial data. Parallel Mode, when executes `foreground' routine service this interrupt, checks PACK* Signal still present returned inactive state. still active, foreground process hands
CD1400 UXART Serial/Parallel Controller
duty searching PACK* background task terminates interrupt, since waiting PACK* become inactive during foreground processing would seriously degrade device performance. Figure Relationship between RCOR/RBPR PACK* Pulse
PACK*
Sample point highest performance. Data taken immediately scheduled.
Sampled early; foreground cannot take data. Task given background code, which will take data later, time dependent device activity. Data cannot acknowledged until data taken cycle extends generated until background completes task.
other hand, PACK* already returned inactive state, take appropriate action immediately, during foreground loop. case Receive Mode (when PACK* actually performing strobe input), retrieves data from parallel port inserts directly FIFO. Transmit Mode, allow background code schedule next character immediately. ability foreground code handle transaction greatly decreases response time since background code cycles through channels round-robin fashion. Thus there variable delay between each channel's processing time. highest performance will obtained when RCOR/RBPR pair programmed produce bit-time whose half bit-time just slightly longer than expected strobe width PACK* Input. this way, when foreground process begins execution, PACK* Input will have returned inactive state handle data transaction immediately. example, expected strobe width (100 kbaud), RCOR/RBPR pair should programmed produce effective baud rate little less than 50K, allow small margin error. produce this baud rate, RCOR would loaded with zero, which selects clk0 (CLK divided clock source RBPR would loaded with (hex 33). These numbers assume 20-MHz system clock (CLK). timing diagram Figure page shows sample point that yields highest performance, explained above.
7.11
Hardware Configurations
simplicity host interface CD1400 allows built into systems that popular microprocessors, such Intel 80x86 family (8086, 80286, 80386, on), Motorola family (68000, 68010, 68020, on), National 32x32 family (32CG16, 32332, 32532, 32GX32, on), AMD29000.
UXART Serial/Parallel Controller CD1400
7.11.1
Interfacing Intel Microprocessor-Based System
With little extra logic, CD1400 interfaced system based processor Intel 80x86 family. Figure page shows generalized view I/O-mapped interface with 80286-based system. provide proper strobes controls, IOR* IOW* control strobes used synthesize R/W* Signals. DTACK* used input waitstate generation logic that will hold processor necessary) until CD1400 completed request.
7.11.2
Interfacing Motorola Microprocessor-Based System
Interfacing 68000 family device straightforward. timing interface signal definitions very closely match those 68000 microprocessor, thus allowing direct connection most cases. With later versions (68020, 68030), some additional logic required generate DSACK0* DSACK1* functions that replace DTACK* earlier devices. example Figure page shows generalized interface 68020 device.
7.11.3
Interfacing National S
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