Complete Chipset based Asymmetric Digital Subscriber Loop (ADSL) Suita
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Complete ADSL Chipset
Complete Chipset based Asymmetric Digital Subscriber Loop (ADSL) Suitable either ATU-C ATU-R Designed ANSI T1.413 ETSI TR238 G.adsl (Category FDM) Standards Typical performance over loop: 6Mbps downstream, 224Kbps duplex. Also supports user-defined data-rates 4Mbps/512Kbps Internet access, 1.5M/224Kbps long reach) Absolute maximum 12Mbps/2Mbps Supports rate adaption variable data rates (32Kbps steps) optimize performance loop reach/ rate trade-off Complete software control protocol stack/API Implements many features Issue Meets strict mask requirements (exceeds Issue Complete Data-pump five compact ICs: Three 128TQFP, 80PQFP, VR15 Power: (excl. driver signal) operation
AD20msp910
GENERAL DESCRIPTION
This complete chipset implementing ADSL modems, designed ANSI T1.413 ETSI standard (Category FDM). includes components, including controller, analog front-end, driver/receiver software. same chipset used AD20msp910 uses standard modulation method, which highly resistant noise supports rate adaption deliver optimum performance over loop. example, standard performance 6Mbps/224Kbps over 12,000 feet, modem will easily reach more shorter lengths (absolute 12Mbps downstream 2Mbps duplex), achieve longer reaches reduced rate. This chipset complete solution, containing framer, transceiver, analog components (driver, receiver, filter) control processor. Also supplied object code software both modem complete management control functions (API protocol stack) that superset those defined T1.413, handles real-time functions (including performance logging statistics gathering). chipset also implements many features Issue standard. This complete solution reduces development time risk system designers.
Simplex data Duplex data AD6435 Framer/ Interface AD6436 Coprocessor AD6437 Analog Front
hybrid line POTS splitter
(interleave) ADTSP-2183 boot EPROM Control messages
AD816 Driver/receiver
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Table ADSL Category MODEM SPECIFICATIONS
SPECIFICATION Absolute Maximum Data Rates Downstream Duplex Typical Payload Data Rate T1.601 Downstream Duplex Typical Payload Data Rate Downstream Duplex ADSL overhead Downstream Duplex Bandwidth Bandwidth VALUE UNITS COMMENTS Actual performance primarily limited loop noise crosstalk. These figures apply bestcase loops, where limit function datapacking interfacing. Loop T1.601 (7,13) approximately 13,500 (4.2km 0.4mm) Configuration vary depending split assignments. This configuration corresponds default requirements T1.413 Loop (4,6,7) mid-CSA 12,000 (3.7 0.5mm) Other configurations possible, under software control.
12.288 2.048
Mbps Mbps
1.544
Mbps Kbps
6.144 0.11-1.1 30-85
Mbps Kbps kbps kbps
Category frequency division multiplexing. downstream signals. POTS located (0-4kHz). Till 30kHz guard band filters. Typical allocation bins 8-19 upstream, 20255 downstream. support power boost boosted 15dBm specified T1.413, tolerance 50ppm Actual loading depends sub-band swapping supported. This better than required T1.413
Power Power Width Symbols/Bin
4.3125 bits
Latency: Fast Channel Interleaved channel
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Table Bill Materials ADSL Generation
PART
AD6435XST
NAME
DTIR
DESCRIPTION
Digital Interface Implements Interface Elastic store operations, errorcorrection/detection etc. Discrete Multitone Engine. Performs core operations DMT. Complete single-chip analog front Integrates ADC, DAC, PGA, filters support analog circuitry. 16-bit general purpose fixed-point DSP, with internal RAM; version ADTSP-2181. Used training operations, general purpose controller system. AD8042AR AD826AR AD8042AR AD8072JR +26dBm distortion, high bandwidth line driver. Also includes op-amps used receive-side hybrid network.
PACKAGE
128TQFP
POWER
600mW 180mA, 3.3V 750mW 227mA, 3.3V 400mW 50mA, 250mW 76mA, 3.3V
AD6436XST AD6437XS
AFIC
128TQFP 80PQFP
ADTSP2183BST-115
128TQFP
Op-amps AD816AVR
HPF, DRIVER /Receiver
RT:3
8SOIC VR15 Surface mount DDPAK
30mW 6mA, 2.5W 2.1W Depends rate
these components included chipset.
Table Example Non-ADI Parts Needed
DESCRIPTION
32Kx8, 3.3V fast CMOS SRAM Interleave memory. required interleave path disabled. 35MHz VCXO Boot EPROM Wideband transformer hybrid Passives (for filters, decoupling etc)
EXAMPLE PART
IDT71V256SA
Champion Technologies K1523BA only)
AT&T
2718AF
These parts equivalents required complete modem, included reference design, part chipset. They listed here completeness.
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Table Power Requirements: ATU-C
Part AD6435 AD6436 ADSP2183 AD6437 AD8042 Core chipset AD816 Subtotal SIGNAL Supply Power Total Power
Digital Analog Analog 3.3V +/-15V 0.60 0.75 0.25 0.40 0.03 1.60 0.43 0.00 1.00 1.60 0.43 1.00 0.16 1.44 1.60 0.59 2.44 4.63
Table Power Requirements: ATU-R]
Part AD6435 AD6436 ADSP2183 AD6437 AD8042 AD812 Core Chipset AD816 Subtotals SIGNAL Supply Power Total Power
Figures Watts
Digital Analog Analog 3.3V +/-15V 0.60 0.75 0.25 0.50 0.07 0.04 1.60 0.61 0.00 1.00 1.60 0.61 1.00 0.12 1.08 1.60 0.73 2.08 4.41
These power budgets worst case (maximum data rate maximum reach) cases, using power levels specified T1.413. many cases, actual implementations will require lower power consumption, example lower data rate used. lower data rates, power dissipation driver (AD816) reduced dramatically reducing supply voltage. ATU-R, with lower upstream rate, this would allow operation off, say, even lower rail. addition, system design reduce power with power-down "sleep" options.
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Figure System Block Functional Diagram
Payload data Framer, TICL Elastic Store Insert Sync. Remove Elastic Store Payload data
Detect
AD6435 DTIR
Scrambler Unscramble
encode Tone shuffle
Interleaver
Deinterleaver
decode
ADTSP2183
Tone reorder
Constellation encode
Training Line Probing UPdating Bitswapping
AD6436
Inverse
Constellation decode System interface Performance Logging Entity Management
Interpolate
Decimate, filter equalizer
Control
Serial VCXO)
AD6437 AFIC
Filter
Filter
Driver
AD816 Driver /Receiver
Hybrid Transformer
POTS Splitter
POTS
Line
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AD20msp910 Complete ADSL Chipset
SYSTEM DESCRIPTION
ADSL chipset optimized ANSI T1.413 compliant systems. consists dedicated digital ICs, which handles digital interfacing processing, other core functionality; single-chip analog front end, integrating mixed-signal analog signal processing into package; power driver/receiver general-purpose 16-bit DSP, used training available system management control tasks. Firmware from Aware implements high performance signal processing algorithms needed category ADSL operation. chipset includes silicon required ADSL datapump; however does include system control functions, framer POTS splitter these system specific realm OEM. This Category modem. upstream downstream bands separated using FDM. chipset rate adaptive, depending software mode settings, optimize data rate suit given loop. However, allocation tones upstream downstream must done hardware. Many configurations supported, controlled software settings analog filter values. Some typical ones are: 6.1Mbps 224Kbps over loop (Based T1.413 standard) Mbps Kbps (optimized extended range margin) 4Mbps 512Kbps over loop (more suited data services Internet access) TCP/IP requires typical asymmetry more than 10:1 between down/up stream data allow acknowledgment packets. small upstream `choke' downstream). maximum rate will determined loop environment crosstalk. chipset absolute maximum rates 12Mbps duplex 2Mbps duplex link. These will limited channel (attenuation, noise, crosstalk) rather than chipset these rates would achieved only very short loops (detailed simulations provided Figures 3-6). AD6435 interface supports rates 12Mbps simplex, 4Mbps duplex streams; this allow future developments that will allow more upstream tones. Although described having simplex duplex channels which case these correspond T1.413), more accurate description that there three independent channels: high speed downstream, medium speed downstream, medium speed upstream. There requirement that data rates "duplex" same even that both used. example, networking application, medium speed downstream redundant connected. split between (total) downstream determined filters analog stage bins 8-20 used bins 21-255 downstream). Given that, exact rate established configuration, according control information passed DSP. conventional ADSL implementations, lower bins (0-7) reserved analog POTS filter roll-off. However, possible change this, AD20msp910 will automatically adapt. typical examples would no-POTS operation, using dedicated copper line data, using bins from increase upstream traffic; using fewer bins starting higher frequency order support ADSL over ISDN application.
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DIGITAL SECTION
There three components digital section: AD6435 DTIR AD6436 ADTSP-2183
AD6435 DTIR
TheAD6435 interfaces ADSL modem external system, either modem.
separate sections: TICL (transfer, interface control logic) implements interfacing buffering operations, including
bit-stuffing/robbing, elastic store, FIFO etc. (digital interface area) implements error correction/detection interleaving operations (this section essentially same earlier AD6442 circuit).
AD6435 four simple synchronous connections, simplex (downstream) out, duplex out. These have "clean" clock data, operate asynchronously another, modem itself. "duplex" streams treated such, operate independently, with asynchronous clocks data rates. ATU-C simplex used, conversely simplex unused ATU-R). TICL section DTIR performs interface signal buffering timing recovery functions. This function complicated asynchronicity simplex duplex data streams from modem clock from each other. role differs depending whether mode. downstream transmission mode, payload input data clocked directly into FIFO data subsequently read from FIFO multiplexed into outgoing ADSL frames. This operation performed independently simplex duplex data streams: operation simplex stream will described with understanding that identical operations performed downstream data except different rate. performs cyclic redundancy checks, data scramble/descrambler, Reed-Solomon endec functions, interleaving/de-interleaving, data insertion extraction functions indicator bits.
Interfacing
standard interface very straightforward buffered demultiplexed synchronous connection. same both ATU-R ATU-C, presents four channels (simplex out, duplex out), with just signals connection, clock data. (Obviously, simplex ATU-R used). framing signals provided.
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Table Interface Descriptions
name
duplex_rx duplex_clko duplex_tx duplex_clki simplex_rx
description
Duplex data output from DTIR data received) clock associated with duplex_rx (output) Duplex data input from DTIR data transmitted) clock associated with duplex_tx Simplex data output from DTIR ATU-R: downstream data received ATU-C: used clock associated with simplex_rx (output) Simplex data transmitted from DTIR ATU-R: used ATU-C: downstream data sent clock associated with simplex_tx (input)
simplex_clko simplex_tx
simplex_clki
general clock signals duplex_clocki, simplex_clki) input DTIR, while received data clock signals (duplex_clko, simplex_clko) outputs. other words, sending modem ATU-C ATU-R) supplies clock DTIR, receiving modem's DTIR recovers (using digital phase locked loop) supplies external system. channels have separate independent clocks. There exception this; recovered duplex_rx clock ATU-R used duplex_clki duplex_tx data transmitted upstream. this case does need clock, simplex both duplex channels clocked from Although DTIR includes much interfacing elastic store, stuffing/robbing), does support full suite multiplexing/demultiplexing. Instead, simple bit-synchronous data streams provided. These essentially correspond with variable rate, merely fixed multiples standard rates, with optuion that duplex treated independent streams. framing operation then defined system their requirements, V.35, 10BaseT. Alternatively, asynchronous access, buffering multiplex/demultiplex stuff/rob operations bypassed. These blocks then power-downed, reducing AD6435's power consumption. interface presented then "raw" stream upstream downstream data, external system responsible framing. elastic store been disabled, these have relic ADSL line super-frame structure, will show irregular clock (with pause every 69th frame).
AD6436
consists five major blocks, encoder/decoder block, block, IFFT block, DFIC block, control logic block. block performs constellation encoding decoding required each sub-carriers. shared paths. These sub-carriers then combined into single stream transmittal (more specifically, this implemented inverse which translates frequency domain information separate subcarriers combines into time domain sequence transmittal). Conversely, block receives sequence received data, separates give sub-carriers demodulation. IFFT block performs inverse mode inverse mode transmit data. block performs mode mode. receives real data produces complex conjugate symmetric data. addition, block performs operation data after
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completed.
AD20msp910 Complete ADSL Chipset
ADTSP-2183
versatile general-purpose 16-bit fixed point with 80Kbytes on-chip SRAM, ADTSP-2183 3.3V version ADSP-2181. used training synchronization tasks where programmability important. also responsible channels, which inserted extracted from line data. This allows processor monitor them, under program control. operates entirely from internal memory, with program being downloaded from boot EPROM. Onchip there 16Kwords program memory, 16Kwords data memory. system (except interleave memory) internal. processor most occupied during training initialization, although regularly active overseeing operations, managing bit-swapping etc. such, used general purpose control processor OAM&P duties. Since control software based, there considerable flexibility configuration management. modem configured managed passing instructions this processor through serial port (SPORT1) IDMA port.
Software (Configuration Management)
addition modem (datapump) software, full control management protocol stack API) supplied with chipset. Configuration management modem implemented using simple messaging protocol (MP). This allows management entity -ME- (for example, this could dedicated system microcontroller serial line read from write Configuration Management Variables (CMVs) within ADSL chipset. This MP/CMV pairing similar SNMP/ combination commonly used network management. ATU-C ATU-R controlled entity, generally from from CO). However, configuration management (and usually will) different each. CMVs accessible ATU-C ATU-R data passed ATU-C). Security authentication also supported. There variables corresponding control information operating modes, desired data rate remote reset); performance measurements diagnostics errored seconds log, attenuation measurements); status modem serial number) others. functionality super-set that defined T1.413. also implements full management rate adaptivity operating mode. Full details this protocol structure available.
ANALOG SECTION
AD6437 implements virtually analog mixed-signal operations required ADSL system, single (80PQFP). These include: Progammable Gain Amplifier (0-30dB gain, steps) Anti-aliassing filters (4th order pass) High-speed (10MSPS, 12-bit resolution) High-performance (14-bit, 35MSPS, current output) Reconstruction filters (4th order pass)
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Output buffer References Auxiliary control VCXO (7bit)
AD20msp910 Complete ADSL Chipset
internal sections AD6437 used they individually bypassed, which allows easy customization bypassing standard filters using external discrete ones) testing. configuration control AD6437 serial port internal control registers. This used filter corners mode), gain, load data into auxiliary DAC, enable bypass various blocks, enable built-in test operations. external dual opamps also required implement filters; these supplied with chipset (AD8042 high-pass filter band-pass filter). transmitter output delivered AD816 differential line driver through matched termination resistors step transformer. AD816 includes high-speed high-power amplifiers drive section, amps. These implement receive path operations hybrid, designed minimize noise handle large voltage levels arising line interface. drivers typically configured differential mode, delivering output signal +26dBm, with distortion required driver. discrete balance network that optimized match typical loop impedances used provide good hybrid cancellation. POTS Splitter also required ADSL system allow regular telephone service coexist with ADSL signals. Frequency Division Multiplexing used transmit both ADSL signal POTS same twisted pair line already installed POTS (with analog phone line below 4KHz ADSL data signal starting above 30KHz). POTS Splitter located between twisted pair ADSL modem provide necessary filtering isolate signal from other route then their proper destinations (the lower frequencies passed telephone, high ones signal processing ADSL modem). splitter must designed that POTS signal unaffected power interrupts, ADSL data circuitry unaffected high-voltages present telephone circuit. Specifications splitter depend operator (primarily, whether active passive design required). such, splitter part chipset.
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EXPECTED SYSTEM PERFORMANCE
following table curves summarize some performance expectations Gen. chipset. These models have been tested calibrated believed representative. These numbers show achievable rate given loops assuming standard margin, using true device accurate simulation including quantization non-ideal behavior ADC, DAC; transistor level performance amplifiers, filters drivers; modeled effects transmission line bit-accurate, fixed-point/finite precision implementation details algorithm software). performance curves plotted three noise conditions: AWGN only -140dBm); AWGN ETSI Noise Model "A"; AWGN with HDSL crosstalkers. However, they contain allowance implementation board noise harmonics from switching PSU, manufacturing variation modems etc). Table includes variety standard loops under different conditions (crosstalk, using PIOTS band data, etc) provides range simulated result then (lower) value with allowance further degradation system level implementation. This very conservative figure; experience shows implementation losses significantly less than 3dB. Note that, when crosstalk included, more dominant effect. Because modem supports rate-adaptive mode this less concern, rates provided several representative environments.
Table Achievable Rates With Generation Chipset
Test Loop
15kft 26AWG T1.601 T1.601 (13)
Margin
xtalk POTS
730-810 7600-8500 1020-1110 770-8650 975-1060 5700-6600 800-880 3800-4400 560-640 1400-1750 690-770 2240-2650 680-760 2300-2800
xtalk POTS
580-665 7000-8000 680-780 7000-7900 730-810 5500-6400
xtalk POTS
410-490 5000-5900 405-500 5000-5800 480-580 4450-5300
xtalk POTS
690-790 7100-8100 800-910 7000-7900 860-980 5700-6600 600-720 3100-3700
xtalk POTS
540-650 4800-5700 500-620 5000-5800 630-750 4550-5400
170-260 670-1000 290-370 1475-1920 275-350 1860-2350
20-60 20-130 60-95 380-600 55-100 700-1050
180-280 660-790 350-450 1500-1950 325-450 1875-2400
25-105 30-140 130-190 380-600 100-175 700-1100
crosstalk cases are: xtalk (1)10 ISDN xtalk 10HDSL
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loops contain bridge taps. allocation 8-27 upstream, 28-255 downstream standard overhead included these rates payload). hybrid matching circuit optimized AWG, results suffer echo could improved upon
AWGN (-140dBm only)
AWGN ETSI
AWGN 20HDSL
Figure Downstream Data Rate Reach. 24AWG (0.5mm)
AWGN (-140dBm only)
AWGN ETSI
AWGN 20HDSL
Figure Upstream Data Rate Loop Reach. 24AWG (0.5mm)
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AWGN (-140dBm only)
AWGN ETSI
AWGN 20HDSL
Figure Downstream Data Rate Loop Reach. 26AWG (0.4mm)
AWGN (-140dBm only)
AWGN ETSI
AWGN 20HDSL
Figure Upstream Data Rate Loop Reach. 26AWG (0.4mm)
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