High apaci Single-Chip ASIC Alternative 3,000 54,000 System Gates
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40MX 42MX FPGA Families
High apaci
Single-Chip ASIC Alternative 3,000 54,000 System Gates kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry User-Programmable Pins Clock-to-Out Performance Dual-Port SRAM Access FIFOs 35-Bit Address Decode
Commercial, Military Temperature MIL-STD-883 Ceramic Packages Certification Ceramic Devices Available DSCC
Mixed Voltage Operation (5.0V 3.3V I/O) Synthesis-Friendly Architecture Support ASIC Design Methodologies 100% Resource Utilization 100% Fixing Deterministic, User-Controllable Timing Unique In-System Diagnostic Verification Capability with Silicon Explorer Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing 5.0V 3.3V Programmable PCI-Compliant
High ance
Feat
Commercial, Industrial, Military Temperature Plastic Packages
Device Capacity A40MX02 A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
System Gates SRAM Bits
Logic Modules
3,000
6,000
14,000 100,
24,000 100, 160,
36,000 1,410 160,
54,000 2,560 1,230 1,184 1,230 1,822 208, 208,
Sequential Combinatorial Decode
Clock-to-Out SRAM Modules (64x4 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks User (Maximum) Boundary Scan Test (BST) Packages count)
PLCC PQFP VQFP TQFP CQFP PBGA
2001 Actel Corporation
40MX 42MX FPGA Families
Actel's 40MX 42MX families provide high-performance, single-chip solution shortening system design development cycle, offering cost-effective alternative ASICs. 40MX 42MX devices excellent choices integrating logic that currently implemented multiple PALs, CPLDs, FPGAs. Example applications include high-speed controllers address decoding, peripheral interfaces, DSP, co-processor functions. device architecture based Actel's patented antifuse technology implemented 0.45µ triple-metal CMOS process. With capacities ranging from 3,000 54,000 system gates, synthesis-friendly devices provide performance MHz, live power-up, require five times lower stand-by power consumption than other FPGA device. Actel's FPGAs provide user I/Os available wide variety packages speed grades. Actel's 42MX devices also feature MultiPlex I/Os, which support mixed voltage systems, enable programmable PCI, deliver high-performance operation both 5.0V 3.3V, provide low-power mode. PCI-Compliant devices fully compliant with Local Specification (version 2.1). They deliver
A42MX16
on-chip operation clock-to-output performance with capacities spanning from 36,000 54,000 system gates. devices comply percent electrical timing specifications detailed specification. However, with programmable logic devices, performance final product depends upon user's design optimization techniques. MX24 MX36 devices also include system-level features such IEEE Standard 1149.1 (JTAG) Boudary Scan Testing, dual-port SRAM, fast wide-decode modules. A42MX36 device offers dual-port SRAM implementing fast FIFOs, LIFOs, temporary data storage. large number storage elements efficiently address applications requiring wide datapath manipulation perform transformation functions such those required telecommunications, networking, DSP. products 40MX 42MX families available percent tested over military temperature range. addition, largest member family, A42MX36, available both CQ208 CQ256 ceramic packages screened MIL-STD-883 levels. easy prototyping conversion from plastic ceramic, CQ208 PQ208 devices compatible.
Application (Temperature Range) Blank Commercial +70°C) Industrial (-40 +85°C) Military (-55 +125°C) MIL-STD-883 Package Lead Count Package Type Plastic Leaded Chip Carrier Plastic Quad Flat Pack Thin (1.4 Quad Flat Pack Very Thin (1.0 Quad Flat Pack Ball Grid Array Ceramic Quad Flat Pack Speed Grade Blank Standard Speed Approximately Faster than Standard Approximately Faster than Standard Approximately Faster than Standard Approximately Slower than Standard Part Number A40MX02= A40MX04= A42MX09= A42MX16= A42MX24= A42MX36= 3,000 System Gates 6,000 System Gates 14,000 System Gates 24,000 System Gates 36,000 System Gates 54,000 System Gates
Speed Grade* A40MX02 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 80-Pin Very Thin Plastic Quad Flat Pack (VQFP) A40MX04 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 80-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX09 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX16 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX24 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 160-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A42MX36 Device 208-Pin Plastic Quad Flat Pack (PQFP) 240-Pin Plastic Quad Flat Pack (PQFP) 272-Pin Plastic Ball Grid Array (PBGA) 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP)
Application
Contact your Actel sales representative product availability. Applications: Commercial Availability: Available *Speed Grade: Industrial Planned Military Planned
Approx. faster than Standard Approx. faster than Standard Approx. faster than Standard Approx. slower than Standard
Only Std, Speed Grade Only Std, Speed Grade
40MX 42MX FPGA Families
devices fully supported Actel's line FPGA development tools, including Actel DeskTOP series Designer Series tools. Actel DeskTOP series integrated design environment that includes design entry, simulation, synthesis, place-and-route tools. Designer Series, Actel's suite FPGA development point tools Workstations, includes ACTgen Macro Builder, timing-driven place-and-route analysis tools, device programming software. addition, devices contain ActionProbe circuitry that provides built-in access every node design,
enabling percent real-time observation analysis device's internal logic nodes without design iteration. probe circuitry accessed Silicon Explorer easy-to-use integrated verification logic analysis tool that sample data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard port, turning into fully functional 18-channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle only seconds.
User I/Os Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 44-Pin PLCC 68-Pin PLCC 84-Pin PQFP PQFP PQFP PQFP 100-Pin 160-Pin 208-Pin 240-Pin VQFP 80-Pin VQFP TQFP PBGA 100-Pin 176-Pin 272-Pin
Package Definitions (Contact your Actel sales representative product availability.) PLCC Plastic Leaded Chip Carrier, PQFP Plastic Quad Flat Pack, TQFP Thin Quad Flat Pack, VQFP Very Thin Quad Flat Pack, PBGA Plastic Ball Grid Array
User I/Os Device A42MX36 CQFP CQFP 208-Pin 256-Pin
Package Definitions (Contact your Actel sales representative product availability.) CQFP Ceramic Quad Flat Pack
40MX
40MX FPGAs will operate 5.0V-only systems 3.3V-only systems. 5.0V 3.3V
42MX
Input 5.0V 3.3V
Output 5.0V 3.3V
42MX FPGAs will operate 5.0V-only systems, 3.3V-only systems, mixed 5.0V/3.3V systems. VCCA 5.0V 3.3V 5.0V VCCI 5.0V 3.3V 3.3V Input 5.0V 3.3V 3.3V, 5.0V Output 5.0V 3.3V 3.3V
40MX 42MX devices composed fine-grained building blocks that enable fast, efficient logic designs. devices within these families composed logic modules, modules, routing resources, clock networks, which building blocks designing fast logic designs. addition, A42MX36 device contains embedded dual-port SRAM wide decode modules. dual-port SRAM modules optimized high-speed datapath functions such FIFOs, LIFOs, scratchpad memory. "Product Profile" page lists specific logic resources contained within each device.
Logi Modu
40MX logic module eight-input, one-output logic circuit designed implement wide range logic functions with efficient interconnect routing resources (Figure logic module implement four basic logic functions (NAND, AND, NOR) gates two, three, four inputs. Each function have many versions with different combinations active inputs. logic module also implement variety D-latches, exclusivity functions, AND-ORs, OR-ANDs. dedicated hard-wired latches flip-flops required array, since latches flip-flops constructed from logic modules wherever needed application.
When powering device mixed voltage mode (VCCA 5.0V VCCI 3.3V), VCCA must greater than equal VCCI throughout power-up sequence. VCCI 0.5V greater than VCCA when both above 1.5V, then I/Os' input protection junction I/Os will forward biased, causing them draw large amounts current. When VCCA VCCI 1.5V 2.0V region VCCI greater than VCCA, I/Os would momentarily behave outputs that logical high state, rises high levels. power down, sequence with VCCA VCCI implemented.
42MX devices have power-saving feature enabled special Power (LP). this mode, device consumes very minimal power, with standby current 15µA (see "Electrical Specifications" page 14). I/Os tristated, input buffers turned off, core device turned off. Since core turned off, state registers contents SRAM lost. device enters power mode 800ns after High. will resume normal operation 200µs after driven logic Low.
Figure 40MX Logic Module
40MX 42MX FPGA Families
42MX devices contain three types logic modules: combinatorial (C-modules), sequential (S-modules), decode (D-modules). C-module, shown Figure implements following function: where S0=A0*B0 S1=A1+B1 S-module, shown Figure designed implement high-speed sequential functions within single logic module. S-module implements same combinatorial logic function C-module while adding sequential element. sequential element configured either flip-flop transparent latch. increase flexibility, S-module register bypassed that implements purely combinatorial logic.
Figure C-Module Implementation
GATE
7-Input Function Plus D-Type Flip-Flop with Clear
7-Input Function Plus Latch
GATE
4-Input Function Plus Latch with Clear
8-Input Function Same C-Module)
Figure S-Module Implementation
Some 42MX devices contain D-modules, which arranged around periphery devices. D-modules contain wide-decode circuitry, which provides fast, wide-input function similar that found product-term architectures (Figure D-module allows 42MX devices perform wide-decode functions speeds comparable CPLDs PALs. output D-module programmable inverter active HIGH assertion. D-module output hard-wired output pin, also back into array incorporated into other logic.
ules
offering active HIGH implementation. SRAM block contains eight data inputs (WD[7:0]), eight outputs (RD[7:0]) which connected segmented vertical routing tracks. 42MX dual-port SRAM blocks provide optimal solution high-speed buffered applications requiring fast FIFO LIFO queues. Actel's ACTgen Macro Builder provides capability quickly design memory functions, such FIFOs, LIFOs, arrays. addition, unused SRAM blocks used implement registers other logic within design.
A42MX36 device contains dual-port SRAM modules that have been optimized synchronous asynchronous applications. SRAM modules arranged 256-bit blocks that configured 32x8 64x4. SRAM modules cascaded together form memory spaces user-definable width depth. block diagram 42MX dual-port SRAM block shown Figure 42MX SRAM modules true dual-port structures containing independent read write ports. Each SRAM module contains bits read write addressing (RDAD[5:0] WRAD[5:0], respectively) 64x4-bit blocks. When configured byte mode, highest order address bits (RDAD5 WRAD5) used. read write ports SRAM block contain independent clocks (RCLK WCLK) with programmable polarities
Inputs
Hard-Wire Programmable Inverter
Feedback Array
Figure D-Module Implementation
WD[7:0]
Latches [7:0]
[5:0] Write Port Logic SRAM Module (256 Bits) Read Port Logic Latches
RDAD[5:0]
WRAD[5:0] Latches
[5:0]
Read Logic
RCLK
MODE BLKEN WCLK Write Logic RD[7:0]
Routing Tracks
Figure 42MX Dual-Port SRAM Block
40MX 42MX FPGA Families
odul
Horizontal Routing
MultiPlex supports most common voltage standards today: pure 5.0V operation, pure 3.3V operation, mixed 3.3V operation with 5.0V tolerance maximum performance. Internal array performance retained 3.3V systems using complimentary pass gates that operate fast they 5.0V 3.3V. MultiPlex includes selectable output drives certain 42MX devices, enabling 100% PCI-compliance both 5.0V 3.3V systems. low-power systems, MultiPlex used turn inputs outputs current consumption below 100µA. MultiPlex modules provide interface between device pins logic array. Figure block diagram 42MX module. variety user functions, determined library macro selection, implemented module. (Refer Macro Library Guide more information.) 42MX modules contain tristate buffers, with input output latches that configured input, output, bi-directional operation. 42MX devices contain flexible structures (Figure page where each output dedicated output-enable control. module used latch input output data, both, providing fast set-up time. addition, Actel Designer Series software tools build D-type flip-flop using C-module register input output signals. achieve 5.0V 3.3V PCI-compliant output drives A42MX24 A42MX36 devices, chip-wide fuse programmed. When fuse programmed, output drive standard. (See bottom portion Figure Actel's Designer Series development tools provide design library macrofunctions that implement configurations supported FPGAs.
Horizontal channels located between rows modules composed several routing tracks. horizontal routing tracks within channel divided into more segments. minimum horizontal segment length width module pair, maximum horizontal segment length full length channel. segment that spans more than one-third length considered long horizontal segment. typical channel shown Figure page Non-dedicated horizontal routing tracks used route signal nets; dedicated routing tracks used global clock networks power ground tie-off tracks.
From Array
G/CLK*
Array
G/CLK* Configured Latch Flip-Flop (Using C-Module) Schematic
Signal Output Drive Enable Fuse
architecture uses vertical horizontal routing tracks interconnect various logic modules. These routing tracks metal interconnects that either continuous length broken into pieces called segments. Varying segment lengths allows interconnect over design tracks occur with only antifuse connections. Segments joined together ends using antifuses increase their lengths full length track. interconnects accomplished with maximum four antifuses.
Figure 42MX Module
Vertical Routing
Another routing tracks vertically through module. There three types vertical tracks: input, output, long, which also divided into more segments. Each segment input track dedicated input particular module; each segment output track dedicated output particular module. Long segments uncommitted assigned during
From Internal Logic
internally-generated clock signal clock network. Since both clock networks identical, does matter whether CLK0 CLK1 being used. clock input pads also used normal I/Os, bypassing clock networks (Figure A42MX36 device four additional register control resources, called quadrant clock networks (Figure page 10). Each quadrant clock provides local, high-fanout resource contiguous logic modules within quadrant device. Quadrant clock signals originate from specific pins from internal array used secondary register clock, register clear, output enable.
Segmented Horizontal Routing Tracks Logic Modules
Internal Logic
Figure 40MX Module routing. Each output segment spans four channels (two above below), except near bottom array, where edge effects occur. Long vertical tracks contain either segments. example vertical routing tracks segments shown Figure
Antifuse Structures
antifuse "normally open" structure opposed normally connected fuse structure used PROMs PALs. antifuses implement programmable logic device results highly testable structures well efficient programming algorithms. structure highly-testable because there pre-existing connections; therefore, temporary connections made using pass transistors. These temporary connections isolate individual antifuses programmed individual circuit structures tested, which done before after programming. example, metal tracks tested continuity shorts between adjacent tracks, functionality logic modules verified.
Antifuses
Vertical Routing Tracks
Figure Routing Structure
CLKB CLKA From Pads CLKMOD CLKINB CLKINA Internal Signal CLKO(17) Clock Drivers CLKO(16) CLKO(15)
40MX devices have global clock distribution network (CLK). low-skew, high-fanout clock distribution networks provided each 42MX device. These networks referred CLK0 CLK1. Each network clock module (CLKMOD) that selects source clock signal driven follows: Externally from CLKA Externally from CLKB Internally from CLKINTA input Internally from CLKINTB input clock modules located modules. Clock drivers dedicated horizontal clock track located each horizontal routing channel. user controls clock module selecting clock macros from macro library. macro CLKBUF used connect external clock pins clock network, macro CLKINT used connect
CLKO(2) CLKO(1)
Clock Tracks
Figure Clock Networks
40MX 42MX FPGA Families
devices contain Actel's ActionProbe test circuitry which test debug design once programmed into device. Once device been programmed, ActionProbe test circuitry allows designer probe internal node during device operation debugging design. addition, 42MX devices contain IEEE Standard 1149.1 boundary scan test circuitry.
IEEE Standard 1149.1 Boundary Scan Testing (BST)
interconnections. signals shared among devices test chain that components operate same state. 42MX family implements subset IEEE Standard 1149.1 instruction addition private instruction, which allows Actel's ActionProbe facility with BST. Refer IEEE Standard 1149.1 specification detailed information regarding BST.
Boundary Scan Circuitry
IEEE Standard 1149.1 defines four-pin Test Access Port (TAP) interface testing integrated circuits system. 42MX family provides five pins: Test Data (TDI), Test Data (TDO), Test Clock (TCK), Test Mode Select Test Reset (TRST) (42MX24A only). Devices configured test "chain" where data transmitted serially between devices TDO-to-TDI
42MX boundary scan circuitry consists Test Access Port (TAP) controller, test instruction register, JPROBE register, bypass register, boundary scan register. Figure page shows block diagram 42MX boundary scan circuitry.
QCLKA Quad Clock Module Quad Clock Module
QCLKC
QCLKB *QCLK1IN
QCLK1
QCLK3
QCLKD *QCLK3IN
Quad Clock Module *QCLK2IN
QCLK2
QCLK4
Quad Clock Module *QCLK4IN
*QCLK1IN, QCLK2IN, QCLK3IN, QCLK4IN internally-generated signals.
Figure Quadrant Clock Network
JPROBE Register Boundary Scan Register Bypass Register Control Logic JTAG
Output
Controller
Instruction Decode
JTAG Instruction Register
Figure 42MX IEEE 1149.1 Boundary Scan Circuitry When device operating mode, four pins used TDI, TDO, TMS, signals. active reset (nTRST) supported; however, 42MX device contain power-on circuitry that resets boundary scan circuitry upon power-up. Table summarizes functions IEEE 1149.1 signals. Table IEEE 1149.1 Signals
Signal Name Test Data Function Serial data input instructions data. Data shifted rising edge TCK. Serial data output instructions test data. Serial data input mode. Data shifted rising edge TCK. Clock signal shift data into device.
JTAG fuse programmed: must terminated-logical high doesn't matter avoid floating input) TDI, float logical high (internal pull-up present) float connect another device (it's output) JTAG fuse programmed: TCK, TDI, TDO, user I/O. used, they will configured tristated output.
Instructions
Test Data Test Mode Select Test Clock
Boundary scan testing within 42MX devices controlled Test Access Port (TAP) state machine. controller drives three-bit instruction register, bypass register, boundary scan data registers within device. controller uses signal control testing device. mode determined bitstream entered pin. Table describes test instructions supported 42MX devices.
Reset
JTAG
SX-A devices IEEE 1149.1 (JTAG) compliant. SX-A devices offer superior diagnostic testing capabilities providing JTAG probing capabilites. These functions controlled through special JTAG pins conjunction with program fuse.
equipped with internal pull-up resistor. This allows controller remain return Test-Logic-Reset state when there input when logical pin. reset controller, must HIGH least five cycles.
40MX 42MX FPGA Families
Table Instructions
Test Mode EXTEST Code Description Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Allows snapshot signals device pins captured examined during device operation. private instruction allowing user connect Actel's Micro Probe registers test chain. Allows user build application-specific instructions such READ WRITE. Refer IEEE Standard 1149.1 specification. Refer IEEE Standard 1149.1 specification. Enables bypass register between pins. test data passes through selected device adjacent devices test chain.
SAMPLE/ PRELOAD
JPROBE
USER INSTRUCTION
HIGH CLAMP BYPASS
Free Rang
Parameter Commercial Industrial 4.75 5.25 4.75 5.25 3.14 3.47 Military Units %VCC
Symbol Parameter VCCA/ VCCI TSTG Supply Voltage Input Voltage Output Voltage Storage Temperature
Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150
Units
Temperature Range1 Power Supply Tolerance VCCI VCCA VCCI2
+125
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions. Device inputs normally high impedance draw extremely current. However, when input voltage greater than VCCA 0.5V less than 0.5V, internal protection diode will forward-biased draw excessive current.
Notes: Ambient temperature (TA) used commercial industrial; case temperature (TC) used military. Operating condition I/Os mixed voltage mode.
Commercial Symbol VOH1 Parameter Min. (IOH (IOH (IOH (VIN 0.5) (VIN 2.7)
Commercial `-F' Min. Max.
Industrial Min. Max.
Military Units Min. Max.
Max.
0.40 -0.3 VCCI Notes -0.3 VCCI 25.0 -0.3 VCCI Notes
0.40
(IOL
(IOL
-0.3
VCCI
Input Transition Time Capacitance2,
Standby Current,
ICC(D) Dynamic VCCI Supply Current Power Mode Standby Current Note
"Power Dissipation" section page
Notes: Only output tested time. VCCI min. tested, information only. Includes worst-case 84-pin PLCC package capacitance. VOUT MHz. outputs unloaded. inputs VCCI GND. limit includes during normal operation. A40MX02 A40MX04 A42MX09 A42MX16 A42MX24, A42MX24A, A42MX36 available special request. Contact your local Actel Sales representative additional information. A40MX02 A40MX04 A42MX09, A42MX16, A42MX24, A42MX24A, A42MX36 Power Mode, A42MX09 A42MX16, A42MX24, A42MX36 A40MX02 A40MX04 N/A.
40MX 42MX FPGA Families
ange
Parameter Temperature Range1 Power Supply Tolerance VCCI VCCA Commercial Industrial Military +125 Units
Symbol TSTG
Parameter Supply Voltage Input Voltage Output Voltage Source Sink Current2 Storage Temperature
Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150
Units
Note: Ambient temperature (TA) used commercial, industrial; case temperature (TC) used military.
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions. Device inputs normally high impedance draw extremely current. However, when input voltage greater than 0.5V less than 0.5V, internal protection diodes will forward-bias draw excessive current.
Commercial Parameter Min. VOH1 VOL1 Input Transition Time Capacitance2,
Commercial `-F' Min. 2.15 Max.
Industrial Min. Max.
Military Units Min. Max.
Max.
(IOH (IOH -3.2 (IOL
2.15 -0.3 Notes
-0.3 -0.3
0.48 Notes -0.3
0.48
Standby Current,
ICC(D) Dynamic Supply Current Power Mode Standby Current Note
"Power Dissipation" section page
Notes: Only output curve tested time. min. tested, information only. Includes worst-case 84-pin PLCC package capacitance. VOUT MHz. outputs unloaded. inputs GND. A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 1.5mA available special request. Contact your Actel Sales representative additional information. A40MX02 A40MX04 A42MX09, A42MX16, A42MX24, A42MX36 Power Mode, A42MX09 A42MX16, A42MX24, A42MX36 A40MX02 A40MX04 N/A.
device drivers were designed specifically high-performance systems. Figure page shows typical output drive characteristics devices. output drivers compliant with Local Specification.
igna
Symbol CCLK LPIN Parameter Supply Voltage Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance VIN=0.5 IOUT IOUT IOUT 0.55 3.84 Condition Minimum 4.75 -0.5 Maximum 5.25 Minimum 4.75 -0.3
Maximum 5.25
Units
0.33
Notes: Local Specification Section 4.2.1.1. Maximum rating -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance.
(5.0 gnal
Symbol Slew Slew Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.4V 2.4V load 2.4V 0.4V load Minimum (VIN /0.015 Maximum
Minimum Maximum Units V/ns V/ns
Note: Local Specification Section 4.2.1.2.
40MX 42MX FPGA Families
igna
Symbol CCLK LPIN Parameter Supply Voltage Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance IOUT IOUT Condition Minimum -0.5 Maximum Minimum -0.3
Maximum Units
Notes: Local Specification Section 4.2.2.1. Maximum rating -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance.
igna
Symbol Slew Slew Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.2V 0.6V load 0.6V 0.2V load Minimum (VIN /0.015 Maximum
Minimum Maximum Units V/ns V/ns
Note: Local Specification Section 4.2.2.2.
0.50 0.45 0.40 0.35 0.30 0.25 0.20 Current 0.15 0.10
Maximum
Minimum
0.05 0.00
-0.05 -0.10 -0.15 -0.20
Maximum
Minimum
Voltage
Figure Typical Output Drive Characteristics (Based upon measured data)
40MX 42MX FPGA Families
device junction-to-case thermal characteristic junction-to-ambient characteristic thermal characteristics shown with different flow rates. Ambient temperature (TA) used commercial industrial; case temperature (TC) used military.
Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed PQFP 160-pin package commercial temperature follows:
Max. junction temp. (°C) Max. commercial temp. 150°C 70°C 2.5W (°C/W) 32°C/W Plastic Packages Count Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Plastic Ball Grid Array Ceramic Packages Ceramic Quad Flat Pack Ceramic Quad Flat Pack Count
Still 34°C/W 32°C/W 30°C/W 19°C/W 43°C/W 36°C/W 32°C/W 28°C/W 39°C/W 38°C/W 20°C/W ft/min 31°C/W 24°C/W 23°C/W 16°C/W 31°C/W 25°C/W 22°C/W 21°C/W 33°C/W 32°C/W 14.5°C/W
Still 22°C/W 20°C/W
Gener quat
[ICCstandby ICCactive] VCCI IOL* VOL* (VCCI VOH) where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. Accurate values difficult determine because they depend family type, design details, system I/O. power divided into components: static active.
Actel FPGAs have small static power components that result power dissipation lower than PALs CPLDs. integrating multiple PALs/CPLDs into FPGA, even greater reduction board-level power dissipation achieved. power standby current typically small component overall power. Standby power calculated commercial, worst-case conditions: VCCA 5.25 Power 10.5
static power dissipation loads depends number outputs driving HIGH LOW, load current. Again, this number typically small. instance, 32-bit sinking 0.33V will generate with outputs driving LOW, with outputs driving HIGH. actual dissipation will average somewhere between, I/Os switch states with time.
ower nent
where: Number logic modules switching frequency Number input buffers switching frequency Number output buffers switching frequency Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock CEQM Equivalent capacitance logic modules CEQI Equivalent capacitance input buffers CEQO Equivalent capacitance output buffers CEQCR Equivalent capacitance routed array clock Output load capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate
Capa
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency-dependent function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation.
quiv apac ance
power dissipated CMOS circuit expressed equation: Power (µW) VCCA2 where: Equivalent capacitance expressed picofarads (pF) Switching frequency megahertz (MHz)
VCCA Power supply volts Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCC. Equivalent capacitance frequency-independent, results used over wide range operating conditions. Equivalent capacitance values shown below.
Valu
Device Type A40MX02 A40MX04
routed_Clk1 41.4 68.6
routed_Clk2
Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR)
18.2
A42MX09 A42MX16 A42MX24 A42MX36
calculate active power dissipated from complete design, switching frequency each part logic must known. equation below shows piece-wise linear summation over components. Power VCCA2 CEQM fm)Modules CEQI fn)Inputs (CEQO fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2
40MX 42MX FPGA Families
Frequ ency
determine switching frequency design, data input values circuit must clearly understood. following guidelines represent worst-case scenarios; these used generally predict upper limits power dissipation. Logic Modules Combinatorial Modules Inputs/4 Outputs/4 Sequential Modules Sequential Modules
Logic Modules
Combinatorial Modules F/10 F/10
Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2)
Inputs Switching Outputs Switching First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL)
Input Delay Module tINYL 0.62 IRD2 2.59
Internal Delays
Predicted Routing Delays
Output Delay Module
Logic Module tDLH 3.32 tIRD1 2.09 tIRD4 3.64 tIRD8 5.73 1.24 1.24 tRD1 1.28 tRD2 1.80 tRD4 2.33 tRD8 4.93 tENHZ 7.92
Array Clock
tCKH 4.55 FMAX
Values shown 40MX `-3' speed devices 5.0V worst-case commercial conditions.
Input Delays Module tINYL 1.16 tIRD1 2.24 Combinatorial Logic Module 1.55 tRD1 0.80 tRD2 1.00 tRD4 1.50 tRD8 2.50 Internal Delays Predicted Routing Delays Output Delays Module
tDLH 2.70
tINH 0.00 tINSU 0.54 tINGL 1.40 Sequential Logic Module
Combinatorial Logic included tSUD
Module tDLH 2.70
tRD1 0.80
tENHZ 5.40
tOUTH 0.00 tOUTSU 0.30 tGLH 2.90
Array Clocks
tCKH 2.70 FMAX
tSUD 0.36 0.00
1.37
tLCO 5.60 (light loads, pad-to-pad)
*Values shown A42MX09 `-2' 5.0V worst-case commercial conditions Input module predicted routing delay
40MX 42MX FPGA Families
Input Delays Module tINPY 1.14 IRD1 2.18 Combinatorial Module 1.46 tRD1 1.04 tRD2 1.42 tRD4 2.18 Internal Delays Predicted Routing Delays Output Delays Module
tDLH 2.84
tINH 0.00 tINSU 0.53 tINGO 1.55 Decode Module tPDD 1.78 Module tDLH 2.84
tRDD 0.38
Sequential Logic Module
Combinatorial Logic included tSUD
tRD1 1.04
tENHZ 5.80
0.00 tLSU 0.53 tGHL= 3.27
tSUD 0.30 0.00 Quadrant Clocks tCKH 3.03 ns** FMAX
1.43
Preliminary values shown A42MX36 `-2' 5.0V worst-case commercial conditions Load-dependent
Input Delays Module tINPY 1.14 IRD1 2.18
tINSU 0.53 tINH 0.00 tINGO 1.55
Predicted Routing Delays [7:0] WRAD [5:0] BLKEN WCLK tADSU 1.80 tADH 0.00 tWENSU 2.90 tBENS 2.90 [7:0] RDAD [5:0] tRD1 1.04
Module tDLH 2.84
RCLK tADSU 1.80 tADH 0.00 tRENSU 0.80 tRCO 3.80
tGHL= 5.50 tLSU 0.30 0.00
Array Clocks FMAX
*Values shown A42MX36 `-2' 5.0V worst-case commercial conditions.
40MX 42MX FPGA Families
TRIBUFF test loads (shown below)
1.5V 1.5V
VCCI
1.5V tENLZ
1.5V tENHZ
tDLH
tDHL
tENZL
tENZH
Load (Used measure propagation delay)
Load (Used measure rising/falling edges) VCCI
output under test
output under test
VCCI tPLZ/tPZL tPHZ/tPZH
Modu
INBUF
tINYH 1.5V 1.5V VCCI tINYL
tPLH tPHL tPLH
tPHL
(Positive Edge-Triggered)
tSUD
tWCLKA tSUENA tHENA
tWCLKI
PRE, tWASYN Note: represents data functions involving multiplexed flip-flops.
40MX 42MX FPGA Families
(continued)
Inpu Buffer
DATA
IBDL
CLKBUF
DATA tINH tINSU tHEXT tSUEXT
uffer ches
OBDLHS
tOUTSU tOUTH
A-G,
tPHL tPLH
Write Port WRAD [5:0] BLKEN WCLK [7:0] Array 32x8 64x4 (256 Bits)
Read Port RDAD [5:0] RCLK [7:0]
40MX 42MX FPGA Families
42MX
tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU tBENSU BLKEN Valid tBENH tWENH tADH
tRCKHL
Note:
Identical timing falling edge clock.
42MX hronou
tCKHL RCLK
tRCKHL
tRENSU tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Data Data
Note:
Identical timing falling edge clock.
42MX chrono
(Read Address Controlled)
tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data ADDR2 tRPD Data
42MX chrono
(Write Address Controlled)
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Data
Data
40MX 42MX FPGA Families
Propagation delay between logic modules depends resistive capacitive loading routing tracks, interconnect elements, module inputs being driven. Propagation delay increases length routing tracks, number interconnect elements, number inputs increases. From design perspective, propagation delay statistically correlated modeled fanout (number loads) driven module. Higher fanout usually requires some paths have longer routing tracks. FPGAs deliver tight fanout delay distribution, which achieved ways: decreasing delay interconnect elements decreasing number interconnect elements path. Actel's patented antifuse offers very resistive/capacitive interconnect. antifuses, fabricated 0.45 lithography, offer nominal levels resistance femtofarad (fF) capacitance antifuse. fanout distribution also tight number antifuses required each interconnect path. proprietary architecture limits number antifuses path maximum four, with percent interconnects using only antifuses.
Some nets design long tracks, which special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes four antifuse connections, which increase capacitance resistance, resulting longer delays macros connected long tracks. Typically, percent nets fully utilized device require long tracks. Long tracks approximately delay, which represented statistically higher fanout (FO=8) routing delays data sheet specifications section, beginning page
timing derating factor 0.45 used reflect best-case processing. Note that this factor relative standard speed timing parameters must multiplied appropriate voltage temperature derating factors given application.
cial Indus
Industrial Min. (Commercial Specification) 0.69 Max. 1.11
cial pica
Device timing characteristics fall into three categories: family-dependent, device-dependent, design-dependent. input output buffer characteristics common devices. mixed voltage A42MX devices, timing numbers defined 3.3V section I/Os while internal logic resources, timing numbers defined 5.0V section. Internal routing delays device-dependent. Design dependency means actual delays determined until after place-and-route user's design complete. Delay values then determined using Designer Series utility performing simulation with post-layout delays.
Commerical Typical 25°C, 5.0V) (Commercial, Worst-Case Condition) Note: 0.85
This derating factor applies routing propagation delays.
Propagation delays this data sheet apply typical nets. abundant routing resources architecture allows deterministic timing using Actel's Designer Series development tools, which include TDPR, timing-driven place-and-route tool. Using Timer, designer specify timing-critical nets system clock frequency. Using these timing specifications, place-and-route software optimizes layout design meet user's specifications.
(Normalized 25°C, 5.0V)
42MX Voltage 4.50 4.75 5.00 5.25 5.50
Temperature -55°C 0.93 0.88 0.85 0.84 0.83 -40°C 0.95 0.90 0.87 0.86 0.85 1.05 1.00 0.96 0.95 0.94 25°C 1.09 1.03 1.00 0.97 0.96 70°C 1.25 1.18 1.15 1.12 1.10 85°C 1.29 1.22 1.18 1.14 1.13 125°C 1.41 1.34 1.29 1.28 1.26
(Normalized 25°C, VCCA/VCCI 5.0V)
1.50 1.40
Derating Factor
1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 5.25 5.50
Voltage
Note: This derating factor applies routing propagation delays.
40MX 42MX FPGA Families
(Normalized 25°C, 5.0V)
40MX Voltage 4.50 4.75 5.00 5.25 5.50
Temperature -55°C 0.89 0.84 0.82 0.80 0.79 -40°C 0.93 0.88 0.85 0.82 0.82 1.02 0.97 0.94 0.91 0.90 25°C 1.09 1.03 1.00 0.97 0.96 70°C 1.25 1.18 1.15 1.12 1.10 85°C 1.31 1.24 1.20 1.16 1.15 125°C 1.45 1.37 1.33 1.29 1.28
40MX Junction Temperature Voltage Derating Curves (Normalized 25°C, VCCA/VCCI 5.0V)
1.50 1.40
Derating Factor
1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 5.25 5.50
Voltage
Note: This derating factor applies routing propagation delays.
Table Table list critical timing parameters corresponding timing parameter PCI-compliant devices. Table Clock Specification
Actel provides synthesizable VHDL Verilog-HDL models Target interface, Target Target+DMA Master interface. Contact your Actel sales representative more details.
Symbol TCYC THIGH TLOW Parameter Cycle Time High Time Time Min. Max.
A42MX24 Min. Max.
A42MX36 Min. Max. Units
Table Timing Parameters
Symbol TVAL TVAL(PTP) TOFF TSU(PTP) Parameter Signal Valid-Bused Signals Signal Valid-Point-to-Point Float Active Active Float Input Set-Up Time CLK-Bused Signals Input Set-Up Time CLK-Point-to-Point Input Hold Min. Max. A42MX24 Min. Max. 8.31 A42MX36 Min. Max. 8.31 Units
Note: TOFF system dependent. devices have turn-off time, reflection typically additional
40MX 42MX FPGA Families
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.6
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Series later Timer check hold time this macro.
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 12.4 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input High 3.01 10.0 10.4 10.4 10.4
Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 0.03 0.02 0.04 0.02 10.4 0.04 0.03 6.05 12.2 0.05 0.03 10.5 17.0 12.6 0.07 0.04 ns/pF ns/pF 0.02 0.03 0.02 0.03 10.4 0.03 0.03 12.2 0.03 0.04 10.1 17.1 12.6 0.04 0.06 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.9
15.2
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
14.6
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Series later Timer check hold time this macro.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 9.26 10.5 12.6 11.0 17.3 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 10.1 10.4 14.1 14.6 10.4 10.4 13.7 13.7 14.5 14.5
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 11.1 0.05 0.03 12.8 0.05 0.03 14.5 10.7 0.06 0.04 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns/pF ns/pF 11.1 0.03 0.04 12.8 0.03 0.04 14.5 10.7 0.04 0.05 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
40MX 42MX FPGA Families
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.9
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Series later Timer check hold time this macro.
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 12.4 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH 10.1 10.4 10.4 10.4
Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 0.03 0.02 0.04 0.02 10.4 0.04 0.03 12.2 0.05 0.03 10.5 17.1 12.6 0.07 0.04 ns/pF ns/pF 0.02 0.02 0.02 0.03 10.4 0.03 0.03 12.2 0.03 0.04 10.1 17.1 12.6 0.04 0.06 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.9
15.2
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
14.6
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Series later Timer check hold time this macro.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 3.34 10.5 12.4 11.0 17.2 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 10.1 10.4 14.1 14.6 10.4 10.4 13.8 13.8 14.6 14.6
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 11.1 0.05 0.03 12.8 0.05 0.03 14.5 10.7 0.06 0.04 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns/pF ns/pF 11.1 0.03 0.04 12.8 0.03 0.04 14.5 10.7 0.04 0.05 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
40MX 42MX FPGA Families
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays1 tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
0.03 0.04
0.03 0.04
0.03 0.04
10.9 0.04 0.05
10.2 11.1
10.8 15.3 0.06 0.07
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad
0.03 0.04
0.03 0.04
0.03 0.04
10.9 0.04 0.05
10.2 11.1
Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
10.8 15.3 0.06 0.07
ns/pF ns/pF
Note: Delays based loading.
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 12.9
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH 2.17 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.8
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency 12.9 14.2 10.2 11.2
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
12.2 0.00 0.09
13.5 0.00 0.10
10.9 15.4 0.00 0.10
10.2 11.1 12.9 18.1 0.10 0.10
14.2 15.5 12.0 12.0
18.0 25.3 0.01 0.10
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad
12.2 0.04 0.05
13.5 0.04 0.05
10.9 15.4 0.05 0.06
10.2 11.1 12.9 18.1 0.06 0.07
14.2 15.5 12.0 12.0
Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
18.0 25.3 0.08 0.10
ns/pF ns/pF
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit 75V,
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3,4 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 1955 1795 10.1 1565 14.1
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH 4.67 4.59 10.7
Minimum Pulse Width Maximum Skew
Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 0.03 0.04 0.03 0.04 10.1 0.03 0.04 11.9 0.04 0.05 11.2 10.4 11.9 16.7 0.06 0.07 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 0.03 0.04 0.03 0.04 10.1 0.03 0.04 11.9 0.04 0.05 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 ns/pF ns/pF
Note: Delays based loading.
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3, tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 10.6 12.0 0.89 14.1 1.01 1.01 12.9 19.8
Notes: dual-module macros tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.5
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up 10.7 16.2 17.8 11.8 13.7 11.0 12.9 11.0 12.9
Input Latch External Hold Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 10.1 14.2 0.05 0.06 11.2 10.4 11.9 16.7 0.06 0.07 15.7 14.5 10.0 10.0 16.7 23.3 0.08 0.10 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
11.3 0.04 0.05
12.5 0.04 0.05
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 11.3 0.04 0.05 12.5 0.04 0.05 10.1 14.2 0.05 0.06 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 15.7 14.5 14.7 14.7 16.7 23.3 0.08 0.10 ns/pF ns/pF
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit 75V,
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2'Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH FO=32 FO=486 FO=32 FO=486 10.9 11.9
Minimum Pulse Width HIGH FO=32 FO=486 Minimum Pulse Width FO=32 FO=486 Maximum Skew FO=32 FO=486
Input Latch External Set-Up FO=32 FO=486 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.4 10.7 Min. Max. `-2'Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
22.0 0.07 0.06
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.3 10.7 10.1 10.1
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
22.0 0.07 0.06
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2'Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
12.6
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
40MX 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 13.5 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.0
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH FO=32 FO=486 FO=32 FO=486 9.47 10.4 10.8 11.9 18.2 19.9 10.0 10.6 12.4
Minimum Pulse Width HIGH FO=32 FO=486 Minimum Pulse Width FO=32 FO=486 Maximum Skew FO=32 FO=486
Input Latch External Set-Up FO=32 FO=486 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 7.67 9.07 11.3 10.7 15.9 14.9 13.9 10.0 10.0 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
14.8 0.05 0.04
16.5 0.05 0.04
18.7 0.06 0.05
22.0 0.07 0.06
30.8 0.10 0.08
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 9.01 11.3 10.7 10.1 10.1 15.9 14.9 13.9 14.2 14.2
tACO
14.8 0.05 0.04
16.5 0.05 0.04
18.7 0.06 0.05
22.0 0.07 0.06
30.8 0.10 0.08
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit 75V,
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
0.34
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Logic Module Timing Parameter Description Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 3.78 10.0 10.0 14.0 14.0 `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 1.34 11.1 10.2 13.0 12.0 18.2 16.8
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input HIGH Input HIGH FO=32 FO=635 FO=32 FO=635 12.7 13.8 10.1
Minimum Pulse Width HIGH FO=32 FO=635 Minimum Pulse Width FO=32 FO=635 Maximum Skew FO=32 FO=635
Input Latch External Set-Up FO=32 FO=635 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.8 10.9 10.2 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
0.07 0.07
0.08 0.08
0.09 0.09
11.5 0.10 0.10
16.1 0.14 0.14
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.8 10.9 10.2 10.4 10.4
tACO
7.78 0.07 0.07
0.08 0.08
0.09 0.09
11.5 0.10 0.10
16.1 0.14 0.14
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
12.6
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Logic Module Timing Parameter Description Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 10.5 10.5 11.9 11.9 14.0 14.0 19.6 19.6 `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 12.3 11.3 13.7 12.6 15.5 14.3 18.2 16.8 25.5 23.5
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 13.5 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 4.07 12.6
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input HIGH Input HIGH FO=32 FO=635 FO=32 FO=635 10.2 11.0 11.1 12.0 12.7 13.8 21.2 23.0 10.1 10.3 11.0 14.1
Minimum Pulse Width HIGH FO=32 FO=635 Minimum Pulse Width FO=32 FO=635 Maximum Skew FO=32 FO=635
Input Latch External Set-Up FO=32 FO=635 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 7.34 10.0 11.8 10.9 10.2 16.5 15.3 14.3 10.2 10.2 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
10.9 0.10 0.10
12.1 0.11 0.11
13.7 0.12 0.12
16.1 0.14 0.14
22.5 0.20 0.20
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 10.0 11.8 10.9 10.2 10.4 10.4 16.5 10.3 15.3 14.3 14.6 14.6
tACO
10.9 0.10 0.10
12.1 0.11 0.11
13.7 0.12 0.12
16.1 0.14 0.14
22.5 0.20 0.20
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor Cond 4.5V,
`-2' Speed Parameter Description
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Combinatorial Functions tPDD
Internal Array Module Delay Internal Decode Module Delay
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Military Conditions, 4.5V, 125°C)
Logic Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 10.0 10.0 14.0 14.0
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 11.1 10.2 13.0 12.0 18.2 16.8
40MX 42MX FPGA Families
(continued)
(Worst-Case Military Conditions, 4.5V, 125°C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 12.7 13.8 10.1
Maximum Datapath Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Military Conditions, 4.5V, 125°C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
0.08 0.08
0.09 0.09
11.5 0.10 0.10
11.0 10.2
11.8 16.1 0.14 0.14
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
0.08 0.08
9.78 0.09 0.09
11.5 0.10 0.10
10.9 10.2 10.4 10.4
11.8 16.1 0.14 0.14
ns/pF ns/pF
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor Cond 3.0V,
`-2' Speed Parameter Description
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Combinatorial Functions tPDD Internal Array Module Delay
Internal Decode Module Delay
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
10.5
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Military Conditions, 3.0V, 125°C)
Logic Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units
Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 12.1 12.1 13.8 13.8 16.2 16.2
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 15.9 14.7 18.0 16.6 21.1 19.5
40MX 42MX FPGA Families
(continued)
(Worst-Case Military Conditions, 3.0V, 125°C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 11.2
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.5
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 11.8 12.7 12.8 13.8 14.7 15.9 10.0 11.7
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Military Conditions, 3.0V, 125°C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
10.2 14.0 0.13 0.13
10.8 10.0 11.6 15.9 0.14 0.14
12.7 11.8
13.7 18.7 0.16 0.16
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
10.2 14.0 0.13 0.13
10.8 10.0 10.3 10.3 13.7 18.7 0.16 0.16
12.7 11.8 12.1 12.1
13.7 18.7 0.16 0.16
ns/pF ns/pF
Note: Delays based loading.
40MX 42MX FPGA Families
CLK, CLKA, CLKB Global Clock (Input)
accessible when MODE HIGH. This functions when MODE LOW.
QCLKA,B,C,D Quadrant Clock (Input/Output)
clock inputs clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
DCLK Diagnostic Clock (Input)
Quadrant clock inputs. When used register control signal, these pins function general-purpose I/Os.
Serial Data Input (Input)
clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground (Input)
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
SDO, TDO, Serial Data (Output)
Input supply voltage.
Input/Output (Input, Output)
Input, output, tri-state, bi-directional buffer. Input output levels compatible with standard CMOS specifications. Unused pins automatically driven Designer Series software.
Power Mode
Serial data output diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW. available 40MX devices.
Test Clock
Controls power mode 42MX devices. This must HIGH switch device power mode. exit power mode, must LOW.
MODE Mode (Input)
Clock signal shift Boundary Scan Test (BST) data into device. This functions when test fuse programmed. pins only available A42MX24, A42MX24A, A42MX36 devices.
Test Data
Controls multifunction pins (DCLK, PRA, PRB, SDI, TDO). provide verification capability, MODE should held HIGH. facilitate this, MODE should terminated through resistor that MODE pulled HIGH when required.
Connection
Serial data input instructions data. Data shifted rising edge TCK. This functions when test fuse programmed. pins only available A42MX24 A42MX36 devices.
Test Data
This connected circuitry within device. These pins driven voltage left floating with effect operation device.
PRA, Probe (Output)
Serial data output instructions test data. This functions when test fuse programmed. pins only available A42MX24 A42MX36 devices.
Test Mode Select
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. accessible when MODE HIGH. This functions when MODE LOW.
PRB, Probe (Output)
Serial data input boundary scan test mode. Data shifted rising edge TCK. This functions when test fuse programmed. pins only available A42MX24 A42MX36 devices.
Supply Voltage (Input)
Input HIGH supply voltage.
Supply Voltage (Input)
Input HIGH supply voltage, supplies array core only.
Supply Voltage (Input)
Input HIGH supply voltage, supplies cells only.
Wide Decode Output
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality.
When wide decode module used 42MX device, this used dedicated output from wide decode module. This direct connection eliminates additional interconnect delays associated with regular logic modules. implement direct connection, connect output buffer type output wide decode macro place this output reserved pins.
44-Pin PLCC
44-Pin PLCC
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
40MX 42MX FPGA Families
68-Pin PLCC
68-Pin PLCC
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
(continued)
84-Pin PLCC
84-Pin PLCC
40MX 42MX FPGA Families
A40MX04 A42MX09 A42MX16 A42MX24 Number Function Function Function Function PRB, MODE VCCA VCCI PRB, MODE VCCI VCCA PRB, (WD) (WD) (WD) MODE VCCI VCCA TMS, TDI, (WD) (WD) (WD)
A40MX04 A42MX09 A42MX16 Number Function Function Function CLK, MODE SDI, DCLK, PRA, PRB, VCCA SDO, (LP) VCCA VCCI SDI, PRA, VCCA VCCA (LP) VCCA VCCI SDI, PRA, VCCA
A42MX24 Function VCCA (WD) (WD) (WD) (WD) (WD) (WD) TCK, (LP) VCCA VCCI SDI, (WD) (WD) (WD) PRA, CLKA, VCCA
CLKB, CLKB, CLKB,
DCLK, DCLK, DCLK,
SDO, SDO, (WD)
CLKA, CLKA,
(continued)
100-Pin PQFP Package (Top View)
100-Pin PQFP
40MX 42MX FPGA Families
100-
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function PRB, PRB,
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function VCCA SDO, VCCA SDO,
DCLK, DCLK, MODE VCCA VCCI MODE VCCA VCCA
(LP) (LP) VCCA VCCI VCCA VCCA VCCI VCCA
100-
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function SDI, PRA, SDI, PRA,
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function CLK, MODE SDI, CLK, MODE SDI, VCCA VCCA
CLKB, CLKB, PRB, PRB,
DCLK, DCLK, PRA, PRA,
CLKA, CLKA,
40MX 42MX FPGA Families
(continued)
160-Pin PQFP Package (Top View)
160-Pin PQFP
160-
Number
A42MX09 Function DCLK, PRB, CLKB, VCCA CLKA, PRA, SDI,
A42MX16 Function DCLK, VCCI PRB, CLKB, VCCA CLKA, PRA, VCCI SDI,
A42MX24 Fucntion DCLK, (WD) (WD) VCCI (WD) (WD) PRB, CLKB, VCCA CLKA, PRA, (WD) (WD) (WD) (WD) VCCI (WD) (WD) SDI,
Number
A42MX09 Function VCCA VCCI VCCA (LP)
A42MX16 Function VCCA VCCA VCCI VCCA (LP)
A42MX24 Fucntion VCCA VCCA VCCI VCCA (LP) TCK,
40MX 42MX FPGA Families
160-
Number
A42MX09 Function SDO, VCCA
A42MX16 Function SDO, VCCI VCCA VCCI
A42MX24 Fucntion SDO, TDO, (WD) (WD) VCCI (WD) (WD) VCCA (WD) (WD) (WD) (WD) VCCI (WD) (WD) TDI, TMS,
Number
A42MX09 Function VCCI MODE
A42MX16 Function VCCA VCCA VCCI VCCA MODE
A42MX24 Fucntion VCCA VCCA VCCI VCCA MODE
(continued)
208-Pin PQFP Package (Top View)
208-Pin PQFP
40MX 42MX FPGA Families
208-
Number
A42MX16 Function MODE VCCA VCCI VCCA VCCA
A42MX24 Function VCCA MODE VCCA VCCI VCCA VCCA
A42MX36 Function VCCA MODE VCCA VCCI VCCA VCCA
Number
A42MX16 Function VCCI VCCA
A42MX24 Function TMS, TDI, (WD) (WD) VCCI (WD) (WD) (WD) (WD) VCCA VCCI
A42MX36 Function TMS, TDI, (WD) (WD) VCCI QCLKA, (WD) (WD) (WD) (WD) VCCA VCCI
208-
Number
A42MX16 Function VCCI SDO,
A42MX24 Function (WD) (WD) (WD) (WD) VCCI (WD) (WD) VCCA
A42MX36 Function (WD) (WD) QCLKB, (WD) (WD) VCCI (WD) (WD) VCCA
Number
A42MX16 Function (LP) VCCA VCCI VCCA VCCA SDI, VCCI
A42MX24 Function TCK, (LP) VCCA VCCI VCCA VCCA SDI, (WD) (WD) VCCI (WD)
A42MX36 Function TCK, (LP) VCCA VCCI VCCA VCCA SDI, (WD) (WD) VCCI (WD)
SDO, TDO, SDO, TDO,
40MX 42MX FPGA Families
208-
Number
A42MX16 Function PRA, CLKA, VCCA CLKB, PRB,
A42MX24 Function (WD) (WD) (WD) PRA, CLKA, VCCI VCCA CLKB, PRB,
A42MX36 Function (WD) QCLKD, (WD) (WD) PRA, CLKA, VCCI VCCA CLKB, PRB,
Number
A42MX16 Function VCCI DCLK,
A42MX24 Function (WD) (WD) (WD) (WD) VCCI (WD) (WD) DCLK,
A42MX36 Function (WD) (WD) (WD) (WD) QCLKC, VCCI (WD) (WD) DCLK,
(continued)
240-Pin PQFP Package (Top View)
240-Pin PQFP
40MX 42MX FPGA Families
240-
Number
A42MX36 Function DCLK, (WD) (WD) VCCI QCLKC, (WD) (WD) (WD) (WD) PRB, CLKB, VCCA VCCI CLKA, PRA, (WD) (WD)
Number
A42MX36 Function QCLKD, (WD) (WD) VCCI (WD) (WD) SDI, VCCA VCCI
Number
A42MX36 Function VCCA VCCA VCCI VCCA (LP) TCK, VCCI VCCA
Number
A42MX36 Function SDO, TDO, (WD) (WD) VCCI (WD) (WD) QCLKB, (WD) (WD) VCCI VCCA (WD) (WD)
240-
Number
A42MX36 Function (WD) (WD) QCLKA, VCCI (WD) (WD) TDI, TMS,
Number
A42MX36 Function VCCA VCCI
Number
A42MX36 Function VCCA VCCA VCCI VCCA
Number
A42MX36 Function VCCI MODE VCCA
40MX 42MX FPGA Families
Package Assignments (continued) 80-Pin VQFP
80-Pin VQFP
VQFP
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
40MX 42MX FPGA Families
(continued)
100- ackag
100-Pin VQFP
100-Pin VQFP Package
Number
A42MX09 Function MODE VCCA VCCI VCCA SDO,
A42MX16 Function MODE VCCI VCCA SDO,
Number
A42MX09 Function (LP) VCCA VCCI VCCA SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK,
A42MX16 Function (LP) VCCA VCCI VCCA SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK,
40MX 42MX FPGA Families
(continued)
176-Pin TQFP Package (Top View)
176-Pin TQFP
176-
Number
A42MX09 Function MODE VCCA VCCI
A42MX16 Function MODE VCCA VCCI VCCA VCCA
A42MX24 Function MODE VCCA VCCI VCCA VCCA
Number
A42MX09 Function VCCA SDO,
A42MX16 Function VCCI VCCA VCCI SDO,
A42MX24 Function TMS, TDI, (WD) (WD) VCCI (WD) (WD) (WD) (WD) VCCA (WD) (WD) (WD) (WD) VCCI (WD) (WD) SDO, TDO,
40MX 42MX FPGA Families
176-
Number
A42MX09 Function (LP) VCCA VCCI VCCA
A42MX16 Function (LP) VCCA VCCI VCCA VCCA
A42MX24 Function TCK, (LP) VCCA VCCI VCCA VCCA
Number
A42MX09 Function SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK,
A42MX16 Function SDI, VCCI PRA, CLKA, VCCA CLKB, PRB, VCCI DCLK,
A42MX24 Function SDI, (WD) (WD) VCCI (WD) (WD) (WD) (WD) PRA, CLKA, VCCA CLKB, PRB, (WD) (WD) (WD) (WD) VCCI (WD) (WD) DCLK,
208-Pin CQFP (Top View)
Index
A42MX36 208-Pin CQFP
40MX 42MX FPGA Families
208-Pin CQFP
Number
A42MX36 Function VCCA MODE VCCA VCCI VCCA VCCA
Number
A42MX36 Function TMS, TDI, (WD) (WD) VCCI QCLKA, (WD) (WD) (WD) (WD)
Number
A42MX36 Function VCCA VCCI (WD) (WD) QCLKB, (WD) (WD) VCCI (WD) (WD) TDO, VCCA
Number
A42MX36 Function TCK, (LP) VCCA VCCI VCCA VCCA
208-Pin CQFP (Continued)
Number
A42MX36 Function SDI, (WD) (WD) VCCI (WD) (WD)
Number
A42MX36 Function QCLKD, (WD) (WD) PRA, CLKA, VCCI
Number
A42MX36 Function VCCA CLKB, PRB, (WD) (WD) (WD) (WD)
Number
A42MX36 Function QCLKC, VCCI (WD) (WD) DCLK,
40MX 42MX FPGA Families
(continued)
256-Pin CQFP (Top View)
Index
A42MX36 256-Pin CQFP
256-Pin CQFP
Number
A42MX36 Function VCCA VCCA VCCI VCCA TCK,
Number
A42MX36 Function VCCA SDO, TDO, (WD) (WD) VCCI (WD) I/O, (WD) QCLKB,
Number
A42MX36 Function I/O, (WD) I/O, (WD) VCCI VCCA I/O, (WD) I/O, (WD) I/O, (WD) I/O, (WD) QCLKA, VCCI I/O, (WD) I/O, (WD)
Number
A42MX36 Function VCCA VCCA VCCI VCCA
40MX 42MX FPGA Families
256-Pin CQFP (Continued)
Number
A42MX36 Function MODE VCCA
Number
A42MX36 Function DCLK, (WD) (WD) VCCI QCLKC, (WD) (WD)
Number
A42MX36 Function (WD) (WD) PRB, CLKB, VCCA VCCI CLKA, PRA, (WD) (WD)
Number
A42MX36 Function QCLKD, (WD) (WD) VCCI (WD) (WD) SDI,
(continued)
272-
272-Pin PBGA
40MX 42MX FPGA Families
272-Pin PBGA
Ball
A42MX36 Function (WD) (WD) (WD) CLKA (WD) DCLK, (WD) PRB, (WD) (WD) (WD) MODE
Ball
A42MX36 Function (WD) QCLKC, CLKB PRA, (WD) QCLKD, (WD) SDI, VCCI VCCA (WD) VCCI VCCI VCCI VCCA VCCA VCCI
Ball
A42MX36 Function VCCI VCCI VCCI VCCA VCCI VCCA VCCI
Ball
A42MX36 Function VCCA VCCA (LP) VCCA VCCA VCCI TCK, VCCI VCCI VCCI VCCA
272-Pin PBGA (Continued)
Ball
A42MX36 Function VCCI VCCI VCCA VCCI
Ball
A42MX36 Function (WD) (WD) VCCA VCCI QCLKB, VCCI (WD)
Ball
A42MX36 Function (WD) (WD) SDO, TDO, TMS, (WD) (WD) (WD)
Ball
A42MX36 Function (WD) (WD) TDI, (WD) QCLKA, (WD)
40MX 42MX FPGA Families
following table lists critical changes that were made current version document.
Previous version v4.0.1 Changes current version (v6.0) Page
Because changes this data sheet extensive technical nature, this should viewed document. Please read would data sheet that published first time. Note that "Package Characteristics Mechanical Drawings" section been eliminated from data sheet. mechanical drawings contained separate document, "Package Characteristics Mechanical Drawings," available Actel site.
order provide latest information designers, some data sheets published before data been fully characterized. These data sheets marked "Advanced" Preliminary" data sheets. definition these categories follows:
data sheet contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
data sheet contains information based simulation and/or initial characterization. information believed correct, changes possible.
ion)
data sheet contains information that considered final.
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