PM7349 S/UNI4xD3F S/UNI-4xD3F Quad DS-3 Framer Data She
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S/UNI®-4xD3F Data Sheet Released
PM7349 S/UNI4xD3F
S/UNI-4xD3F
Quad DS-3 Framer
Data Sheet
Released Issue June 2001
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S/UNI®-4xD3F Data Sheet Released
Legal Information
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2001 PMC-Sierra, Inc. information proprietary confidential PMC-Sierra, Inc., customers' internal use. event, cannot reproduce part this document, form, without express written consent PMC-Sierra, Inc. PMC-2000314 (R5)
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None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage.
Trademarks
S/UNI SATURN registerd trademarks PMC-Sierra, Inc. SCI-PHY trademark PMC-Sierra, Inc.
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Contacting PMC-Sierra
PMC-Sierra 8555 Baxter Place Burnaby, Canada Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Site: http://www.pmc-sierra.com
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Revision History
Issue
Issue Date
June 2001
Details Change
Included Application Examples, Description, complete Normal Mode Register Description, Operation, Functional Timing, Absolute Maximum Rating, A.C. Timing Characteristics, Microprocessor Interface Timing sections. Changed references PMDL (path maintenance data link). Modified block diagram include ROHM[4:1]. Corrected references TDAT TDATI.
July 2000 July 2000 June 2000 March 2000
Name datasheet corrected reflect device name change. name S/UNI-4xD3F. Device name changed from 4x45 S/UNI-4xDS3F. Corrected listing description section. Corrected diagram REF8KI. Document created.
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Table Contents
Features.14 Applications References Definitions Application Example Block Diagram Description.23 Diagram Descriptions.28 Functional Description 10.1 Framer.40 10.2 Framer 10.3 Framer.44 10.3.1 Frame Find Algorithms 10.4 RBOC Bit-Oriented Code Detector 10.5 RDLC PMDL Receiver 10.6 PMON Performance Monitor Accumulator.49 10.7 PRGD Pseudo-Random Sequence Generator/Detector 10.8 Transmitter 10.9 Transmitter.50 10.10 Transmitter 10.11 XBOC Oriented Code Generator 10.12 TDPR PMDL Transmitter 10.13 JTAG Test Access Port.53 10.14 Microprocessor Interface Normal Mode Register Descriptions.57 Test Features Description.171 12.1 JTAG Test Port .174 Operation .177 13.1 Software Initialization Sequence.177 13.2 Register Settings Basic Configurations .178 13.3 Frame Format .178 13.4 G.751 Frame Format .181
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13.5 G.832 Frame Format .182 13.6 Frame Format .183 13.7 Servicing Interrupts .184 13.8 Using Performance Monitoring Features .185 13.9 Using TDPR Internal PMDL Transmitter .185 13.9.1 TDPR Polling Mode.186 13.9.2 TDPR Interrupt-driven Mode .187 13.9.3 TDPR Interrupt Routine.187 13.10 Using RDLC Internal Data Link Receiver .188 13.10.1 RDLC Interrupt-driven Mode .189 13.10.2 RDLC Polled Mode.190 13.11 PRGD Pattern Generation .192 13.11.1 Generating Detecting Repetitive Patterns with PRGD.193 13.11.2 Common Test Patterns.193 13.12 JTAG Support.195 13.12.1 Controller .196 13.12.2 Boundary Scan Instructions .198 13.12.3 Boundary Scan Cell Description .199 Functional Timing.201 Absolute Maximum Ratings.221 D.C. Characteristics.222 Microprocessor Interface Timing Characteristics .224 A.C. Timing Characteristics .228 Ordering Thermal Information .238 Mechanical Information .239
Notes .240
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List Registers
Register 000H, 100H, 200H, 300H: S/UNI-4xD3F Configuration Register 001H, 101H, 201H, 301H: S/UNI-4xD3F Configuration Register 002H, 102H, 202H, 302H: S/UNI-4xD3F Transmit Configuration.62 Register 003H, 103H, 203H, 303H: S/UNI-4xD3F Receive Configuration Register 004H, 104H, 204H, 304H: Data Link FERF/RAI Control Register 005H, 105H, 205H, 305H: S/UNI-4xD3F Interrupt Status Register 006H: S/UNI-4xD3F Identification, Master Reset, Global Monitor Update Register 007H, 107H, 207H, 307H: S/UNI-4xD3F Clock Activity Monitor Interrupt Identification.71 Register 010H, 110H, 210H, 310H: Change PMON Performance Meters Register 011H, 111H, 211H, 311H: PMON Interrupt Enable/Status Register 014H, 114H, 214H, 314H: PMON Event Count Register 015H, 115H, 215H, 315H: PMON Event Count Register 016H, 116H, 216H, 316H: PMON Framing Error Event Count LSB.75 Register 017H, 117H, 217H, 317H: PMON Framing Error Event Count MSB.75 Register 018H, 118H, 218H, 318H: PMON EXZS Count Register 019H, 119H, 219H, 319H: PMON EXZS Count Register 01AH, 11AH, 21AH, 31AH: PMON Parity Error Event Count Register 01BH, 11BH, 21BH, 31BH: PMON Parity Error Event Count Register 01CH, 11CH, 21CH, 31CH: PMON Path Parity Error Event Count Register 01DH, 11DH, 21DH, 31DH: PMON Path Parity Error Event Count Register 01EH, 11EH, 21EH, 31EH: PMON FEBE/J2-EXZS Event Count LSB.79 Register 01FH, 11FH, 21FH, 31FH: PMON FEBE/J2-EXZS Event Count Register 030H, 130H, 230H, 330H: FRMR Configuration Register 031H, 131H, 231H, 331H: FRMR Interrupt Enable (ACE=0) Register 031H, 131H, 231H, 331H: FRMR Additional Configuration Register (ACE=1).84 Register 032H, 132H, 232H, 332H: FRMR Interrupt Status Register 033H, 133H, 233H, 333H: FRMR Status Register 034H, 134H, 234H, 334H: TRAN Configuration Register 035H, 135H, 235H, 335H: TRAN Diagnostic.93 Register 038H, 138H, 238H, 338H: FRMR Framing Options Register 039H, 139H, 239H, 339H: FRMR Maintenance Options
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Register 03AH, 13AH, 23AH, 33AH: FRMR Framing Interrupt Enable Register 03BH, 13BH, 23BH, 33BH: FRMR Framing Interrupt Indication Status.100 Register 03CH, 13CH, 23CH, 33CH: FRMR Maintenance Event Interrupt Enable .102 Register 03DH, 13DH, 23DH, 33DH: FRMR Maintenance Event Interrupt Indication .104 Register 03EH, 13EH, 23EH, 33EH: FRMR Maintenance Event Status .106 Register 040H, 140H, 240H, 340H: TRAN Framing Options.108 Register 041H, 141H, 241H, 341H: TRAN Status Diagnostic Options.109 Register 042H, 142H, 242H, 342H: TRAN BIP-8 Error Mask Register 043H, 143H, 243H, 343H: TRAN Maintenance Adaptation Options Register 044H, 144H, 244H, 344H: J2-FRMR Configuration. Register 045H, 145H, 245H, 345H: J2-FRMR Status Register 046H, 146H, 246H, 346H: J2-FRMR Alarm Interrupt Enable Register 047H, 147H, 247H, 347H: J2-FRMR Alarm Interrupt Status Register 048H, 148H, 248H, 348H: J2-FRMR Error/Xbit Interrupt Enable .121 Register 049H, 149H, 249H, 349H: J2-FRMR Error/Xbit Interrupt Status .123 Register 04CH, 14CH, 24CH, 34CH: J2-TRAN Configuration.125 Register 04DH, 14DH, 24DH, 34DH: J2-TRAN Diagnostic .126 Register 04EH, 14EH, 24EH, 34EH: J2-TRAN TS97 Signaling.127 Register 04FH, 14FH, 24FH, 34FH: J2-TRAN TS98 Signaling .128 Register 050H, 150H, 250H,350H: RDLC Configuration .129 Register 051H, 151H, 251H, 351H: RDLC Interrupt Control.131 Register 052H, 152H, 252H, 352H: RDLC Status.132 Register 053H, 153H, 253H, 353H: RDLC Data .134 Register 054H, 154H, 254H, 354H: RDLC Primary Address Match .135 Register 055H, 155H, 255H, 355H: RDLC Secondary Address Match .136 Register 058H, 158H, 258H, 358H: TDPR Configuration .137 Register 059H, 159H, 259H, 359H: TDPR Upper Transmit Threshold .139 Register 05AH, 15AH, 25AH, 35AH: TDPR Lower Interrupt Threshold.140 Register 05BH, 15BH, 25BH, 35BH: TDPR Interrupt Enable .141 Register 05CH, 15CH, 25CH, 35CH: TDPR Interrupt Status/UDR Clear .142 Register 05DH, 15DH, 25DH, 35DH: TDPR Transmit Data.144 Register 090H, 190H, 290H, 390H: Control .145 Register 091H, 191H, 291H, 391H: Identifier Status.147
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Register 092H, 192H, 292H, 392H: Indirect Address.148 Register 093H, 193H, 293H, 393H: Indirect Data .149 Register 094H, 194H, 294H, 394H: EXPLD Type Label .150 Register 095H, 195H, 295H, 395H: Payload Type Label Control/Status .151 Register 098H, 198H, 298H, 398H: RBOC Configuration/Interrupt Enable.153 Register 099H, 199H, 299H, 399H: RBOC Interrupt Status.154 Register 09AH, 19AH, 29AH, 39AH: XBOC Code .155 Register 09BH, 19BH, 29BH, 39BH: S/UNI-4xD3F Miscellaneous .156 Register 09CH, 19CH, 29CH, 39CH: S/UNI-4xD3F FRMR Status .158 Register 0A0H, 1A0H, 2A0H, 3A0H: PRGD Control.159 Register 0A1H, 1A1H, 2A1H, 3A1H: PRGD Interrupt Enable/Status.161 Register 0A2H, 1A2H, 2A2H, 3A2H: PRGD Length .163 Register 0A3H, 1A3H, 2A3H, 3A3H: PRGD Tap.164 Register 0A4H, 1A4H, 2A4H, 3A4H: PRGD Error Insertion.165 Register 0A8H, 1A8H, 2A8H, 3A8H: Pattern Insertion .166 Register 0A9H, 1A9H, 2A9H, 3A9H: Pattern Insertion .166 Register 0AAH, 1AAH, 2AAH, 3AAH: Pattern Insertion #3.167 Register 0ABH, 1ABH, 2ABH, 3ABH: Pattern Insertion #4.167 Register 0ACH, 1ACH, 2ACH, 3ACH: PRGD Pattern Detector #1.168 Register 0ADH, 1ADH, 2ADH, 3ADH: PRGD Pattern Detector #2.168 Register 0AEH, 1AEH, 2AEH, 3AEH: PRGD Pattern Detector .169 Register 0AFH, 1AFH, 2AFH, 3AFH: PRGD Pattern Detector .169 Register 40CH: S/UNI-4xD3F Identification .170 Register 400H: S/UNI-4xD3F Master Test .173
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List Figures
Figure S/UNI-4xD3F Operating Quad Framer Device Frame Relay Equipment Figure Block Diagram Figure Framing Algorithm (CRC_REFR 0).46 Figure Framing Algorithm (CRC_REFR 1).47 Figure Frame Structure .179 Figure G.751 Frame Structure .181 Figure G.832 Frame Structure .182 Figure Frame Structure .183 Figure Typical Data Frame.191 Figure Example Multi-Packet Operational Sequence .191 Figure PRGD Pattern Generator .192 Figure Boundary Scan Architecture .195 Figure Controller Finite State Machine.197 Figure Input Observation Cell (IN_CELL) .199 Figure Output Cell (OUT_CELL) .199 Figure Bi-directional Cell (IO_CELL) .200 Figure Layout Output Enable Bi-directional Cells .200 Figure Receive Stream.201 Figure Receive Stream .201 Figure Receive Bipolar Stream .202 Figure Receive Unipolar Stream .202 Figure Receive Bipolar Stream .202 Figure Receive Unipolar Stream.203 Figure Receive Bipolar Stream .203 Figure Receive Unipolar Stream .204 Figure Generic Receive Stream .204 Figure Receive Overhead .205 Figure Receive G.832 Overhead .206 Figure Receive G.751 Overhead .206 Figure Receive Overhead.207 Figure Transmit Stream.207 Figure Transmit Stream .208 Figure Transmit Bipolar Stream .208
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Figure Transmit Unipolar Stream .209 Figure Transmit Bipolar Stream .209 Figure Transmit Unipolar Stream.210 Figure Transmit Bipolar Stream .210 Figure Transmit Unipolar Stream .211 Figure Generic Transmit Stream .211 Figure Transmit Overhead .212 Figure Transmit G.832 Overhead .214 Figure Transmit G.751 Overhead .214 Figure Transmit Overhead.215 Figure Framer Mode Transmit Input Stream.215 Figure TGAPCLK Framer Mode Transmit Input Stream .216 Figure Framer Mode with Receive Output Stream .216 Figure RGAPCLK Framer Mode with Receive Output Stream .216 Figure Framer Mode G.751 Transmit Input Stream .217 Figure TGAPCLK Framer Mode with G.751 Transmit Input Stream .217 Figure Framer Mode G.751 Receive Output Stream.217 Figure RGAPCLK Framer Mode G.751 Receive Output Stream .218 Figure Framer Mode G.832 Transmit Input Stream .218 Figure TGAPCLK Framer Mode with G.832 Transmit Input Stream .218 Figure Framer Mode G.832 Receive Output Stream.219 Figure RGAPCLK Framer Mode G.832 Receive Output Stream .219 Figure Framer Mode Transmit Input Stream .219 Figure TGAPCLK Framer Mode Transmit Input Stream .220 Figure Framer Mode Receive Output Stream .220 Figure RGAPCLK Framer Mode Receive Output Stream .220 Figure Microprocessor Interface Read Timing .225 Figure Microprocessor Interface Write Timing .226 Figure RSTB Timing.228 Figure Transmit Interface Timing .230 Figure Receive Interface Timing .234 Figure JTAG Port Interface Timing.236
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List Tables
Table Transmission System Sublayer Processing Acceptance Output Table Summary Receive Detection Features Table Framer Multiframe Format.44 Table Register Memory Table STATSEL[2:0] Options Table TFRM[1:0] Transmit Frame Structure Configurations Table LOF[1:0] Integration Period Configuration Table RFRM[1:0] Receive Frame Structure Configurations Table FRMR EXZS/LCV Count Configurations.85 Table FRMR Configurations Table FRMR FORMAT[1:0] Configurations Table TRAN FORMAT[1:0] Configurations.108 Table FRMR Threshold Configurations.115 Table RDLC PBS[2:0] Data Status.132 Table Payload Type Match Configurations .150 Table PRGD Pattern Detector Register Configuration.159 Table PRGD Generated Error Rate Configurations.165 Table Test Mode Register Memory .171 Table Instruction Register .174 Table Identification Register.174 Table Boundary Scan Register .175 Table Register Settings Basic Configurations.178 Table Frame Overhead Operation .179 Table G.751 Frame Overhead Operation .181 Table G.832 Frame Overhead Operation .182 Table Frame Overhead Operation.184 Table Pseudo Random Pattern Generation 0).193 Table Repetitive Pattern Generation 1).194 Table Receive Overhead Bits.205 Table Transmit Overhead Bits.213 Table Absolute Maximum Ratings.221 Table Characteristics .222 Table Microprocessor Interface Read Access .224
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Table Microprocessor Interface Write Access (Figure .226 Table RSTB Timing (Figure .228 Table Transmit Interface Timing (Figure 63).228 Table Receive Interface Timing (Figure 64).233 Table JTAG Port Interface (Refer Figure .235 Table Packaging Information.238 Table Thermal Information .238
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Features
S/UNI®-4xD3F quad DS3, (G.751 G.832), framer device. Each channel independently configured DS3, Framer. Furthermore, Optionally generates gapped transmit receive clocks interfacing with devices that only need access payload data bits. Provides programmable pseudo-random test pattern generation, detection, analysis features. Provides integral transmit receive HDLC controllers with 128-byte FIFO depths. Provides performance monitoring counters suitable accumulation periods second. Provides 8-bit microprocessor interface configuration, control status monitoring. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. power CMOS technology with tolerant inputs. available high density 256-pin SBGA package mm).
receiver section: Provides frame synchronization C-bit parity applications, alarm detection, accumulates line code violations (LCVs), framing errors, parity errors, path parity errors, far-end block error (FEBE) events. Also detects alarm channel (FEAC) codes provides integral HDLC receiver terminate path maintenance data link (PMDL). Provides frame synchronization G.751 G.832 applications, alarm detection, accumulates LCVs, framing errors, parity errors, FEBE events. Also, G.832, detects Trail Trace provides integral HDLC receiver terminate either Network Requirement General Purpose data link. Provides frame synchronization G.704 6.312 Mbit/s applications, alarm detection, accumulates LCVs, framing errors, parity errors. Also provides integral HDLC receiver terminate data link. Provides receive HDLC controller with 128-byte FIFO accumulate data link information. Provides detection yellow alarm loss frame (LOF), accumulates BIP-8 errors, framing errors FEBE events. Provides programmable pseudo-random test-sequence detection length patterns conforming ITU-T O.151 standards) analysis features.
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transmitter section: Provides frame insertion C-bit parity applications, alarm insertion, diagnostic features. Also inserts, FEAC codes provides integral HDLC transmitter insert PMDL. Provides frame insertion G.751 G.832 applications, alarm insertion, diagnostic features. Also, G.832, inserts Trail Trace provides integral HDLC transmitter insert either Network Requirement General Purpose data link. Provides frame insertion G.704 6.312 Mbit/s applications, alarm insertion, diagnostic features. Also provides integral HDLC transmitter insert PMDL. Provides transmit HDLC controller with 128-byte FIFO. Provides programmable pseudo-random test sequence generation 232-1 length sequences conforming ITU-T O.151 standards). Diagnostic abilities include single error insertion error insertion error rates ranging from 10-1 10-7.
S/UNI-4xD3F also provides diagnostic loopbacks, line loopbacks, payload loopbacks.
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Applications
SONET/SDH E3/DS3 Tributary Interfaces J2/E3/DS3 Line Interfaces DS3/E3/J2 Digital Cross Connect Interfaces DS3/E3/J2 Internet Access Interfaces DS3/E3/J2 Frame Relay Interfaces
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References
ANSI T1.627 1993, "Broadband ISDN ALayer Functionality Specification". ANSI T1.107a 1990, "Digital Hierarchy Supplement Formats Specifications (DS3 Format Applications)". ANSI T1.107 1995, "Digital Hierarchy Formats Specifications". ANSI T1.646 1995, "Broadband ISDN Physical Layer Specification User-Network Interfaces Including DS1/ATM". AForum, af-phy-0029.000, "6,312 Kbps Specification, Version 1.0", June 1995. ITU-T Recommendation O.151 "Error Performance Measuring Equipment Operating Primary Rate Above", October, 1992. ITU-T Recommendation I.432 "B-ISDN User-Network Interface Physical Layer Specification", 1993 ITU-T Recommendation G.703 "Physical/Electrical Characteristics Hierarchical Digital Interfaces", 1991. ITU-T Recommendation G.704 "General Aspects Digital Transmission Systems; Terminal Equipments Synchronous Frame Structures Used 1544, 6312, 2048, 8488 kbit/s Hierarchical Levels", July, 1995. ITU-T Recommendation G.751 CCITT Blue Book Fasc. III.4, "Digital Multiplex Equipments Operating Third Order Rate 34,368 kbit/s Fourth Order Rate 139,264 kbit/s Using Positive Justification", 1988. ITU-T Draft Recommendation G.775 "Loss Signal (LOS) Alarm Indication Signal (AIS) Defect Detection Clearance Criteria", October 1993. ITU-T Recommendation G.832 "Transport Elements Networks: Frame Multiplexing Structures", 1993. ITU-T Recommendation Q.921 "ISDN User-Network Interface Data Link Layer Specification", March, 1993. Technical Reference, "NTT Technical Reference High-Speed Digital Leased Circuit Services", 1991. ITU-T Recommendation O.161 "In-Service Code Violation Monitors Digital Systems", CCITT Blue Book Fasc. IV.4, 1988. ITU-T Recommendation I.413 "B-ISDN User-Network Interface", March 1993 686, "Business TeleCommunications (BTC); Mbit/s Mbit/s digital leased lines (D34U, D34S, D140U D140S); Network interface presentation", January 1996. 689, "Business TeleCommunications (BTC); Mbit/s digital leased lines (D34U D34S); Terminal equipment interface", April 1995.
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687, "Business TeleCommunications (BTC); Mbit/s digital leased lines (D34U D34S); Connection characteristics", January 1996. Telcordia, GR-499-CORE, "Transport Systems Generic Requirements (TSGR): Common Requirements", Issue Dec. 1995. ANSI T1.624 1993, "Broadband ISDN User-Network Interfaces Rates Formats Specifications".
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Definitions
following table defines abbreviations used this document.
ABIP CMOS COFA CPERR DSLAM EXZS F-bit FEAC FEBE FERF FERR FIFO HDLC ISDN JTAG PERR PMDL PMON Application Identification Channel Alarm Indication Signal Asynchronous Transfer Mode Interleaved Parity Complementary Metal Oxide Semiconductor Change Frame Alignment Path Parity Error Cyclic Redundancy Check Access Multiplexer Digital Signal Level Digital Signal Level Excess Zeros Framing Frame Alignment Signal Far-End Alarm Control Far-End Block Error Receive Failure Framing Error First-In First-Out Header Check Sequence High-level Data Link Controller Integrated Services Digital network International Telecommunications Union Joint Test Action Group Loss Cell Delineation Line Code Violation Loss Frame Loss Signal Return Zero Frame Parity Error Physical Layer Path Maintenance Data Link Performance Monitor Packet Over SONET Point-to-Point Protocol Receive Alarm Indication
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RBOC RDLC SBGA SCI-PHY SMDS SONET
Oriented Code Detector Data Link Receiver Receive Error Detection Super Ball Grid Array SATURN® Compatible Interface Specification Alayer devices Switched Multi-Megabit Data Service Synchronous Optical Network Test Access Port Telecom System Block Trail Trace Buffer
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Application Example
PM7349 S/UNI-4xD3F functionally equivalent PM7349 S/UNI-QJET placed DS3/E3/J2 Transceiver mode. J2/E3/T3 framer, S/UNI-4xD3F used router, frame relay switch, multiplexer applications. Refer Figure
Figure S/UNI-4xD3F Operating Quad Framer Device Frame Relay Equipment
Access Side Uplink Side
Unchannelized J2/E3/T3 Card Port Channelized Card PM4314 QDSX PM4388 TOCTL J2/E3/T3
PM7366 FREEDM-8
Switch/Router Core Switch Fabric
PM7366 FREEDM-8
PM7349 S/UNI4xD3F
J2/E3/T3 J2/E3/T3 J2/E3/T3
Port Channelized Card PM4314 QDSX PM6344 EQUAD PM7366 FREEDM-8
Processor Port Unchannelized Card (M13) PM4388 TOCTL PM7364 FREEDM32
Packet Memory
Packet Over SONET Card DS-3s Over OC-3) PM7366 FREEDM-8 PM7349 S/UNI4xD3F PM5342 SPECTRA155
DS-3
PM8313 D3MX
PM7366 FREEDM-8
Optics
unchannelized J2/E3/T3 line card, S/UNI-4xD3F directly connects more PM7366 FREEDM-8 HDLC controllers. Each FREEDM-8 process high-speed links such process eight lower speed links such S/UNI-4xD3F gaps overhead bits that only payload data passed from FREEDM-8. line side, S/UNI-4xD3F connected more J2/E3/T3 line interface units. system side, S/UNI-4xD3F interfaces with data link device over serial interface. PPP-Over-SONET (POS) application, S/UNI-4xD3F connects PM5342 SPECTRA155 three data streams onto three corresponding STS-1 services that collectively carried over OC-3 link.
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Block Diagram
Figure Block Diagram
TDATI[4:1] TFPI/TMFP[4:1] TICLK[4:1] TOHINS[4:1] TOH[4:1] TOHCLK[4:1] TOHFP[4:1] TFPO/TMFPO/ TGAPCLK[4:1]
XBOC FEAC
TDPR HDLC
Access
Trail Buffer
IEEE P1149.1 JTAG Test Access Port
TPOS/TDATO[4:1] TNEG/TOHM[4:1] TCLK[4:1]
Line Encode
TRAN Transmit Framer
RCLK[4:1] RPOS/RDATI[4:1] RNEG/RLCV/ROHM[4:1]
Line Decode
FRMR Receive Framer
PRGD Tester
RBOC FEAC
RDLC HDLC
PMON Perf. Monitor
Access
Trail Buffer
Microprocessor
A[10:0]
TRSTB RSTB INTB
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RDATO [4:1] ROVRHD [4:1] FRMSTAT[4:1] RSCLK/RGAPCLK[4:1] REF8KD/RFPO/RMFPO[4:1]
[4:1] ROHCLK [4:1] ROHPF [4:1]
D[7:0]
S/UNI®-4xD3F Data Sheet Released
Description
PM7349 S/UNI-4xD3F comprised integrated quad DS3, framers. functionally equivalent PM7346 S/UNI-QJET placed DS3/E3/J2 Transceiver mode. S/UNI-4xD3F contains: Integral framers that provide framing error accumulation accordance with ANSI T1.107, T1.107a. Integral framers that provide framing accordance with ITU-T Recommendations G.832 G.751. Integral framers that provide framing accordance with ITU-T Recommendation G.704 I.432.
S/UNI-4xD3F accepts outputs appropriate type bipolar unipolar signals described Table
Table Transmission System Sublayer Processing Acceptance Output Transmission System Sublayer Processing
Acceptance Output
Accepts outputs both digital B3ZS-encoded bipolar unipolar signals compatible with C-bit parity applications. Accepts outputs both HDB3-encoded bipolar unipolar signals compatible with G.751 G.832 applications. Accepts outputs both B8ZS-encoded bipolar unipolar signals compliant with G.704 6.312 Mbit/s applications.
receive direction, S/UNI-4xD3F frames signals with maximum average reframe time detects LCVs, LOS, framing errors, parity errors, path parity errors, AIS, FERF, idle code. overhead bits extracted presented serial outputs. When C-bit parity mode, PMDL FEAC channels extracted. (HDLC receivers provided PMDL support.) Valid bit-oriented codes FEAC channels also detected available through microprocessor port.
Table Summary Receive Detection Features Transmission System Sublayer Processing
Transmit Receive
Receive Receive Receive
Detected Features
LCVs, LOS, framing errors, parity errors, path parity errors, AIS, FERF, idle code LCVs, LOS, framing errors, AIS, LCVs, LOS, LOF, framing errors, physical layer AIS, payload AIS, CRC-5 errors, Remote Alarm,
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S/UNI®-4xD3F Data Sheet Released
receive direction, S/UNI-4xD3F frames G.751 G.832 signals with maximum average reframe times G.751 frames G.832 frames. LCVs, LOS, framing errors, alarm indication signals (AIS), receive alarm indications (RAI) detected. Also detected when processing G.832 formatted data parity errors, FERF, FEBEs. well, trace message extracted made available through microprocessor port. HDLC receivers provided either G.832 Network Requirement G.832 General Purpose Data Link support. receive direction, S/UNI-4xD3F frames G.704 6.312 signals with maximum average reframe time 5.07 alternate framing algorithm that uses CRC-5 bits rule 99.9% static mimic framing patterns available with maximum average reframe time 10.22 when operating with error rate. This algorithm selected CRC_REFR J2-FRMR Configuration register. LCVs, LOS, loss frame (LOF), framing errors, physical layer AIS, payload AIS, CRC-5 errors, Remote Alarm, detected. HDLC receivers provided Data Link support. S/UNI-4xD3F also provides error event accumulation. Framing errors, LCVs, parity errors, path parity errors, FEBEs accumulated, when appropriate, saturating counters DS3, frames. detection DS3, provided recommended ITU-T G.783 with integration times transmit direction, S/UNI-4xD3F inserts framing, bits. When enabled C-bit parity operation, bit-oriented code transmitters HDLC transmitters provided insertion FEAC channels PMDL appropriate overhead bits. inserted using internal register bits other status signals such idle signal inserted when they enabled internal register bits. When operation selected, Cbit Parity (the first C-bit first sub-frame) forced toggle that downstream equipment will confuse M23-formatted stream with "stuck-at C-bits C-bit parity application. transmit direction, S/UNI-4xD3F inserts framing either G.832 G.751 format. When device enabled G.832 operation, provides HDLC transmitter that Network Requirement General Purpose Data Link inserted into appropriate overhead bits. other status signals inserted internal register bits. transmit direction, S/UNI-4xD3F inserts 6.312 Mbit/s G.704 framing. HDLC transmitters provided Data Links inserted. CRC-5 check bits calculated inserted into multiframe. External pins provided that overhead bits within frame overwritten. S/UNI-4xD3F also supports diagnostic options that allow insert, when appropriate, transmit framing format, parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, LCVs, all-zeros, AIS, RAIs, Remote Alarms. S/UNI-4xD3F configured, controlled, monitored generic 8-bit microprocessor through which internal registers accessed. sources interrupts identified, acknowledged, masked with this interface.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
S/UNI-4xD3F requires software. initialization sequence order guarantee proper device operation long term reliability. Please refer Section 13.1 this document details program this sequence.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Diagram
S/UNI-4xD3F packaged 256-pin SBGA package having body size pitch 1.27
Quadrant A11/A20 K11/K20
BIAS D[1] D[0] D[5] D[4] D[2] A[0] D[6] D[3] A[3] A[2] A[1] D[7] A[7] A[6] A[5] A[4]
Bottom View (Top Left)
Quadrant A1/A10 K1/K10
A[9] A[8] A[10] RSTB INTB TRSTB TNEG/ TOHM[4] TCLK[4] RCLK[4] TPOS[3]/ TDATO[3] RPOS[3] RNEG[2]/ RDATI[2] TNEG/ TOHM[1] RCLK[1]
TPOS[4]/ RNEG[4]/ TCLK[3] TDATO[4] RDATI[4] RPOS[4] TNEG/ TOHM[3] BIAS TNEG/ TOHM[2] RCLK[3]
TPOS[2]/ TCLK[2] TDATO RNEG[3]/ RDATI[3] RCLK[2] TCLK[1] TOH[4] TOHFP[4] RPOS[2] TPOS[1]/ TDATO[1] RNEG[1]/ RDATI[1]
Bottom View (Top Right)
RPOS[1] TOHINS[4]
TOHCLK[4] ROH[4] ROHFP[4]
ROHCLK[4] TOH[3]
TOHINS[3] TOHCLK[3]
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Quadrant L11/L20 Y11/Y20
BIAS
Bottom View (Bottom Left)
REF8KO/ RFPO/ RMFPO[4] TFPI/ TMFPI[3] TDATI[3]
TICLK[4] TFPI/ TMFPI[4] TDATI[4]
TFPO/ TMFPO/ TGAPCLK[4] RDATO[4]
ROVRHD[4] RSCLK/ RGAPCLK[4] TICLK[3]
Quadrant L1/L10 Y1/Y10
RSCLK/
ROVRHD[2] RGAPCLK[3] TMFPI[2] TICLK[2] TDATI[2] RSCLK/ TFPI/ RGAPCLK[2] TMFPI[1] RDATO[2] TICLK[1]
TOHINS[2]
TOHFP[3] ROHCLK[3] TOHFP[2] TOH[1] TOHFP[1]
ROH[3] ROHFP[3] TOHCLK[2] ROHFP[2] TOHCLK[1] ROHFP[1]
TOH[2] ROH[2]
Bottom View (Bottom Right)
ROHCLK[2] ROHCLK[1]
TOHINS[1] ROH[1]
FRMSTAT[2] REF8KI RSCLK/ BIAS RGAPCLK[1] TFPO/ REF8KO/ TMFPO/ RFPO/ TGAPCLK[1] RMFPO[1] TDATI[1]
FRMSTAT[1] FRMSTAT[3] FRMSTAT[
ROVRHD[3] TFPI/ RDATO[3] TFPO/
ROVRHD[1] RDATO[1]
REF8KO/ TMFPO/ RFPO/ TGAPCLK[3] RMFPO[3
TFPO/ REF8KO/ TMFPO/ RFPO/ TGAPCLK[2] RMFPO[2]
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Descriptions
Name
TPOS[4] TPOS[3] TPOS[2] TPOS[1] TDATO[4] TDATO[3] TDATO[2] TDATO[1]
Type
Output
Function
Transmit Digital Positive Pulse (TPOS[4:1]) contains positive pulses transmitted B3ZS-encoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail output format selected. Transmit Data (TDATO[4:1]) contains transmit data stream when single-rail (unipolar) output format enabled when non-DS3/E3/J2-based transmission system selected. TPOS/TDATO[4:1] function selection controlled TFRM[1:0] TUNI bits S/UNI-4xD3F Transmit Configuration Registers. Output signal polarity control provided TPOSINV S/UNI-4xD3F Transmit Configuration Registers. Both TPOS[4:1] TDATO[4:1] updated falling edge TCLK[4:1] default, configured update rising edge TCLK[4:1] through TCLKINV S/UNI-4xD3F Transmit Configuration Registers. Both TPOS[4:1] TDATO[4:1] updated rising edge TICLK[4:1], enabled TICLK S/UNI-4xD3F Transmit Configuration Registers.
TNEG[4] TNEG[3] TNEG[2] TNEG[1] TOHM[4] TOHM[3] TOHM[2] TOHM[1]
Output
Transmit Digital Negative Pulse (TNEG[4:1]) contains negative pulses transmitted B3ZSencoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail output format selected. Transmit Overhead Mask (TOHM[4:1]) indicates position overhead bits (non-payload bits) transmission system stream aligned with TDATO[4:1]. TOHM[4:1] indicates location M-frame boundary DS3, position frame boundary position multiframe boundary when single-rail (unipolar) input format enabled. TNEG/TOHM[4:1] function selection controlled TFRM[1:0] TUNI bits S/UNI-4xD3F Transmit Configuration registers. Output signal polarity controlled TNEGINV S/UNI-4xD3F Transmit Configuration registers. Both TNEG[4:1] TOHM[4:1] updated falling edge TCLK[4:1] default, enabled update rising edge TCLK[4:1]. This sampling controlled TCLKINV S/UNI-4xD3F Transmit Configuration registers. Note: Both TNEG[4:1] TOHM[4:1] updated rising edge TICLK[4:1] enabling TICLK S/UNI-4xD3F Transmit Configuration registers.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
TCLK[4] TCLK[3] TCLK[2] TCLK[1]
Type
Output
Function
Transmit Output Clock (TCLK[4:1]) provides transmit direction timing. TCLK[4:1] buffered version TICLK[4:1. TCLK[4:1} enabled update TPOS/TDATO[4:1] TNEG/TOHM[4:1] outputs rising falling edge. Receive Digital Positive Pulse (RPOS[4:1]) contains positive pulses received B3ZS-encoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail input format selected. Receive Data (RDATI[4:1]) contains data stream when single-rail (unipolar) input format enabled when non-DS3/E3/J2 based transmission system being processed (for example RDATI contain stream). RPOS/RDATI[4:1] function selection controlled RFRM[1:0] bits S/UNI-4xD3F Configuration Registers bits FRMR, FRMR, FRMR Configuration Registers. Both RPOS[4:1] RDATI[4:1] sampled rising edge RCLK[4:1] default, enabled sampling falling edge RCLK[4:1]. This sampling controlled RCLKINV S/UNI4xD3F Receive Configuration Registers. Note: Signal polarity control provided RPOSINV same registers.
RPOS[4] RPOS[3] RPOS[2] RPOS[1] RDATI[4] RDATI[3] RDATI[2] RDATI[1]
Input
RNEG[4] RNEG[3] RNEG[2] RNEG[1] RLCV[4] RLCV[3] RLCV[2] RLCV[1] ROHM[4] ROHM[3] ROHM[2] ROHM[1]
Input
Receive Digital Negative Pulse (RNEG[4:1]) contains negative pulses received B3ZS encoded DS3, HDB3-encoded B8ZSencoded transmission system when dual-rail input format selected. Receive (RLCV[4:1]) contains indications when single-rail (unipolar) input format enabled DS3, applications. Each represented RCLK[4:1] period-wide pulse. When alternate frame-based signal received, Receive Overhead Mask (ROHM[4:1]) indicates position each overhead transmission frame. RNEG/RLCV/ROHM[4:1] function selection controlled RFRM[1:0] bits S/UNI-4xD3F Receive Configuration registers, bits FRMR, FRMR, FRMR Configuration registers, PLCPEN bits SPLR Configuration register. RNEG[4:1], RLCV[4:1], ROHM[4:1] sampled rising edge RCLK[4:1] default, enabled sampling falling edge RCLK[4:1]. This sampling controlled RCLKINV S/UNI-4xD3F Receive Configuration registers. Note: Signal polarity control provided RNEGINV S/UNI-4xD3F Receive Configuration registers.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
RCLK[4] RCLK[3] RCLK[2] RCLK[1] TOHINS[4] TOHINS[3] TOHINS[2] TOHINS[1]
Type
Input
Function
Receive Clock (RCLK[4:1]) provides receive direction timing. RCLK[4:1] externally recovered transmission system baud rate clock that samples RPOS/RDATI[4:1] RNEG/RLCV/ROHM[4:1] inputs rising falling edge. Transmit DS3/E3/J2 Overhead Insertion (TOHINS[4:1]) controls insertion DS3, overhead bits from TOH[4:1] input. When TOHINS[4:1] high, associated overhead TOH[4:1] stream inserted transmitted DS3, frame. When TOHINS[4:1] low, DS3, overhead generated inserted internally. TOHINS[4:1] sampled rising edge TOHCLK[4:1]. Note: TOHINS[4:1] logic one, TOH[4:1] input precedence over internal datalink transmitter, internal register setting.
Input
TOH[4] TOH[3] TOH[2] TOH[1]
Input
When configured operation, Transmit DS3/E3/J2 Overhead Data (TOH[4:1]) contains overhead bits that inserted transmit stream. When configured G.832 operation, TOH[4:1] contains overhead bytes (FA1, FA2, mask, that inserted transmit G.832 stream. When configured G.751 operation, TOH[4:1] contains overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) that inserted transmit G.751 stream. When configured operation, TOH[4:1] contains overhead bits (TS97, TS98, Framing, X1-3, E1-5) that inserted transmit stream. TOHINS[4:1] logic one, TOH[4:1] input precedence over internal datalink transmitter, other internal register setting. TOH[4:1] sampled rising edge TOHCLK[4:1].
TOHFP[4] TOHFP[3] TOHFP[2] TOHFP[1]
Output
Transmit DS3/E3/J2 Overhead Frame Position (TOHFP[4:1]) used align individual overhead bits transmit overhead data stream, TOH[4:1], M-frame frame. TOHFP[4:1] high DS3, during overhead position TOH[4:1] stream, G832 during first byte, G.751 during overhead position TOH[4:1] stream, during first timeslot first frame 4frame multiframe. TOHFP[4:1] updated falling edge TOHCLK[4:1].
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
TOHCLK[4] TOHCLK[3] TOHCLK[2] TOHCLK[1]
Type
Output
Function
Transmit DS3/E3/J2 Overhead Clock (TOHCLK[4:1]) active when DS3, stream being processed. TOHCLK[4:1] nominally clock DS3, 1.072 clock G.832 1.074 clock G.751 gapped 6.312 clock with average frequency TOHFP[4:1] updated falling edge TOHCLK[4:1]. TOH[4:1], TOHINS[4:1] sampled rising edge TOHCLK[4:1].
REF8KI TDATI[4] TDATI[3] TDATI[2] TDATI[1]
Input
REF8KI required power sequence described Section 13.1. Framer Transmit Data (TDATI[4:1]) contains serial data transmitted. TDATI[4:1] sampled rising edge TICLK[4:1] TXGAPEN register S/UNI-4xD3F Configuration register logic zero. TXGAPEN logic one, then TDATI[4:1] sampled falling edge TGAPCLK[4:1]. Transmit Path Overhead Frame Position (TFPO[4:1]) logic one, while (the most significant bit) path user channel octet (F1) present TDAT[4:1] stream. TFPO[4:1] updated falling edge TPOHCLK[4:1]. Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO[4:1]) valid setting TXGAPEN-bit S/UNI-4xD3F Configuration registers logic zero. When configured DS3, TFPO[4:1] pulses high every clock cycles, giving free-running mark overhead bits frame. When configured G.751 pulses high every 1536 clock cycles, giving free-running reference G.751 indication, G.832 pulses high every 4296 clock cycles, giving free-running reference G.832 frame indication. pulses high every clock cycles, giving free-running reference frame indication.
TFPO[4] TFPO[3] TFPO[2] TFPO[1]
Output
TMFPO[4] TMFPO[3] TMFPO[2] TMFPO[1]
TMFPO[4:1] pulses high every 4760 clock cycles when configured DS3, giving freerunning reference M-frame indication. TMFPO[4:1] pulses high every 3156 clock cycles when configured giving free-running reference multiframe indication. TMFPO[4:1] behaves same TFPO[4:1] applications. TFPO/TMFPO[4:1] updated rising edge TICLK[4:1] RCLK[4:1] loop-timed.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
TGAPCLK[4] TGAPCLK[3] TGAPCLK[2] TGAPCLK[1]
Type
Output
Function
Framer Gapped Transmit Clock (TGAPCLK[4:1]) valid setting TXGAPEN-bit S/UNI-4xD3F Configuration registers logic one. TGAPCLK[4:1] derived from transmit reference clock TICLK[4:1] from receive clock loop-timed. overhead (gapped) positions generated internal device. TGAPCLK[4:1] held high during overhead positions. This clock useful interfacing devices which source payload data only. TGAPCLK[4:1] used sample TDATI[4:1].
TFPI[4] TFPI[3] TFPI[2] TFPI[1]
Input
Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI[4:1]) indicates position overhead bits each M-subframe, first each G.751 G.832 frame, first framing each frame. TFPI[4:1] required pulse every frame boundary modes. TMFPI[4:1] indicates position first each M-frame, first each frame, first framing each multiframe. TMFPI[4:1] required pulse every multiframe boundary. TFPI/TMFPI[4:1] sampled rising edge TICLK[4:1].
TMFPI[4] TMFPI[3] TMFPI[2] TMFPI[1]
TICLK[4] TICLK[3] TICLK[2] TICLK[1]
Input
Transmit Input Clock (TICLK[4:1]) provides transmit direction timing. TICLK[4:1] externally generated transmission system baud rate clock. internally buffered produce transmit clock output, TCLK[4:1]. enabled update TPOS/TDATO[4:1] TNEG/TOHM[4:1] outputs TICLK[4:1] rising edge. TICLK[4:1] maximum frequency MHz.
ROHFP[4] ROHFP[3] ROHFP[2] ROHFP[1]
Output
Receive DS3/E3/J2 Overhead Frame Position (ROHFP[4:1]) locates individual overhead bits received overhead data stream, ROH[4:1]. ROHFP[4:1] high during overhead position ROH[4:1] stream when processing stream. ROHFP[4:1] high during first byte when processing G.832 stream. ROHFP[4:1] high during overhead position when processing G.751 stream. ROHFP[4:1] high during first "Timeslot first frame 4-frame multiframe when processing stream. ROHFP[4:1] updated falling edge ROHCLK[4:1].
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
ROH[4] ROH[3] ROH[2] ROH[1]
Type
Output
Function
Receive DS3/E3/J2 Overhead Data (ROH[4:1]) contains overhead bits extracted from received stream. ROH[4:1] contains overhead bytes (FA1, FA2, extracted from received G.832 stream; ROH[4:1] contains overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) extracted from received G.751 stream; ROH[4:1] contains overhead bits (Framing, X1-3, E1-5) extracted from received stream. ROH[4:1] updated falling edge ROHCLK[4:1]. Receive DS3/E3/J2 Overhead Clock (ROHCLK[4:1]) active when DS3, stream being processed. ROHCLK[4:1] nominally clock when processing DS3, 1.072 clock when processing G.832 1.074 clock when processing G.751 gapped 6.312 clock with average frequency ROH[4:1], ROHFP[4:1] updated falling edge ROHCLK[4:1].
ROHCLK[4] ROHCLK[3] ROHCLK[2] ROHCLK[1]
Output
REF8KO[4] REF8KO[3] REF8KO[2] REF8KO[1]
Output
Reference 8kHz Output (REF8KO[4:1]) 8kHz reference derived from receive clocks RCLK[4:1]. free-running divide-down counter used generate REF8KO[4:1] will glitch reframe actions. REF8KO[4:1] will pulse high approximately RCLK[4:1] cycle every REF8KO[4:1] should treated glitch-free asynchronous signal.
RFPO[4] RFPO[3] RFPO[2] RFPO[1]
Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO[4:1]) valid when 8KREFO logic zero S/UNI-4xD3F Configuration register. RFPO[4:1] aligned RDATO[4:1] indicates position first each M-subframe, first each G.751 G.832 frame, first framing each frame. RMFPO[4:1] aligned RDATO[4:1] indicates position first each M-frame, first each G.751 G.832 multiframe, first framing each multiframe. RFPO/RMFPO[4:1] updated either falling rising edge RSCLK[4:1] depending setting RSCLKR S/UNI-4xD3F Receive Configuration register. Output Framer Receive Overhead Indication (ROVRHD[4:1]) will high whenever data RDATO[4:1] corresponds overhead position. ROVRHD[4:1] updated either falling rising edge RSCLK[4:1] depending setting RSCLKR S/UNI-4xD3F Receive Configuration register.
RMFPO[4] RMFPO[3] RMFPO[2] RMFPO[1]
ROVRHD[4] ROVRHD[3] ROVRHD[2] ROVRHD[1]
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
RSCLK[4] RSCLK[3] RSCLK[2] RSCLK[1] RGAPCLK[4] RGAPCLK[3] RGAPCLK[2] RGAPCLK[1] RDATO[4] RDATO[3] RDATO[2] RDATO[1] FRMSTAT[4] FRMSTAT[3] FRMSTAT[2] FRMSTAT[1]
Type
Output
Function
Framer Recovered Clock (RSCLK[4:1]) recovered clock timing reference RDATO[4:1], RFPO/RMFPO[4:1], ROVRHD[4:1]. Framer Recovered Gapped Clock (RGAPCLK[4:1]) valid setting RXGAPEN-bit S/UNI-4xD3F Configuration register. RGAPCLK[4:1] recovered clock timing reference RDATO[4:1]. RGAPCLK[4:1] held high positions which correspond overhead.
Output
Framer Receive Data (RDATO[4:1]) received data aligned RFPO/RMFPO[4:1] ROVRHD[4:1]. RDATO[4:1] updated active edge RSCLKR register bit) RSCLK[4:1] RGAPCLK[4:1]. Framer Status (FRMSTAT[4:1]) active high signal which configured show when framers have detected certain conditions. FRMSTAT[4:1] outputs programmed STATSEL[2:0] bits S/UNI-4xD3F Configuration register indicate: E3/DS3 extended LOF, E3/DS3 LOF, AIS, LOS, Idle. FRMSTAT[4:1] should treated glitch-free asynchronous signal. active Chip Select (CSB) signal must enable S/UNI-4xD3F register accesses. used, (RDB determine register reads writes) then should tied inverted version RSTB. active Write Strobe (WRB) signal pulsed enable S/UNI-4xD3F register write access. D[7:0] clocked into addressed register rising edge while low. active Read Enable (RDB). This signal pulsed enable S/UNI-4xD3F register read access. S/UNI-4xD3F drives D[7:0] with contents addressed register while both low. Bi-directional Data (D[7:0]) used during S/UNI-4xD3F register read write accesses.
Input
Input
Input
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB
Type
Input
Function
Address (A[10:0]) selects specific registers during S/UNI-4xD3F register accesses.
Input
Active Reset (RSTB) signal asynchronously reset S/UNI-4xD3F. RSTB Schmitt-trigger input with integral pull-up resistor. Address Latch Enable (ALE) active-high latches address A[10:0] when low. When high, internal address latches transparent. allows S/UNI-4xD3F interface multiplexed address/data bus. integral pull-up resistor. Active Open-Drain Interrupt (INTB) signal goes when unmasked interrupt event detected internal interrupt sources. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source. Test Clock (TCK) signal provides timing test operations that carried using IEEE P1149.1 test access port. Test Mode Select (TMS) signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Input (TDI) signal carries test data into S/UNI-4xD3F IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Output (TDO) signal carries test data S/UNI-4xD3F IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress. active Test Reset (TRSTB) signal provides asynchronous S/UNI-4xD3F test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull resistor. TRSTB must asserted during power sequence. Note: used, TRSTB must connected RSTB input.
Input
INTB
Output
Input
Input
Input
Output
TRSTB
Input
BIAS
Input
When tied +5V, Bias (BIAS) input used bias wells input pads that pads tolerate their inputs without forward biasing internal protection devices. When tied VDD, inputs bi-directional inputs will only tolerate input levels VDD.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15] VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28]
Type
Power
Function
Power pins should connected welldecoupled +3.3V supply.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55]
Type
Ground
Function
Ground pins should connected GND.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
Name
VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71]
Type
Ground
Function
Ground pins should connected GND.
connect
connect.
Notes S/UNI-4xD3F inputs bi-directionals present minimum capacitive loading operate logic levels.
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S/UNI-4xD3F outputs bi-directionals have least drive capability. data outputs, D[7:0], have drive capability. outputs TCLK[4:1], TPOS [4:1], TNEG [4:1], TFPO/TMFPO/TGAPCLK[4:1], RDATO[4:1], ROVRHD[4:1], RSCLK/RGAPCLK[4:1], REF8KO/ RFPO/RMFPO[4:1] have drive capability. other outputs have drive capability. Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors. RSTB, TRSTB, TMS, TDI, TCK, REF8KI, TICLK[4:1], RCLK[4:1] Schmitt trigger input pads. [72:1] ground pins internally connected together. Failure connect these pins externally cause malfunction damage S/UNI-4xD3F. VDD[28:1] power pins internally connected together. Failure connect these pins externally cause malfunction damage device. These power supply connections must utilized must connect common +3.3 ground rail, appropriate. During power-up power-down, voltage BIAS must kept equal greater than voltage [28:1] pins, avoid damage device.
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Functional Description
S/UNI 4xD3F devices contains following blocks: Framers DS3, RBOC Bit-oriented code detector RDLC PMDL receiver PMON Performance monitor accumulator PRGD Pseudo-random sequence generator/detector Transmitters DS3, XBOC Bit-oriented code generator TDPR PMDL transmitter JTAG Test access port
10.1
Framer
Framer (T3-FRMR) Block integrates circuitry required decoding B3ZS-encoded signal framing resulting stream. T3-FRMR directly compatible with C-bit parity applications. T3-FRMR decodes B3ZS-encoded signal provides indications LCVs. B3ZS decoding algorithm definition independently chosen through software. defect also detected B3ZS encoded streams. declared when inputs RPOS RNEG contain zeros consecutive RCLK cycles. removed when ones' density RPOS and/or RNEG greater than RCLK cycles. framing algorithm examines five F-bit candidates simultaneously. When least discrepancy occurred each candidate, algorithm examines next five candidates. When single F-bit candidate remains set, first supposed Msubframe examined M-frame alignment signal (that M-bits, following pattern). Framing declared, removed, M-bits correct three consecutive M-frames while discrepancies have occurred F-bits. During examination M-bits, X-bits P-bits ignored. algorithm gives maximum average reframe time While T3-FRMR synchronized M-frame, F-bit M-bit positions stream examined. out-of-frame (OOF) defect detected when F-bit errors consecutive F-bits observed selected M3O8 FRMR Configuration register), when more M-bit errors detected three four consecutive M-frames. M-bit error criteria disabled MBDIS Framer Configuration register. "three eight consecutive F-bits ratio" provides more robust operation, presence high error rate, than consecutive F-bits ratio. Either criteria allows defect detected quickly when M-subframe alignment patterns optionally, when M-frame alignment pattern lost.
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Also while in-frame, LCVs, M-bit F-bit framing errors, P-bit parity errors indicated. When C-bit parity mode enabled, both C-bit parity errors FEBEs indicated. These error indications, well excessive zeros indication, accumulated over 1-second intervals with PMON. Note that framer off-line framer, indicating both COFA events. Even indicated, framer will continue indicating performance monitoring information based previous frame alignment. Three maintenance signals alarm condition, AIS, idle signal) detected T3-FRMR. maintenance detection algorithm uses simple integrator with slope based occurrence "valid" M-frame intervals. alarm, M-frame said "valid" interval contains defect, which defined occurrence event during that M-frame. IDLE, M-frame interval "valid" contains IDLE, defined occurrence less than discrepancies expected signal pattern (1010. AIS, 1100. IDLE) while valid frame alignment maintained. This discrepancy threshold ensures detection algorithms operate presence 10-3 error rate. AIS, expected pattern selected framed "1010" signal. framed arbitrary signal C-bits zero. framed "1010" signal C-bits zero. framed all-ones signal (with overhead bits ignored). unframed all-ones signal (with overhead bits equal ones).
Each "valid" M-frame causes associated integration counter increment; "invalid" M-frames cause decrement. With "slow" detection option, RED, AIS, IDLE declared when respective counter saturates 127, which results detection time 13.5 With "fast" detection option, RED, AIS, IDLE declared when respective counter saturates which results detection time 2.23 (i.e., times maximum average reframe time). RED, AIS, IDLE removed when respective counter decrements detection provided recommended ITU-T G.783 with programmable integration periods 1ms, 2ms, 3ms. While integrating assert LOF, counter will integrate when framer asserts condition integrates down when framer de-asserts condition. Once asserted, framer must assert entire integration period before de-asserted. Valid X-bits extracted T3-FRMR provide indication FERF (FERF). FERF defect detected extracted X-bits equal logic zero (X1=X2=0); defect removed extracted X-bits equal logic (X1=X2=1). X-bits equal, FERF status remains previous state. extracted FERF status buffered M-frames before being reported within FRMR Status register. This buffer ensures better than 99.99% chance freezing FERF status correct value during occurrence OOF. When C-bit parity application enabled, both FEAC channel PMDL extracted. Codes FEAC channel detected Oriented Code Detector (RBOC). HDLC messages PMDL received Data Link Receiver (RDLC).
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T3-FRMR enabled automatically assert RAI, outgoing transmit stream upon detection combination LOS, RED, AIS. T3-FRMR also enabled automatically insert C-bit Parity FEBE upon detection receive C-bit parity error. T3-FRMR extracts entire overhead bits M-frame) using output, along with ROHCLK, ROHFP outputs. T3-FRMR configured generate interrupts error events status changes. sources interrupts masked acknowledged internal registers. Internal registers also used configure T3-FRMR. Access these registers generic microprocessor bus.
10.2
Framer
Framer (E3-FRMR) Block integrates circuitry required decoding HDB3-encoded signal framing resulting stream. E3-FRMR directly compatible with G.751 G.832 applications. E3-FRMR searches frame alignment incoming serial stream based either G.751 G.832 formats. G.751 format, E3-FRMR expects selected framing pattern error-free three consecutive frames before declaring INFRAME. G.832 format, E3-FRMR expects selected framing pattern error-free consecutive frames before declaring INFRAME. Once frame alignment established, incoming data continuously monitored framing errors byte interleaved parity (BIP) errors G.832 format). While in-frame, E3-FRMR also extracts various overhead bytes processes them according framing format selected: G.832 format, E3-FRMR extracts: Trail Trace bytes outputs them serial stream further processing Trail Trace Buffer (TTB) block. FERF-bit indicates alarm when FERF-bit logic three five consecutive frames. FERF indication removed when FERF-bit logic zero three five consecutive frames. FEBE outputs accumulation PMON. Payload Type bits buffers them that they read microprocessor. Timing Marker asserts Timing Marker indication when value extracted been same state three five consecutive frames. Network Operator byte presents serial stream further processing RDLC block when RNETOP S/UNI-4xD3F Data Link FERF Control register logic one. byte also brought ROH[x] output with associated clock ROHCLK[x]. eight bits Network Operator byte extracted presented overhead output and, optionally, presented RDLC.
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General Purpose Communication Channel byte presents RDLC when RNETOP S/UNI-4xD3F Data Link FERF Control register logic zero. byte also brought ROH[x] output with associated clock ROHCLK[x].
G.751 mode, E3-FRMR extracts: (bit frame) indicates Remote Alarm when logic three five consecutive frames. Similarly, Remote Alarm removed when logic zero three five consecutive frames. National reserved (bit frame) presents serial stream further processing RDLC when RNETOP S/UNI-4xD3F Data Link FERF Control register logic zero. also brought ROH[x] output with associated clock ROHCLK[x]. Optionally, interrupt generated when National changes state.
Further, while in-frame, E3-FRMR indicates position overhead bits incoming digital stream. G.751 mode, tributary justification bits optionally identified either overhead payload payload mappings that take advantage full bandwidth. E3-FRMR declares alignment framing pattern error four consecutive frames. E3-FRMR "off-line" framer, where frame alignment indications, overhead indications, overhead processing continue based previous alignment. Once framer determined frame alignment, indication removed COFA indication declared alignment differs from previous alignment. E3-FRMR detects presence incoming data stream when less than zeros frame detected while framer G.832 mode, when less than five zeros frame detected while G.751 mode. This algorithm provides probability detecting presence 10-3 92.9% G.832 98.0% G.751. declared when marks have been received consecutive bit-periods. deasserted after bit-periods during which there sequence four consecutive zeros. detection provided recommended ITU-T G.783 with programmable integration periods While integrating assert LOF, counter will integrate when framer asserts condition integrates down when framer de-asserts condition. Once asserted, framer must assert entire integration period before de-asserted. E3-FRMR also enabled automatically assert RAI/FERF indication outgoing transmit stream upon detection combination LOS, OOF, AIS. E3-FRMR also enabled automatically insert G.832 FEBE upon detection receive BIP-8 errors.
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10.3
Framer
J2-FRMR integrates circuitry decode unipolar B8ZS encoded signal frame resulting 6312 kbps stream. Having found frame, J2-FRMR extracts variety overhead datalink information from stream. format consists 789-bit frames, each long, consisting bytes payload, reserved bytes, F-bits. frames grouped into 4-frame multiframes. multiframe format follows:
Table Framer Multiframe Format
TS1[1:8] TS1[1:8] TS1[1:8] TS1[1:8] Notes
761-768
TS96[1:8] TS96[1:8] TS96[1:8] TS96[1:8]
769-776
TS97[1:8] TS97[1:8] TS97[1:8] TS97[1:8]
777-784
TS98[1:8] TS98[1:8] TS98[1:8] TS98[1:8]
TS96 byte interleaved payload. TS97 TS98 reserved channels signaling. Frame Alignment Signal represented binary ones zeroes. datalink. spare bits, usually logic one. Remote alarm bit, active high. CRC-5 check sequence. entire 3156-bit multiframe, including CRC-5 check sequence, should have remainder when divided
J2-FRMR frames signal with average reframe time 5.07 alternate framing algorithm that uses CRC-5 check detect static mimic patterns available. Once frame, J2-FRMR provides indications frame multiframe boundaries, marks overhead bits, x-bits, m-bits, reserved channels (TS97 TS98). LOS, bipolar violations, excessive zeroes, change frame alignment, framing errors, errors indicated accumulated PMON (with exception change frame alignment). Maskable interrupts available alert microprocessor occurrence these events. addition marking x-bit values, J2-FRMR provides microprocessor access x-bits, will optionally generate interrupt when x-bits changes state. m-bits associated clock either extracted through RDLC through ROH[x] ROHCLK[x] output pins S/UNI-4xD3F. m-bits also presented RBOC detection generic bit-oriented codes. Status signals such Physical AIS, Payload AIS, m-bits, Remote (a-bit) detected J2-FRMR. addition providing indication signals these states, J2FRMR will optionally generate interrupt when these status signals changes.
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declared when marks have been received consecutive periods. cleared when either consecutive periods have passed without excessive zeros more consecutive zeros) detection required ITU-T G.775. declared when seven more consecutive multiframes with errored framing patterns received. cleared when three more consecutive multiframes with correct framing patterns received. framing algorithm which takes into account calculation also available. framing algorithms described Section 10.3.1. Physical Layer declared when less zeros detected sequence 3156 bits. cleared when three more zeros detected sequence 3156 bits required ITUT G.775. Payload detected when incoming payload less zeros sequence 3072 bits. cleared when three more zeros detected sequence 3072 bits. J2-FRMR forced re-frame microprocessor control. Similarly, microprocessor disable J2-FRMR from reframing framing errors. J2-FRMR configured, sources interrupts masked acknowledged, internal registers. These internal registers accessed through generic microprocessor bus.
10.3.1
Frame Find Algorithms
J2-FRMR searches frame alignment using algorithms, selected CRC_REFR J2-FRMR Configuration register. When CRC_REFR logic zero, J2-FRMR uses only frame alignment sequence find frame, searching three consecutive correct frame alignment sequences. frame find block searches entire 9-bit sequence (spread over multiframes) same time, greatly reducing time required find frame alignment. framing process with CRCREFR cleared illustrated Figure
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Figure Framing Algorithm (CRC_REFR
Reset Fram
Slip
Fram Pattern Matched Mark multiframe alignment
Else
Fail
Confirm Fram Pattern next ultifram
Pass Fail
Confirm Fram Pattern next ultifram
Pass
Declare in-frame
Using this algorithm, J2-FRMR will average find frame 5.07 when starting search worst possible position, given 10-4 error rate static mimic patterns. When CRC_REFR logic one, addition requiring three consecutive correct framing patterns, J2-FRMR requires that first CRC-5 checks correct, reframe initiated. speed process, CRC-5 frame alignment checks concurrently, illustrated Figure
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Figure Framing Algorithm (CRC_REFR
Reset Fram
Slip
Fram Pattern Matched Mark multiframe alignment
Else
Fail
Confirm Fram Pattern next ultifram
Pass Fail
Check CRC-5 Sequence
Pass Fail
Confirm Fram Pattern next ultifram
Pass Fail
Check CRC-5 Sequence
Pass
Declare in-frame
Using this algorithm, J2-FRMR will find frame 10.22 average when starting search worst possible position, given 10-4 error rate static mimic patterns. algorithm will reject 99.90% mimic patterns. Further protection against mimic patterns available monitoring rate CRC-5 errors. Once frame alignment found, block sets indication low, indicates change frame alignment occurred). block declares alignment seven consecutive framing algorithm signals (FAS) have been received error. presence random 10-3 error rate frame loss criteria provides mean time falsely lose frame alignment 1.65 years. Frame Find Block forced initiate frame search time when REFRAME J2-FRMR Configuration. Conversely, when FLOCK logic one, J2FRMR will never declare search frame alignment excess framing errors.
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extended detection provided recommended ITU-T G.783 with programmable integration periods While integrating assert LOF, counter will integrate when framer asserts condition integrates down when framer deasserts condition. Once asserted, framer must assert entire integration period before de-asserted.
10.4
RBOC Bit-Oriented Code Detector
Bit-Oriented Code Detector (RBOC) only used C-bit Parity mode. RBOC Block detects presence possible bit-oriented codes (BOCs) contained C-bit parity FEAC channel datalink signal stream. 64th code ("111111") similar HDLC flag sequence ignored. Bit-oriented codes (BOCs) received FEAC channel 16-bit sequences each consisting ones, zero, code bits, trailing zero ("111111110xxxxxx0"). BOCs validated when repeated least times. RBOC enabled declare code valid been observed times times, specified RBOC Configuration/Interrupt Enable register. RBOC declares that code removed code sequences containing code values different from detected code received moving window code periods. Valid BOCs indicated through RBOC Interrupt Status register. bits allones ("111111") when valid code detected. RBOC programmed generate interrupt when detected code been validated when code removed.
10.5
RDLC PMDL Receiver
RDLC microprocessor peripheral used receive LAPD/HDLC frames serial HDLC stream that provides data clock information such C-bit parity path maintenance data link (PMDL), G.832 Network Requirement byte General Purpose data link (selectable using RNETOP S/UNI-4xD3F Data Link FERF/RAI Control register), G.751 Network bit, m-bit Data Link. RDLC detects change from flag characters first byte data, removes stuffed zeros incoming data stream, receives packet data, calculates CRC-CCITT frame check sequence (FCS). address matching mode, only those packets whose first data byte matches programmable bytes universal address (all-ones) stored FIFO. least significant bits address comparison masked LAPD SAPI matching. Received data placed into 128-level FIFO buffer. interrupt generated when programmable number bytes stored FIFO buffer. Other sources interrupt detection terminating flag sequence, abort sequence, FIFO buffer overrun.
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Status register contains bits which indicate overrun empty FIFO status, interrupt status, occurrence first flag message bytes written into FIFO. Status register also indicates abort, flag, message status data just read from FIFO. message, Status register indicates status packet contained non-integer number bytes.
10.6
PMON Performance Monitor Accumulator
PMON Block interfaces directly with either Framer (T3-FRMR) accumulate events, parity error (PERR) events, path parity error (CPERR) events, FEBE events, excess zeros (EXZS), Framing errors (FERR) events using saturating counters; Framer (E3-FRMR) accumulate LCV, PERR G.832 mode), FEBE FERR events; Framer (J2-FRMR) accumulate LCVs, errors PERR counter), FERR, EXZS. PMON stops accumulating error signal from DS3, Framers once frame synchronization lost. When accumulation interval signaled write PMON register address space write S/UNI-4xD3F Identification, Master Reset, Global Monitor Update register, PMON transfers current counter values into microprocessor accessible holding registers resets counters begin accumulating error events next interval. counters reset such manner that error events occurring during reset period missed. When counter data transferred into holding registers, interrupt generated, providing interrupt enabled. holding registers have been read since last interrupt, overrun status set. addition, register provided indicate changes PMON counters since last accumulation interval.
10.7
PRGD Pseudo-Random Sequence Generator/Detector
Pseudo-Random Sequence Generator/Detector (PRGD) block software programmable test pattern generator, receiver, analyzer. types test patterns (pseudo-random repetitive) conform ITU-T O.151. PRGD programmed generate pseudo-random pattern with length 232-1 bits user programmable pattern from bits length. addition, PRGD insert single errors error rate between 10-1 10-7. PRGD programmed check presence generated pseudo-random pattern. PRGD perform auto-synchronization expected pattern, generate interrupts detection loss specified pattern. PRGD accumulate total number bits received total number errors saturating 32-bit counters. counters accumulate over interval defined writes S/UNI-4xD3F Identification/Master Reset, Global Monitor Update register (006H) writes PRGD accumulation register. When accumulation forced either method, then holding registers updated, counters reset begin accumulating next interval. counters reset such that events missed. data then available holding registers until next accumulation. addition counters, record bits received immediately prior accumulation available.
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PRGD also programmed check repetitive sequences. When configured detect pattern length N-bits, PRGD will load N-bits from detected stream, determine whether received pattern repeats itself every subsequent bits. Should fail find such pattern, will continue loading checking until finds repetitive pattern. features (error counting, auto-synchronization, etc.) available pseudo-random sequences also available repetitive sequences. Whenever PRGD accumulation forced, PRGD stores snapshot bits received immediately prior accumulation. This snapshot examined order determine exact nature repetitive pattern received PRGD. pseudo-random repetitive pattern inserted/extracted DS3,
10.8
Transmitter
Transmitter (T3-TRAN) Block integrates circuitry required insert overhead bits into stream produce B3ZS-encoded signal. T3-TRAN directly compatible with C-bit parity formats. Status signals such FERF, AIS, idle signal inserted when their transmission enabled internal register bits. FERF also automatically inserted detection combination LOS, RED, T3-FRMR. valid pair P-bits automatically calculated inserted T3-TRAN. When C-bit parity mode selected, path parity bits, FEBE indications automatically inserted. When enabled C-bit parity operation, FEAC channel sourced XBOC bit-oriented code transmitter. PMDL messages sourced TDPR data link transmitter. These overhead signals also overwritten using TOH[x] TOHINS[x] inputs. When enabled operation, C-bits forced logic with exception Cbit Parity (first C-bit first M-subframe), which forced toggle every M-frame. T3-TRAN supports diagnostic modes which inserts parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, LCVs, all-zeros. User control each overhead bits frame provided. Overhead bits inserted bit-by-bit basis from user supplied data stream. overhead clock kHz) overhead alignment output provided allow control user provided stream.
10.9
Transmitter
Transmitter (E3-TRAN) Block integrates circuitry required insert overhead bits into stream produce HDB3-encoded signal. E3-TRAN directly compatible with G.751 G.832 framing formats.
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E3-TRAN generates frame alignment signal inserts into incoming serial stream based either G.751 G.832 formats. overhead status bits each frame format individually controlled register bits transmit overhead stream. While certain framing format modes, E3-TRAN generates various overhead bytes according following: G.832 format, E3-TRAN: Inserts BIP-8 byte calculated over preceding frame. Inserts Trail Trace bytes through block. Inserts FERF-bit register optionally, when E3-FRMR declares OOF, when defect declared. Inserts FEBE bit, which logic when more BIP-8 errors detected receive framer. there BIP-8 errors indicated E3-FRMR, E3-TRAN sets FEBE logic zero. Inserts Payload Type bits based register value microprocessor. Inserts Tributary Unit multiframe indicator bits either overhead stream register values microprocessor. Inserts Timing Marker register bit. Inserts Network Operator (NR) byte from TDPR block when TNETOP S/UNI-4xD3F Data Link FERF Control register logic one; otherwise, byte all-ones. byte overwritten using TOH[x] TOHINS[x] input pins. eight bits Network Operator byte available datalink. Inserts General Purpose Communication Channel (GC) byte from TDPR block when TNETOP S/UNI-4xD3F Data Link FERF Control register logic zero; otherwise, byte all-ones. byte overwritten using TOH[x] TOHINS[x] input pins.
G.751 mode, E3-TRAN Inserts (bit frame) either register optionally, when E3-FRMR declares OOF; Inserts National reserved (bit frame) either fixed value through register from TDPR block configured TNETOP S/UNI-4xD3F Data Link FERF Control register NATUSE TRAN Configuration register. Optionally identifies tributary justification bits stuff opportunity bits either overhead payload SPLT payload mappings that take advantage full bandwidth.
Further, E3-TRAN provide insertion errors framing pattern parity bits, insertion single LCVs diagnostic purposes. Most overhead bits overwritten using TOH[x] TOHINS[x] input pins.
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10.10 Transmitter
Transmitter (J2-TRAN) Block integrates circuitry required insert overhead bits into stream produce B8ZS-encoded signal. J2-TRAN directly compatible with framing format specified G.704 Technical Reference High-Speed Digital Leased Circuit Services. J2-TRAN generates frame alignment signal inserts into incoming serial stream. overhead status bits each frame format individually controlled either register bits transmit overhead stream. J2-TRAN: Inserts CRC-5 bits calculated over preceding multiframe. Inserts x-bits through microprocessor programmable register bits. Inserts a-bit through microprocessor programmable register bit. Inserts m-bit data link through TDPR block. Inserts payload physical layer through microprocessor programmable register bits. Inserts over m-bits, overwriting HDLC frames, using XBOC block through automatic activation upon detection certain remote alarm conditions.
J2-TRAN allows overwriting overhead bits using TOH[x], TOHINS[x], TOHFP[x], TOHCLK[x] overhead signals. Further, J2-TRAN provide insertion single errors framing pattern CRC-5 bits, insertion single LCVs diagnostic purposes.
10.11 XBOC Oriented Code Generator
Oriented Code Generator (XBOC) Block transmits possible BOCs Cbit parity FEAC channel. 16-bit sequence consisting eight ones, zero, code bits, trailing zero (111111110xxxxxx0) that repeated long code 111111. code transmitted programmed writing XBOC Code register. 64th code (111111) similar HDLC idle sequence used disable transmission oriented codes. When transmission disabled, FEAC channel all-ones.
10.12 TDPR PMDL Transmitter
Path Maintenance Data Link Transmitter (TDPR) provides serial data link C-bit parity PMDL DS3, serial Network Operator byte General Purpose datalink G.832 National datalink G.751 m-bit datalink TDPR used under microprocessor control transmit HDLC data frames. performs data serialization, generation, zero-bit stuffing, well flag, abort sequence insertion. Upon completion message, CRC-CCITT appended, followed flags. TDPR transmit data FIFO underflows, abort sequence automatically transmitted.
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When enabled, TDPR continuously transmits flags (01111110) until data ready transmitted. Data bytes transmitted written into TDPR Transmit Data register. TDPR automatically begins transmission data once least complete packet written into FIFO. complete packets data will transmitted error condition occurs. After last data byte packet, insertion been enabled) flag, just flag insertion been enabled) transmitted. TDPR then returns transmission flag characters until next packet available transmission. TDPR will also force transmission FIFO data once FIFO depth surpassed programmable upper limit threshold. Transmission commences regardless whether packet been completely written into FIFO. user must careful avoid overfilling FIFO. Underruns only occur packet length greater than programmed upper limit threshold because, such case, transmission will begin before complete packet stored FIFO. interrupt generated once FIFO depth fallen below user configured lower threshold indicator user write more data. Interrupts also generated FIFO underflows while transmitting packet, when FIFO full, FIFO overrun. there more than five consecutive ones transmit data data, zero stuffed into serial data output. This prevents unintentional transmission flag abort sequences. Abort sequences (01111111 sequence where transmitted first) continuously transmitted time setting control bit. During packet transmission, underrun situation occur data written TDPR Transmit Data register before previous byte been depleted. this case, abort sequence transmitted, controlling processor notified register bit. abort sequence will also transmitted user overflows FIFO with packet length greater than bytes. Overflows where other complete packets still stored FIFO will generate abort. Only packet which caused overflow corrupted interrupt generated user register bit. other packets remain unaffected. When TDPR disabled, logic (Idle) inserted PMDL.
10.13 JTAG Test Access Port
JTAG Test Access Port block provides JTAG support boundary scan. standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE STCTEST instructions supported. S/UNI4xD3F identification code 073460CD hexadecimal.
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10.14 Microprocessor Interface
microprocessor interface block provides normal test mode registers, logic required connect microprocessor interface. Normal mode registers required normal operation. Test mode registers used enhance testability S/UNI-4xD3F. register accessed described Table
Table Register Memory Address
000H 001H 002H 003H 004H 005H 006H 106H 007H 010H 011H 012H013H 014H 015H 016H 017H 018H 019H 01AH 01BH 01CH 01DH 01EH 01FH 030H 031H 032H 033H 034H 107H 110H 111H 112H113H 114H 115H 116H 117H 118H 119H 11AH 11BH 11CH 11DH 11EH 11FH 130H 131H 132H 133H 134H 206H 207H 210H 211H 212H213H 214H 215H 216H 217H 218H 219H 21AH 21BH 21CH 21DH 21EH 21FH 230H 231H 232H 233H 234H 306H 307H 310H 311H 312H313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 330H 331H 332H 333H 334H 100H 101H 102H 103H 104H 105H 200H 201H 202H 203H 204H 205H 300H 301H 302H 303H 304H 305H
Register
S/UNI-4xD3F Configuration S/UNI-4xD3F Configuration S/UNI-4xD3F Transmit Configuration S/UNI-4xD3F Receive Configuration S/UNI-4xD3F Data Link FERF/RAI Control S/UNI-4xD3F Interrupt Status S/UNI-4xD3F Identification, Master Reset, Global Monitor Update S/UNI-4xD3F Reserved S/UNI-4xD3F Clock Activity Monitor Interrupt Identification PMON Change PMON Performance Meters PMON Interrupt Enable/Status PMON Reserved PMON Event Count PMON Event Count PMON Framing Error Event Count PMON Framing Error Event Count PMON Excessive Zeros Count PMON Excessive Zeros Count PMON Parity Error Event Count PMON Parity Error Event Count PMON Path Parity Error Event Count PMON Path Parity Error Event Count PMON FEBE/J2-EXZS Event Count PMON FEBE/J2-EXZS Event Count FRMR Configuration FRMR Interrupt Enable FRMR Interrupt Status FRMR Status TRAN Configuration
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Address
035H 036H037H 038H 039H 03AH 03BH 03CH 03DH 03EH 03FH 040H 041H 042H 043H 044H 045H 046H 047H 048H 049H 04AH04BH 04CH 04DH 04EH 04FH 050H 051H 052H 053H 054H 055H 056H 057H 058H 059H 05AH 05BH 05CH 135H 136H137H 138H 139H 13AH 13BH 13CH 13DH 13EH 13FH 140H 141H 142H 143H 144H 145H 146H 147H 148H 149H 14AH14BH 14CH 14DH 14EH 14FH 150H 151H 152H 153H 154H 155H 156H 157H 158H 159H 15AH 15BH 15CH 235H 236H237H 238H 239H 23AH 23BH 23CH 23DH 23EH 23FH 240H 241H 242H 243H 244H 245H 246H 247H 248H 249H 24AH24BH 24CH 24DH 24EH 24FH 250H 251H 252H 253H 254H 255H 256H 257H 258H 259H 25AH 25BH 25CH 335H 336H337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H 342H 343H 344H 345H 346H 347H 348H 349H 34AH34BH 34CH 34DH 34EH 34FH 350H 351H 352H 353H 354H 355H 356H 357H 358H 359H 35AH 35BH 35CH
Register
TRAN Diagnostics TRAN Reserved FRMR Framing Options FRMR Maintenance Options FRMR Framing Interrupt Enable FRMR Framing Interrupt Indication Status FRMR Maintenance Event Interrupt Enable FRMR Maintenance Event Interrupt Indication FRMR Maintenance Event Status FRMR Reserved TRAN Framing Options TRAN Status Diagnostic Options TRAN BIP-8 Error Mask TRAN Maintenance Adaptation Options FRMR Configuration FRMR Status FRMR Alarm Interrupt Enable FRMR Alarm Interrupt Status FRMR Error/X-bit Interrupt Enable FRMR Error/X-bit Interrupt Status FRMR Reserved TRAN Configuration TRAN Diagnostics TRAN TS97 Signaling TRAN TS98 Signaling RDLC Configuration RDLC Interrupt Control RDLC Status RDLC Data RDLC Primary Address Match RDLC Secondary Address Match RDLC Reserved RDLC Reserved TDPR Configuration TDPR Upper Transmit Threshold TDPR Lower Interrupt Threshold TDPR Interrupt Enable TDPR Interrupt Status/UDR Clear
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S/UNI®-4xD3F Data Sheet Released
Address
05DH 05EH05FH 090H 091H 092H 093H 094H 095H 096H097H 098H 099H 09AH 09BH 09CH 0A0H 0A1H 0A2H 0A3H 0A4H 0A5H0A7H 0A8H 0A9H 0AAH 0ABH 0ACH 0ADH 0AEH 0AFH 0B0H0FFH 400H 401H 7FFH Note 15DH 15EH15FH 180H 181H 182H 183H 184H 195H 196H197H 198H 199H 19AH 19BH 19CH 1A0H 1A1H 1A2H 1A3H 1A4H 1A5H1A7H 1A8H 1A9H 1AAH 1ABH 1ACH 1ADH 1AEH 1AFH 1B0H1FFH 25DH 25EH25FH 290H 291H 292H 293H 294H 295H 296H297H 298H 299H 29AH 29BH 29CH 2A0H 2A1H 2A2H 2A3H 2A4H 2A5H2A7H 2A8H 2A9H 2AAH 2ABH 2ACH 2ADH 2AEH 2AFH 2B0H2FFH 35DH 35EH35FH 390H 391H 392H 393H 394H 395H 396H397H 398H 399H 39AH 39BH 39CH 3A0H 3A1H 3A2H 3A3H 3A4H 3A5H3A7H 3A8H 3A9H 3AAH 3ABH 3ACH 3ADH 3AEH 3AFH 3B0H3FFH
Register
TDPR Transmit Data TDPR Reserved Control Register Trail Trace Identifier Status Indirect Address Register Indirect Data Register Expected Payload Type Label Register Payload Type Label Control/Status Reserved RBOC Configuration/Interrupt Enable RBOC Status XBOC Code S/UNI-4xD3F Misc. S/UNI-4xD3F FRMR Status. PRGD Control PRGD Interrupt Enable/Status PRGD Length PRGD PRGD Error Insertion PRGD Reserved PRGD Pattern Insertion Register PRGD Pattern Insertion Register PRGD Pattern Insertion Register PRGD Pattern Insertion Register PRGD Pattern Detector Register PRGD Pattern Detector Register PRGD Pattern Detector Register PRGD Pattern Detector Register S/UNI-4xD3F Reserved S/UNI-4xD3F Master Test Register Reserved S/UNI-4xD3F Test
must register accesses.
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S/UNI®-4xD3F Data Sheet Released
Normal Mode Register Descriptions
Normal mode registers used configure monitor operation S/UNI-4xD3F. Normal mode registers opposed test mode registers) selected when A[10] low. Notes Normal Mode Register Bits: Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions product, unused register bits must written with logic zero. Reading back unused bits produce either logic logic zero; hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling S/UNI-4xD3F determine programming state block. Writable normal mode register bits cleared logic zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect S/UNI-4xD3F operation unless otherwise noted. Certain register bits reserved. These bits associated with megacell functions that unused this application. ensure that S/UNI-4xD3F operates intended, reserved register bits must only written with suggested logic levels. Similarly, writing reserved registers should avoided. S/UNI-4xD3F requires software initialization sequence order guarantee proper device operation long term reliability. Please refer Section 10.1 this document details program this sequence. reserved bits must programmed order device function properly.
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S/UNI®-4xD3F Data Sheet Released
Register 000H, 100H, 200H, 300H: S/UNI-4xD3F Configuration
Type
Function
8KREFO Reserved6 Reserved5 FRAMER LOOPT LLOOP DLOOP PLOOP
Default
PLOOP PLOOP controls DS3, payload loopback. When logic zero written PLOOP, DS3, payload loopback disabled. When logic written PLOOP, DS3, overhead bits regenerated inserted into received DS3, stream resulting stream transmitted. Setting PLOOP disables effect TICLK S/UNI-4xD3F Transmit Configuration register, thereby forcing flowthrough timing. TFRM[1:0] RFRM[1:0] bits S/UNI-4xD3F Transmit Configuration Receive Configuration registers respectively, must same value PLOOP work properly. DLOOP DLOOP controls diagnostic loopback. When logic zero written DLOOP, diagnostic loopback disabled. When logic written DLOOP, transmit data stream looped receive direction. TFRM[1:0] RFRM[1:0] bits S/UNI4xD3F Transmit Configuration Receive Configuration registers respectively, must same value DLOOP work properly. DLOOP should logic when either PLOOP, LLOOP, LOOPT logic one. TUNI register S/UNI-4xD3F Transmit Configuration register should same value DS3, FRMR registers. LLOOP LLOOP controls line loopback. When logic zero written LLOOP, line loopback disabled. When logic written LLOOP, stream received RPOS/RDATI RNEG/RLCV/ROHM looped TPOS/TDATO TNEG/TOHM outputs. Note that TPOS, TNEG, TCLK outputs referenced RCLK when LLOOP logic one.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
LOOPT LOOPT selects transmit timing source. When logic written LOOPT, transmitter loop-timed receiver. When loop timing enabled, receive clock (RCLK) used transmit timing source. Setting LOOPT disables effect TICLK TXREF-bits S/UNI-4xD3F Transmit Configuration S/UNI-4xD3F Configuration registers, respectively, thereby forcing flow-through timing. FRAMER This must programmed logic proper operation. Reserved5 This reserved must programmed logic zero proper operation. Reserved6 This reserved must programmed logic proper operation. 8KREFO 8KREFO logic one1, then 8kHz reference will derived from RCLK[x] signal output REF8KO. 8KREFO logic zero, then RXMFPO register S/UNI-4xD3F Configuration registers will select either RFPO RMFPO function.
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S/UNI®-4xD3F Data Sheet Released
Register 001H, 101H, 201H, 301H: S/UNI-4xD3F Configuration
Type
Function
STATSEL[2] STATSEL[1] STATSEL[0] TXMFPI TXGAPEN RXGAPEN TXMFPO RXMFPO
Default
RXMFPO RXMFPO controls which outputs RMFPO[4:1] RFPO[4:1] valid. RXMFPO logic one, then RMFPO[4:1] will available. RXMFPO logic zero, then RFPO[4:1] will available. This effective only FRMRONLY S/UNI-4xD3F Configuration register logic one. TXMFPO TXMFPO controls which outputs TMFPO[4:1] TFPO[4:1] valid. TXMFPO logic one, then TMFPO[4:1] will available. TXMFPO logic zero, then TFPO[4:1] will available. This effective only FRMRONLY S/UNI-4xD3F Configuration register logic one. TXGAPEN-bit takes precedence over TXMFPO bit. RXGAPEN RXGAPEN-bit configures S/UNI-4xD3F enable RGAPCLK[x] outputs. When RXGAPEN logic one, then RGAPCLK[x] output enabled. When RXGAPEN logic zero, then RSCLK[x] output enabled. FRMRONLY register must logic RXGAPEN have effect. TXGAPEN TXGAPEN-bit configures S/UNI-4xD3F enable TGAPCLK[x] outputs. When TXGAPEN logic one, TGAPCLK[x] output enabled. When TXGAPEN logic zero, then either TFPO[x] TMFPO[x] output enabled, depending setting TXMFPO register bit. FRMRONLY register must logic TXGAPEN have effect.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
TXMFPI TXMFPI controls which inputs TMFPI[4:1] TFPI[4:1] valid. TXMFPI logic one, then TMFPI[4:1] will expected. TXMFPI logic zero, then TFPI[4:1] will expected. This effective only FRMRONLY S/UNI-4xD3F Configuration register logic one. STATSEL[2:0] STATSEL[2:0] bits used select function FRMSTAT[4:1] output. selection shown Table
Table STATSEL[2:0] Options STATSEL[2:0]
FRMSTAT output indication function
E3/DS3 extended (integration periods selected LOFINT[1:0] register bits S/UNI-4xD3FReceive Configuration register) E3/DS3 Idle Reserved
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S/UNI®-4xD3F Data Sheet Released
Register 002H, 102H, 202H, 302H: S/UNI-4xD3F Transmit Configuration
Type
Function
TFRM[1] TFRM[0] TXREF TICLK TUNI TCLKINV TPOSINV TNEGINV
Default
TNEGINV TNEGINV provides polarity control outputs TNEG/TOHM. When logic zero written TNEGINV, TNEG/TOHM output inverted. When logic written TNEGINV, TNEG/TOHM output inverted. TNEGINV setting does affect loopback data diagnostic loopback. TPOSINV TPOSINV provides polarity control outputs TPOS/TDATO. When logic zero written TPOSINV, TPOS/TDATO output inverted. When logic written TPOSINV, TPOS/TDATO output inverted. TPOSINV setting does affect loopback data diagnostic loopback. TCLKINV TCLKINV provides polarity control output TCLK. When logic zero written TCLKINV, TCLK inverted outputs TPOS/TDATO TNEG/TOHM updated falling edge TCLK. When logic written TCLKINV, TCLK inverted outputs TPOS/TDATO TNEG/TOHM updated rising edge TCLK. TUNI TUNI enables S/UNI-4xD3F transmit unipolar bipolar DS3, data streams. When logic written TUNI, S/UNI-4xD3Ftransmits unipolar DS3, data TDATO. When TUNI logic one, TOHM output indicates start M-Frame (the bit), start frame (bit frame), first framing multiframe. When logic zero written TUNI, S/UNI-4xD3Ftransmits B3ZS-encoded data, HDB3-encoded data, B8ZS-encoded data TPOS TNEG. TUNI effect TFRM[1:0] binary output data automatically configured unipolar format.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
TICLK TICLK selects transmit clock used update TPOS/TDATO TNEG/TOHM outputs. When logic zero written TICLK, buffered version input transmit clock, TCLK, used update TPOS/TDATO TNEG/TOHM edge selected TCLKINV bit. When logic written TICLK, TPOS/TDATO TNEG/TOHM updated rising edge TICLK, eliminating flow-through TCLK signal. TICLK effect LOOPT, LLOOP, PLOOP logic one. TXREF TXREF register determines TICLK[1] TIOHM/TFPI/TMFPI[1] should used reference transmit clock overhead/frame pulse, respectively, instead TICLK[X] TIOHM/TFPI/TMFPI[X]. TXREF logic one, then TICLK[1] TIOHM/TFPI/TMFPI[1] will used reference transmit clock overhead/frame pulse, respectively. TXREF logic zero, then TICLK[X] TIOHM/TFPI/TMFPI[X] will used reference transmit clock overhead/frame pulse, respectively, quadrant loop-timing enabled (LOOPT TXREF-bit effect corresponding quadrant. Note: When TXREF logic one, unused TICLK[x] TIOHM/TFPI/TMFPI[x] should tied power ground, left floating. TFRM[1:0] TFRM[1:0] bits determine frame structure transmitted signal. Refer Table
Table TFRM[1:0] Transmit Frame Structure Configurations TFRM[1:0]
Transmit Frame Structure
(C-bit parity depending setting CBIT TRAN Configuration register) (G.751 G.832 depending setting FORMAT[1:0] bits TRAN Framing Options register) (G.704 compliant framing format) DS1/E1/Arbitrary framing format SPLT Configuration register logic zero, then direct-mapped. logic one, then arbitrary framing format selected overhead positions indicated TIOHM[x] input pin.
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S/UNI®-4xD3F Data Sheet Released
Register 003H, 103H, 203H, 303H: S/UNI-4xD3F Receive Configuration
Type
Function
RFRM[1] RFRM[0] LOFINT[1] LOFINT[0] RSCLKR RCLKINV RPOSINV RNEGINV
Default
RNEGINV RNEGINV provides polarity control input RNEG/RLCV/ROHM. When logic zero written RNEGINV, input RNEG/RLCV/ROHM inverted. When logic written RNEGINV, input RNEG/RLCV/ROHM inverted. RNEGINV setting does affect loopback data diagnostic loopback. RPOSINV RPOSINV provides polarity control input RPOS/RDATI. When logic zero written RPOSINV input RPOS/RDATI inverted. When logic written RPOSINV input RPOS/RDATI inverted. RPOSINV setting does affect loopback data diagnostic loopback. RCLKINV RCLKINV provides polarity control input RCLK. When logic zero written RCLKINV, RCLK inverted inputs RPOS/RDATI RNEG/RLCV/ROHM sampled rising edge RCLK. When logic written RCLKINV, RCLK inverted inputs RPOS/RDATI RNEG/RLCV/ROHM sampled falling edge RCLK. RSCLKR RSCLKR effect only when FRMRONLY S/UNI-4xD3F Configuration register logic one. When RSCLKR logic one, RDATO, RFPO/RMFPO, ROVRHD outputs updated rising edge RSCLK. When RSCLKR logic zero, RDATO, RFPO/RMFPO, ROVRHD outputs updated falling edge RSCLK. RXGAPEN-bit logic one, then RSCLKR affects RGAPCLK same manner affects RSCLK.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
LOFINT[1:0] LOFINT[1:0] bits determine integration period used asserting de-asserting extended FRMLOF register S/UNI-4xD3FFRMR Status register (x9CH) FRMSTAT[4:1] output pins this function enabled STATSEL[2:0] register bits S/UNI-4xD3F Configuration register). integration times selected shown Table
Table LOF[1:0] Integration Period Configuration LOFINT[1:0]
Integration Period
Reserved
RFRM[1:0] RFRM[1:0] bits determine expected frame structure received signal. Refer Table
Table RFRM[1:0] Receive Frame Structure Configurations RFRM[1:0]
Expected Receive Frame Structure
(C-bit parity depending setting FRMR Configuration register) (G.751 G.832 depending setting FORMAT[1:0] bits FRMR Framing Options register) (G.704 compliant framing format) DS1/E1/Arbitrary framing format (When SPLR Configuration register logic zero, then direct-mapped. When logic one, then arbitrary framing format selected overhead positions indicated ROHM[x] input pin.)
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S/UNI®-4xD3F Data Sheet Released
Register 004H, 104H, 204H, 304H: Data Link FERF/RAI Control
Type
Function
Reserved AISEN RBLEN OOFEN LOSEN TNETOP RNETOP DLINV
Default
DLINV DLINV provides polarity control C-bit Parity PMDL, which located three C-bits M-subframe When logic written DLINV, PMDL inverted before being processed. rationale behind this safe-guard S/UNI4xD3Fin case inversion required future. Currently, ANSI standard T1.107 specifies that C-bits, which carry PMDL, all-zeros while maintenance signal transmitted. data link obviously inactive during transmission, ideally HDLC idle sequence (all-ones) should transmitted. inverting data link, all-zeros C-bit pattern becomes idle sequence data link terminated gracefully. RNETOP RNETOP enables Network Operator Byte (NR) extracted from G.832 stream terminated internal HDLC receiver, RDLC. When RNETOP logic one, byte extracted from G.832 stream terminated RDLC. When RNETOP logic zero, byte extracted from G.832 stream terminated RDLC. Both byte byte extracted output external processing. TNETOP TNETOP enables Network Operator Byte (NR) inserted G.832 stream sourced internal HDLC transmitter, TDPR. When TNETOP logic one, byte inserted into G.832 stream through TDPR block; byte G.832 stream sourced through TOH[x] TOHINS[x] pins. TOH[x] TOHINS[x] active, then all-ones signal will inserted into byte. When TNETOP logic zero, byte inserted into G.832 stream through TDPR block; byte G.832 stream sourced TOH[x] TOHINS[x] pins. TOH[x] TOHINS[x] active, then all-ones signal will inserted into byte.
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S/UNI®-4xD3F Data Sheet Released
G.751 streams, National sourced TDPR block TNETOP NATUSE (from TRAN Configuration register x41H) both logic zero. either TNETOP NATUSE logic one, National will sourced from NATUSE register register x41H. S/UNI-4xD3F configured operation, TNETOP effect. C-bit Parity datalink inserted into stream through internal HDLC transmitter TDPR. TOH[x] TOHINS[x] input pins used overwrite values these overhead bits transmit stream. LOSEN LOSEN-bit enables receive indication automatically generate FERF indication transmit stream. This operates regardless framer selected (DS3, J2). When LOSEN logic one, assertion indication framer causes FERF (RAI G.751 mode) transmitted TRAN duration assertion. When LOSEN logic zero, assertion indication does cause transmission FERF/RAI. Note: automatically transmitted when format, FEAC[5:0] bits XBOC Code register must logic one. XBOC FEAC code transmitted mode, LOSEN, OOFEN, AISEN, LCDEN should logic zero. OOFEN OOFEN-bit enables receive indication automatically generate FERF indication (RAI G.751 mode) transmit stream. This operates when framer selected when framer selected RBLEN-bit logic zero. When OOFEN logic one, assertion indication framer causes FERF/RAI transmitted TRAN duration assertion. When OOFEN logic zero, assertion indication does cause transmission FERF/RAI. Note: automatically transmitted when format, FEAC[5:0] bits XBOC Code register must logic one. XBOC FEAC code transmitted mode, LOSEN, OOFEN, AISEN, LCDEN should logic zero.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000314, Issue
S/UNI®-4xD3F Data Sheet Released
RBLEN RBLEN-bit enables: receive alarm (persistent OOF) indication automatically generate FERF indication transmit stream, BIP8 error detection G.832 Framer generate FEBE indication G.832 transmit stream, generate RLOF indication (A-bit) transmit stream. When G.751 framer selected, this effect. When RBLEN logic one, TFRM[1:0] binary, RFRM[1:0] binary, assertion indication framer causes FERF transmitted DS3_TRAN duration assertion. Also, frame format, OOFEN-bit internally forced logic zero when RBLEN logic one. When RBLEN logic zero, assertion indication does cause transmission FERF. When RBLEN logic one, TFRM[1:0] binary, RFRM[1:0] binary, BIP8 error indication G.832 framer causes FEBE generated G.832 TRAN. When RBLEN logic zero, BIP8 errors detected framer cause FEBEs generated E3_TRAN. When RBLEN logic one, TFRM[1:0] binary, RFRM[1:0] binary, error indication framer causes RLOF-bit (also known bit) transmit stream. When RBLEN logic zero, errors detected framer cause RLOF-bit transmit stream. AISEN AISEN-bit enables signal automatically generate FERF indication (RAI G.751 mode) transmit stream. This operates regardless framer selected (DS3, J2). When AISEN logic one, assertion indication (physical framer causes FERF/RAI transmitted TRAN duration assertion. When AISEN logic zero, assertion indication does cause transmission FERF/RAI. Note: automatically transmitted when format, FEAC[5:0] bits XBOC Code register must logic one. XBOC FEAC code transmitted mode, LOSEN, OOFEN, AISEN, LCDEN should logic zero. Reserved Reserved must programmed logic zero proper operation.
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Register 005H, 105H, 205H, 305H: S/UNI-4xD3F Interrupt Status
Type
Function
SPLRI/TTBI Unused Unused RBOCI/PRGDI FRMRI/LOFI PMONI TDPRI RDLCI
Default
SPLRI/TTBI, RBOCI/PRGDI, FRMRI/LOFI, PMONI, TDPRI, RDLCI These bits interrupt status indicators that identify block that source pending interrupt. SPLRI/TTBI will logic either SPLR block produced interrupt. RBOCI/PRGDI will logic either RBOC PRGD block produced interrupt. FRMRI/LOFI will logic either FRMR (J2, whichever enabled) Extended signal (FRMLOFI from register x9CH) source interrupt. This register typically used interrupt service routines determine source S/UNI-4xD3F interrupt.
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Register 006H: S/UNI-4xD3F Identification, Master Reset, Global Monitor Update
Type
Function
RESET TYPE[3] TYPE[2] TYPE[1] TYPE[0] Reserved ID[1] ID[0]
Default
This register used global performance monitor updates, global software resets, device identification. Writing value except into this register initiates latching performance monitor counts PMON block four quadrants S/UNI-4xD3F. register used signal when latching complete. RESET RESET allows software asynchronously reset S/UNI-4xD3F. software reset equivalent setting RSTB input low, except that S/UNI-4xD3FMaster Test register affected. When logic written RESET, S/UNI-4xD3F reset. When logic zero written RESET, reset removed. RESET must explicitly cleared writing corresponding logic value this register. TYPE[3:0] TYPE[3:0] bits allow software identify this device S/UNI-4xD3Fmember S/UNI family products. Reserved reserved must connect. ID[1:0] ID[1:0] bits allows software identify version level S/UNI-4xD3F.
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Register 007H, 107H, 207H, 307H: S/UNI-4xD3F Clock Activity Monitor Interrupt Identification
Type
Function
INT[4] INT[3] INT[2] INT[1] RCLKA TICLKA Unused Unused
Default
TICLKA TICLKA monitors low-to-high transitions TICLK[x] input. TICLKA when this register read high rising edge TICLK[x]. RCLKA RCLKA monitors low-to-high transitions RCLK[x] input. RCLKA when this register read high rising edge RCLK[x]. INT[4:1] INT[4:1] bits identify which four quadrants S/UNI-4xD3Fhave generated current interrupt. When INT[x] logic one, then quadrant generated interrupt. particular block(s) within that quadrant that generated interrupt identified reading corresponding quadrant's S/UNI-4xD3F Interrupt Status register. When INT[x] logic zero, then quadrant generated interrupt. Note: INT[4:1] bits valid only register address 007H.
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S/UNI®-4xD3F Data Sheet Released
Register 010H, 110H, 210H, 310H: Change PMON Performance Meters
Type
Function
Unused Unused LCVCH FERRCH EXZS PERRCH CPERRCH FEBECH
Default
FEBECH FEBECH logic more FEBE events EXZS events when framing format selected) have occurred during latest PMON accumulation interval. CPERRCH CPERRCH logic more path parity error events have occurred during latest PMON accumulation interval. PERRCH PERRCH logic more parity error events CRC-5 errors) have occurred during latest PMON accumulation interval. EXZS EXZS logic more summed events mode have occurred during latest PMON accumulation interval. FERRCH FERRCH logic more F-bit M-bit error events have occurred during latest PMON accumulation interval. LCVCH LCVCH logic more events have occurred during latest PMON accumulation interval.
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S/UNI®-4xD3F Data Sheet Released
Register 011H, 111H, 211H, 311H: PMON Interrupt Enable/Status
Type
Function
Unused Unused Unused Unused Unused INTE INTR
Default
indicates overrun status PMON holding registers. logic this position indicates that previous interrupt been cleared before next accumulation interval, that contents holding registers have been overwritten. logic zero indicates that overrun occurred. This reset logic zero when this register read. INTR INTR indicates current status interrupt signal. logic this position indicates that transfer counter values holding registers occurred; logic zero indicates that transfer occurred. INTR logic zero when this register read. INTE INTE enables generation interrupt when PMON counter values transferred holding registers. When logic written INTE, interrupt generation enabled.
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Register 014H, 114H, 214H, 314H: PMON Event Count
Type
Function
LCV[7] LCV[6] LCV[5] LCV[4] LCV[3] LCV[2] LCV[1] LCV[0]
Default
Register 015H, 115H, 215H, 315H: PMON Event Count
Type
Function
LCV[15] LCV[14] LCV[13] LCV[12] LCV[11] LCV[10] LCV[9] LCV[8]
Default
LCV[15:0] LCV[15:0] represents number DS3, errors that have been detected since last time counter polled. counter (and other counters PMON) polled writing PMON register addresses (x14H x1FH) S/UNI-4xD3F Identification, Master Reset, Global Monitor Update register (006H). Such write transfers internally accumulated count Error Count registers simultaneously resets internal counter begin cycle error accumulation. This transfer reset carried manner that coincident events lost. transfer takes three RCLK[x] cycles complete.
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S/UNI®-4xD3F Data Sheet Released
Register 016H, 116H, 216H, 316H: PMON Framing Error Event Count
Type
Function
FERR[7] FERR[6] FERR[5] FERR[4] FERR[3] FERR[2] FERR[1] FERR[0]
Default
Register 017H, 117H, 217H, 317H: PMON Framing Error Event Count
Type
Function
Unused Unused Unused Unused Unused Unused FERR[9] FERR[8]
Default
FERR[9:0] FERR[9:0] represents number F-bit M-bit errors, framing pattern errors, that have been detected since last time framing error counter polled. counter (and other counters PMON) polled writing PMON register addresses (x14H x1FH) S/UNI-4xD3F Identification, Master Reset, Global Monitor Update register (006H). Such write
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