PM7347 S/UNI S/UNI®-JET SATURN® USER NETWORK INTERFACE
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S/UNI®-JET Data Sheet Released
PM7347
S/UNI
S/UNI®-JET
SATURN® USER NETWORK INTERFACE J2/E3/T3
Data Sheet
Released Issue June 2001
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-1990267, Issue
S/UNI®-JET Data Sheet Released
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2001 PMC-Sierra, Inc. information proprietary confidential PMC-Sierra, Inc., customers' internal use. event, cannot reproduce part this document, form, without express written consent PMC-Sierra, Inc. PMC-1990267 (R3)
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None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage.
Trademarks
S/UNI SATURN registerd trademarks PMC-Sierra, Inc. SCI-PHY trademark PMC-Sierra, Inc.
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Contacting PMC-Sierra
PMC-Sierra 8555 Baxter Place Burnaby, Canada Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Site: http://www.pmc-sierra.com
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Revision History
Issue
Issue Date
June 2001
Details Change
Included Application examples, Description, Functional Description, Functional Timing, Microprocessor Timing, A.C. Timing sections. Completed Normal Mode Register Operation sections. Changed read-only "Reserved" bits "Unused". Changed IDDOP values. Changed Thermal "Case" temperature "Ambient", Section Divided Diagram into quadrants readability.
March 2000 April 1999
Preliminary label removed. S/UNI-JET errata added. Document created.
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Table Contents
Features.17 Applications References Definitions Application Examples Block Diagram Description.29 Diagram Description.34 Functional Description 10.1 Framer.54 10.2 Framer 10.3 Framer.58 10.3.1 Frame Find Algorithms 10.4 RBOC Bit-Oriented Code Detector 10.5 RDLC PMDL Receiver 10.6 PMON Performance Monitor Accumulator.63 10.7 SPLR PLCP Layer Receiver 10.8 ATMF ACell Delineator.64 10.9 PRGD Pseudo-Random Sequence Generator/Detector 10.10 RXCP-50 Receive Cell Processor 10.11 RXFF Receive FIFO.68 10.12 CPPM Cell PLCP Performance Monitor 10.13 Transmitter 10.14 Transmitter.70 10.15 Transmitter 10.16 XBOC Oriented Code Generator 10.17 TDPR PMDL Transmitter 10.18 SPLT SMDS PLCP Layer Transmitter 10.19 TXCP-50 Transmit Cell Processor 10.20 TXFF Transmit FIFO 10.21 Trail Trace Buffer 10.22 JTAG Test Access Port.75
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10.23 Microprocessor Interface Normal Mode Register Description.81 Test Features Description.249 12.1 Test Mode Details.251 12.2 JTAG Test Port .255 Operation .259 13.1 Software Initialization Sequence.259 13.2 Register Settings Basic Configurations .260 13.3 PLCP Frame Formats .261 13.3.1 PLCP Path Overhead Octet Processing .264 13.4 Frame Format .267 13.5 G.751 Frame Format .269 13.6 G.832 Frame Format .270 13.7 Frame Format .271 13.8 S/UNI-JET Cell Data Structure.273 13.9 Resetting RXFF TXFF FIFOs .277 13.10 Servicing Interrupts .277 13.11 Using Performance Monitoring Features .277 13.12 Using Internal PMDL Transmitter.278 13.12.1 Interrupt Driven Mode.279 13.12.2 TDPR Interrupt Routine.280 13.13 Using Internal Data Link Receiver .281 13.14 PRGD Pattern Generation .285 13.14.1 Generating detecting repetitive patterns .286 13.14.2 Common Test Patterns.286 13.15 JTAG Support.288 13.15.1 Controller .289 Functional Timing.295 Absolute Maximum Ratings.319 D.C. Characteristics.320 Microprocessor Interface Timing Characteristics .322 A.C. Timing Characteristics .325 Ordering Thermal Information .339 Mechanical Information .340
Notes .341
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-1990267, Issue
S/UNI®-JET Data Sheet Released
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List Registers
Register 300H: S/UNI-JET Configuration 1.82 Register 301H: S/UNI-JET Configuration 2.85 Register 302H: S/UNI-JET Transmit Configuration Register 303H: S/UNI-JET Receive Configuration.89 Register 304H: S/UNI-JET Data Link FERF/RAI Control.91 Register 305H: S/UNI-JET Interrupt Status.95 Register 006H: S/UNI-JET Identification, Master Reset, Global Monitor Update Register 307H: S/UNI-JET Clock Activity Monitor Interrupt Identification Register 308H: SPLR Configuration.98 Register 309H: SPLR Interrupt Enable .100 Register 30AH: SPLR Interrupt Status .102 Register 30BH: SPLR Status.104 Register 30CH: SPLT Configuration.106 Register 30DH: SPLT Control.109 Register 30EH: SPLT Diagnostics Octet Register 30FH: SPLT Octet. Register 310H: Change PMON Performance Meters Register 311H: PMON Interrupt Enable/Status Register 314H: PMON Event Count LSB. Register 315H: PMON Event Count MSB. Register 316H: PMON Framing Error Event Count 317H: PMON Framing Error Event Count MSB. Register 318H: PMON Excessive Zero Count Register 319H: PMON Excessive Zero Count Register 31AH: PMON Parity Error Event Count Register 31BH: PMON Parity Error Event Count Register 31CH: PMON Path Parity Error Event Count LSB.120 Register 31DH: PMON Path Parity Error Event Count MSB.120 Register 31EH: PMON FEBE/J2-EXZS Event Count LSB.121 Register 31FH: PMON FEBE/J2-EXZS Event Count MSB.121 Register 321H: CPPM Change CPPM Performance Meters .122 Register 322H: CPPM Error Count .123 Register 323H: CPPM Error Count .123
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Register 324H: CPPM Framing Error Event Count .124 Register 325H: CPPM Framing Error Event Count .124 Register 326H: CPPM FEBE Count .125 Register 327H: CPPM FEBE Count .125 Register 330H: FRMR Configuration.126 Register 331H: FRMR Interrupt Enable (ACE=0) .128 Register 331H: FRMR Additional Configuration Register .130 Register 332H: FRMR Interrupt Status.133 Register 333H: FRMR Status .135 Register 334H: TRAN Configuration .137 Register 335H: TRAN Diagnostic.139 Register 338H: FRMR Framing Options .141 Register 339H: FRMR Maintenance Options .143 Register 33AH: FRMR Framing Interrupt Enable .145 Register 33BH: FRMR Framing Interrupt Indication Status .146 Register 33CH: FRMR Maintenance Event Interrupt Enable .148 Register 33DH: FRMR Maintenance Event Interrupt Indication .150 Register 33EH: FRMR Maintenance Event Status .152 Register 340H: TRAN Framing Options.154 Register 341H: TRAN Status Diagnostic Options.155 Register 342H: TRAN BIP-8 Error Mask.157 Register 343H: TRAN Maintenance Adaptation Options .158 Register 344H: J2-FRMR Configuration.160 Register 345H: J2-FRMR Status .162 Register 346H: J2-FRMR Alarm Interrupt Enable .163 Register 347H: J2-FRMR Alarm Interrupt Status .165 Register 348H: J2-FRMR Error/Xbit Interrupt Enable .167 Register 349H: J2-FRMR Error/Xbit Interrupt Status .169 Register 34CH: J2-TRAN Configuration.171 Register 34DH: J2-TRAN Diagnostic .172 Register 34EH: J2-TRAN TS97 Signaling.173 Register 34FH: J2-TRAN TS98 Signaling .174 Register 350H: RDLC Configuration .175 Register 351H: RDLC Interrupt Control.177 Register 352H: RDLC Status.178
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S/UNI®-JET Data Sheet Released
Register 353H: RDLC Data .180 Register 354H: RDLC Primary Address Match .181 Register 355H: RDLC Secondary Address Match .182 Register 358H: TDPR Configuration .183 Register 359H: TDPR Upper Transmit Threshold .185 Register 35AH: TDPR Lower Interrupt Threshold .186 Register 35BH: TDPR Interrupt Enable.187 Register 35CH: TDPR Interrupt Status/UDR Clear .188 Register 35DH: TDPR Transmit Data.190 Register 360H: RXCP-50 Configuration 1.191 Register 361H: RXCP-50 Configuration 2.193 Register 362H: RXCP-50 FIFO/UTOPIA Control Configuration .195 Register 363H: RXCP-50 Interrupt Enables Counter Status.197 Register 364H: RXCP-50 Status/Interrupt Status.199 Register 365H: RXCP-50 Count Threshold (MSB) .201 Register 366H: RXCP-50 Count Threshold (LSB) .201 Register 367H: RXCP-50 Idle Cell Header Pattern.203 Register 368H: RXCP-50 Idle Cell Header Mask.204 Register 369H: RXCP-50 Corrected Error Count .205 Register 36AH: RXCP-50 Uncorrected Error Count.206 Register 36BH: RXCP-50 Receive Cell Counter (LSB) .207 Register 36CH: RXCP-50 Receive Cell Counter .207 Register 36DH: RXCP-50 Receive Cell Counter (MSB) .208 Register 36EH: RXCP-50 Idle Cell Counter (LSB).209 Register 36FH: RXCP-50 Idle Cell Counter .209 Register 370H: RXCP-50 Idle Cell Counter (MSB) .210 Register 380H: TXCP-50 Configuration Register 381H: TXCP-50 Configuration .213 Register 382H: TXCP-50 Cell Count Status.215 Register 383H: TXCP-50 Interrupt Enable/Status .216 Register 384H: TXCP-50 Idle Cell Header Control .218 Register 385H: TXCP-50 Idle Cell Payload Control.219 Register 386H: TXCP-50 Transmit Cell Count (LSB).220 Register 387H: TXCP-50 Transmit Cell Count .220 Register 388H: TXCP-50 Transmit Cell Count (MSB).221
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Register 390H: Control .222 Register 391H: Trail Trace Identifier Status .224 Register 392H: Indirect Address.225 Register 393H: Indirect Data .226 Register 394H: Expected Payload Type Label .227 Register 395H: Payload Type Label Control/Status .228 Register 398H: RBOC Configuration/Interrupt Enable.230 Register 399H: RBOC Interrupt Status.231 Register 39AH: XBOC Code .232 Register 39BH: S/UNI-JET Miscellaneous .233 Register 39CH: S/UNI-JET FRMR Status. .235 Register 3A0H: PRGD Control .237 Register 3A1H: PRGD Interrupt Enable/Status .239 Register 3A2H: PRGD Length.241 Register 3A3H: PRGD .242 Register 3A4H: PRGD Error Insertion Register .243 Register 3A8H: Pattern Insertion #1.244 Register 3A9H: Pattern Insertion #2.244 Register 3AAH: Pattern Insertion .245 Register 3ABH: Pattern Insertion .245 Register 3ACH: PRGD Pattern Detector #1.246 Register 3ADH: PRGD Pattern Detector #2.246 Register 3AEH: PRGD Pattern Detector .247 Register 3AFH: PRGD Pattern Detector .247 Register 40CH: S/UNI-JET Identification Register .248
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S/UNI®-JET Data Sheet Released
List Figures
Figure S/UNI-JET Operating APHY ASwitch Figure S/UNI-JET Operating Framer Device Frame Relay Equipment.27 Figure Block Diagram Figure Framing algorithm (CRC_REFR Figure Framing Algorithm (CRC_REFR 1).61 Figure Cell delineation State Diagram Figure Verification State Diagram.68 Figure PLCP Frame Format .262 Figure PLCP Frame Format .262 Figure G.751 PLCP Frame Format.263 Figure PLCP Frame Format.264 Figure Frame Structure .267 Figure G.751 Frame Structure .269 Figure G.832 Frame Structure .270 Figure Frame Structure .272 Figure 16-bit Wide, 26-byte Word Structure.273 Figure 16-bit Wide, 27-byte Word Structure.274 Figure 8-bit Wide, 52-byte Word Structure.275 Figure 8-bit Wide, 53-byte Word Structure.276 Figure Typical Data Frame.284 Figure Example Multi-Packet Operational Sequence .284 Figure PRGD Pattern Generator .285 Figure Boundary Scan Architecture .288 Figure Controller Finite State Machine.290 Figure Input Observation Cell (IN_CELL) .293 Figure Output Cell (OUT_CELL) .293 Figure Bi-directional Cell (IO_CELL) .294 Figure Layout Output Enable Bi-directional Cells .294 Figure Receive Stream.295 Figure Receive Stream .295 Figure Receive Bipolar Stream .296 Figure Receive Unipolar Stream .296 Figure Receive Bipolar Stream .296
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S/UNI®-JET Data Sheet Released
Figure Receive Unipolar Stream.297 Figure Receive Bipolar Stream .297 Figure Receive Unipolar Stream .298 Figure Generic Receive Stream .298 Figure Receive Overhead .299 Figure Receive G.832 Overhead .300 Figure Receive G.751 Overhead .300 Figure Receive Overhead.301 Figure Receive PLCP Overhead .301 Figure Transmit Stream.302 Figure Transmit Stream .302 Figure Transmit Bipolar Stream .303 Figure Transmit Unipolar Stream .303 Figure Transmit Bipolar Stream .304 Figure Transmit Unipolar Stream.304 Figure Transmit Bipolar Stream .305 Figure Transmit Unipolar Stream .305 Figure Generic Transmit Stream .306 Figure Transmit Overhead .307 Figure Transmit G.832 Overhead .308 Figure Transmit G.751 Overhead .309 Figure Transmit Overhead.309 Figure Transmit PLCP Overhead .310 Figure Framer Mode Transmit Input Stream.311 Figure Framer Mode Transmit Input Stream With TGAPCLK.311 Figure Framer Mode Receive Output Stream .311 Figure Framer Mode Receive Output Stream with RGAPCLK .312 Figure Framer Mode G.751 Transmit Input Stream .312 Figure Framer Mode G.751 Transmit Input Stream With TGAPCLK .312 Figure Framer Mode G.751 Receive Output Stream.313 Figure Framer Mode G.751 Receive Output Stream with RGAPCLK .313 Figure Framer Mode G.832 Transmit Input Stream .314 Figure Framer Mode G.832 Transmit Input Stream With TGAPCLK .314 Figure Framer Mode G.832 Receive Output Stream.314 Figure Framer Mode G.832 Receive Output Stream with RGAPCLK .314
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S/UNI®-JET Data Sheet Released
Figure Framer Mode Transmit Input Stream .315 Figure Framer Mode Transmit Input Stream With TGAPCLK.315 Figure Framer Mode Receive Output Stream .316 Figure Framer Mode Receive Output Stream with RGAPCLK .316 Figure Multi-PHY Polling Addressing Transmit Cell Interface.317 Figure Multi-PHY Polling Addressing Receive Cell Interface.318 Figure Microprocessor Interface Read Timing .322 Figure Microprocessor Interface Write Timing .324 Figure RSTB Timing.325 Figure Transmit ACell Interface Timing .326 Figure Receive ACell Interface Timing .328 Figure Transmit Interface Timing .330 Figure Receive Interface Timing .335 Figure JTAG Port Interface Timing.337
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S/UNI®-JET Data Sheet Released
List Tables
Table Supported Operating Formats.17 Table Transmission System Sublayer Processing Acceptance Output Table Summary Receive Detection Features Table Multiframe Format Table Octet Pattern.74 Table Register Memory Table STATSEL[2:0] Options Table TFRM[1:0] Transmit Frame Structure Configurations Table LOF[1:0] Integration Period Configuration Table RFRM[1:0] Receive Frame Structure Configurations Table SPLR FORM[1:0] Configurations Table PLCP Declaration/Removal Times.104 Table SPLT FORM[1:0] Configurations .107 Table FRMR EXZS/LCV Count Configurations.131 Table FRMR Configurations .132 Table FRMR FORMAT[1:0] Configurations .141 Table TRAN FORMAT[1:0] Configurations.154 Table FRMR Threshold Configurations.161 Table RDLC PBS[2:0] Data Status.178 Table RXCP-50 Filtering Configurations .193 Table RXCP-50 Cell Delineation Algorithm Base .193 Table RXCP-50 Integration Periods.201 Table TXCP-50 FIFO Depth Configurations .213 Table Payload Type Match Configurations .227 Table PRGD Pattern Detector Register Configuration.237 Table PRGD Generated Error Rate Configurations.243 Table Test Mode Register Memory .249 Table Test Mode Input Read Address Locations .251 Table Test Mode Output Write Address Locations .253 Table Instruction Register .255 Table Identification Register.256 Table Boundary Scan Register .256 Table Register Settings Basic Configurations.260
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Table PLCP Overhead Processing .264 Table PLCP Path Overhead Identifier Codes .266 Table PLCP Trailer Length.266 Table PLCP Trailer Length .267 Table Frame Overhead Operation .268 Table G.751 Frame Overhead Operation .269 Table G.832 Frame Overhead Operation .270 Table Frame Overhead Operation.272 Table Pseudo Random Pattern Generation 0).286 Table Repetitive Pattern Generation 1).287 Table Receive Overhead Bits.299 Table Transmit Overhead Bits.307 Table Absolute Maximum Ratings.319 Table Characteristics .320 Table Microprocessor Interface Read Access (Figure 75).322 Table Microprocessor Interface Write Access (Figure .323 Table RSTB Timing (Figure .325 Table Transmit ACell Interface Timing (Figure .325 Table Receive ACell Interface Timing (Figure .327 Table Transmit Interface Timing (Figure 80).329 Table Receive Interface Timing (Figure 81).334 Table JTAG Port Interface (Refer Figure .336 Table Packaging Information.339 Table Thermal Information .339
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Features
S/UNI®-JET single chip Asynchronous Transfer Mode (ATM) User Network Interface (UNI) operating 44.736 Mbit/s, 34.368 Mbit/s, 6.312 Mbit/s that: Conforms AF-Physical (PHY)-0054.000, AF-PHY-0034.000 AF-PHY-0029.000. Implements ADirect Cell Mapping into DS1, DS3, transmission systems according ITU-T Recommendation G.804. Provides UTOPIA Level compatible ATM-PHY Interface. Implements Physical Layer Convergence Protocol (PLCP) transmission systems according AForum User Network Interface Specification ANSI TATSY-000773, TA-TSY-000772, transmission systems according ETSI 300-269 ETSI 300-270. Supports Switched Multi-megabit Data Service (SMDS) Amappings into various rate transmission systems shown Table
Table Supported Operating Formats Rate
(44.736 Mbit/s) (34.368 Mbit/s) (6.312 Mbit/s) (2.048 Mbit/s) (1.544 Mbit/s) Arbitrary Cell Rate Mbit/s) CRC-4 PCM30 external external external external bypass
Format
C-bit Parity G.751 G.832 G.704
Framer Only
SMDS PLCP Mapping
ADirect Mapping
Implements Aphysical layer Broadband ISDN according ITU-T Recommendation I.432. Provides on-chip DS3, (G.751 G.832), framers. configurable sole DS3, Framer use.
Note: When configured operate DS3, Framer, gapped transmit receive clocks optionally generated interface devices which only need access payload data bits. Provides support arbitrary rate external transmission system interface maximum rate Mbit/s, which enables S/UNI-JET used Acell delineator.
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Uses PMC-SierraPM4351 COMET, PM4341 T1XC PM6341 E1XC framer/line interface chips applications. Provides programmable pseudo-random test pattern generation, detection, analysis features. Provides integral transmit receive HDLC controller with 128-byte FIFO depth. Provides performance monitoring counters suitable accumulation periods second. Provides 8-bit microprocessor interface configuration, control status monitoring. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. Uses power 3.3V CMOS technology with tolerant inputs. available 256-pin SBGA package (27mm 27mm).
receiver section S/UNI-JET: Provides frame synchronization C-bit parity applications alarm detection. Also: Accumulates line code violations, framing errors, parity errors, path parity errors FEBE events. Detects alarm channel codes. Provides integral HDLC receiver terminate path maintenance data link. Provides frame synchronization G.751 G.832 applications alarm detection. Also: Accumulates line code violations, framing errors, parity errors, FEBE events. Detects Trail Trace G.832, Trail Trace detected. Provides integral HDLC receiver provided terminate either Network Requirement General Purpose data link. Provides frame synchronization G.704 6.312 Mbit/s applications alarm detection. Also: Accumulates line code violations, framing errors, parity errors. Provides integral HDLC receiver terminate data link. Provides frame synchronization, cell delineation extraction DS3, G.751 G.832 G.704 Adirect-mapped formats. Provides PLCP frame synchronization, path overhead extraction, cell extraction PLCP, PLCP, PLCP, G.751 PLCP formatted streams. Provides 8-bit wide 16-bit wide Utopia FIFO buffer receive path with parity support, multi-PHY (Level control signals. Provides Aframing using cell delineation. Note: Acell delineation optionally disabled allow passing cell bytes regardless cell delineation status.
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Provides cell descrambling, header check sequence (HCS) error detection, idle cell filtering, header descrambling (for with packets), accumulates number received idle cells, number received cells written FIFO, number errors. Provides four cell FIFO rate decoupling between line, higher layer processing entity. FIFO latency reduced changing number operational cell FIFOs. Provides receive HDLC controller with 128-byte FIFO accumulate data link information. Provides detection yellow alarm loss frame (LOF), accumulates BIP-8 errors, framing errors FEBE events. Provides programmable pseudo-random test-sequence detection length patterns conforming ITU-T O.151 standards) analysis features.
transmitter section S/UNI-JET: Provides frame insertion C-bit parity applications, alarm insertion, diagnostic features. Also: Optionally inserts alarm channel codes. Provides integral HDLC transmitter provided insert path maintenance data link. Provides frame insertion G.751 G.832 applications, alarm insertion, diagnostic features. Also: Inserts Trail Trace G.832 Provides integral HDLC transmitter insert either Network Requirement General Purpose data link. Provides frame insertion G.704 6.312 Mbit/s applications, alarm insertion, diagnostic features, also integral HDLC transmitter insert path maintenance data link. Provides frame insertion path overhead insertion DS1, DS3, based PLCP formats, also alarm insertion diagnostic features. Provides 8-bit wide 16-bit wide Utopia FIFO buffer transmit path with parity support multi-PHY (Level control signals. Provides optional Acell scrambling, header scrambling (for with packets), generation/insertion, programmable idle cell insertion, diagnostics features accumulates transmitted cells read from FIFO. Provides four cell FIFO rate decoupling between line higher layer processing entity. FIFO latency reduced changing number operational cells FIFO. Provides transmit HDLC controller with 128-byte FIFO. Provides reference input locking transmit PLCP frame rate externally applied frame reference.
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Provides programmable pseudo-random test sequence generation 232-1 length sequences conforming ITU-T O.151 standards). Diagnostic abilities include single error insertion error insertion error rates ranging from 10-1 10-7.
bypass loopback features S/UNI-JET: Allow bypassing DS3, framers enable transmission system sublayer processing external device. Allow bypassing PLCP Afunctions enable S/UNI-JET DS3, framer. Provide diagnostic loopbacks, line loopbacks, payload loopbacks.
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Applications
SMDS Switches, Multiplexers, Routers SONET/SDH E3/DS3 Tributary Interfaces J2/E3/DS3 Line Interfaces DS3/E3/J2 Digital Cross Connect Interfaces DS3/E3/J2 Internet Access Interfaces DS3/E3/J2 Frame Relay Interfaces DSLAM Uplinks
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References
ANSI T1.627 1993, "Broadband ISDN ALayer Functionality Specification". ANSI T1.107a 1990, "Digital Hierarchy Supplement Formats Specifications (DS3 Format Applications)". ANSI T1.107 1995, "Digital Hierarchy Formats Specifications". ANSI T1.646 1995, "Broadband ISDN Physical Layer Specification User-Network Interfaces Including DS1/ATM". AForum AUser-Network Interface Specification, V3.1, October, 1995. AForum "UTOPIA, APHY Interface Specification, Level Version June, 1995. AForum, af-PHY-0034.000, (34,368 kbps) Physical Layer Interface", August, 1995. AForum, af-PHY-0054.000, "DS3 Physical Layer Interface Specification", January, 1996. AForum, af-PHY-0029.000, "6,312 Kbps Specification, Version 1.0", June 1995. Bell Communications Research, TA-TSY-000773 "Local Access System Generic Requirements, Objectives, Interface Support Switched Multi-megabit Data Service" Issue March 1990 Supplement December 1990. Draft Standard T/NA(91)17 "Metropolitan Area Network Physical Layer Convergence Procedure 2.048 Mbit/s", April 1994. Draft Standard T/NA(91)18 "Metropolitan Area Network Physical Layer Convergence Procedure 34.368 Mbit/s", April 1994. ITU-T Recommendation O.151 "Error Performance Measuring Equipment Operating Primary Rate Above", October, 1992. ITU-T Recommendation I.432 "B-ISDN User-Network Interface Physical Layer Specification", 1993 ITU-T Recommendation G.703 "Physical/Electrical Characteristics Hierarchical Digital Interfaces", 1991. ITU-T Recommendation G.704 "General Aspects Digital Transmission Systems; Terminal Equipment Synchronous Frame Structures Used 1544, 6312, 2048, 8488 kbit/s Hierarchical Levels", July, 1995. ITU-T Recommendation G.751 CCITT Blue Book Fasc. III.4, "Digital Multiplex Equipment Operating Third Order Rate 34,368 kbit/s Fourth Order Rate 139,264 kbit/s Using Positive Justification", 1988. ITU-T Draft Recommendation G.775 "Loss Signal (LOS) Alarm Indication Signal (AIS) Defect Detection Clearance Criteria", October 1993. ITU-T Recommendation G.804 "ACell Mapping into Plesiochronous Digital Hierarchy (PDH)", 1993.
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ITU-T Recommendation G.832 "Transport Elements Networks: Frame Multiplexing Structures", 1993. ITU-T Recommendation Q.921 "ISDN User-Network Interface Data Link Layer Specification", March, 1993. Technical Reference, "NTT Technical Reference High-Speed Digital Leased Circuit Services", 1991.
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Definitions
following table defines abbreviations S/UNI-JET.
ABIP CMOS COFA CPERR DSLAM EXZS F-bit FEAC FEBE FERF FERR FIFO HDLC ISDN JTAG PERR PLCP PMDL PMON Application Identification Channel Alarm Indication Signal Asynchronous Transfer Mode Interleaved Parity Complementary Metal Oxide Semiconductor Change Frame Alignment Path Parity Error Cyclic Redundancy Check Access Multiplexer Digital Signal Level Digital Signal Level Excess Zeros Framing Framing Alignment Signal Far-End Alarm Control Far-End Block Error Receive Failure Framing Error First-In First-Out Header Check Sequence High-level Data Link Control Integrated Services Digital network International Telecommunications Union Joint Test Action Group Loss Cell Delineation Line Code Violation Loss Frame Loss Signal Return Zero Frame Parity Error Physical Layer Physical Layer Convergence Procedure Path Maintenance Data Link Performance Monitor Packet Over SONET Point-to-Point Protocol
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RBOC RDLC SBGA SCI-PHY SMDS SONET
Receive Alarm Indication Oriented Code Detector Data Link Receiver Receive Error Detection Super Ball Grid Array SATURN® Compatible Interface Specification Alayer devices Switched Multi-Megabit Data Service Synchronous Optical Network Test Access Port Telecom System Block Trail Trace Buffer
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Application Examples
S/UNI-JET configurable Adevice J2/E3/T3 framer cell processor
ATM-PHY layer device, S/UNI-JET connects line side J2/E3/T3 line interface unit system side, interfaces with Alayer device, such PM7322 RCMP-800, over 16-bit wide UTOPIA Level interface. Refer Figure
Figure S/UNI-JET Operating APHY ASwitch
T1/E1 Line Card
OC-12 Line Card PM4314 QDSX PM7344 S/UNI-MPH
PM5355 S/UNI-622
UTOPIA
ASwitch Core J2/E3/T3 Line Card Switch Fabric
OC-3 Line Cards PM5346 S/UNI-LITE
J2/E3/T3
PM7322 RCMP-800
Egress Device
PM7347 S/UNI-JET
PM7348 S/UNIDUAL PM5347 S/UNI-PLUS
J2/E3/T3 framer, S/UNI-JET used router, frame relay switch, multiplexer applications. Refer Figure
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UTOPIA
S/UNI®-JET Data Sheet Released
Figure S/UNI-JET Operating Framer Device Frame Relay Equipment
Access Side
Uplink Side
Unchannelized J2/E3/T3 Card
Port Channelized Card PM4314 QDSX PM4388 TOCTL
J2/E3/T3
PM7366 FREEDM-8
Switch/Router Core Switch Fabric
PM7366 FREEDM-8
PM7347 S/UNIJET
Port Channelized Card PM4314 QDSX PM6344 EQUAD PM7366 FREEDM-8
Processor Port Unchannelized Card (M13) PM4388 TOCTL PM7364 FREEDM32
Packet Memory
DS-3
PM8313 D3MX
unchannelized J2/E3/T3 line card, S/UNI-JET directly connects PM7366 FREEDM-8 HDLC controller. Each FREEDM-8 process high-speed links such process eight lower speed links such S/UNI-JET gaps overhead bits that only payload data passed from FREEDM-8. line side, S/UNIJET connected J2/E3/T3 line interface unit. system side, S/UNI-JET interfaces with data link device over serial interface.
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S/UNI®-JET Data Sheet Released
Block Diagram
Figure Block Diagram
TPOHFP/TFPO/TMFPO/TGAPCLK/TCELL
TIOHM/TFPI/TMFPI
TPOH/TDATI
TPOHCLK
TPOHINS
TOHFP TOHCLK
TOHINS
REF8KI
TRSTB
TICLK
XBOC FEAC
TDPR HDLC
Access
Trail Buffer
IEEE P1149.1 JTAG Test Access Port
PRGD Tester
TPOS/TDATO TNEG/TOHM TCLK
Line Encode
TRAN Transmit Framer
SPLT Transmit Aand PLCP Framer
TXCP_50 Cell Processor
TXFF Cell FIFO System
RCLK RPOS/RDATI RNEG/RLCV/ROHM
Line Decode
FRMR Receive Framer
ATMF/SPLR Receive Aand PLCP Framer
RXCP_50 Cell Processor
RXFF Cell FIFO
RBOC FEAC
RDLC HDLC
PMON Perfor. Monitor
Access
Trail Buffer
CPPM PLCP/cell Performance Monitor
DTCA TDAT[15.0] TPRTY TSOC TADR[2.0] TENB TFCLK PHY_ADR[2.0] ATM8 RFCLK RENB RADR[2.0] RSOC RPRTY RDAT[15.0] DRCA
Microprocessor Interface
ROHFP
LCD/RDATO
ROHCLK
RPOH/ROVRHD
RPOHCLK/RSCLK/RGAPCLK
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REF8KO/RPOHFP/RFPO/RMFPO
FRMSTAT
D[7.0] A[10.0]
RSTB INTB
S/UNI®-JET Data Sheet Released
Description
PM7346 S/UNI-JET Aphysical layer processor with integrated DS3, framers. supports PLCP sublayer DS1, DS3, processing Acell delineation. S/UNI-JET contains: Integral framer that provides framing error accumulation accordance with ANSI T1.107, T1.107a. Integral framer that provide framing accordance with ITU-T Recommendations G.832 G.751. Integral framer that provide framing accordance with ITU-T Recommendation G.704 I.432.
When configured various transmission system sublayer processing, S/UNI-JET accepts outputs appropriate type bipolar unipolar signals described Table
Table Transmission System Sublayer Processing Acceptance Output Transmission System Sublayer Processing
DS1, Other transmission systems
Acceptance Output
Accepts outputs both digital B3ZS-encoded bipolar unipolar signals compatible with C-bit parity applications. Accepts outputs both HDB3-encoded bipolar unipolar signals compatible with G.751 G.832 applications. Accepts outputs both B8ZS-encoded bipolar unipolar signals compliant with G.704 6.312 Mbit/s applications. Accepts outputs outputs unipolar signals with appropriate clock frame pulse signals physical sublayer processing. Provides generic interface physical sublayer processing.
receive direction, S/UNI-JET frames signals with maximum average reframe time detects line code violations (LCV), loss signal (LOS), framing errors, parity errors, path parity errors, alarm indication signals (AIS), receive failure (FERF), idle code. overhead bits extracted presented serial outputs. When C-bit parity mode, Path Maintenance Data Link (PMDL) Alarm Control (FEAC) channels extracted. HDLC receivers provided PMDL support. Valid bit-oriented codes FEAC channels also detected available through microprocessor port.
Table Summary Receive Detection Features Transmission System Sublayer Processing
Transmit Receive
Receive Receive
Detected Features
LCV, LOS, framing errors, parity errors, path parity errors, AIS, FERF, idle code LCV, LOS, framing errors, AIS,
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Transmission System Sublayer Processing
Transmit Receive
Receive
Detected Features
LCV, LOS, LOF, framing errors, physical layer AIS, payload AIS, CRC-5 errors, Remote Alarm,
receive direction, S/UNI-JET frames G.751 G.832 signals with maximum average reframe times G.751 frames G.832 frames. LCVs, LOS, framing errors, AIS, remote alarm indication (RAI) detected. Further, when processing G.832 formatted data, parity errors, receive failure, block errors also detected; Trail Trace message extracted made available through microprocessor port. HDLC receivers provided either G.832 Network Requirement G.832 General Purpose Data Link support. receive direction, S/UNI-JET frames G.704 6.312 signals with maximum average reframe time 5.07 alternate framing algorithm that uses CRC-5 bits rule 99.9% static mimic framing patterns available with maximum average reframe time 10.22 when operating with error rate. alternate framing algorithm selected CRC_REFR J2-FRMR Configuration Register. LCV, LOS, loss frame (LOF), framing errors, physical layer AIS, payload AIS, CRC-5 errors, Remote Alarm, detected. HDLC receivers provided Data Link support. Error event accumulation also provided S/UNI-JET. Framing errors, LCV, parity errors, path parity errors, block errors (FEBE) accumulated, when appropriate, saturating counters DS3, frames. detection DS3, provided recommended ITU-T G.783 with integration times 1ms, 2ms, 3ms. transmit direction, S/UNI-JET inserts framing, bits. When enabled C-bit parity operation, bit-oriented code transmitters HDLC transmitters provided insertion FEAC channels PMDL appropriate overhead bits. inserted using internal register bits other status signals such idle signal inserted when enabled internal register bits. When operation selected, C-bit Parity (the first C-bit first sub-frame) forced toggle that downstream equipment will confuse M23-formatted stream with stuck-at C-bits C-bit parity application. transmit direction, S/UNI-JET inserts framing either G.832 G.751 format. When enabled G.832 operation, HDLC transmitter provided that Network Requirement General Purpose Data Link inserted into appropriate overhead bits. other status signals inserted internal register bits. transmit direction, S/UNI-JET inserts 6.312 Mbit/s G.704 framing. HDLC transmitters provided Data Links inserted. CRC-5 check bits calculated inserted into multiframe. External pins provided that overhead bits within frame overwritten. S/UNI-JET also supports diagnostic options that allow insert, when appropriate, transmit framing format, parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, LCV, all-zeros, AIS, RAIs, Remote Alarms.
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S/UNI-JET provides cell delineation Acells using PLCP framing format, using header check sequence octet Acell header specified ITU-T Recommendation I.432. DS1, DS3, E3-based PLCP frame formats processed. Non-PLCP-based cell delineation done with either bit, nibble, byte-wide search algorithms depending line interface used. interface consistent with generic physical interface defined ITU-T Recommendation I.432 provided arbitrary rates Mbit/s. This interface used layer support transmission systems that have associated PLCP sublayer, provide efficient means directly mapping Acells existing transmission system formats (such DS1). PLCP receive direction, framing, path overhead extraction, cell extraction provided. BIP-8 error events, frame octet error events, FEBE events accumulated. PLCP transmit direction, S/UNI-JET provides overhead insertion using inputs internal registers, nibble byte stuffing, automatic BIP-8 octet generation insertion, automatic FEBE insertion. Diagnostic features BIP-8 error, framing error FEBE insertion also supported. cell receive path, idle cells dropped according programmable filter. default, incoming cells with single errors corrected written FIFO buffer. Optionally, cells dropped upon detection error. Cell delineation optionally disabled allow cells pass, regardless cell delineation status. Acell payloads optionally descrambled. Acell headers optionally descrambled (for with packets). Assigned cells containing detectable errors written FIFO buffer. Cell data read from FIFO using synchronous 8-bit wide 16-bit wide SCI-PHY Utopia Level 2-compatible interface. Cell data parity also provided. Counts error-free assigned cells, cells containing errors accumulated independently performance monitoring purposes. cell transmit path, cell data written FIFO buffer using synchronous 8-bit wide 16-bit wide SCI-PHYcompatible interface. Cell data parity also examined errors. Idle cells automatically inserted when FIFO contains less than full cell. generation, cell payload scrambling, cell header scrambling (for with packets) optionally provided. Counts transmitted cells accumulated performance monitoring purposes. Both receive transmit cell FIFOs provide buffering four cells. FIFOs provide rate matching interface between higher layer Aentity S/UNI-JET. S/UNI-JET configured, controlled, monitored generic 8-bit microprocessor through which internal registers accessed. sources interrupts identified, acknowledged, masked with this interface. S/UNI-JET requires software initialization sequence order guarantee proper device operation long term reliability. Please refer Section 13.1 this document details program this sequence.
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Diagram
S/UNI-JET packaged 256-pin SBGA package with body size pitch 1.27
Quadrant A11/A20 K11/K20
TDAT[6] TDAT[2] TADR[2] TENB D[5] D[4] A[0] D[6] D[3] A[3] A[2] A[1] D[7] A[7] A[6] A[5] A[4] TDATI[10] TDATI[14] D[1] TDATI[9] TDATI[7] TDAT[5] TDAT[1] DTCA TDATI[13] D[0]
TDATI[11] TDATI[15] D[2] TDAT[8] TDAT[12]
TDAT[3] TDAT[4] TFCLK TDAT[0]
TADR[0] TADR[1] TSOC BIAS TPRTY
Bottom View (Top Left)
PHY_ADR[2]
Quadrant A1/A10 K1/K10
A[9] A[8] A[10] RSTB INTB TRSTB TPOS/ TDATO RPOS/ RDATI TOHM/ TNEG TCLK RLCV/ RNEG/ ROHM RCLK
BIAS
TOHFP
Bottom View (Top Right)
TOHINS
TOHCLK
ROHFP
ROHCLK
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Quadrant L11/L20 Y11/Y20
DRCA RSOC RADR[1] RDAT[13] RDAT[9] BIAS RDAT[6] RDAT[2] TPOHCLK REF8KO/ RPOHFP/ RFPO/ RMFPO PHY_ADR[1] PHY_ADR[0] ATMB RFCLK RDAT[15] RDAT[11] RADR[2] RDAT[14] RDAT[10] RENB RADR[0] RPRTY RDAT[12] RDAT[8]
Bottom View (Bottom Left)
RDAT[7] RDAT[5]
RDAT[3] RDAT[1]
TICLK
TPOHINS
RPOH/ ROVRHD
TIOHM/ TPOHFP/ RPOHCLK/ TFPO/ RSCLK/ TFPI/ RGAPCLK TMFPI TMFPO/ TGAPCLK/ TCELL TDATI/ TPOH LCD/ RDATO
RDAT[4]
RDAT[0]
Quadrant L1/L10 Y1/Y10
BIAS REF8KI
Bottom View (Bottom Right)
FRMSTAT
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Description
Name
TPOS
Type
Output
Function
Transmit Digital Positive Pulse (TPOS) contains positive pulses transmitted B3ZS-encoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail output format selected. Transmit Data (TDATO) contains transmit data stream when single-rail (unipolar) output format enabled when non-DS3/E3/J2 based transmission system selected. TPOS/TDATO function selection controlled TFRM[1:0] TUNI bits S/UNI-JET Transmit Configuration Register. Output signal polarity control provided TPOSINV S/UNI-JET Transmit Configuration Register. Both TPOS TDATO updated falling edge TCLK default, configured update rising edge TCLK through TCLKINV S/UNI-JET Transmit Configuration Register. Also, both TPOS TDATO updated rising edge TICLK, enabled TICLK S/UNI-JET Transmit Configuration Register.
TDATO
TNEG
Output
Transmit Digital Negative Pulse (TNEG) contains negative pulses transmitted B3ZS-encoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail output format selected. Transmit Overhead Mask (TOHM) indicates position overhead bits (non-payload bits) transmission system stream aligned with TDATO. TOHM indicates location M-frame boundary DS3, position frame boundary position multi-frame boundary when single-rail (unipolar) input format enabled. When PLCP formatted signal transmitted, TOHM logic once transmission frame, indicates frame alignment. When non-PLCP, non-DS3, non-E3, non-J2 based signal transmitted, TOHM delayed version TIOHM input, indicates position each overhead transmission frame. TOHM updated falling edge TCLK. TNEG/TOHM function selection controlled TFRM[1:0] TUNI bits S/UNI-JET Transmit Configuration Register. Output signal polarity control provided TNEGINV S/UNI-JET Transmit Configuration Register.
TOHM
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Name
Type
Function
default, both TNEG TOHM updated falling edge TCLK enabled update rising edge TCLK. This sampling controlled TCLKINV S/UNI-JET Transmit Configuration Register. Also, both TNEG TOHM updated rising edge TICLK, enabled TICLK S/UNI-JET Transmit Configuration Register.
TCLK
Output
Transmit Output Clock (TCLK) provides transmit direction timing. TCLK buffered version TICLK enabled update TPOS/TDATO TNEG/TOHM outputs rising falling edge. Receive Digital Positive Pulse (RPOS) contains positive pulses received B3ZS-encoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail input format selected. Receive Data (RDATI) contains data stream when single-rail (unipolar) input format enabled when non-DS3/E3/J2 based transmission system being processed (for example, RDATI contain stream). RPOS/RDATI function selection controlled RFRM[1:0] bits S/UNI-JET Configuration Register bits FRMR, FRMR, FRMR Configuration Register. Both RPOS RDATI sampled rising edge RCLK default, enabled sampled falling edge RCLK. This sampling controlled RCLKINV S/UNI-JET Receive Configuration Register. Note: Signal polarity control provided RPOSINV S/UNI-JET Receive Configuration Register.
RPOS
Input
RDATI
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Name
RNEG
Type
Input
Function
Receive Digital Negative Pulse (RNEG) contains negative pulses received B3ZS encoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail input format selected. Receive (RLCV) contains indications when single-rail (unipolar) input format enabled DS3, applications. Each represented RCLK period-wide pulse. When PLCP Adirect-mapped signal received, Receive Overhead Mask (ROHM) pulsed once transmission frame, indicates frame alignment relative RDATI data stream. When alternate frame-based signal received, ROHM indicates position each overhead transmission frame. RNEG/RLCV/ROHM function selection controlled RFRM[1:0] bits S/UNI-JET Receive Configuration Register, bits FRMR, FRMR, FRMR Configuration Register, PLCPEN bits SPLR Configuration Register. RNEG, RLCV, ROHM sampled rising edge RCLK default, enabled sampled falling edge RCLK. This sampling controlled RCLKINV S/UNI-JET Receive Configuration Register. Note: Signal polarity control provided RNEGINV S/UNI-JET Receive Configuration Register.
RLCV
ROHM
RCLK
Input
Receive Clock (RCLK) provides receive direction timing. RCLK externally recovered transmission system baud rate clock that samples RPOS/RDATI RNEG/RLCV/ROHM inputs rising falling edge. Transmit DS3/E3/J2 Overhead Insertion (TOHINS) controls insertion DS3, overhead bits from input. When TOHINS high, associated overhead stream inserted transmitted DS3, frame. When TOHINS low, DS3, overhead generated inserted internally. TOHINS sampled rising edge TOHCLK. TOHINS logic one, input precedence over internal datalink transmitter, internal register setting.
TOHINS
Input
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Name
Type
Input
Function
When configured operation, Transmit DS3/E3/J2 Overhead Data (TOH) contains overhead bits that inserted transmit stream. When configured G.832 operation, contains overhead bytes (FA1, FA2, mask, that inserted transmit G.832 stream. When configured G.751 operation, contains overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) that inserted transmit G.751 stream. When configured operation, contains overhead bits (TS97, TS98, Framing, X1-3, E1-5) that inserted transmit stream. TOHINS logic one, input precedence over internal datalink transmitter, other internal register setting. sampled rising edge TOHCLK.
TOHFP
Output
Transmit DS3/E3/J2 Overhead Frame Position (TOHFP) used align individual overhead bits transmit overhead data stream, TOH, Mframe frame. DS3, TOHFP high during overhead position stream. G.832 TOHFP high during first byte. G.751 TOHFP high during overhead position stream. TOHFP high during first timeslot first frame 4-frame multiframe). TOHFP updated falling edge TOHCLK.
TOHCLK
Output
Transmit DS3/E3/J2 Overhead Clock (TOHCLK) active when DS3, stream being processed. TOHCLK nominally clock DS3, 1.072 clock G.832 1.074 clock G.751 gapped 6.312 clock with average frequency TOHFP updated falling edge TOHCLK. TOH, TOHINS sampled rising edge TOHCLK.
REF8KI
Input
PLCP frame rate locked external reference applied Reference Input (REF8KI). internal phase-frequency detector compares transmit PLCP frame rate with externally applied reference adjusts PLCP frame rate. REF8KI input must transition high once every correct operation. REF8KI input treated asynchronous signal must "glitch-free". LOOPT register logic one, PLCP frame rate locked RPOHFP signal instead REF8KI input.
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S/UNI®-JET Data Sheet Released
Name
TPOHINS
Type
Input
Function
Transmit Path Overhead Insertion (TPOHINS) controls insertion PLCP overhead octets TPOH input. When TPOHINS logic one, associated overhead TPOH stream inserted transmit PLCP frame. When TPOHINS logic zero, PLCP path overhead generated inserted internally. TPOHINS sampled rising edge TPOHCLK. Note: When operating G.751 PLCP mode, bits octet should manipulated.
TPOH
Input
Transmit PLCP Overhead Data (TPOH) valid when FRMRONLY S/UNI-JET Configuration Register logic zero. TPOH contains PLCP path overhead octets (Zn, which inserted transmit PLCP frame. octet data TPOH shifted order from most significant (bit least significant (bit TPOH sampled rising edge TPOHCLK. Framer Transmit Data (TDATI) contains serial data transmitted when S/UNI-JET configured DS3, framer device non-Aapplications setting FRMRONLY S/UNIJET Configuration Register. TDATI sampled rising edge TICLK TXGAPEN register S/UNI-JET Configuration Register logic zero. TXGAPEN logic one, then TDATI sampled falling edge TGAPCLK.
TDATI
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S/UNI®-JET Data Sheet Released
Name
TPOHFP
Type
Output
Function
Transmit Path Overhead Frame Position (TPOHFP) valid when FRMRONLY S/UNI-JET Configuration Register logic zero. TPOHFP output locates individual PLCP path overhead bits transmit overhead data stream, TPOH. TPOHFP logic while (the most significant bit) path user channel octet (F1) present TPOH stream. TPOHFP updated falling edge TPOHCLK. Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO) valid when S/UNI-JET configured DS3, framer non-Aapplications setting FRMRONLY S/UNIJET Configuration Register logic TXGAPEN S/UNI-JET Configuration Register logic zero. TFPO pulses high every clock cycles when configured DS3, giving free-running mark overhead bits frame. TFPO pulses high every 1536 clock cycles when configured G.751 giving free-running reference G.751 indication. TFPO pulses high every 4296 clock cycles when configured G.832 giving free-running reference G.832 frame indication. TFPO pulses high every clock cycles when configured giving free-running reference frame indication.
TFPO
TMFPO
TMFPO pulses high every 4760 clock cycles when configured DS3, giving free-running reference M-frame indication. TMFPO pulses high every 3156 clock cycles when configured giving free-running reference multi-frame indication. TMFPO behaves same TFPO applications. TFPO TMFPO updated rising edge TICLK RCLK loop-timed. Framer Gapped Transmit Clock (TGAPCLK) valid when S/UNI-JET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-JET Configuration Register TXGAPEN S/UNI-JET Configuration Register. TGAPCLK derived from transmit reference clock TICLK from receive clock loop-timed. overhead (gapped) positions generated internal device. TGAPCLK held high during overhead positions. This clock useful interfacing devices which source payload data only. TGAPCLK used sample TDATI.
TGAPCLK
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S/UNI®-JET Data Sheet Released
Name
TCELL
Type
Function
Transmit Cell Indication (TCELL) valid when TCELL S/UNI-JET Miscellaneous Register set. TCELL pulses once every cell (idle assigned) transmitted. TCELL updated using timing derived from transmit input clock (TICLK), active minimum TICLK periods RCLK periods looptimed).
TPOHCLK
Output
Transmit PLCP Overhead Clock (TPOHCLK) active when PLCP processing enabled. TPOHCLK nominally 26.7 clock PLCP frame, clock PLCP frame, 33.7 clock based PLCP frame, clock G.751 based PLCP frame. TPOHFP updated falling edge TPOHCLK. TPOH TPOHINS sampled rising edge TPOHCLK.
TIOHM
Input
Transmit Input Overhead Mask (TIOHM) valid only FRMRONLY S/UNI-JET Configuration Register logic zero. TIOHM indicates position overhead bits when configured DS1, DS3, transmission system streams. TIOHM delayed internally produce TOHM output. When configured operation over DS1, DS3, transmission system sublayer, TIOHM required, should logic zero. When configured other transmission systems, TIOHM logic each overhead position. TIOHM logic zero transmission system does contain overhead bits. TIOHM sampled rising edge TICLK. Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI) valid when S/UNI-JET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-JET Configuration Register logic one.
TFPI
TFPI indicates position overhead bits each M-subframe, first each G.751 G.832 frame, first framing each frame. TFPI required pulse every frame boundary modes. TMFPI indicates position first each M-frame, first each frame, first framing each multiframe. TMFPI required pulse every multiframe boundary. TFPI/TMFPI sampled rising edge TICLK.
TMFPI
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Name
TICLK
Type
Input
Function
Transmit Input Clock (TICLK) provides transmit direction timing. TICLK externally generated transmission system baud rate clock. internally buffered produce transmit clock output, TCLK, enabled update TPOS/TDATO TNEG/TOHM outputs TICLK rising edge. TICLK maximum frequency MHz. Receive DS3/E3/J2 Overhead Frame Position (ROHFP) locates individual overhead bits received overhead data stream, ROH. ROHFP high during overhead position stream when processing stream. ROHFP high during first byte when processing G.832 stream. ROHFP high during overhead position when processing G.751 stream. ROHFP high during first Timeslot first frame 4-frame multiframe when processing stream. ROHFP updated falling edge ROHCLK.
ROHFP
Output
Output
Receive DS3/E3/J2 Overhead Data (ROH) contains overhead bits extracted from received stream. also contains overhead bytes (FA1, FA2, extracted from received G.832 stream, overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) extracted from received G.751 stream, overhead bits (Framing, X1-3, E1-5) extracted from received stream. updated falling edge ROHCLK. Receive DS3/E3/J2 Overhead Clock (ROHCLK) active when DS3, stream being processed. ROHCLK nominally clock when processing DS3, 1.072 clock when processing G.832 1.074 clock when processing G.751 gapped 6.312 clock with average frequency ROHFP updated falling edge ROHCLK.
ROHCLK
Output
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S/UNI®-JET Data Sheet Released
Name
REF8KO
Type
Output
Function
Reference 8kHz Output (REF8KO) 8kHz reference derived from receive clock (RCLK). freerunning divide-down counter used generate REF8KO will "glitch" reframe actions. REF8KO will pulse high approximately RCLK cycle every REF8KO should treated "glitch-free" asynchronous signal. Receive PLCP Overhead Frame Position (RPOHFP) locates individual PLCP path overhead bits receive overhead data stream, RPOH. RPOHFP logic while (the most significant bit) path user channel octet (F1) present RPOH stream. RPOHFP updated falling edge RPOHCLK. RPOHFP available when PLCPEN register logic SPLR Configuration Register.
RPOHFP
RFPO RMFPO
Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO) valid when S/UNI-JET configured framer only mode. 8KREFO must logic zero S/UNI-JET Configuration Register. RFPO aligned RDATO indicates position first each M-subframe, first each G.751 G.832 frame, first framing each frame RMFPO aligned RDATO indicates position first each M-frame, first each G.751 G.832 multiframe, first framing each multiframe. RFPO/RMFPO updated either falling rising edge RSCLK depending setting RSCLKR S/UNI-JET Receive Configuration Register.
RPOH
Output
Receive PLCP Overhead Data (RPOH) contains PLCP path overhead octets (Zn, extracted from received PLCP frame when PLCP layer in-frame. When PLCP layer state, RPOH forced ones. octet data RPOH shifted order from most significant (bit least significant (bit RPOH updated falling edge RPOHCLK. Framer Receive Overhead Indication (ROVRHD) valid when S/UNI-JET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-JET Configuration Register. ROVRHD will high whenever data RDATO corresponds overhead position. ROVRHD updated either falling rising edge RSCLK depending setting RSCLKR S/UNI-JET Receive Configuration Register.
ROVRHD
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Name
RPOHCLK
Type
Output
Function
Receive PLCP Overhead Clock (RPOHCLK) active when PLCP processing enabled. frequency this signal depends selected PLCP format. RPOHCLK nominally 26.7 clock PLCP frame, clock PLCP frame, 33.7 clock based PLCP frame, clock G.751 based PLCP frame. RPOHFP RPOH updated falling edge RPOHCLK.
RSCLK
Framer Recovered Clock (RSCLK) valid when S/UNI-JET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-JET Configuration Register. RSCLK recovered clock timing reference RDATO, RFPO/RMFPO, ROVRHD.
RGAPCLK
Framer Recovered Gapped Clock (RGAPCLK) valid when S/UNI-JET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-JET Configuration Register RXGAPEN S/UNI-JET Configuration Register. RGAPCLK recovered clock timing reference RDATO. RGAPCLK held high positions which correspond overhead.
Output
Loss Cell Delineation (LCD) active high signal which asserted while Acell processor detected Loss Cell Delineation defect. FRMRONLY S/UNI-JET Configuration Register must logic zero valid. Framer Receive Data (RDATO) valid when S/UNI-JET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-JET Configuration Register. RDATO received data aligned RFPO/RMFPO ROVRHD. RDATO updated active edge RSCLKR register bit) RSCLK RGAPCLK.
RDATO
FRMSTAT
Output
Framer Status (FRMSTAT) active high signal that configured show when DS3, PLCP framers have detected certain conditions. FRMSTAT output programmed STATSEL[2:0] bits S/UNI-JET Configuration Register indicate: E3/DS3 extended LOF, E3/DS3 LOF, PLCP LOF, PLCP OOF, AIS, LOS, Idle. FRMSTAT should treated "glitch-free" asynchronous signal. AInterface Width Selection (ATM8) input determines whether S/UNI-JET works with 8-bit wide interface (RDAT[7:0] TDAT[7:0]) 16-bit wide interface (RDAT[15:0] TDAT[15:0]). ATM8 logic one, then 8-bit wide interface chosen. ATM8 logic zero, then 16-bit wide interface chosen.
ATM8
Input
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Name
TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TPRTY
Type
Input
Function
Transmit Cell Data (TDAT[15:0]) carries Acell octets that written transmit FIFO. TDAT[15:0] sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-JET been selected TADR[2:0] inputs. S/UNI-JET configured operate with 8bit wide 16-bit wide Adata interface ATM8 input pin. When configured 8-bit wide interface, TDAT[15:8] used should tied ground.
Input
Transmit Parity (TPRTY) signal indicates parity TDAT[15:0] TDAT[7:0] bus. configured 8-bit (via ATM8 input pin), then parity calculated over TDAT[7:0]. configured 16-bit bus, then parity calculated over TDAT[15:0]. parity error indicated status maskable interrupt. Cells with parity errors inserted transmit stream, TPRTY input unused. even parity selection made using TPTYP register bit. TPRTY sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-JET been selected TADR[2:0] inputs.
TSOC
Input
Transmit Start Cell (TSOC) signal marks start cell TDAT bus. When TSOC high, first word cell structure present TDAT bus. necessary TSOC present each cell. interrupt generated TSOC high during word other than first word cell structure. TSOC sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-JET been selected TADR[2:0] inputs.
TENB
Input
Transmit Multi-PHY Write Enable (TENB) signal active input which used along with TADR[2:0] inputs initiate writes transmit FIFO. When sampled using rising edge TFCLK, word TDAT written into transmit FIFO selected TADR[2:0] address bus. When sampled high using rising edge TFCLK, write performed, TADR[2:0] address latched identify transmit FIFO accessed. complete 53-octet cell must written transmit FIFO before inserted into transmit stream. Idle cells inserted when complete cell available.
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Name
TADR[2] TADR[1] TADR[0]
Type
Input
Function
Transmit Address (TADR[2:0]) used device selection device polling accordance with Utopia Level standard. When TADR[2:0] same value PHY_ADR[2:0] inputs than transmit interface this S/UNI-JET either being selected polled. Note: null-PHY address invalid address cannot used select S/UNI-JET. TADR[2:0] sampled rising edge TFCLK.
Output
Transmit Multi-PHY Cell Available (TCA) signal indicates when cell available transmit FIFO device selected TADR[2:0]. When high, indicates that corresponding transmit FIFO full complete cell written. When goes low, configured indicate either that corresponding transmit FIFO near full that corresponding transmit FIFO full. will transition rising edge TFCLK which samples Payload byte (TCALEVEL0=0) (TCALEVEL0=1) 8-bit interface (ATM8=1), rising edge TFCLK which samples Payload word (TCALEVEL0=0) (TCALEVEL0=1) 16-bit interface (ATM8=0) device being polled same selected device. reduce FIFO latency, FIFO depth which indicates "full" one, two, three, four cells. Note: Regardless what fill level indicate "full" transmit cell processor store four complete cells. tri-stated when either null-PHY address (7H) address matching address space PHY_ADR[2:0] latched TFCLK) from TADR[2:0] inputs. polarity (with respect description above) inverted when TCAINV register logic one.
TFCLK
Input
Transmit FIFO Write Clock (TFCLK) used write Acells four-cell transmit FIFOs. TFCLK cycles lower instantaneous rate.
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Name
DTCA
Type
Output
Function
Direct Access Transmit Cell Available (DTCA) output signals indicate when cell available transmit FIFO. When high, DTCA indicates that corresponding transmit FIFO full complete cell written. DTCA configured indicate either that corresponding transmit FIFO near full accept more than four writes that corresponding transmit FIFO full. DTCA will thus transition rising edge TFCLK which samples Payload byte (TCALEVEL0=0) (TCALEVEL0=1) 8-bit interface (ATM8=1), rising edge TFCLK which samples Payload word (TCALEVEL0=0) (TCALEVEL0=1) 16-bit interface (ATM8=0). reduce FIFO latency, FIFO depth which DTCA indicates "full" one, two, three four cells. Note: Regardless what fill level DTCA indicate "full" transmit cell processor store four complete cells. polarity DTCA (with respect description above) inverted when TCAINV register logic one. DTCA outputs used support Utopia Direct Access mode.
RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0]
Output
Receive Cell Data (RDAT[15:0]) carries Acell octets that read from receive AFIFO selected RADR[2:0]. RDAT[15:0] tri-stated when RENB high. RDAT[15:0] updated rising edge RFCLK. S/UNI-JET configured operate with 8bit wide 16-bit wide Adata interface ATM8 input pin. RDAT[15:8] will remain tri-stated ATM8 logic one. RDAT[15:0] tri-stated when either null-PHY address (7H) address matching address space PHY_ADR[2:0] latched from RADR[2:0] inputs when RENB high.
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Name
RPRTY
Type
Output
Function
Receive Parity (RPRTY) signal indicates parity RDAT bus. S/UNI-JET configured operate with 8bit wide 16-bit wide Adata interface ATM8 input pin. 8-bit mode, RPRTY reflects parity RDAT[7:0]. 16-bit mode, RPRTY reflects parity RDAT[15:0]. even parity selection made using RXPTYP register bit. RPRTY tri-stated when either null-PHY address (7H) address matching address space PHY_ADR[2:0] latched from RADR[2:0] inputs when RENB high.
RSOC
Output
Receive Start Cell (RSOC) signal marks start cell RDAT bus. RSOC marks start cell RDAT bus. RSOC tri-stated when either null-PHY address (7H) address matching address space PHY_ADR[2:0] latched from RADR[2:0] inputs when RENB high.
RENB
Input
Receive Multi-PHY Read Enable (RENB) signal used initiate reads from receive FIFO. When sampled using rising edge RFCLK, byte read available) from receive FIFO selected RADR[2:0] address output RDAT bus. When sampled high using rising edge RFCLK, read performed RDAT[15:0], RPRTY, RSOC tri-stated, address RADR[2:0] latched select device port next AFIFO access. RENB must operate conjunction with RFCLK access FIFOs high enough rate prevent FIFO overflows. Alayer device de-assert RENB anytime unable accept another byte.
RADR[2] RADR[1] RADR[0]
Input
Receive Address (RADR[2:0])] used device selection device polling accordance with Utopia Level standard. When RADR[2:0] same value PHY_ADR[2:0] inputs than receive interface this S/UNI-JET either being selected polled. Note: null address invalid address cannot used select S/UNI-JET. RADR[2:0] sampled rising edge TFCLK.
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Name
Type
Output
Function
Receive Multi-PHY Cell Available (RCA) signal indicates when cell available receive FIFO device selected RADR[2:0]. configured de-asserted when either zero four bytes remain selected/addressed FIFO. will thus transition rising edge RFCLK after Payload byte (RCALEVEL0=1) (RCALEVEL0=0) output 8-bit interface (ATM8=1), after Payload word (RCALEVEL0=1) (RCALEVEL0=0) output 16-bit interface (ATM8=0) being polled same selected device. tri-stated when either null-PHY address (7H) address matching address space PHY_ADR[2:0] latched RFCLK) from RADR[2:0] inputs. polarity (with respect description above) inverted when RCAINV register logic one.
RFCLK
Input
Receive FIFO Read Clock (RFCLK) signal used read Acells from receive FIFOs. RFCLK must cycle lower instantaneous rate, high enough rate avoid FIFO overflows. Direct Access Receive Cell Available (DRCA) output signals indicate when cell available receive FIFO. DRCA configured de-asserted when either zero four bytes remain FIFO. DRCA will thus transition rising edge RFCLK after Payload byte (RCALEVEL0=1) (RCALEVEL0=0) output 8-bit interface (ATM8=1), after Payload word (RCALEVEL0=1) (RCALEVEL0=0) output 16-bit interface (ATM8=0). DRCA outputs used support Utopia Direct Access mode.
DRCA
Output
PHY_ADR[2] PHY_ADR[1] PHY_ADR[0]
Input
Device Identification Address (PHY_ADR[2:0]) inputs represent address space which this S/UNI-JET occupies. When PHY_ADR[2:0] inputs match TADR[2:0] RADR[2:0] inputs, then this S/UNI-JET selected transmit receive Aaccess. Note: null-PHY address invalid address will select S/UNI-JET. S/UNI-JET used directly applications requiring fewer ports. Applications requiring more than ports require external decoding Utopia address avoid contention.
Input
Active Chip Select (CSB) signal must enable S/UNI-JET register accesses. used, (RDB determine register reads writes) then should tied inverted version RSTB.
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Name
Type
Input
Function
Active Write Strobe (WRB) signal pulsed enable S/UNI-JET register write access. D[7:0] clocked into addressed register rising edge while low. Active Read Enable (RDB) signal pulsed enable S/UNI-JET register read access. S/UNIJET drives D[7:0] with contents addressed register while both low. Bi-directional Data (D[7:0]) used during S/UNI-JET register read write accesses.
Input
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB
Input
Address (A[10:0]) selects specific registers during S/UNI-JET register accesses.
Input
Active Reset (RSTB) signal asynchronously reset S/UNI-JET. RSTB Schmitttrigger input with integral pull-up resistor. Address Latch Enable (ALE) active-high latches address A[10:0] when low. When high, internal address latches transparent. allows S/UNI-JET interface multiplexed address/data bus. integral pull-up resistor. Active Open-Drain Interrupt (INTB) signal goes when unmasked interrupt event detected internal interrupt sources. Note: INTB will remain until active, unmasked interrupt sources acknowledged their source. Test Clock (TCK) signal provides timing test operations that carried using IEEE P1149.1 test access port. Test Mode Select (TMS) signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Input (TDI) signal carries test data into S/UNI-JET IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor.
Input
INTB
Output
Input
Input
Input
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Name
Type
Output
Function
Test Data Output (TDO) signal carries test data S/UNI-JET IEEE P1149.1 test access port. updated falling edge TCK. tristate output which inactive except when scanning data progress. Active Test Reset (TRSTB) signal provides asynchronous S/UNI-JET test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull resistor. TRSTB must asserted during power sequence. Note: used, TRSTB must connected RSTB input.
TRSTB
Input
BIAS
Input
When tied +5V, Bias (BIAS) input used bias wells input pads that pads tolerate their inputs without forward biasing internal protection devices. When tied VDD, inputs bi-directional inputs will only tolerate input levels VDD. Power pins should connected welldecoupled +3.3V supply.
VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15] VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28] VDD[29] VDD[30] VDD[31] VDD[32]
Power
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Name
VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49]
Type
Ground
Function
Ground pins should connected GND.
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Name
VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] NC[1] NC[2] NC[3] NC[4] NC[5] NC[6] NC[7] NC[8] NC[9] NC[10] NC[11] NC[12] NC[13] NC[14] NC[15] NC[16] NC[17] NC[18] NC[19] NC[20] NC[21] NC[22] NC[23] NC[24] NC[25] NC[26] NC[27] NC[28] NC[29] NC[30] NC[31] NC[32] NC[33] NC[34] NC[35] NC[36] NC[37] NC[38] NC[39] NC[40] NC[41] NC[42] NC[43] NC[44]
Type
Ground
Function
Ground pins should connected GND.
Connect
These pins No-Connects
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Name
NC[45] NC[46] NC[47] NC[48] NC[49] NC[50] NC[51] NC[52] Notes
Type
Connect
Function
These pins No-Connects
S/UNI-JET inputs bi-directionals present minimum capacitive loading operate logic levels. S/UNI-JET outputs bi-directionals have least drive capability. data outputs, D[7:0], have drive capability. FIFO interface outputs, RDAT[15:0], RPRTY, RCA, DRCA, RSOC, TCA, DTCA, have drive capability. outputs TCLK, TPOS/TDATO, TNEG/TOHM, TPOHFP/TFPO/TMFPO/TGAPCLK, LCD/RDATO, RPOH/ROVRHD, RPOHCLK/RSCLK/RGAPCLK, REF8KO/RPOHFP/RFPO/RMFPO have drive capability. other outputs have drive capability. Inputs RSTB, ALE, TMS, TDI, TRSTB have internal pull-up resistors. RSTB, TRSTB, TMS, TDI, TCK, REF8KI, TFCLK, RFCLK, TICLK, RCLK schmitt trigger input pads. [59:1] ground pins internally connected together. Failure connect these pins externally cause malfunction damage S/UNI-JET. VDD[32:1] power pins internally connected together. Failure connect these pins externally cause malfunction damage device. These power supply connections must used must connect common +3.3 ground rail, appropriate. During power-up power-down, voltage BIAS must kept equal greater than voltage [32:1] pins, avoid damage device.
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Functional Description
S/UNI-JET contains following blocks: DS3, Framer DS3, Transmitter RBOC oriented code detector XBOC oriented code detector RDLC PMDL receiver TDPR PMDL transmitter PMON Performance monitor CPPM Cell PLCP performance monitor SPLR PLCP layer receiver SPLT SMDS PLCP Layer Transmitter ATMF Acell delineator PRGD Pseudo-random sequence generator/detector RXCP Receive cell processor TXCP Transmit cell processor RXFF Receive FIFO TXFF Transmit FIFO Trail trace buffer JTAG Test access port
10.1
Framer
Framer (T3-FRMR) Block integrates circuitry required decoding B3ZS-encoded signal framing resulting stream. This block directly compatible with C-bit parity applications. T3-FRMR decodes B3ZS-encoded signal provides indications (LCV). B3ZS decoding algorithm definition independently chosen through software. defect also detected B3ZS encoded streams. declared when inputs RPOS RNEG contain zeros consecutive RCLK cycles. removed when ones density RPOS and/or RNEG greater than RCLK cycles. framing algorithm simultaneously examines five F-bit candidates. When least discrepancy occurred each candidate, algorithm examines next five. When single F-bit candidate remains set, first supposed M-subframe examined M-frame alignment signal such M-bits, following pattern. M-bits correct three consecutive M-frames while discrepancies have occurred F-bit, framing declared out-of-frame (OOF) removed. During examination M-bits, X-bits P-bits ignored. algorithm gives maximum average reframe time
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While T3-FRMR synchronized M-frame, F-bit M-bit positions stream examined. defect detected when three F-bit errors eight consecutive F-bits observed selected M3O8 FRMR Configuration Register), when more M-bit errors detected three four consecutive Mframes. M-bit error criteria disabled MBDIS Framer Configuration Register. three eight consecutive F-bits ratio provides more robust operation, presence high error rate, than three consecutive F-bits ratio. Either criteria allows defect detected quickly when M-subframe alignment patterns optionally, when M-frame alignment pattern lost. Also while in-frame, LCV, M-bit F-bit framing errors, P-bit parity errors indicated. When C-bit parity mode enabled, both C-bit parity errors FEBEs indicated. These error indications, well excessive zeros indication, accumulated over second intervals with Performance Monitor (PMON). Note: framer off-line framer, indicating both COFA events. Even indicated, framer will continue indicating performance monitoring information based previous frame alignment. Three maintenance signals alarm condition, AIS, idle signal) detected T3-FRMR. maintenance detection algorithm uses simple integrator with slope that based occurrence "valid" M-frame intervals. alarm, M-frame said "valid" interval contains defect, defined occurrence event during that M-frame. IDLE, M-frame interval "valid" contains IDLE, defined occurrence less than discrepancies expected signal pattern (1010. AIS, 1100. IDLE) while valid frame alignment maintained. This discrepancy threshold ensures detection algorithms operate presence 10-3 error rate. AIS, expected pattern selected framed "1010" signal; framed arbitrary signal C-bits zero; framed "1010" signal C-bits zero; framed all-ones signal (with overhead bits ignored); unframed all-ones signal (with overhead bits equal ones). Each "valid" M-frame causes associated integration counter increment; "invalid" M-frames cause decrement. With "slow" detection option, RED, AIS, IDLE declared when respective counter saturates 127, which results detection time 13.5 With "fast" detection option, RED, AIS, IDLE declared when respective counter saturates which results detection time 2.23 that times maximum average reframe time. RED, AIS, IDLE removed when respective counter decrements zero. detection provided recommended ITU-T G.783 with programmable integration periods While integrating assert LOF, counter will integrate when framer asserts condition integrates down when framer de-asserts condition. Once asserted, framer must assert entire integration period before de-asserted.
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Valid X-bits extracted T3-FRMR provide indication receive failure (FERF). FERF defect detected extracted X-bits equal logic zero (X1=X2=0); defect removed extracted X-bits equal logic (X1=X2=1). X-bits equal, FERF status remains previous state. extracted FERF status buffered M-frames before being reported within FRMR Status Register. This buffer ensures better than 99.99% chance freezing FERF status correct value during occurrence OOF. When C-bit parity application enabled, both FEAC channel PMDL extracted. Codes FEAC channel detected Oriented Code Detector (RBOC). HDLC messages PMDL received Data Link Receiver (RDLC). T3-FRMR enabled automatically assert indication outgoing transmit stream upon detection combination LOS, RED, AIS. T3-FRMR also enabled automatically insert C-bit Parity FEBE upon detection receive C-bit parity error. T3-FRMR extracts entire overhead bits M-frame) using output, along with ROHCLK, ROHFP outputs. T3-FRMR configured generate interrupts error events status changes. sources interrupts masked acknowledged internal registers. Internal registers also used configure T3-FRMR. Access these registers generic microprocessor bus.
10.2
Framer
Framer (E3-FRMR) Block integrates circuitry required decoding HDB3-encoded signal framing resulting stream. E3-FRMR directly compatible with G.751 G.832 applications. E3-FRMR searches frame alignment incoming serial stream based either G.751 G.832 formats. G.751 format, E3-FRMR expects selected framing pattern error-free three consecutive frames before declaring INFRAME. G.832 format, E3-FRMR expects selected framing pattern error-free consecutive frames before declaring INFRAME. Once frame alignment established, incoming data continuously monitored framing errors byte interleaved parity errors G.832 format). While in-frame, E3-FRMR also extracts various overhead bytes processes them according framing format selected: G.832 format, E3-FRMR extracts: Trail Trace bytes outputs them serial stream further processing Trail Trace Buffer (TTB) block. FERF indicates alarm when FERF logic three five consecutive frames. FERF indication removed when FERF logic zero three five consecutive frames. FEBE outputs accumulation PMON.
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Payload Type bits buffers them that they read microprocessor. Timing Marker asserts Timing Marker indication when value extracted been same state three five consecutive frames. Network Operator byte presents serial stream further processing RDLC block when RNETOP S/UNI-JET Data Link FERF Control Register logic one. byte also brought ROH[x] output with associated clock ROHCLK[x]. eight bits Network Operator byte extracted presented overhead output and, optionally, presented RDLC. General Purpose Communication Channel byte presents RDLC when RNETOP S/UNI-JET Data Link FERF Control Register logic zero byte also brought ROH[x] output with associated clock ROHCLK[x].
G.751 mode, E3-FRMR extracts: (bit frame) indicates Remote Alarm when logic three five consecutive frames. Similarly, Remote Alarm removed when logic zero three five consecutive frames. National reserved (bit frame) presents serial stream further processing RDLC when RNETOP S/UNI-JET Data Link FERF Control Register logic zero. also brought ROH[x] output with associated clock ROHCLK[x]. Optionally, interrupt generated when National changes state.
Further, while in-frame, E3-FRMR indicates position overhead bits incoming digital stream ATMF/SPLR block. G.751 mode, tributary justification bits optionally identified either overhead payload payload mappings that take advantage full bandwidth. E3-FRMR declares alignment framing pattern error four consecutive frames. E3-FRMR "off-line" framer, where frame alignment indications, overhead indications, overhead processing continue based previous alignment. Once framer determined frame alignment, indication removed COFA indication declared alignment differs from previous alignment. E3-FRMR detects presence incoming data stream when less than eight zeros frame detected while framer G.832 mode, when less than five zeros frame detected while G.751 mode. This algorithm provides probability detecting presence 10-3 92.9% G.832 98.0% G.751. declared when marks have been received consecutive periods. deasserted after periods during which there sequence four consecutive zeros.
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detection provided recommended ITU-T G.783 with programmable integration periods While integrating assert LOF, counter will integrate when framer asserts condition integrates down when framer de-asserts condition. Once asserted, framer must assert entire integration period before de-asserted. E3-FRMR also enabled automatically assert RAI/FERF indication outgoing transmit stream upon detection combination LOS, AIS. E3-FRMR also enabled automatically insert G.832 FEBE upon detection receive BIP-8 errors.
10.3
Framer
J2-FRMR integrates circuitry decode unipolar B8ZS encoded signal frame resulting 6312 kbps stream. Having found frame, J2-FRMR extracts variety overhead datalink information from stream. format consists 789-bit frames, each long, consisting bytes payload, reserved bytes, five F-bits. frames grouped into 4-frame multiframes. multiframe format described Table
Table Multiframe Format
Notes TS96 byte interleaved payloads. TS97, TS98 reserved channels signaling. Frame Alignment Signal represented binary ones zeroes.
TS1[1:8] TS1[1:8] TS1[1:8] TS1[1:8]
761-768
TS96[1:8] TS96[1:8] TS96[1:8] TS96[1:8]
769-776
TS97[1:8] TS97[1:8] TS97[1:8] TS97[1:8]
777-784
TS98[1:8] TS98[1:8] TS98[1:8] TS98[1:8]
4-kHz datalink. spare bits, usually logic one. remote alarm bit, active high. e1.e5 represent CRC-5 check sequence. entire 3156-bit multiframe, including CRC-5 check sequence, should have remainder when divided
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J2-FRMR frames signal with average reframe time 5.07 alternate framing algorithm that uses CRC-5 check detect static mimic patterns also available. Once frame, J2-FRMR provides indications frame multiframe boundaries, marks overhead bits, x-bits, m-bits, reserved channels (TS97 TS98). Indications LOS, bipolar violations, excessive zeroes, change frame alignment, framing errors, errors provided, accumulated PMON (with exception change frame alignment). Maskable interrupts available alert microprocessor occurrence these events. addition marking x-bit values, J2-FRMR provides microprocessor access x-bits, will optionally generate interrupt when x-bits change state. mbits associated clock either extracted through RDLC through ROH[x] ROHCLK[x] output pins S/UNI-JET m-bits also presented RBOC detection generic bit-oriented codes. J2-FRMR detects status signals such Physical AIS, Payload AIS, m-bits, Remote (a-bit). also optionally generates interrupt when these status signals change. declared when marks have been received consecutive periods. cleared when either consecutive periods have passed without detection excessive zeros (meaning eight more consecutive zeros) required ITU-T G.775. declared when seven more consecutive multiframes with errored framing patterns received. cleared when three more consecutive multiframes with correct framing patterns received. Also available framing algorithms that take into account calculation. These framing algorithms described following section. Physical Layer declared when less zeros detected sequence 3156 bits. cleared when three more zeros detected sequence 3156 bits required ITU-T G.775. Payload detected when incoming payload less zeros sequence 3072 bits. cleared when three more zeros detected sequence 3072 bits. Note: J2-FRMR forced re-frame microprocessor control. Similarly, microprocessor disable J2-FRMR from reframing framing errors. configure J2-FRMR mask acknowledge sources interrupts through internal registers. These internal registers accessed from generic microprocessor bus.
10.3.1
Frame Find Algorithms
J2-FRMR searches frame alignment using algorithms, selected CRC_REFR J2-FRMR Configuration Register.
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When CRC_REFR logic zero, J2-FRMR uses only frame alignment sequence find frame, searching three consecutive correct frame alignment sequences. frame find block searches entire 9-bit sequence (spread over multiframes) same time, greatly reducing time required find frame alignment. framing process with CRCREFR cleared illustrated Figure
Figure Framing algorithm (CRC_REFR
Reset Fram
Slip
Fram Pattern Matched Mark multiframe alignment
Else
Fail
Confirm Fram Pattern next ultifram
Pass Fail
Confirm Fram Pattern next ultifram
Pass
Declare in-frame
Using this algorithm, J2-FRMR will average find frame 5.07 when starting search worst possible position, given 10-4 error rate static mimic patterns. When CRC_REFR logic one, addition requiring three consecutive correct framing patterns, J2-FRMR requires that first CRC-5 checks correct, reframe initiated. speed process, CRC-5 frame alignment checks concurrently, illustrated Figure
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Figure Framing Algorithm (CRC_REFR
Reset Fram
Slip
Fram Pattern Matched Mark multiframe alignment
Else
Fail
Confirm Fram Pattern next ultifram
Pass Fail
Check CRC-5 Sequence
Pass Fail
Confirm Fram Pattern next ultifram
Pass Fail
Check CRC-5 Sequence
Pass
Declare in-frame
Using this algorithm, J2-FRMR will find frame 10.22 average when starting search worst possible position, given 10-4 error rate static mimic patterns. algorithm will reject 99.90% mimic patterns. Further protection against mimic patterns available monitoring rate CRC-5 errors. Once frame alignment found, block sets indication low, indicates change frame alignment occurred). block declares alignment consecutive FASs have been received error. presence random 10-3 error rate frame loss criteria provides mean time falsely lose frame alignment 1.65 years. Frame Find Block forced initiate frame search time when REFRAME J2-FRMR configuration. Conversely, when FLOCK logic one, J2-FRMR will never declare search frame alignment excess framing errors.
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extended detection provided recommended ITU-T G.783 with programmable integration periods While integrating assert LOF, counter will integrate when framer asserts condition integrates down when framer deasserts condition. Once asserted, framer must assert entire integration period before de-asserted.
10.4
RBOC Bit-Oriented Code Detector
Note: Bit-Oriented Code Detector only used C-bit Parity mode. Bit-Oriented Code Detector (RBOC) Block detects presence possible bitoriented codes (BOCs) contained C-bit parity far-end alarm control (FEAC) channel datalink signal stream. 64th code ("111111") similar HDLC flag sequence ignored. BOCs received FEAC channel 16-bit sequences each consisting eight ones, zero, code bits, trailing zero ("111111110xxxxxx0"). BOCs validated when repeated least times. RBOC enabled declare code valid been observed eight times four five times, specified RBOC Configuration/Interrupt Enable Register. RBOC declares that code removed code sequences containing code values that different from detected code received moving window code periods. Valid BOCs indicated through RBOC Interrupt Status Register. bits all-ones ("111111") when valid code detected. RBOC programmed generate interrupt when detected code been validated when code removed.
10.5
RDLC PMDL Receiver
RDLC microprocessor peripheral used receive LAPD/HDLC frames serial HDLC stream that provides data clock information such C-bit parity Path Maintenance Data Link, G.832 Network Requirement byte General Purpose data link (selectable using RNETOP S/UNI-JET Data Link FERF/RAI Control Register), G.751 Network bit, m-bit Data Link. RDLC detects change from flag characters first byte data, removes stuffed zeros incoming data stream, receives packet data, calculates CRC-CCITT frame check sequence (FCS). address matching mode, only those packets whose first data byte matches programmable bytes universal address (all ones) stored FIFO. least significant bits address comparison masked LAPD SAPI matching. Received data placed into 128-level FIFO buffer. interrupt generated when programmable number bytes stored FIFO buffer. Other sources interrupt detection terminating flag sequence, abort sequence, FIFO buffer overrun.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-1990267, Issue
S/UNI®-JET Data Sheet Released
Status Register contains bits that indicate overrun empty FIFO status, interrupt status, occurrence first flag message bytes written into FIFO. Status Register also indicates abort, flag, end-of-message status data just read from FIFO. message, Status Register indicates status packet contained non-integer number bytes.
10.6
PMON Performance Monitor Accumulator
PMON Block interfaces directly with either Framer (T3-FRMR) accumulate events, parity error (PERR) events, path parity error (CPERR) events, FEBE events, excess zeros (EXZS), framing error (FERR) events using saturating counters: Framer (E3-FRMR) accumulate LCV, PERR G.832 mode), FEBE FERR events, Framer (J2-FRMR) accumulate LCVs, errors PERR counter), Framing errors (FERR), excess zeros (EXZS).
PMON stops accumulating error signals from DS3, Framers once frame synchronization lost. When accumulation interval signaled write PMON Register address space write S/UNI-JET Identification, Master Reset, Global Monitor Update Register, PMON transfers current counter values into microprocessor-accessible holding registers resets counters begin collecting error events next interval. counters reset such manner that error events occurring during reset period missed. When counter data transferred into holding registers, interrupt will generated been enabled. holding registers have been read since last interrupt, overrun status set. Also provided register indicate changes PMON counters since last accumulation interval.
10.7
SPLR PLCP Layer Receiver
PLCP Layer Receiver (SPLR) Block integrates circuitry support DS1, DS3, G.751 PLCP frame processing. SPLR provides framing PLCP based transmission formats. SPLR frames DS1, DS3, G.751 based PLCP frames with maximum average reframe times respectively. Framing declared (OOF removed) upon finding valid, consecutive sets framing octets valid sequential path overhead identifier (POHID) octets. While framed, POHID octets examined. declared when error detected both octets when consecutive POHID octets found error. declared when state persists more than DS1, DS3, G.751 PLCP formats respectively. events intermittent, counter decremented rate 1/12 (DS3 PLCP), 1/10 (E1, PLCP) 1/9(G.751 PLCP) incrementing rate. thus removed when in-frame state persists more than signal, signal, signal, G.751 signal. When declared, PLCP reframe initiated.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-1990267, Issue
S/UNI®-JET Data Sheet Released
When frame, SPLR extracts path overhead octets outputs them serially output RPOH, along with RPOHCLK RPOHFP outputs. Framing octet errors path overhead identifier octet errors indicated frame errors. interleaved parity errors FEBEs indicated. yellow signal extracted accumulated indicate yellow alarms. Yellow alarms declared when consecutive yellow signal bits logic one. removed when consecutive received yellow signal bits logic zero. octet examined maintain nibble alignment with incoming transmission system sublayer stream.
10.8
ATMF ACell Delineator
ACell Delineator (ATMF) Block integrates circuitry support HCS-based cell delineation non-PLCP based transmission formats. ATMF block accepts serial cell stream from upstream transmission system sublayer entity (such T3-FRMR, E3-FRMR, J2-FRMR Block) performs cell delineation locate cell boundaries. PLCP applications, Acell positions fixed relative PLCP frame, ATMF still performs cell delineation locate cell boundaries. Cell delineation process framing Acell boundaries using field found Acell header. CRC-8 calculation over first four octets Acell header. When performing delineation, correct calculations assumed indicate cell boundaries. ATMF performs sequential bit-by-bit, nibble-by-nibble (DS-3 direct mapped), byteby-byte direct-mapped) hunt correct sequence. This state referred HUNT state. When receiving serial cell stream from upstream transmission-system sublayer entity, bit, nibble, byte boundaries determined from location overhead. When correct found, ATMF locks particular cell boundary assumes PRESYNC state. This state verifies that previously detected pattern false indication. pattern false indication then incorrect should received within next DELTA cells. that point transition back HUNT state executed. incorrect found this PRESYNC period then transition SYNC state made. this state synchronization relinquished until ALPHA consecutive incorrect patterns found. such event transition made back HUNT state. state diagram cell delineation process shown Figure
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-1990267, Issue
S/UNI®-JET Data Sheet Released
Figure Cell delineation State Diagram
Correct (bit bit)
HUNT Incorrect (cell cell)
ESYNC
ALPHA consecutive incorrect HCS's (cell cell)
SYNC
DELTA consecutive correct HCS's (cell cell)
values ALPHA DELTA determine robustness delineation method. ALPHA determines robustness against false misalignments errors. DELTA determines robustness against false delineation synchronization process. ALPHA chosen DELTA chosen recommended ITU-T Recommendation I.432. These values result maximum average time frame stream carrying Acells directly mapped into information payload. detected counting number incorrect cells while HUNT state. counter value stored RXCP-50 Count Threshold Register. threshold default value which results application detection time G.832 application detection time G.751 application detection time application time 24.8ms, application detection time application detection time
counter value zero, output signal asserted every incorrect cell.
10.9
PRGD Pseudo-Random Sequence Generator/Detector
Pseudo-Random Sequence Generator/Detector (PRGD) block software programmable test pattern generator, receiver, analyzer. types test patterns (pseudo-random repetitive) conform ITU-T O.151.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-1990267, Issue
S/UNI®-JET Data Sheet Released
PRGD programmed generate pseudo-random pattern with length 232-1 bits user programmable pattern from bits length. PRGD also insert single errors error rate between 10-1 10-7. PRGD programmed check presence generated pseudo-random pattern. PRGD perform auto-synchronization expected pattern, generate interrupts detection loss specified pattern. PRGD accumulate total number bits received total number errors saturating 32-bit counters. counters accumulate over interval defined writes S/UNI-JET Identification/Master Reset, Global Monitor Update Register (006H) writes PRGD accumulation register. When accumulation forced either method, then holding registers updated, counters reset begin accumulating next interval. counters reset such that events missed. data then available holding registers until next accumulation. addition counters, record bits received immediately prior accumulation available. PRGD also programmed check repetitive sequences. When configured detect pattern length bits, PRGD will load bits from detected stream, determine whether received pattern repeats itself every subsequent bits. Should fail find such pattern, will continue loading checking until finds repetitive pattern. features (error counting, auto-synchronization, etc.) available pseudo-random sequences also available repetitive sequences. Whenever PRGD accumulation forced, PRGD stores snapshot bits received immediately prior accumulation. This snapshot examined order determine exact nature repetitive pattern received PRGD. pseudo-random repetitive pattern inserted/extracted PLCP payload PLCP framing enabled) DS3, Arbitrary framing format payload PLCP framing disabled). cannot inserted into Acell payload.
10.10 RXCP-50 Receive Cell Processor
Receive Cell Processor (RXCP-50) Block integrates circuitry support: Scrambled unscrambled cell payloads. Scrambled unscrambled cell headers. verification. Idle cell filtering. Performance monitoring.
RXCP-50 operates upon delineated cell stream. PLCP based transmissions systems, cell delineation performed SPLR. non-PLCP based transmission systems, cell delineation performed ATMF. Framing status indications from these blocks ensure that cells written RXFF while SPLR state, cells written RXFF while ATMF HUNT PRESYNC states.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-1990267, Issue
S/UNI®-JET Data Sheet Released
RXCP-50 descrambles cell payload field using self synchronizing descrambler with polynomial header portion cells optionally descrambled also. Note: Cell payload scrambling enabled default S/UNI-JET required ITU-T Recommendation I.432, disabled ensure backwards compatibility with older equipment. CRC-8 calculation over first four octets Acell header. RXCP-50 verifies received using accumulation polynomial, coset polynomial added (modulo received octet before comparison with calculated result required AForum specification, ITU-T Recommendation I.432. RXCP-50 programmed drop cells containing error filter cells based cell header. Filtering according particular GFC, PTI, bits Acell header programmable through RXCP-50 Registers. Note: bits must logic zero. More precisely, filtering performed when filtering enabled when errors found when checking enabled. Otherwise, cells passed regardless error conditions. Cells blocked pattern invalid filtering 'Match Pattern' 'Match Mask' Registers programmed with certain blocking pattern. AIdle cells filtered default. Acells, null idle cells identified standardized header pattern 'H00, 'H00, 'H00 'H01 first four octets followed valid octet. While cell delineation state machine SYNC state, verification circuit implements state machine shown Figure
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S/UNI®-JET Data Sheet Released
Figure Verification State Diagram
ADELINEATIO SYNC STATE
Errors Detected (Pass Cell)
ALPHA consecutive incorrect HCS's HUNT state)
Apparent Multi-Bit rror (Drop Cell)
CORRECTION MODE Single Error (Correct error pass cell) DETE CTION MODE
Drop Cell
DELTA consecutive correct HCS's (From PRESYNC state)
Errors Detected consecutive cells (Pass Last ell)
normal operation, verification state machine remains 'Correction' state. Incoming cells containing errors passed receive FIFO. Incoming single-bit errors corrected, resulting cell passed FIFO. Upon detection single-bit error multi-bit error, state machine transitions 'Detection' state. programmable hysteresis provided when dropping cells based errors. When cell with error detected, RXCP-50 programmed continue discard cells until (where cells received with correct HCS. cell discarded (see Figure Note: dropping cells errors only occurs while ATMF SYNC state. Cell delineation optionally disabled, allowing RXCP-50 pass data bytes receives.
10.11 RXFF Receive FIFO
Receive FIFO (RXFF) provides FIFO management S/UNI-JET receive cell interface. receive FIFO contains four cells. FIFO provides cell rate decoupling function between transmission system physical layer Alayer. general management functions RXFF are:
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S/UNI®-JET Data Sheet Released
Filling receive FIFO. Indicating when receive FIFO contains cells. Maintaining receive FIFO read write pointers. Detecting FIFO overrun underrun conditions.
FIFO interface "UTOPIA Level 2"-compliant. accepts read clock (RFCLK) read enable signal (RENB). receive FIFO output (RDAT[15:0]) tri-stated when RENB logic device address (RADR[4:0]) selected does match this device's address. interface indicates start cell (RSOC) receive cell available status (RCA DRCA[4:1]) when data read from receive FIFO (using rising edges RFCLK). (and DRCA[x]) status changes from available unavailable when FIFO either empty (RCALEVEL0=1) near empty (RCALEVEL0 logic zero). interface also indicates FIFO overruns maskable interrupt register bits. Read accesses while DRCA[x]) logic zero will output invalid data.
10.12 CPPM Cell PLCP Performance Monitor
Cell PLCP Performance Monitor (CPPM) Block interfaces directly SPLR accumulate interleaved parity error events, framing octet error events, FEBE events saturating counters. When PLCP framer (SPLR) declares LOF, following counted: interleaved parity error events, framing octet error events, FEBE events, error events. When accumulation interval signaled write CPPM register address space S/UNI-JET Identification, Master Reset, Global Monitor Update Register, CPPM transfers current counter values into holding registers resets counters begin accumulating error events next interval. counters reset such manner that error events occurring during reset period missed.
10.13 Transmitter
Transmitter (T3-TRAN) Block integrates circuitry required insert overhead bits into stream produce B3ZS-encoded signal. T3-TRAN directly compatible with C-bit parity formats. Status signals such receive failure (FERF), AIS, idle signal inserted when their transmission enabled internal register bits. FERF also automatically inserted detection combination LOS, RED, T3-FRMR. valid pair P-bits automatically calculated inserted T3-TRAN. When C-bit parity mode selected, path parity bits, FEBE indications automatically inserted. When enabled C-bit parity operation, FEAC channel sourced XBOC bit-oriented code transmitter. PMDLmessages sourced TDPR data link transmitter. These overhead signals also overwritten using TOH[x] TOHINS[x] inputs.
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S/UNI®-JET Data Sheet Released
When enabled operation, C-bits forced logic with exception Cbit Parity (first C-bit first M-subframe), which forced toggle every M-frame. T3-TRAN supports diagnostic modes which inserts parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, LCV, all-zeros. User control each overhead bits frame provided. Overhead bits inserted bit-by-bit basis from user supplied data stream. overhead clock kHz) overhead alignment output provided allow control user provided stream.
10.14 Transmitter
Transmitter (E3-TRAN) Block integrates circuitry required insert overhead bits into stream produce HDB3-encoded signal. E3-TRAN directly compatible with G.751 G.832 framing formats. E3-TRAN generates frame alignment signal inserts into incoming serial stream based either G.751 G.832 formats alignment pulse applied SPLT block. overhead status bits each frame format individually controlled register bits transmit overhead stream. While certain framing format modes, E3-TRAN generates various overhead bytes according following format mode. G.832 format, E3-TRAN: Inserts BIP-8 byte calculated over preceding frame. Inserts Trail Trace bytes through Trail Trace Buffer (TTB) block. Inserts FERF register optionally, when E3-FRMR declares OOF, when loss cell delineation (LCD) defect declared. Inserts FEBE bit, which logic when more BIP-8 errors detected receive framer. there BIP-8 errors indicated E3-FRMR, E3-TRAN sets FEBE logic zero. Inserts Payload Type bits based register value microprocessor. Inserts Tributary Unit multiframe indicator bits either overhead stream register values microprocessor. Inserts Timing Marker register bit. Inserts Network Operator (NR) byte from TDPR block when TNETOP S/UNI-JET Data Link FERF Control Register logic one; otherwise, byte ones. byte overwritten using TOH[x] TOHINS[x] input pins. eight bits Network Operator byte available datalink. Inserts General Purpose Communication Channel (GC) byte from TDPR block when TNETOP S/UNI-JET Data Link FERF Control Register logic zero; otherwise, byte ones. byte overwritten using TOH[x] TOHINS[x] input pins.
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S/UNI®-JET Data Sheet Released
G.751 mode, E3-TRAN Inserts (bit frame) either register optionally, when E3-FRMR declares OOF. Inserts National reserved (bit frame) either fixed value through register from TDPR block configured TNETOP S/UNI-JET Data Link FERF Control Register NATUSE TRAN Configuration Register. Optionally identifies tributary justification bits stuff opportunity bits either overhead payload SPLT payload mappings that take advantage full bandwidth.
Further, E3-TRAN provide insertion errors framing pattern parity bits, insertion single diagnostic purposes. Most overhead bits overwritten using TOH[x] TOHINS[x] input pins.
10.15 Transmitter
Transmitter (J2-TRAN) Block integrates circuitry required insert overhead bits into stream produce B8ZS-encoded signal. J2-TRAN directly compatible with framing format specified G.704 Technical Reference High-Speed Digital Leased Circuit Services. J2-TRAN generates frame alignment signal inserts into incoming serial stream. overhead status bits each frame format individually controlled either register bits transmit overhead stream. J2-TRAN inserts: CRC-5 bits calculated over preceding multiframe. x-bits through microprocessor programmable register bits. a-bit through microprocessor programmable register bit. m-bit data link through TDPR block. Payload physical layer through microprocessor programmable register bits. over m-bits, overwriting HDLC frames, using XBOC block through
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