PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER PM7351
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
PM7351
VORTEX
S/UNI
S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
DATA SHEET
RELEASED ISSUE MARCH 2000
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
REVISION HISTORY Issue Issue Issue Date March 2000 Details Change Changes marked with side bars. Incorporated errata items updated data sheet Production Release. Updated A.C. Timing Characteristics tHRCLK tHTCLK. Updated D.C. Characteristics VODM Issue Issue Issue January 2000 June 1999 April 1999 Changes marked with side bars. Matches functionality PM7351 Changed confidentiality notices document's public release. Changes areas from Issue Matches functionality product PM7351-BI, Preliminary Document
Issue
,1998
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
CONTENTS FEATURES APPLICATIONS REFERENCES. APPLICATION EXAMPLES BLOCK DIAGRAM DESCRIPTION DIAGRAM DESCRIPTION. FUNCTIONAL DESCRIPTION. CELL INTERFACE HIGH-SPEED SERIAL INTERFACES CELL BUFFERING FLOW CONTROL TIMING REFERENCE INSERTION RECOVERY JTAG TEST ACCESS PORT. MICROPROCESSOR INTERFACE INTERNAL REGISTERS REGISTER MEMORY
NORMAL MODE REGISTER DESCRIPTION TEST FEATURES DESCRIPTION .117 11.1 11.2 BUILT-IN-SELF-TEST JTAG TEST PORT
OPERATION
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
12.1 12.2 12.3 12.4 12.5
DETERMINING VALUE FREADY[5:0]. INTERACTION BETWEEN LVDS CONFIGURATIONS MINIMUM PROGRAMMING JTAG SUPPORT MICROPROCESSOR INBAND COMMUNICATION
FUNCTIONAL TIMING. ABSOLUTE MAXIMUM RATINGS D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS. A.C. TIMING CHARACTERISTICS. ORDERING THERMAL INFORMATION. MECHANICAL INFORMATION.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
LIST REGISTERS REGISTER 0X000: MASTER RESET IDENTITY LOAD PERFORMANCE METERS REGISTER 0X001: MASTER CONFIGURATION REGISTER 0X002: RECEIVE SERIAL INTERRUPT STATUS. REGISTER 0X003: TRANSMIT SERIAL INTERRUPT STATUS REGISTER 0X004: MISCELLANEOUS INTERRUPT STATUSES. REGISTER 0X005: CONTROL CHANNEL BASE ADDRESS REGISTER 0X006: CONTROL CHANNEL BASE ADDRESS REGISTER 0X007: CLOCK MONITOR. REGISTER 0X008: DOWNSTREAM CELL INTERFACE CONFIGURATION REGISTER 0X00A: DOWNSTREAM CELL INTERFACE INTERRUPT ENABLE REGISTER 0X00B: DOWNSTREAM CELL INTERFACE INTERRUPT STATUS REGISTER 0X00C: UPSTREAM CELL INTERFACE CONFIGURATION INTERRUPT STATUS. REGISTER 0X010: MICROPROCESSOR CELL BUFFER INTERRUPT CONTROL STATUS. REGISTER 0X011: MICROPROCESSOR INSERT FIFO CONTROL. REGISTER 0X012: MICROPROCESSOR EXTRACT FIFO CONTROL REGISTER 0X013: MICROPROCESSOR INSERT FIFO READY. REGISTER 0X014: MICROPROCESSOR EXTRACT FIFO READY REGISTER 0X015: INSERT CRC-32 ACCUMULATOR (LSB). REGISTER 0X016: INSERT CRC-32 ACCUMULATOR (2ND BYTE)
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
REGISTER 0X017: INSERT CRC-32 ACCUMULATOR (3RD BYTE) REGISTER 0X018: INSERT CRC-32 ACCUMULATOR (MSB) REGISTER 0X019: EXTRACT CRC-32 ACCUMULATOR (LSB) REGISTER 0X01A: EXTRACT CRC-32 ACCUMULATOR (2ND BYTE) REGISTER 0X1B: EXTRACT CRC-32 ACCUMULATOR (3RD BYTE) REGISTER 0X01C: EXTRACT CRC-32 ACCUMULATOR (MSB). REGISTER 0X01D: MICROPROCESSOR CELL BUFFER DATA REGISTERS 0X080, 0X0A0, 0X0C0, 0X0E0, 0X100, 0X120, 0X140, 0X160: RECEIVE HIGH SPEED SERIAL CONFIGURATION. REGISTERS 0X081, 0X0A1, 0X0C1, 0X0E1, 0X101, 0X121, 0X141, 0X161: RECEIVE HIGH-SPEED SERIAL CELL FILTERING CONFIGURATION/STATUS. REGISTERS 0X082, 0X0A2, 0X0C2, 0X0E2, 0X102, 0X122, 0X142, 0X162: RECEIVE HIGH-SPEED SERIAL INTERRUPT ENABLES REGISTERS 0X083, 0X0A3, 0X0C3, 0X0E3, 0X103, 0X123, 0X143, 0X163: RECEIVE HIGH-SPEED SERIAL INTERRUPT STATUS REGISTER 0X084, 0X0A4, 0X0C4, 0X0E4, 0X104, 0X124, 0X144, 0X164: RECEIVE HIGH-SPEED SERIAL ERROR COUNT REGISTERS 0X085, 0X0A5, 0X0C5, 0X0E5, 0X105, 0X125, 0X145, 0X165: RECEIVE HIGH-SPEED SERIAL CELL COUNTER (LSB). REGISTERS 0X086, 0X0A6, 0X0C6, 0X0E6, 0X106, 0X126, 0X146, 0X166: RECEIVE HIGH-SPEED SERIAL CELL COUNTER. REGISTERS 0X087, 0X0A7, 0X0C7, 0X0E7, 0X107, 0X127, 0X147, 0X167: RECEIVE HIGH-SPEED SERIAL CELL COUNTER (MSB). REGISTERS 0X088, 0X0A8, 0X0C8, 0X0E8, 0X108, 0X128, 0X148, 0X168: RECEIVE HIGH-SPEED SERIAL FIFO OVERFLOW. REGISTERS 0X089, 0X0A9, 0X0C9, 0X0E9, 0X109, 0X129, 0X149, 0X169: UPSTREAM ROUND ROBIN WEIGHT
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
REGISTERS 0X08A, 0X0AA, 0X0CA, 0X0EA, 0X10A, 0X12A, 0X14A, 0X16A: LOGICAL CHANNEL BASE ADDRESS REGISTER 0X08B, 0X0AB, 0X0CB, 0X0EB, 0X10B, 0X12B, 0X14B, 0X16B: LOGICAL CHANNEL ADDRESS RANGE LOGICAL CHANNEL BASE ADDRESS REGISTERS 0X08C, 0X0AC, 0X0CC, 0X0EC, 0X10C, 0X12C, 0X14C, 0X16C: DOWNSTREAM LOGICAL CHANNEL FIFO CONTROL. REGISTER 0X08D, 0X0AD, 0X0CD, 0X0ED, 0X10D, 0X12D, 0X14D, 0X16D: DOWNSTREAM LOGICAL CHANNEL FIFO INTERRUPT STATUS REGISTERS 0X08F, 0X0AF, 0X0CF, 0X0EF, 0X10F, 0X12F, 0X14F, 0X16F: DOWNSTREAM LOGICAL CHANNEL FIFO READY LEVEL. REGISTERS 0X090, 0X0B0, 0X0D0, 0X0F0, 0X110, 0X130, 0X150, 0X170: TRANSMIT HIGH-SPEED SERIAL CONFIGURATION REGISTERS 0X091, 0X0B1, 0X0D1, 0X0F1, 0X111, 0X131, 0X151, 0X171: TRANSMIT HIGH-SPEED SERIAL CELL COUNT STATUS. REGISTERS 0X092, 0X0B2, 0X0D2, 0X0F2, 0X112, 0X132, 0X152, 0X172: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (LSB) REGISTERS 0X093, 0X0B3, 0X0D3, 0X0F3, 0X113, 0X133, 0X153, 0X173: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER REGISTER 0X094, 0X0B4, 0X0D4, 0X0F4, 0X114, 0X134, 0X154, 0X174: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (MSB) REGISTERS 0X095, 0X0B5, 0X0D5, 0X0F5, 0X115, 0X135, 0X155, 0X175: SERIAL LINK MAINTENANCE REGISTERS 0X097, 0X0B7, 0X0D7, 0X0F7, 0X117, 0X137, 0X157, 0X177: TRANSMIT ORIENTED CODE REGISTERS 0X098, 0X0B8, 0X0D8, 0X0F8, 0X118, 0X138, 0X158, 0X178: ORIENTED CODE RECEIVER ENABLE.112 REGISTER 0X099, 0X0B9, 0X0D9, 0X0F9, 0X119, 0X139, 0X159, 0X179: RECEIVE ORIENTED CODE STATUS .113 REGISTERS 0X09C, 0X0BC, 0X0DC, 0X0FC, 0X11C, 0X13C, 0X15C, 0X17C: UPSTREAM LINK FIFO CONTROL .114
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
REGISTER 0X200: MASTER TEST .118 REGISTER 0X201: MASTER TEST CONTROL .119
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
LIST FIGURES FIG. TYPICAL TARGET APPLICATION FIG. THREE STAGE MULTIPLEX ARCHITECTURE. FIG. SCI-PHY/ANY-PHY CELL FORMAT. FIG. HIGH-SPEED SERIAL LINK DATA STRUCTURE FIG. LOOPBACKS FIG. CELL DELINEATION STATE DIAGRAM. FIG. MICROPROCESSOR CELL FORMAT. FIG. BOUNDARY SCAN ARCHITECTURE FIG. CONTROLLER FINITE STATE MACHINE FIG. UPSTREAM SCI-PHY INTERFACE TIMING FIG. UPSTREAM ANY-PHY INTERFACE TIMING. FIG. DOWNSTREAM ANY-PHY INTERFACE POLLING TIMING FIG. DOWNSTREAM ANY-PHY INTERFACE TRANSFER TIMING. FIG. MICROPROCESSOR INTERFACE READ TIMING FIG. MICROPROCESSOR INTERFACE WRITE TIMING FIG. RSTB TIMING FIG. RECEIVE SCI-PHY/ANY-PHY INTERFACE TIMING FIG. TRANSMIT SCI-PHY INTERFACE TIMING FIG. JTAG PORT INTERFACE TIMING.
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
LIST TABLES TABLE SCI-PHY ANY-PHY COMPARISON TABLE PREPENDED FIELDS. TABLE ASSIGNED ORIENTED CODES TABLE BOUNDARY SCAN REGISTER TABLE FROM NEAR-END DOWNSTREAM FAR-END UPSTREAM
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
FEATURES Integrated analog/digital device that interfaces high speed parallel bidirectional data streams, each transported over high speed Voltage Differential Signal (LVDS) serial link. Works with sister device, S/UNI-DUPLEX, satisfy full system level requirements backplane interconnect: Transports user data providing inter-card data-path. Inter-processor communication providing integrated inter-card control channel. Exchanges flow control information (back-pressure) prevent data loss. Provides embedded command control signals across backplane: system reset, error indications, protection switching commands, etc. Clock/timing distribution (system clocks well reference clocks such timing references). Fault detection, redundancy, protection switching, inserting/removing cards while system running (hot swap).
Each S/UNI-VORTEX Interfaces S/UNI-DUPLEX devices (via LVDS links) create point-to-multipoint serial backplane architecture. S/UNI-VORTEX devices (interfacing maximum S/UNIDUPLEXs) reside single system bus. LVDS receive direction: accepts cell streams from LVDS links, multiplexing them into single cell stream which presented system single Utopia compatible PHY. LVDS transmit direction: receives cell streams from master, routes cells appropriate serial link. Cell read/write LVDS links available microprocessor port. Provides optional hardware assisted CRC32 calculation across cells create embedded inter-processor communication channel across LVDS links. Optionally routes embedded control channels from link's from system bus.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Under software control, LVDS links individually marked active standby. This used S/UNI-DUPLEXs implement protected systems. Error monitoring cell counting links. Requires external memories. power 3.3V CMOS technology. Standard P1149 JTAG port. ball SBGA, 31mm 31mm.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
APPLICATIONS Single shelf multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM). ATM, frame relay, switch. Multiservice access multiplexer. Universal Mobile Telecommunication System (UMTS) wireless base stations. UMTS wireless base station controllers. Multi-shelf access concentrators.
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
REFERENCES PMC-Sierra; "Saturn Compatible Interface APHY Layer ALayer Devices, Level PMC-940212; Dec. 1995 PMC-Sierra; "Saturn Interface Specification Interoperability Framework Packet Cell Transfer Between Physical Layer Link Layer Devices", PMC-980902, Draft AForum, "Universal Test Operations Interface A(UTOPIA), Level Version 1.0, af-phy-0039.000, June 1995 ITU-T Recommendation I.432.1, "B-ISDN user-network interface Physical layer specification: General characteristics", 08/96 American National Standard Telecommunications, "Network Customer Installation Interfaces Asymmetric Digital Subscriber Line (ADSL) Metallic Interface", ANSI T1.413-1998, November, 1998
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
APPLICATION EXAMPLES When designing communication equipment such access switches, multiplexers, wireless base stations, base station controllers equipment architect faced with common problem: efficiently connect large number lower speed ports small number high speed ports? Typically, number line-side ports (analog modems, xDSL modems APHYs, modems) terminated each line card. Numerous line cards then slotted into more shelves backplane traces inter-shelf cables used connect line cards centralized (often protected) common card, hereafter referred core card. core card normally includes more high speed up-link ports that transport traffic from high speed broadband network. block diagram redundant system shown Fig. Fig. Typical Target Application
Modem Modem Modem Line Card S/UNIDUPLEX S/UNIVORTEX Policing OA&M Buffering Discard Scheduling up-link
OA&M
Card
Modem Modem Modem
Line Card S/UNIDUPLEX
S/UNIVORTEX
Policing OA&M
Buffering Discard Scheduling
OA&M
up-link
Card
this type equipment majority (perhaps all) user traffic goes from port line port, from line port port. Although individual ports line cards often relatively speed interfaces such xDSL, there many ports line card many line cards system, resulting hundreds even thousands lines terminating single up-link. upstream direction (from line card up-link), equipment must have capacity buffer intelligently manage bursts upstream traffic simultaneously from numerous line cards.
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
downstream direction equipment must handle similar issue, "big pipe feeding little pipe" problem. When large burst traffic destined single line port received high speed port must buffered managed queues waiting much lower speed line port clear. line cards always most numerous cards this type equipment. individual line card, even terminates dozen speed ports, does generate receive enough traffic justify putting complex buffering traffic management devices ideal architecture cost "dumb" line cards feature rich, "smart" core card. order enhance fault tolerance, architecture should also inherently support protection using redundant core card up-link without significantly increasing line card complexity. system architecture that keeps buffering traffic management line card will typically exhibit following features: Connection setup simpler both terms programming during execution because there minimal requirement line card intervention during connection setup process. In-service feature upgrades simpler because feature complexity limited common equipment. Component costs reduced, while system reliability increases reduced component count. this type architecture there often three stages signal concentration multiplexing, shown Fig.
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Fig. Three Stage Multiplex Architecture
Modem Modem Modem
Line Card
S/UNIDUPLEX
Modem Modem Modem
Line Card
S/UNIDUPLEX
S/UNIVORTEX
S/UNIVORTEX
Policing OA&M
Buffering Discard Scheduling
OA&M Card
up-link
Modem Modem Modem
Line Card
S/UNIDUPLEX
Stage
Stage
Stage
first stage resides line card spans only those ports physically terminated that card. Since confined single card, this first stage multiplexing readily lends itself simple parallel based multiplex topology. second stage concentration occurs between core card(s) line cards, including line cards that separate shelf. This second stage best served redundant serial point-to-point technology. third stage multiplexing optional resides core card. This third stage used systems with large number line cards that require several S/UNI-VORTEX devices terminate second stage aggregation. Since third stage aggregation confined core card, lends itself readily parallel implementation. This three stage approach implemented directly S/UNI-VORTEX sister device, S/UNI-DUPLEX. S/UNI-DUPLEX acts line card's master. implements first stage multiplexing routing traffic from PHYs transmitting traffic simultaneously over high speed Mbps) serial 4-wire LVDS links. serial link attaches active core card, other standby core
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
card.1 downstream direction S/UNI-DUPLEX demultiplexes traffic from active core card's LVDS serial link routes this traffic appropriate PHYs. active core card LVDS link) should fail, protection switching commands embedded spare LVDS link will direct S/UNI-DUPLEX start receiving traffic from this spare link. S/UNI-VORTEX resides core card terminates LVDS links connected S/UNI-DUPLEX devices. S/UNI-VORTEX implements second stage multiplexing. More than S/UNI-VORTEX will required more than links required will case system with more than line cards. S/UNI-VORTEX device(s) share high speed parallel with core card's traffic management OA&M layers, implemented devices such PMC-Sierra's S/UNI-APEX S/UNI-ATLAS. This third stage multiplexing.
single core card implementation also supported, course.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
BLOCK DIAGRAM
RX8K TX8K
TENB TADR[11:0] T[15:0] TCLK VADR[4:0] RENB RADR[4:0] RDAT[15:0] RSOP RCLK
Any-PH Transm Slave
Cell per-PH buffer Cell FIFO Cell FIFO
Cell Processor
0RXD0+ RXD0-
SCI-PHY/ Any-PH Receive Slave
Cell FIFO
7RXD7+ RXD7-
A[9:0] RSTB D[7:0] blocks MicroProcessor Interface
Clock Synthesis
REFCLK
JTAG Test Access Port
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
DESCRIPTION PM7351 S/UNI-VORTEX monolithic integrated circuit typically used with sister device, S/UNI-DUPLEX, implement point-to-point serial backplane interconnect architecture. sixteen S/UNI-VORTEX devices reside common cell processing card along side traffic management device. traffic management device exchanges cells with S/UNI-VORTEX 16-bit SCI-PHY Any-PHY interfaces. Flow control effected across this interface cell available signals generated S/UNI-VORTEX. downstream direction, availability buffer each logical channel polled traffic management device. upstream direction, indication provided whether there more cells queued S/UNI-VORTEX transfer. Each S/UNI-VORTEX connected eight line cards Mb/s serial links. Each upstream link queue. queue becomes nearly full, flow control indication sent downstream. downstream direction, each logical channel dedicated cell buffer avoid head line blocking. serialization cells from cell buffers throttled flow control information sent from line card upstream high-speed link. microprocessor port provides access internal configuration monitoring registers. port also used insert extract cells support control channel. LVDS INTERFACES, BOTH DIRECTIONS independent 4-wire LVDS serial transceivers each operating Mbps across backplane traces, across meters 4-wire twisted pair cabling inter-shelf communications. Usable bandwidth (excludes system overhead) Mbps direction LVDS link. Full integrated LVDS clock synthesis recovery. external analog components required.
LVDS RECEIVE DIRECTION Weighted round robin multiplex cell streams from LVDS links into single cell stream which transferred parallel under control master.
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
LVDS link S/UNI-VORTEX identifiers added each cell (along with identifier already added S/UNI-DUPLEX) Alayer identify cell source. Back-pressure sent prevent overflow receiver FIFO.
LVDS TRANSMIT DIRECTION microprocessor port back-pressure used each links prevent overflow downstream buffers. Device polling: provides Utopia-like status PHYs (includes control channels) based back-pressure from LVDS links. Cell transfer: master adds address each cell identifier. S/UNI-Vortex decodes accepts cells links based software configured base addresses.
PARALLEL INTERFACE: Both directions: wide, clock rate, slave. Cells transferred bus: Utopia compatible with optional expanded length cells. Appears single PHY, with cell prepend identifying source each cell. Alternatively, Utopia compliance supported placing inside UDF/HEC fields standard Acell. Cells received from bus: Any-PHY similar Utopia with optional expanded length cells expanded addressing capabilities. S/UNI-VORTEX appears master port multi-PHY device links, each with PHYs communication channel). address added cell prepend optionally HEC/UDF field when standard length cells desired.
MICROPROCESSOR INTERFACE data bus, address bus. Provides read/write access configuration status registers. Provides CRC32 calculation cell transfer registers support embedded microprocessor microprocessor communication channel over LVDS link.
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
DIAGRAM S/UNI-VORTEX packaged 304-ball enhanced ball grid array (BGA) package having body size ball pitch 1.27
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
DESCRIPTION Ball Name RXD0+ RXD0RXD1+ RXD1RXD2+ RXD2RXD3+ RXD3RXD4+ RXD4RXD5+ RXD5RXD6+ RXD6RXD7+ RXD7TXD0+ TXD0TXD1+ TXD1TXD2+ TXD2TXD3+ TXD3TXD4+ TXD4TXD5+ TXD5TXD6+ TXD6TXD7+ TXD7Ball
Type Diff. LVDS Input
Function High Speed LVDS Links high-speed receive data (RXD0+/- RXD7+/-) inputs present data from serial backplane. These truly differential inputs offering superior common-mode noise rejection. They have sufficient sensitivity common-mode range support LVDS signals. These inputs high-impedance. external resistor must connected between pins signal pair terminate transmission line. D.C. A.C. coupling used depending application.
Diff. LVDS Output
transmit differential data (TXD0+/- -TXD7+/-) outputs present encoded data serial backplane. These outputs open drain current sinks which interface directly with twisted-pair cabling board interconnect. D.C. A.C. coupling used depending application. current sinks, these outputs must reflected impedance between pins signal pair produce correct LVDS signal levels.
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Ball Name REFCLK
Type Input
Ball
Function
AB13 reference clock input (REFCLK) must provide jitter-free reference clock. used reference clock both clock recovery clock synthesis circuits. jitter below transferred directly TXDn+/- outputs. high speed serial interface rate eight times REFCLK frequency. 4.75k resistor must connected between these balls achieve correct LVDS output signal levels. Analog Test Points (ATP) provided production test purposes. mission mode they high impedance should connected ground. transmit timing reference (TX8K) input allows traceable signal transmitted high-speed serial links TXD0+/- through TXD7+/-. rising edge TX8K encoded next cell transmitted. Although TX8K targeted typical need transporting signal, frequency constrained kHz. frequency less than cell rate permissible.
RESK ATP0 ATP1 TX8K
Analog
Analog
Input
RX8K
Output
receive timing reference (RX8K) output presents timing extracted from receive high-speed serial links. rising edge RX8K accurate nearest byte boundary high-speed serial link; therefore, small amount jitter present. link rate 155.52 Mb/s, jitter 63ns peak-to-peak. Pulses RX8K always high-speed serial link periods wide (two REFCLK periods).
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Ball Name RANYPHY
Type Input
Ball
Function Upstream (Receive) Receive Any-PHY configuration input determines protocol upstream cell interface. RANYPHY logic low, interface complies SCI-PHY specification. such, outputs have single cycle latency. RANYPHY logic high, interface complies Any-PHY specification. Relative SCI-PHY, outputs have additional cycle latency. RANYPHY asynchronous input expected held static.
RCLK
Input
Receive FIFO clock (RCLK) used read words from S/UNI-VORTEX upstream cell buffer. RCLK must cycle lower instantaneous rate. RSOP, RPA, RPRTY RDAT[15:0] updated rising edge RCLK. RENB RADR[4:0] sampled rising edge RCLK. signal indicates whether least cell queued transfer. Upon sampling RADR[4:0] value that equals value VADR[4:0], S/UNI-VORTEX drives with cell availability status immediately RANYPHY logic low. RANYPHY logic high, additional cycle latency. will least entire cell available. high-impedance when polled. updated rising edge RCLK.
Output
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PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Ball Name RENB
Type Input
Ball
Function active read enable (RENB) output used initiate transfer cells from S/UNI-VORTEX traffic management device. When RENB sampled S/UNI-VORTEX been selected, word output RDAT[15:0]. Selection occurs when RENB last sampled high RADR[4:0] value equals state VADR[4:0]. RENB must between cycles transfer entire cell depending whether cell contains prepended words H5/UDF word. RANYPHY logic low, valid data driven immediately upon sampling RENB low. RANYPHY logic high, RSX, RSOP, RDAT[15:0] RPRTY outputs have additional cycle latency. permissible pause cell transfer deasserting RENB high. RANYPHY logic low, S/UNIVORTEX's address must presented RADR[4:0] last cycle RENB high reselect device. RANYPHY logic high, cell transfer resumes unconditionally when RENB asserted again. either case, cell transfer must completed before another device selected. Any-PHY protocol supports autonomous deselection. RANYPHY logic high, outputs become high impedance after last word cell transferred until S/UNI-VORTEX reselected. RANYPHY logic low, subsequent cell transferred (provided available) RENB held beyond cell. When RENB sampled high S/UNI-VORTEX selected, read performed outputs RDAT[15:0], RPRTY, RSOP become high impedance. RENB input sampled rising edge RCLK.
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Ball Name RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]
Type Input
Ball
Function RADR[4:0] signals used address sixteen S/UNI-VORTEX devices purposes polling selection cell transfer. When RADR[4:0] value sampled that equals state VADR[4:0], output driven indicate whether cell available transfer. RANYPHY logic high, additional cycle latency. RADR[4:0] value equals state VADR[4:0] when RENB last sampled high, S/UNIVORTEX will initiate cell transfer. RANYPHY logic low, device must reselected resume cell transferred that been halted deasserting RENB high. RADR[4:0] sampled rising edge RCLK.
VADR[4] VADR[3] VADR[2] VADR[1] VADR[0]
Input
device identification address (VADR[4:0]) inputs most-significant bits upstream polling address space which this S/UNI-VORTEX occupies. When VADR[4:0] inputs match value sampled RADR[4:0] inputs, S/UNI-VORTEX drives indicate existence queued cells. Otherwise, high impedance. VADR[4:0] expected held static.
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Ball Name RSOP
Type
Ball
Function Receive Start Packet (RSOP) marks either first second word cell RDAT[15:0] bus. When RSOP high RANYPHY low, first word cell structure present RDAT[15:0] stream. When RSOP RANYPHY both high, second word cell structure present RDAT[15:0] stream. RSOP updated rising edge RCLK considered valid only when S/UNI-VORTEX device selected after polling process RENB signal sampled low. RANYPHY logic RSOP driven immediately upon sampling RENB low, additional cycle latency when RANYPHY logic high. RSOP becomes high impedance upon sampling RENB high S/UNIVORTEX device selected transfer. When RANYPHY high, autonomous deselection occurs after last word cell resulting setting RSOP high-impedance until reselection.
Output
Output
Receive Start Transfer (RSX) only active when RANYPHY input logic high. When RANYPHY logic low, during cell transfers high-impedance otherwise. marks start cell RDAT[15:0] bus. When high, first word cell structure present RDAT[15:0] stream. updated rising edge RCLK considered valid only when RENB signal sampled previous cycle S/UNIVORTEX device selected after polling process. becomes high impedance (with cycle latency) upon sampling RENB high S/UNIVORTEX device selected transfer. When RANYPHY high, autonomous deselection occurs after last word cell resulting setting high-impedance until reselection.
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Ball Name RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] RPRTY
Type
Ball
Function receive cell data (RDAT[15:0]) carries Acell words that have been read from S/UNIVORTEX internal cell buffers. RDAT[15:0] updated rising edge RCLK considered valid only when S/UNIVORTEX device selected after polling process RENB signal sampled low. RANYPHY logic RDAT[15:0] driven immediately upon sampling RENB low, additional cycle latency when RANYPHY logic high. RDAT[15:0] becomes high impedance upon sampling RENB high S/UNI-VORTEX device selected transfer. When RANYPHY high, autonomous deselection occurs after last word cell resulting setting RDAT[15:0] high-impedance until reselection. Receive Parity (RPRTY) signal completes parity (programmable even parity) RDAT[15:0] bus. RPRTY signal updated rising edge RCLK considered valid only when S/UNIVORTEX device selected after polling process RENB signal sampled low. RANYPHY logic RPRTY driven immediately upon sampling RENB low, additional cycle latency when RANYPHY logic high. RPRTY becomes high impedance upon sampling RENB high S/UNI-VORTEX device selected transfer. When RANYPHY high, autonomous deselection occurs after last word cell resulting setting RPRTY high-impedance until reselection.
Output Output
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Ball Name TCLK
Type Input
Ball
Function Downstream (Transmit) transmit FIFO clock (TCLK) used transfer cells from traffic scheduler device internal downstream cell buffers. TCLK must cycle lower instantaneous rate. TSX, TENB, TADR[11:0], TPRTY TDAT[15:0] sampled rising edge TCLK. updated rising edge TCLK. S/UNI-VORTEX indicates availability space FIFO associated with logical channel when polled using TADR[11:0] signals. S/UNIVORTEX will drive signal appropriate value during second clock cycle following that which particular logical channel addressed. When high, indicates that corresponding buffer segment empty complete cell written. buffer status particular logical channel involved transfer updated immediately upon sampling first word cell when INADDUDF Downstream Cell Interface Configuration register logic When INADDUDF logic buffer status stale until nine cycles after cell transfer completed; therefore, master should refrain from polling that logical channel interim. becomes high impedance when address matching address space Control Channel Base Address, Logical Channel Base Address Logical Channel Address Range Logical Channel Base Address registers sampled from TADR[11:3] inputs. updated rising edge TCLK.
Output
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Ball Name TENB
Type Input
Ball
Function active write enable (TENB) signal used indicate cell transfers internal cell buffers. segment buffer associated with particular logical channel determined inband address prepended cell bytes. TENB ignored high. Upon completion cell transfer, TENB held because cell transfer only initiated assertion TSX. TENB must (depending inclusion optional words) cycles transfer entire cell. TENB deasserted high time pause cell transfer. TENB updated rising edge TCLK.
TADR[11] TADR[10] TADR[9] TADR[8] TADR[7] TADR[6] TADR[5] TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]
Input
AA23
TADR[11:0] signals used address logical channels purposes polling. Upon sampling TADR[11:3] value within address ranges Control Channel Base Address, Logical Channel Base Address Logical Channel Address Range Logical Channel Base Address registers, will driven indicate availability buffer segment addressed TADR[4:0]. When TADR[11:3] does match programmed address range, becomes high impedance. TADR[11:0] sampled rising edge TCLK. transmit start cell (TSX) indication signal marks start cell TDAT[15:0] data bus. When high, first word cell structure present TDAT[15:0] stream. must asserted each cell. interrupt generated high during word other than expected first word cell structure. sampled rising edge TCLK.
Input
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Ball Name TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TPRTY
Type Input
Ball
Function transmit cell data (TDAT[15:0]) carries Acell octets that transferred internal cell buffer. TDAT[15:0] sampled rising edge TCLK considered valid only when TENB signal asserted signal asserted high.
Input
transmit parity (TPRTY) signal completes parity (programmable even parity) TDAT[15:0] bus. parity error indicated status maskable interrupt. TPRTY signal sampled rising edge TCLK considered valid only when TENB signal asserted signal asserted high. Microprocessor
Input
AA17 active-low chip select (CSB) signal during S/UNI-VORTEX register accesses. required (i.e., registers accesses controlled using signals only), must connected inverted version RSTB input.
Input
active-low read enable (RDB) signal during S/UNI-VORTEX register read accesses. S/UNIVORTEX drives D[7:0] with contents addressed register while low.
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Ball Name
Type Input
Ball
Function
AC17 active-low write strobe (WRB) signal during S/UNI-VORTEX register write accesses. D[7:0] contents clocked into addressed register rising edge while low. AC14 bi-directional data D[7:0] used during AB14 S/UNI-VORTEX register read write accesses. AA14 AC15 AB15 AA15 AB16 address A[9:0] selects specific registers during S/UNI-VORTEX register accesses. test register select (TRS) signal selects between normal test mode register accesses. high during test mode register accesses, during normal mode register accesses.
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[9]/TRS A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB
Input AB18 AC19 AA18 AB19 AC20 AA19 AB20 AC21 Input
AA16 active-low reset (RSTB) signal provides asynchronous S/UNI-VORTEX reset. RSTB Schmitt triggered input with integral pull-up resistor. AB17 address latch enable (ALE) active-high latches address A[9:0] when low. When high, internal address latches transparent. allows S/UNI-VORTEX interface multiplexed address/data bus. integral pull-up resistor. active-low interrupt (INTB) signal goes when S/UNI-VORTEX interrupt source active that source unmasked. S/UNI-VORTEX enabled report many alarms events interrupts. INTB becomes high impedance when interrupt acknowledged appropriate register access. INTB open drain output. JTAG Boundary Scan Port
Input
INTB
Output
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Ball Name
Type Input
Ball
Function test clock (TCK) signal provides timing test operations that carried using IEEE P1149.1 test access port. integral pull-up resistor. test mode select (TMS) signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. test data input (TDI) signal carries test data into S/UNI-VORTEX IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. test data output (TDO) signal carries test data S/UNI-VORTEX IEEE P1149.1 test access port. updated falling edge TCK. tristate output which inactive except when scanning data progress. active-low test reset (TRSTB) signal provides asynchronous S/UNI-VORTEX test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull-up resistor. Note that when being used, TRSTB must connected RSTB input. Power Ground
Input
Input
Tristate
TRSTB
Input
BIAS
Power
When tied +5V, BIAS inputs used bias wells input pads that pads tolerate their inputs without forward biasing internal protection devices. When tied +3.3V, inputs bi-directional inputs will only tolerate 3.3V level inputs.
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Ball Name
Type Power
Ball
Function
ring power (VDD) pins should connected well-decoupled +3.3 supply. AC23 AB22 AA21
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Ball Name
Type Ground
Ball
Function
ring ground (VSS) pins should connected GND. AC12 AC16 AC18 AC22 AB21 AB23 AA22 Quiet Analog Power (QAVD1, QAVD0). QAVD1 QAVD0 should connected analog +3.3 Quiet Analog Ground (QAVS1, QAVS0). QAVS1 QAVS0 should connected analog GND.
QAVD1 QAVD0 QAVS1 QAVS0
Analog Power
Analog Power
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Ball Name CAVD
Type Analog Power Analog Ground Analog Power Analog Ground Analog Power
Ball
Function power (CAVD) pins analog clock synthesis unit. These pins should connected analog +3.3V. ground (CAVS) pins analog clock synthesis unit. These pins should connected analog GND. power (RAVD) pins LVDS receivers. These pins should connected analog +3.3V. ground (RAVS) pins LVDS receivers. These pins should connected analog GND. power (TAVD) pins LVDS transmitters. These pins should connected analog +3.3V.
CAVS
RAVD
RAVS
TAVD
TAVS
Analog Ground
ground (TAVS) pins LVDS transmitters. These pins should connected analog GND.
Notes Description: S/UNI-VORTEX inputs bi-directionals present minimum capacitive loading operate logic levels, except RXD0+/- through RXD7+/-. Inputs RSTB, ALE, RANYPHY, TMS, TDI, TRSTB have internal pull-up resistors. improve noise immunity, designs where these inputs no-connects still recommend that they tied VDD. recommended power supply sequencing follows:
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During power-up, voltage BIAS pins must kept equal greater than voltage pins, avoid damage device. power must applied before input pins driven input current limited less than maximum input current specification. Analog power supplies (QAVD, CAVD, RAVD, TAVD) must have their current limited maximum latch-up current specification (100 mA). operation, differential voltage measured between supplies must less than relative power sequencing multiple power supplies important. Power down device reverse sequence.
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FUNCTIONAL DESCRIPTION First, brief note terminology. Throughout this document term "downstream" implies data read from parallel microprocessor port) sent LVDS links. However, since S/UNI-VORTEX slave device direction (transmit receive) normally defined with respect master, downstream called Transmit bus. Conversely, "upstream" used describe data path from LVDS parallel bus, which called Receive bus.
Cell Interface Cell transfer from S/UNI-VORTEX (bus slave) traffic management device (bus master) upstream direction configurable either SCI-PHY AnyPHY. SCI-PHY very similar UTOPIA, supports appended bytes used S/UNI-VORTEX carrying address information. option place addressing information H5/UDF field enabled, SCIPHY compatible Utopia Level Any-PHY defines inband selection polling techniques support large number logical channels, where SCI-PHY limited UTOPIA limited downstream interface only provides Any-PHY slave interface. While downstream cell transfer mechanism compatible with existing SCI-PHY devices UTOPIA devices supporting extended cells), channel status polling extension. 16-bit wide busses plus parity supported; wide supported.
9.1.1 Downstream Conceptually, Any-PHY protocol divided into processes: polling cell transfer. Polling downstream direction used master typically traffic buffering management device determine when buffered data cell safely sent downstream PHY. S/UNI-VORTEX provides independent cell buffer each logical downstream channel each LVDS link. total there data path cell buffers (maximum channels LVDS link times links) plus microprocessor communication channel buffers (one link). This arrangement ensures there head line blocking while eliminating risk buffer overflow. traffic manager need only poll those logical channels which downstream cells queued. cell transfer initiated after polled logical
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channel asserts output. Each channel's cell buffer availability status (i.e. status that will driven onto output when channel polled) deasserted when first byte cell written into buffer. re-asserted only after number bytes programmed associated Downstream Logical Channel FIFO Ready Level register have been serialized onto highspeed link. Determining what value FIFO ready level discussed Section 12.1. Polling performed using TADR[11:0] bus, which supports 4096 logical channel address space. logical channels associated with each highspeed link mapped anywhere within this address space with granularity eight locations through Logical Channel Base Address registers. provide optimal address regardless number logical channels high-speed link, each high-speed link programmed address locations through Logical Channel Address Range registers. eight control channels each S/UNI-VORTEX mapped eight contiguous address locations starting address Control Channel Base Address register. control channels associated with addresses numerical, i.e. control channel TXD0+/- belongs lowest order address TXD7+/- belongs highest order address. With respect cell transfers, Any-PHY port appears like single entity. band addressing required. Instead, first word transferred cell identifies destination logical channel. format cell data structure illustrated Fig. programmed through register bits, User Prepend word prepended basic Acell support applications where context information carried inband. default, only logical channel index (Word prepended. cell will transferred S/UNI-VORTEX ADDR[11:0] (ADDR[13:12] unused downstream direction.) field value matches logical channel mapping programmed through Control Channel Base Address, Logical Channel Base Address Logical Channel Address Range Logical Channel Base Address registers. Normally, ADDR[11:0] contained within Word Any-PHY data structure, mapped H5/UDF fields. H5/UDF (User Defined Field) User Prepend fields handled four ways: They excluded from Any-PHY data structure. They exist Any-PHY data structure, passed across high-speed serial interfaces. contents ignored. They passed transparently across high-speed serial interfaces.
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H5/UDF fields contain ADDR[11:0] value used route transferred cells. this case Word used should generated master. treatment H5/UDF field, address prepend(word their corresponding fields LVDS link independent that User Prepend. Section 12.2 Interaction Between LVDS Configurations page further details. Although ability carry inband address H5/UDF fields provided compatibility with devices that cannot generate address prepend, there constraints that must respected this configuration: Recall that default case (i.e. Word provides address) logical channel participating cell transfer will deassert upon first word cell transfer. However, when H5/UDF provides address, channel's status will return deasserted until nine TCLK periods after last word cell transfer complete. This implies that once cell transfer channel begun that channel should polled again until least nine cycles after transfer complete. Once cell transfer started, TENB input must remain until after H5/UDF word been transferred. After that, permissible TENB toggle high momentarily halt cell transfer. aware that Any-PHY data structures transported transparently. There constraints contents. Therefore, data streams other than Acells transferred across Any-PHY interface; only timing protocols need respected.
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Fig. SCI-PHY/Any-PHY Cell
(optional) (optional) (optional) PAYLOAD1 PAYLOAD3 Reserved ADDR[13:0] User Prepend PAYLO PAYLO
PAYLOAD47
PAYLOAD48
FormatNote ptionally, H5/UDF fields overw ritten ADDR[13:0]. 9.1.2 Upstream upstream direction, each S/UNI-VORTEX appears single SCI-PHY Any-PHY slave. traffic from each high-speed serial link (RXD0+/- through RXD7+/) queued independently support logical channel flow control without head line blocking. Weighted round robin servicing determines order cells presented RDAT[15:0]. Weights strictly linear. example, compared link with weight one, LVDS link with weight four will average have four times number opportunities place cell from receive buffer onto upstream bus. Each high speed serial link assigned weight between When state RADR[4:0] inputs equals state VADR[4:0] pins, output indicates whether there least cell available transfer from link.
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support current future devices, interface configurable either Any-PHY SCI-PHY interface. Table summarizes distinctions between protocols. Table SCI-PHY Any-PHY Comparison
Attribute Latency SCI-PHY RDAT[15:0], RPRTY, RSOP driven become high impedance immediately upon sampling RENB high, respectively. driven immediately upon sampling RADR[4:0] value that matches VADR[4:0]. Undefined. when high impedance. High coincident with first word cell data structure. Permitted deasserting RENB high, S/UNI-VORTEX's address must presented RADR[4:0] last cycle RENB high. supported. subsequent cell output (provided available) RENB held beyond cell. Any-PHY RDAT[15:0], RPRTY, RSOP driven become high impedance RCLK rising edge following that samples RENB high, respectively. driven RCLK rising edge following that samples RADR[4:0] value that matches VADR[4:0]. High coincident with first word cell data structure. High coincident with second word cell data structure. Permitted deasserting RENB high. cell transfer resumes unconditionally when RENB asserted again. outputs become high impedance after last word cell transferred until S/UNIVORTEX reselected.
RSOP Paused transfers
Autonomous deselection
cell format same downstream interface (Fig. address manipulation performed upstream direction; ADDR[13:0] field encoding fixed relationship physical ports. ADDR[13:9] will always equal VADR[4:0] input pins' state. ADDR[8:6] corresponds index high speed serial link (RXD0+/- through RXD7+/-) over which cell received. ADDR[5:0] presents logical channel index that been encoded cell received high-speed serial link. encoding "111110" ADDR[5:0] indicates cell control channel cell.
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High-Speed Serial Interfaces S/UNI-VORTEX provides backplane interconnection Mb/s serial links. data destined coming from line cards concentrated these high-speed links. transceivers support UTP-5 cable lengths 10m. avoid clock skew issues, clock transmitted receivers recover local clock from incoming data. serial links typically carry Acells with prepended bytes. cell format illustrated Fig. S/UNI-VORTEX appends first four bytes Header Check Sequence (HCS) byte downstream direction strips them parses them upstream direction. remainder bytes data structure transferred transparently. bytes serialized most significant first. stream simple concatenation extended cells. Cell rate decoupling accomplished through introduction stuff cells. transmitter inserts correct CRC-8 that protects both Acell header prepended bytes byte. receiver uses byte delineation. Failure establish cell alignment results loss cell delineation (LCD) alarm. entire stream scrambled with self-synchronous scrambler. Table summarizes contents system prepended bytes. Fig. High-Speed Serial Link Data Structure
Byte
User Prepend
User Header bytes
System Prepend
APayload bytes
APayload
bytes, where
Table Prepended Fields Byte Bits Mnemonic CA[15:8] CA[7:0] Description CA[15:0] bits carry logical channel flow control information upstream direction. support logical channels, status each logical channel sent every other cell; CASEL indicates
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Byte
Bits
Mnemonic
Description which half represented. CASEL logic CA[15:0] corresponds those logical channels with UTOPIA addresses through CASEL logic CA[15:0] corresponds those logical channels with UTOPIA addresses through downstream direction, CA[0] only relevant flow controls aggregate. logic indicates accept more cells, S/UNIDUPLEX will immediately start sending idle cells. this logic S/UNIDUPLEX free send queued traffic. allow inter-operability with device that flow controlled logical channel basic, CA[15:1] same state CA[0]. event errored header detected incorrect HCS), bits will assumed zero. This ensures cells transmitted which there buffer space.
CASEL
state select determines which half modems CA[15:0] bits correspond CASEL toggles with each cell transmitted. UPCA carries flow control information microprocessor control channel. this one, control channel cells transferred. event errored header, UPCA will assumed zero. This ensures cells transmitted which there buffer space.
UPCA
PHYID
identifier determines which cell destined downstream direction from which came upstream direction. also indicates whether cell stuff control channel cell. field encoded
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Byte
Bits
Mnemonic
Description follows: "111111" Stuff cell provided cell rate decoupling. payload carries useful data cell shall discarded. "111110" Control channel cell. transmit serial link, PHYID shall equal this value cells inserted Microprocessor Cell Buffer cells received from Any-PHY interface whose inband address matches that programmed Control Channel Base Address register. cells received serial link with this encoding will routed local microprocessor ROUTECC register logic Otherwise, cells routed SCIPHY/Any-PHY interface. "100000" "111101" Reserved "000000" "011111" Logical channel index device.
Oriented Code (BOC) position carries repeating pattern that encodes possible code words used remote control status reporting. Three codes predefined represent remote defect, loopback activate request loopback deactivate request. remaining codes either reserved user defined. receiver ensures pattern same (default) repetitions before validating code word. Refer Oriented Codes section more details.
ACTIVE
link active indicates which redundant links currently chosen. S/UNI-DUPLEX will switch link which contains this location least consecutive cells. line card microprocessor override this selection.
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Byte
Bits
Mnemonic
Description transmitted ACTIVE per-link ACTIVE register bits. confirm which link active, received ACTIVE will associated link selected S/UNI-DUPLEX. event errored header cell delineation state, previous ACTIVE value retained.
TREF[5:0]
timing reference encodes signal inband that independent serial rate. TREF[5:0] binary value represents number high-speed link bytes after this which timing reference inferred. ones value indicates timing mark associated with this cell.
transmitter outputs internally terminated current mode drivers. Correct termination receiver required provide correct signal levels. internal transmit clock synthesized from 12.5 clock. resulting data rate eight times frequency REFCLK input. jitter below REFCLK passed unattenuated TXDn+/- outputs. design loop filter optimized minimum intrinsic jitter. With jitter free reference input noise board layout, intrinsic jitter typically less than 0.01 0.10 peak-to-peak when measured using band pass filter with cutoff frequencies. eight truly differential receivers capable handling signal swings down 100mV. wide common mode range makes them compatible with LVDS signals. External termination resisters must provided match cable impedance. receivers monitor loss signal (LOS) links. declared upon 2048 periods (13.2 155.52 Mb/s) without signal transition scrambled data. consequence, status set, maskable interrupt asserted codeword sent repetitively corresponding downstream link. indication cleared when signal transition occurred each consecutive intervals periods each. Clock recovery performed digital phase locked loop (DPLL). implementation robust against operating condition variations power supply
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noise. receive link constrained within eight times REFCLK frequency. shown Fig. datapath loopbacks provided each LVDS link fault isolation continuity verification. metallic loopback routes receive data transmitter. diagnostic loopback replaces receive data with transmit data. loopbacks enabled individually simultaneously same link, each link looped back independently other seven. Fig. Loopbacks
RX8K TX8K
TENB TADR[11:0] T[15:0] TCLK VADR[4:0] RENB RADR[4:0] RDAT[15:0] RSOP RCLK
Any-PH Transm Slave
Diagnostic Loopback
Cell per-PH buffer Cell FIFO Cell FIFO
etallic Loopback
Cell Processor
0RXD0+ RXD0-
SCI-PHY/ Any-PH Receive Slave
Cell FIFO
7RXD7+ RXD7-
A[9:0] RSTB D[7:0] blocks MicroProcessor Interface
Clock Synthesis
REFCLK
JTAG Test Access Port
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diagnostic loopback effected Serial Link Maintenance register logic transmit data clock inserted into receive datapath downstream clock recovery. metallic loopback effected three ways: after receipt loopback activate bit-oriented code described page 39), when Serial Link Maintenance register logic when RSTB input asserted low. loopback occurs LVDS transceiver after conversion digital before clock recovery looped back data slightly distorted data slicing (conversion from differential single-ended) re-buffering that occurs. Metallic loopback terminated loopback deactivate oriented code received validated, provided Serial Link Maintenance register logic 9.2.1 Link Integrity Monitoring Although serial link error rate inferred from accumulated Header Check Sequence (HCS) errors, option exists perform error monitoring over entire stream. When feature enabled second User Prepend byte transmitted shall overwritten CRC-8 syndrome preceding cell. encoding valid cells, including stuff cells. CRC-8 polynomial receiver shall raise maskable interrupt optionally increment error count. Simultaneous cell CRC-8 errors result single increment. 9.2.2 Oriented Codes Oriented Codes (BOCs) carried position System Prepend. possible codes used carry predefined user defined signaling. oriented codes transmitted repeating 16-bit sequence consisting ones, zero, code bits, trailing zero (111111110xxxxxx0). code transmitted programmed writing Transmit Oriented Code register. autonomously generated Remote Defect Indication (RDI) code, which generated upon loss-of-signal loss-of-cell-delineation, takes precedence over programmed code. insertion disabled RDIDIS Serial Link Maintenance register. inserted manually setting Transmit Oriented Code register zeros. receiver enabled declare received code valid been observed times times, specified
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Oriented Code Receiver Enable register. Unless fast declaration necessary, recommended that logic improve error tolerance. Valid indicated through Receive Oriented Code Status register. bits ones (111111) valid code been detected. maskable interrupt generated signal when detected code been validated, optionally, when valid code goes away (i.e. bits ones). When receiver cell delineation (OCD) Receive Oriented Code Status register will produce ones (111111). valid codes provided Table Reserved codes anticipate future enhanced feature devices should used. User Defined codes used without restriction. Regardless definition, codes validated read microprocessor. Note that processing metalic loopback activate code handled special case. RXDn+/- data looped back onto TXDn+/- reception loopback activate code rather than when code first validated. loopback initiated loopback activate code must first validated (received times) then invalidated, typical reception another code. loopback enable upon initial validation loopback activate code because looped back signal, which still contains original loopback activate command, would cause far-end receiver into metallic loopback well, thereby forming undesirable closed loop condition! loopback cleared immediately upon validation loopback deactivate code, assuming register logic produce loopback end, program Transmit Oriented Code register with loopback activate code least then revert another (typically idle) code. Upon termination loopback activate code, data transmitted TXDn+/- expected received verbatim RXDn+/inputs. When transmitting loopback activate code, recommended RDIDIS register logic else loss-of-signal loss-of-celldelineation event, would cause premature loopback pre-emptive Remote Defect Indication (RDI) code being sent. remote reset activate deactivate code words supported S/UNI-DUPLEX (PM7350) device. S/UNI-VORTEX send reset activate code cause S/UNI-DUPLEX device assert active RSTOB output. deactivate code causes deassertion RSTOB. S/UNIDUPLEX datasheet details. Remote Defect Indication (RDI) sent whenever Loss Signal (LOS) Loss Cell Delineation (LCD) declared. This code word takes precedence over others.
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Table Assigned Oriented Codes Function Remote Defect Indication (RDI) Loopback activate Loopback deactivate Remote reset activate Remote reset deactivate Reserved Reserved User Defined User Defined Idle Code 9.2.3 Cell Delineation Process S/UNI-VORTEX performs cell delineation, payload descrambling, idle cell filtering header error detection recover valid cells from receive high-speed links. These functions performed spirit ITU-T Recommendation I.432.1, support byte cell headers. Cell delineation process framing cell boundaries using header check sequence (HCS) field found cell header. CRC-8 calculation over octets cell header. accordance with ITUT Recommendation I.432.1, coset polynomial added (modulo received octet before comparison with calculated result. When performing delineation, correct calculations assumed indicate cell boundaries. cell delineation circuitry performs sequential bit-by-bit hunt correct sequence. This state referred HUNT state. When correct found, particular cell boundary assumed PRESYNC state entered. This state verifies that previously detected pattern false indication. pattern false indication then incorrect should received within next DELTA cells delineation state machine falls back HUNT state. incorrect found this Codeword (left transmitted first) 11111111 00000000 11111111 01000000 11111111 00100000 11111111 01100000 11111111 00010000 11111111 01010000 11111111 00000100 11111111 01000100 11111111 00111110 11111111 01111110
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PRESYNC period then transition SYNC state made, cell delineation declared non-idle cells with correct passed SYNC state synchronization relinquished until ALPHA consecutive incorrect patterns found. such event transition made back HUNT state. state diagram cell delineation process shown Fig. Fig. Cell delineation State Diagram
correct (bit bit)
HUNT
Incorrect (cell cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell cell)
SYNC
DELTA consecutive correct HCS's (cell cell)
values ALPHA DELTA determine robustness delineation method. ALPHA determines robustness against false misalignments errors. DELTA determines robustness against false delineation synchronization process. ALPHA chosen DELTA chosen loss cell delineation (LCD) alarm declared after 1318 consecutive cell periods (4.0 155.52Mb/s) HUNT PRESYNC states. alarm cleared after 1318 consecutive cells SYNC state. cells with incorrect octet filtered counted. Header correction performed. 9.2.4 Protection Switching Protocol S/UNI-VORTEX sister device, S/UNI-DUPLEX inherently support system architectures requiring fault tolerance redundancy system's common equipment. point-to-point backplane architectures such these, protection also includes associated LVDS links connecting
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common equipment line cards. S/UNI-VORTEX S/UNI-DUPLEX, perform clock recovery, cell delineation, header error monitoring receive high-speed serial links simultaneously. maintained error counts alarm status indications used control system determine state viability each high speed serial link. these architectures, S/UNI-DUPLEX will connected S/UNIVORTEXs, active common card spare common card Upon failure active card, spare card becomes conduit traffic. S/UNI-VORTEX facilitates link selection upon start-up well switching between links upon failure conditions. Typically centralized resource cooperating distributed microprocessor subsystems will determine which common card considered active each downstream S/UNI-DUPLEX. link selection lies "ACTIVE" handled S/UNI-VORTEX S/UNI-DUPLEX. control system uses ACTIVE within each Serial Link Maintenance registers independently state each link's ACTIVE status. current state link's ACTIVE sent downstream once transmitted cell. ACTIVE status debounced acted upon S/UNI-DUPLEX. S/UNI-DUPLEX will only accept data traffic from LVDS links, normally link marked ACTIVE that considered working link. However, S/UNI-DUPLEX override this using local control. Thus, although S/UNI-VORTEX indicate ACTIVE spare links, actually S/UNI-DUPLEX that must effect protection switching. S/UNI-DUPLEX data sheet additional details. S/UNI-DUPLEX returns ACTIVE status indicate which link chosen active. This reflected ACTIVE does have direct affect S/UNI-VORTEX, status debounced (must remain same received cells) then stored S/UNI-VORTEX Receive HighSpeed Serial Cell Filtering Configuration/Status register. reflected status used local control system confirm receipt ACTIVE status S/UNI-DUPLEX. Cell Buffering Flow Control possibility congestion inherent access multiplexer. downstream direction, link generate burst cells particular modem rate exceeding modem's bandwidth capacity. Therefore, feedback traffic scheduler required cause buffer smooth cell bursts prevent downstream buffer overflow. upstream direction, subscribed aggregate bandwidth exceed that accommodated
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uplink. Flow control required ensure fair access up-link, minimize cell loss minimize impact greedy users others. very nature, upstream downstream flow control implemented S/UNI-VORTEX only explained context overall system, including role played eight S/UNI-DUPLEX devices connected S/UNI-VORTEX. Therefore, reader referred companion document provided PMC-Sierra titled S/UNI-VORTEX S/UNI-DUPLEX TECHNICAL OVERVIEW. document number PMC-981025 obtained various means described last page this document. remainder this data sheet will focus describing cell buffering flow control implemented S/UNI-VORTEX. 9.3.1 Downstream Traffic Flow Control S/UNI-VORTEX cell deep buffers each downstream LVDS links. Section 9.1.1 Page describe S/UNIVORTEX responds polling asserts signal when another cell safely written into these downstream cell buffers. will describe how, link basis, S/UNI-VORTEX schedules cells these cell buffers transmits them their LVDS link. describe individual link here, reader reminded that there scheduling interaction interdependence among LVDS links each cell buffer each scheduler. Downstream scheduling only occurs when previous cell been fully transmitted over downstream link. other words, once cell (data stuff cell) been scheduled entire cell sent before another cell scheduled. When there buffered data buffers S/UNIVORTEX generates stuff cell sends link. stuff cell meets requirements standard data cell, including valid system overhead information, stuff cells discarded far-end receiver. When there more non-empty buffers, S/UNI-VORTEX must decide which far-end channels PHYs microprocessor port) should have buffered cell scheduled onto downstream link. This decision consists steps: first channel that presenting far-end buffer full status (described below) eliminated from this scheduling round. far-end channels have full buffers stuff cell generated automatically. Otherwise, simple round robin algorithm used among remaining eligible channels share downstream link fairly schedule next cell sent.
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shown Table each cell transmitted over each eight upstream LVDS upstream links contains bits information that convey far-end cell buffer status (full full) maximum active PHYs supported each link. After cells received upstream link downstream buffer status far-end PHYs been updated. separate overhead cell conveys buffer status far-end microprocessor port. Hence, given instant S/UNI-VORTEX using information that either cells date. far-end device (typically S/UNI-DUPLEX) therefore required have enough buffer space accommodate slight delay conveying "buffer full" information S/UNI-VORTEX. S/UNI-VORTEX uses full full information determine which channels should involved current round scheduling, discussed above. 9.3.2 Upstream Traffic Flow Control upstream traffic flow control within S/UNI-VORTEX allows some system engineering flexibility. When system engineered such that maximum aggregate burst upstream bandwidth less than equal link device bandwidth each stage concentration, congestion will occur prior upstream traffic queuing device1. this case, upstream traffic flow control unnecessary will utilized within S/UNI-DUPLEX S/UNI-VORTEX devices. However, when system engineered such that upstream burst bandwidth capacity exceed link bandwidth, then depending over subscription employed, misbehaving users, traffic burst scenarios, congestion upstream S/UNI-VORTEX buffers occur. ensure that these buffers overflow, upstream traffic flow control implemented S/UNI-VORTEX S/UNI-DUPLEX. Far-end scheduling upstream channels microprocessor channel onto upstream LVDS link discussed S/UNIDUPLEX Data Sheet. This section discusses upstream flow control implemented prevent overflow S/UNI-VORTEX's upstream FIFOs. Unlike downstream direction, upstream direction does require channel buffering channel buffer status indication. S/UNI-VORTEX, each upstream LVDS serial links provided with simple cell FIFO. SCI-PHY/Any-PHY slave state machine services FIFOs with weighted round-robin algorithm presents data upstream
Upstream queues could congest restricted up-link capacity, which case appropriate congestion management algorithms within device should invoked.
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master single cell stream. Scheduling from S/UNI-VORTEX onto upstream described more fully Section 9.1.2 Page aggregate, upstream links burst data into S/UNI-VORTEX Gbps, which twice maximum bandwidth upstream bus. Further, master servicing several S/UNI-VORTEX devices once otherwise restricted maximum sustained bandwidth able receive from S/UNI-VORTEX. Therefore, potential overflow more cell upstream FIFOs real possibility. When upstream FIFO less than three empty cell buffers, deasserts cell available (CA[0]) sent system overhead corresponding downstream LVDS link (see Table responsibility device (typically S/UNI-DUPLEX) start sending stuff cells immediately upon indication that S/UNI-VORTEX accept more traffic. setting full mark cells S/UNI-VORTEX allows additional cells accepted after cell available deasserted. This accommodates far-end latency reaction CA[0] indication. Timing Reference Insertion Recovery high-speed LVDS links capable transporting timing reference both directions, independent LVDS rate. shown Table every cell transmitted over LVDS contains timing reference field called TREF[5:0]. Although timing reference targeted typical need transporting signal, frequency constrained kHz. frequency less than cell rate permissible. transmit direction, rising edges TX8K input encoded cells transmitted eight serial links. each LVDS links, rising edge TX8K causes internal counter initialized cell length minus counter decrements with each subsequent byte transmitted until fourth byte next extended cell, which point state counter written into outgoing TREF[5:0] field. rising edge TX8K occurred, TREF[5:0] ones. receive direction S/UNI-VORTEX typically receiving cells from S/UNI-DUPLEX device, which implements same TX8K process described above. determined value RX8KSEL[2:0] bits Master Configuration register, timing signal received over eight LVDS links recreated RX8K. S/UNI-VORTEX monitors TREF[5:0] field selected upstream LVDS link initializes internal counter value TREF[5:0] each time field received. counter decrements with each subsequent byte
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received. When count becomes zero, rising edge generated RX8K. value TREF[5:0] ones, RX8K remains low. RX8K left asserted high speed (REFCLK) reference clock periods, then deasserted. recovered timing event generated cell period later than inserted timing with resolution byte. Because limited resolution, some jitter present. link rate 155.52 Mb/s, 63ns peak-to-peak jitter will occur RX8K. external local high-Q phase locked loop (PLL) used remove jitter. JTAG Test Access Port JTAG Test Access Port block provides JTAG support boundary scan. standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE STCTEST instructions supported. S/UNI-VORTEX identification code 173510CD hexadecimal. Microprocessor Interface microprocessor interface provided device configuration, control monitoring external microprocessor. Normal mode registers test mode registers accessed through this port. Test mode registers used enhance testability S/UNI-VORTEX. interface 8-bit wide data bus. Multiplexed address data operation supported. 9.6.1 Inband Communication Channel provide flexibility, mechanisms being provided transport control channel. Control channel cells inserted extracted either microprocessor interface external device transferring control channel cells across SCI-PHY/Any-PHY interfaces. control channel cell insertion extraction capabilities provide simple unacknowledged (but flow controlled) cell relay capability. fully robust control channel implementation, assumed local microprocessor remote entity running reliable communications protocol. 9.6.2 Insertion Extraction SCI-PHY/Any-PHY Interfaces Control channel cells inserted downstream Any-PHY interface treated same manner normal data traffic with respect flow control, buffering, cell format. transmitting control cells across high-speed serial
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link throttled UPCA upstream cell prepends. UPCA reflects buffer availability line card. downstream direction, control channels eight links provided with polling address range Control Channel Base Address register. discussed Section 9.1.1, status each control channel discovered presenting TADR[11:0] value specified range. transferred control channel cell accepted when ADDR[11:0] field cell structure corresponds eight addresses specified Control Channel Base Address register. upstream direction, control channel cells given special treatment when they directed upstream SCI-PHY/Any-PHY bus. traffic management device identify them encoding "111110" ADDR[5:0] field cell prepend H5.UDF field. 9.6.3 Insertion Extraction Micro-Processor Interface Control cells inserted extracted through parallel microprocessor interface. 9.6.3.1 Writing Cells S/UNI-VORTEX contains cell buffer high-speed link insertion cell microprocessor onto high-speed serial links. Optional CRC-32 calculation over last bytes cell relieves microprocessor this task. CRC-32 generator polynomial consistent with AAL5: G(x)
cells written microprocessor will have binary 111110 encoded PHYID[5:0] field within cell prepend bytes. This distinction between user cells control cells provides clear channel both types cells. microprocessor cell format illustrated Fig. 8-bit cell data structure fixed bytes long regardless SCI-PHY/Any-PHY LVDS link configured. microprocessor must transfer bytes cell, including unused ones. unused bytes included received cell when made available far-end microprocessor, value bytes undefined. Bytes marked with asterisk Fig. must included cells written into cell transfer register, they will only sent across LVDS corresponding Transmit High-Speed Serial Configuration register far-
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end's corresponding Receive High-Speed Serial Configuration register have been programmed include them1. Other than what already been mentioned, there constraints contents cells written microprocessor. They transported across LVDS link transparently. Specifically, although standard Aheader bytes H1-H5 shown Fig. there restriction values they contain. Operation section details cell write protocol.
Obviously near must configure their corresponding High-Speed Serial Configuration registers such that high speed link format same both transmitter receiver receiver will always frame.
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Fig. Microprocessor Cell Format
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Unused Unused User Prepend User Prepend* Unused Unused PAYLOAD1
Byte
PAYLO AD48
*Depending serial link program ing, these fields undefined transm itted.
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9.6.3.2 Reading Cells default, control cells terminated Microprocessor Cell Buffer, instead routed SCI-PHY/Any-PHY interface along with other cells. Control cells that routed SCI-PHY/Any-PHY will stripped padded required) match cell format bus. redirection control cells must enabled ROUTECC register Master Configuration register. ROUTECC logic cells received high-speed serial link with binary 111110 PHYID[5:0] prepend field will routed Microprocessor Cell Buffer. buffer capacity four cells dedicated each high-speed link. control channel flow controlled avoid cell loss. maskable interrupt status upon receipt cell. format received cell when read from Microprocessor Cell Buffer Data register shown Fig. Unused bytes have undefined value. value optional bytes depends configuration corresponding LVDS link source cell. Control cells that come from far-end SCI-PHY/Any-PHY will have their optional fields defined only both SCI-PHY/Any-PHY LVDS link have been configured carry them. Control cells that come from far-end microprocessor port have their optional fields defined (i.e. equal value originally written far-end microprocessor) only LVDS link been configured carry them. This discussed further Operations section. Operation section details cell read protocol. Internal Registers microprocessor interface provides access normal test mode registers. normal mode registers required mission mode operation, test mode registers used enhance testability S/UNI-VORTEX. register accessed follows: Register Memory
Address 0x000 0x001 0x002 0x003 0x004
Register Master Reset Identity Load Performance Meters Master Configuration Receive Serial Interrupt Status Transmit Serial Interrupt Status Miscellaneous Interrupt Statuses
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0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 0x01A 0x01B 0x01C 0x01D 0x01E 0x07F 0x080 0x09F 0x0A0 0x0BF 0x0C0 0x0DF 0x0E0 0x0FF 0x100 0x11F 0x120 0x13F 0x140 0x15F 0x160 0x17F
Control Channel Base Address Control Channel Base Address Clock Monitor Downstream Cell Interface Configuration Reserved Downstream Cell Interface Interrupt Enable Downstream Cell Interface Interrupt Status Upstream Cell Interface Configuration Interrupt Status Reserved Microprocessor Cell Buffer Interrupt Control Status Microprocessor Insert FIFO Control Microprocessor Extract FIFO Control Microprocessor Insert FIFO Ready Microprocessor Extract FIFO Ready Insert CRC-32 Accumulator (LSB) Insert CRC-32 Accumulator (2nd byte) Insert CRC-32 Accumulator (3rd byte) Insert CRC-32 Accumulator (MSB) Extract CRC-32 Accumulator (LSB) Extract CRC-32 Accumulator (2nd byte) Extract CRC-32 Accumulator (3rd byte) Extract CRC-32 Accumulator (MSB) Microprocessor Cell Buffer Data Reserved Registers associated with RXD0+/- TXD0+/Registers associated with RXD1+/- TXD1+/Registers associated with RXD2+/- TXD2+/Registers associated with RXD3+/- TXD3+/Registers associated with RXD4+/- TXD4+/Registers associated with RXD5+/- TXD5+/Registers associated with RXD6+/- TXD6+/Registers associated with RXD7+/- TXD7+/-
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0x180 0x1FF 0x200 0x3FF
Reserved Reserved test registers.
9.8.1 Per-Link Registers Each pair serial links (RXDn+/- TXDn+/-) identical bank registers. These registers located within address space base address offset according following formula: register address 0x080 0x20*(link index) offset where link index Address Offset 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 Register Receive High-Speed Serial Configuration Receive High-Speed Serial Cell Filtering Configuration/Status Receive High-Speed Serial Interrupt Enables Receive High-Speed Serial Interrupt Status Receive High-Speed Serial Error Count Receive High-Speed Serial Cell Counter (LSB) Receive High-Speed Serial Cell Counter Receive High-Speed Serial Cell Counter (MSB) Receive High-Speed Serial FIFO Overflow Upstream Round Robin Weight Logical Channel Base Address Logical Channel Address Range Logical Channel Base Address Downstream Logical Channel FIFO Control Downstream Logical Channel FIFO Interrupt Status Reserved Downstream Logical Channel FIFO Ready Level Transmit High-Speed Serial Configuration Transmit High-Speed Serial Cell Count Status Transmit High-Speed Serial Cell Counter (LSB) Transmit High-Speed Serial Cell Counter Transmit High-Speed Serial Cell Counter (MSB) Serial Link Maintenance Reserved Transmit Oriented Code Oriented Code Receiver Enable
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0x019 0x01A 0x01B 0x01C 0x01D 0x01F
Receive Oriented Code Status Reserved Upstream Link FIFO Control Reserved
register accesses, must low.
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NORMAL MODE REGISTER DESCRIPTION Normal mode registers used configure monitor operation S/UNI-DUPLEX. Normal mode registers opposed test mode registers) selected when (A[8]) low. Notes Normal Mode Register Bits: Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions product, unused register bits must written with logic zero. Reading back unused bits produce either logic logic zero; hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling S/UNI-VORTEX determine programming state block. Writeable normal mode register bits cleared logic zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect S/UNIVORTEX operation unless otherwise noted. Certain register bits reserved. These bits associated with megacell functions that unused this application. ensure that S/UNI-VORTEX operates intended, reserved register bits must only written with logic zero. Similarly, writing reserved registers should avoided.
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Register 0x000: Master Reset Identity Load Performance Meters Type Function RESET TYPE[2] TYPE[1] TYPE[0] ID[3] ID[2] ID[1] ID[0] Default
This register allows revision number S/UNI-VORTEX read software permitting graceful migration newer, feature-enhanced versions S/UNI-VORTEX. addition, writing this register simultaneously loads performance meter registers S/UNI-VORTEX. ID[3:0]: bits read provide binary S/UNI-VORTEX revision number. TYPE[2:0]: TYPE bits read distinguish S/UNI-VORTEX from other members S/UNI family devices. RESET: RESET allows S/UNI-VORTEX reset under software control. RESET logic one, entire S/UNI-VORTEX held reset. This self-clearing. Therefore, logic zero must written bring S/UNI-VORTEX reset. Holding S/UNI-VORTEX reset state places into power, stand-by mode. hardware reset clears RESET bit, thus negating software reset. Otherwise, effect software reset equivalent that hardware reset with exception that Master Test Register (0x200) reset software reset. Register 0x200 should written after software reset ensure known state.
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Register 0x001: Master Configuration Type Function Reserved Unused MINTE TPAEN ROUTECC RX8KSEL[2] RX8KSEL[1] RX8KSEL[0] Default
RX8KSEL[2:0]: RX8KSEL select (RX8KSEL[2:0]) bits determine high-speed serial link from which RX8K derived. RX8K extracted from RXDn+/- serial link whose index equals binary RX8KSEL value. ROUTECC: ROUTECC determines upstream control channel cells handled. ROUTECC logic control channel cells presented RDAT[15:0] cell bus. ROUTECC logic control channel cells directed microprocessor port through four cell FIFO. TPAEN: Enable (TPAEN) determines whether output driven response polling. TPAEN logic unconditionally high impedance. TPAEN logic drives upon sampling TADR[11:0] value that lies range addresses specified Control Channel Base Address, Logical Channel Base Address Logical Channel Address Range registers. TPAEN should only logic after aforementioned registers have been initialized. MINTE: Master Interrupt Enable allows internal interrupt statuses propagated interrupt output. MINTE logic INTB will asserted upon assertion interrupt status whose individual enable set. MINTE logic INTB unconditionally high-impedance.
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Reserved: Reserved should logic correct operation.
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Register 0x002: Receive Serial Interrupt Status RXI[7:0]: This register indicates whether there pending interrupt particular serial link. RXI[n] associated with RXDn+/-. RXI[n] logic least interrupt status within associated Receive High-Speed Serial Interrupt Status, Receive High-Speed Serial FIFO Overflow Receive Oriented Code Status registers that corresponding enable logic These bits self-clearing; they only cleared logic reading associated Receive High-Speed Serial Interrupt Status, Receive High-Speed Serial FIFO Overflow Receive Oriented Code Status registers. Type Function RXI[7] RXI[6] RXI[5] RXI[4] RXI[3] RXI[2] RXI[1] RXI[0] Default
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Register 0x003: Transmit Serial Interrupt Status TXI[7:0]: This register indicates whether there pending interrupt particular serial link. TXI[n] associated with TXDn+/-. TXI[n] logic least interrupt status within associated Transmit High-Speed Serial Cell Count Status Downstream Logical Channel FIFO Interrupt Status registers that corresponding enable logic These bits self-clearing; they only cleared logic reading associated Transmit High-Speed Serial Cell Count Status Downstream Logical Channel FIFO Interrupt Status registers. Type Function TXI[7] TXI[6] TXI[5] TXI[4] TXI[3] TXI[2] TXI[1] TXI[0] Default
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Register 0x004: Miscellaneous Interrupt Statuses DCIFI: This indicates whether there pending interrupt Downstream Cell Interface. DCIFI logic least interrupt status within Downstream Cell Interface Interrupt Status register that corresponding enable logic This self-clearing; only cleared logic reading Downstream Cell Interface Interrupt Status register. UCIFI: This indicates whether there pending interrupt Upstream Cell Interface. UCIFI logic interrupt status Upstream Cell Interface Configuration Interrupt Status register corresponding enable logic This self-clearing; only cleared logic reading Upstream Cell Interface Configuration Interrupt Status register. UPCBI: This indicates whether there pending interrupt Microprocessor Cell Buffer. UPCBI logic least interrupt status within Microprocessor Cell Buffer Interrupt Control Status register that corresponding enable logic This self-clearing; only cleared logic reading Microprocessor Cell Interrupt Status register. Type Function Unused Unused Unused Unused ROOLI UPCBI UCIFI DCIFI Default
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PM7351 S/UNI-VORTEX
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ROOLI: Reference Lock interrupt (ROOLI) status logic ROOLV Clock Monitor register changed state since last time this register read. ROOLI reset when this register read.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x005: Control Channel Base Address CCBA[10:3] This register conjunction with CCBA[11] Control Channel Base Address register determines location control channels S/UNI-VORTEX within available address space purposes polling transfer selection. This register only relevant downstream direction; address remapping done upstream. value CCBA[11:3]*8 subtracted from TADR[11:0] input value sampled. difference less than will drive buffer availability status (provided TPAEN register logic control channel whose link index (the TXDn+/- RXDn+/-) matches difference. value CCBA[11:3]*8 subtracted from ADDR[11:0] value encoded cell structures (see Fig. received TDAT[15:0]. difference less than cell shall written control channel buffer whose link index matches difference. Type Function CCBA[10] CCBA[9] CCBA[8] CCBA[7] CCBA[6] CCBA[5] CCBA[4] CCBA[3] Default
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x006: Control Channel Base Address CCBA[11] This most significant Control Channel Base Address. Type Function Unused Unused Unused Unused Unused Unused Unused CCBA[11] Default
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x007: Clock Monitor Type Function Unused Unused Unused ROOLE ROOLV REFCLKA RCLKA TCLKA Default
This register provides activity monitoring S/UNI-VORTEX clocks. When monitored clock signal makes high transition, corresponding register high. will remain high until this register read, which point, bits this register cleared. lack transitions indicated corresponding register reading low. This register should read periodic intervals detect clock failures. register also reports state clock synthesis unit that generates internal clocks. TCLKA: TCLK active (TCLKA) monitors high transitions TCLK transmit FIFO clock input. TCLKA high rising edge TCLK, when this register read. RCLKA: RCLK active (RCLKA) monitors high transitions RCLK receive FIFO clock input. RCLKA high rising edge RCLK, when this register read. REFCLKA: REFCLK active (REFCLKA) monitors high transitions REFCLK reference clock input. REFCLKA high rising edge REFCLK, when this register read.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
ROOLV: reference lock status indicates clock synthesis phase locked loop unable lock reference REFCLK. ROOLV logic synthesized clock frequency within eight times REFCLK frequency. ROOLE: ROOLE interrupt enable transmit reference lock status. When ROOLE Master Interrupt Enable Master Configuration register logic one, INTB output asserted when ROOLV changes state.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x008: Downstream Cell Interface Configuration PTYP: Parity Type (PTYP) selects even parity input TPRTY. When logic TPRTY even parity TDAT[15:0]. When logic TPRTY parity TDAT[15:0]. PREPEND: PREPEND determines whether word prepended each cell. When PREPEND logic optional "Word illustrated Fig. included data structure expected TDAT[15:0]. Reserved: Reserved should logic correct operation. INADDUDF: INADDUDF (inband addressing byte) re-locates inband address. When this set, logical channel address band selection located twelve lower bits bytes there extended address word front prepend word. H5UDF must also (its default value) this interface will function correctly. Although ability carry inband address H5/UDF fields provided compatibility with devices that cannot generate prepend, there couple constraints that must respected this configuration: Type Function H5UDF Unused Unused INADDUDF Reserved PREPEND Unused PTYP Default
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
logical channel participating cell transfer cannot polled until nine TCLK periods after cell transfer complete. Once cell transfer started, TENB input must remain until after H5/UDF word been transferred. After that, permissible TENB toggle high momentarily halt cell transfer. H5UDF: H5UDF determines whether H5/UDF octets included cells transferred over interface. When H5UDF logic (default), octets included, i.e. optional "Word illustrated Fig. included data structure expected TDAT[15:0].
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x00A: Downstream Cell Interface Interrupt Enable Type Function Unused Unused Unused Unused Unused Reserved CELLXFERRE PARERRE Default
Master Interrupt Enable Master Configuration register must also logic these enables take effect. CELLXFERRE: Cell Transfer Error Interrupt Enable (CELLXFERRE) register interrupt enable invalid start cell. When start cell occurs when expected, INTB asserted this logic external interrupt generated this zero (Even interrupt enabled, always reported Downstream Cell Interface Interrupt Status register). PARERRE: Parity Error Interrupt Enable (PARRERRE) register interrupt enable invalid parity over TDAT[15:0] data bus. When parity error occurs over TDAT[15:0] data bus, external interrupt generated this one. external interrupt generated this zero (Even interrupt enabled, always reported Downstream Cell Interface Interrupt Status register). Reserved: This must logic correct operation.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x00B: Downstream Cell Interface Interrupt Status CELLXFERRI: Cell Transfer Error Interrupt Status (CELLXFERRI) read only register reports current status interrupt invalid start cell. When asserted when expected, interrupt generated. interrupt reset when this register read. same event that asserts this also result corrupted cell being transmitted high-speed serial link. PARERRI: Parity Error Interrupt Status (PARERRI) read only register reports current status interrupt invalid parity over input data bus. When parity error occurs over TDAT[15:0] data bus, interrupt generated. interrupt reset when this register read. Type Function Unused Unused Unused Unused Unused Unused CELLXFERRI PARERRI Default
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x00C: Upstream Cell Interface Configuration Interrupt Status PTYP: Parity Type (PTYP) selects even parity RPRTY output. When logic RPRTY completes even parity RDAT[15:0]. When logic RPRTY completes parity bits RDAT[15:0]. PREPEND: PREPEND determines whether word prepended each cell. When PREPEND logic optional "Word illustrated Fig. included data structure presented RDAT[15:0]. Reserved: This must logic correct operation. H5UDF: H5UDF determines whether H5/UDF octets included cells transferred over interface. When H5UDF logic (default), octets included, i.e. optional "Word illustrated Fig. included data structure presented RDAT[15:0]. INADDUDF: INADDUDF (inband addressing byte) re-locates inband address. When this set, logical channel address band selection located fourteen lower bits bytes there extended address word front prepend word. This supercedes H5UDF bit, that forces inclusion "Word This effect RANYPHY input logic Type Function CELLXFERRI CELLXFERRE Unused INADDUDF H5UDF Reserved PREPEND PTYP Default
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
CELLXFERRE: Cell Transfer Error Interrupt Enable (CELLXFERRE) allows generation interrupt invalid selection external master device. This occurs when cell transfer attempted, VORTEX indicated cell available returning when polled. When CELLXFERRE logic INTB output asserted when CELLXFERRI logic CELLXFERRI: CELLXFERRI provides status Cell Transfer Error Interrupt. This interrupt status asserted when external master device selects Upstream Cell Interface (i.e. RADR[4:0] value equals state VADR[4:0] when RENB last sampled high) transfer without cell being available. This does indicate case where RENB held beyond cell transfer, when there second cell transfer. This reset immediately after read this register.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x010: Microprocessor Cell Buffer Interrupt Control Status Type Function EXTCRCERRI EXTRDYI INSOVRI INSRDYI EXTCRCERRE EXTRDYE INSOVRE INSRDYE Default
Master Interrupt Enable Master Configuration register must also logic interrupt enables take effect. INSRDYE: INSRDYE allows generation interrupt when Insert FIFO becomes available. When INSRDYE logic INTB output asserted when INSRDYI logic INSOVRE: INSOVRE controls generation interrupt upon overflow insert buffer. When INSOVRE logic INTB output asserted when INSOVRI logic EXTRDYE: EXTRDYE allows generation interrupt when Extract FIFO becomes ready. When EXTRDYE logic INTB output asserted when EXTRDYI logic EXTCRCERRE: EXTCRCERRE controls generation interrupt upon CRC32 error. When EXCRCERRE logic INTB output asserted when EXTCRCERRI logic INSRDYI: INSRDYI provides status Insert FIFOs Ready Interrupt. This logic when Insert FIFOs becomes ready accept
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
cell (i.e. cell transferred from full FIFO) upon completion cell write least more cell written. ready status specific FIFO indicated logic corresponding Microprocessor Insert FIFO Ready register. INSRDYI reset immediately after read this register. INSOVRI: INSOVRI indicates status write access Microprocessor Insert FIFO. This logic when write access being attempted full Microprocessor Insert FIFO data been discarded. This reset immediately after read this register. EXTRDYI: EXTRDYI provides status Microprocessor Extract FIFOs Ready Interrupt. This logic when Microprocessor Extract FIFOs becomes ready cell read (i.e. upon reception only cell FIFO) upon completion cell read there least more cell read from FIFO. Ready status specific FIFO indicated logic corresponding Microprocessor Extract FIFO Ready register. EXTRDYI reset immediately after read this register. EXTCRCERRI: EXTCRCERRI indicates CRC-32 status cell read from Extract FIFO. When EXTCRCCHK logic EXTCRCERRI updated when last byte cell read microprocessor. logic value Extract Accumulator register differs from expected CRC-32 remainder polynomial. Otherwise, logic This also reset immediately after read this register.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x011: Microprocessor Insert FIFO Control Type Function Unused Unused INSCRCEND INSCRCPR INSRST INSFSEL[2] INSFSEL[1] INSFSEL[0] Default
INSFSEL[2:0]: INSFSEL[2:0] bits used select eight Microprocessor Insert FIFOs cell write operation. Insert FIFO selected prior starting cell transfer. value INSFSEL[2:0] corresponds index serial link (i.e. TXDn+/-) which cell will presented. Microprocessor Insert FIFO selected prior starting cell transfer. synchronization delays, read Microprocessor Cell Buffer Data register should initiated until REFCLK periods after completion write these bits. INSRST: INSRST allows microprocessor abort cell write Microprocessor Insert FIFO. INSRST logic when previously logic insert write pointer reset without completing transaction. Setting INSRST after last write (i.e. beginning next cell) effect. abort cell, microprocessor must have written least first byte cell less than bytes. INSRST readable. This cleared every write Microprocessor Cell Data register. INSCRCPR: INSCRCPR used force value Insert CRC-32 accumulation register preset value. INSCRCPR logic Insert CRC-32 accumulation register kept preset value. INSCRCPR logic CRC-32 calculations performed inserted cells. CRC-
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
calculations performed cell payload bytes being written Microprocessor Cell Data register. synchronization delays, write Microprocessor Cell Buffer Data register should initiated until REFCLK periods after completion write this bit. INSCRCEND: INSCRCEND used indicate that following inserted cell last CPCS-PDU. Setting this logic will cause last four bytes cell transferred from microprocessor replaced value ones complement Insert CRC-32 Accumulation register.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x012: Microprocessor Extract FIFO Control Type Function Unused Unused EXTCRCCHK EXTCRCPR EXTABRT EXTFSEL[2] EXTFSEL[1] EXTFSEL[0] Default
EXTFSEL[2:0]: EXTFSEL [2:0] bits used select eight Microprocessor Extract FIFOs cell read operation. value EXTFSEL[2:0] corresponds index serial link (i.e. RXDn+/-) which cell received. Microprocessor Extract FIFO selected prior starting cell transfer. synchronization delays, read Microprocessor Cell Buffer Data register should initiated until REFCLK periods after completion write these bits. EXTABRT: EXTABRT allows microprocessor discard cell without reading remaining contents. EXTABRT logic when previously logic extract pointer reset, effectively discarding remaining contents cell. Setting EXTABRT after last read (i.e. beginning next cell) effect. abort cell, microprocessor must have read least first word cell more than bytes. synchronization delays, cell extraction operation should initiated until REFCLK periods after completion write this bit. EXTABRT readable. cleared every read from normal mode Microprocessor Cell Data register.
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RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
EXTCRCPR: EXTCRCPR used force value Extract CRC-32 accumulation register preset value. EXTCRCPR logic Insert CRC-32 accumulation register kept preset value. EXTCRCPR logic CRC-32 verification performed extracted cells. CRC-32 calculations performed bytes being read from location Microprocessor Cell Data register corresponding payload extract cells. synchronization delays, read Microprocessor Cell Buffer Data register should initiated until REFCLK periods after completion write this bit. EXTCRCCHK: EXTCRCCHK used enable CRC-32 field check. Setting this logic will cause S/UNI-VORTEX verify value Extract CRC-32 Accumulation register equal expected CRC-32 remainder polynomial cell read access microprocessor. EXTCRCCHK logic EXTCRCERRI will logic CRC-32 incorrect.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x013: Microprocessor Insert FIFO Ready INSRDY[7:0]: INSRDY[7:0] bits provide ready status Microprocessor Insert FIFOs. logic INSRDY[7:0] indicates that corresponding Microprocessor Insert FIFO ready accept cell. index corresponds serial link index. Note that INSRDY FIFO currently being written will always return logic Type Function INSRDY[7] INSRDY[6] INSRDY[5] INSRDY[4] INSRDY[3] INSRDY[2] INSRDY[1] INSRDY[0] Default
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x014: Microprocessor Extract FIFO Ready EXTRDY[7:0]: EXTRDY[7:0] bits provide ready status Microprocessor Extract FIFOs. logic EXTRDY[7:0] indicates that corresponding Microprocessor Extract FIFO least cell available reading. index corresponds serial link index. Note that EXTRDY FIFO currently being read will always return logic Type Function EXTRDY[7] EXTRDY[6] EXTRDY[5] EXTRDY[4] EXTRDY[3] EXTRDY[2] EXTRDY[1] EXTRDY[0] Default
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x015: Insert CRC-32 Accumulator (LSB) Type Function INSCRCACC[7] INSCRCACC[6] INSCRCACC[5] INSCRCACC[4] INSCRCACC[3] INSCRCACC[2] INSCRCACC[1] INSCRCACC[0] Default
Register 0x016: Insert CRC-32 Accumulator (2nd byte) Type Function INSCRCACC[15] INSCRCACC[14] INSCRCACC[13] INSCRCACC[12] INSCRCACC[11] INSCRCACC[10] INSCRCACC[9] INSCRCACC[8] Default
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980582 ISSUE
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
Register 0x017: Insert CRC-32 Accumulator (3rd byte) Type Function INSCRCACC[23] INSCRCACC[22] INSCRCACC[21] INSCRCACC[20] INSCRCACC[19] INSCRCACC[18] INSCRCACC[17] INSCRCACC[16] Default
Register 0x018: Insert CRC-32 Accumulator (MSB) Type Function INSCRCACC[31] INSCRCACC[30] INSCRCACC[29] INSCRCACC[28] INSCRCACC[27] INSCRCACC[26] INSCRCACC[25] INSCRCACC[24] Default
INSCRCACC[31:0]: four registers INSCRCACC[31:0] allows microprocessor read write contents Insert Accumulator register. This register accumulates CRC-32 value over data being written Microprocessor Insert FIFO. rising edge successive write a
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