PM7350 S/UNI-DUPLEX DUAL SERIAL LINK MULTIPLEXER PM7350 S/UN
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
PM7350 S/UNI
DUPLEX
S/UNI-DUPLEX
DUAL SERIAL LINK, MULTIPLEXER
DATA SHEET
RELEASED ISSUE APRIL 2000
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
REVISION HISTORY
Issue Issue
Issue Date April 2000
Originator Phil Walston
Details Change Updated analog parameters, IDDOP, thermal info corrected register description typos. Release production. Updated incorporate Revision changes outinled previous Errata. Change bars highlight specific changes. Changed confidentiality notices document's public release. Extensive updates throughout First release
Issue
February 2000
Phil Walston
Issue Issue Issue
June 1999 May, 1999 May, 1998
James Lamothe Jeff Brown Jeff Brown
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
CONTENTS FEATURES APPLICATIONS REFERENCES. APPLICATION EXAMPLES BLOCK DIAGRAM DESCRIPTION DIAGRAM DESCRIPTION. FUNCTIONAL DESCRIPTION. PARALLEL INTERFACE CLOCKED SERIAL DATA INTERFACE HIGH-SPEED SERIAL INTERFACE CELL BUFFERING FLOW CONTROL TIMING REFERENCE INSERTION RECOVERY JTAG TEST ACCESS PORT. MICROPROCESSOR INTERFACE INTERNAL REGISTERS REGISTER MEMORY
NORMAL MODE REGISTER DESCRIPTION TEST FEATURES DESCRIPTION 11.1 11.2 BUILT-IN-SELF-TEST JTAG TEST PORT
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
OPERATION 12.1 12.2 12.3 12.4 12.5 MICROPROCESSOR INBAND COMMUNICATION INTERACTION BETWEEN LVDS CONFIGURATIONS MAXIMUM CELL RATE MINIMUM PROGRAMMING JTAG SUPPORT
FUNCTIONAL TIMING. 13.1 13.2 SCI-PHY/ANY-PHY INTERFACE CLOCKED SERIAL DATA INTERFACE
ABSOLUTE MAXIMUM RATINGS D.C. CHARACTERISTICS .211 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS. A.C. TIMING CHARACTERISTICS. ORDERING THERMAL INFORMATION. MECHANICAL INFORMATION.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
LIST REGISTERS REGISTER 0X00: MASTER RESET IDENTITY LOAD PERFORMANCE METERS REGISTER 0X01: MASTER CONFIGURATION REGISTER 0X02: MASTER INTERRUPT STATUS REGISTER 0X03: MISCELLANEOUS INTERRUPT STATUS REGISTER 0X04: CLOCK MONITOR. REGISTER 0X05: SERIAL LINKS MAINTENANCE REGISTER 0X06: EXTENDED ADDRESS MATCH (LSB). REGISTER 0X07: EXTENDED ADDRESS MATCH (MSB). REGISTER 0X08: EXTENDED ADDRESS MASK (LSB) REGISTER 0X09: EXTENDED ADDRESS MASK (MSB) REGISTER 0X0A: OUTPUT ADDRESS MATCH REGISTER 0X0B: CONFIGURATION PINS STATUS. REGISTER 0X0C: SCI-PHY/ANY-PHY INPUT CONFIGURATION REGISTER 0X0D: SCI-PHY/ANY-PHY INPUT CONFIGURATION REGISTER 0X0E: SCI-PHY/ANY-PHY INPUT INTERRUPT ENABLES REGISTER 0X0F: SCI-PHY/ANY-PHY INPUT INTERRUPT STATUS REGISTER 0X10: INPUT CELL AVAILABLE ENABLE (LSB). REGISTER 0X11: INPUT CELL AVAILABLE ENABLE (2ND) REGISTER 0X12: INPUT CELL AVAILABLE ENABLE (3RD) .110 REGISTER 0X13: INPUT CELL AVAILABLE ENABLE (MSB).110 REGISTER 0X14: SCI-PHY/ANY-PHY OUTPUT CONFIGURATION.112 REGISTER 0X15: SCI-PHY/ANY-PHY OUTPUT POLLING RANGE .115
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
REGISTERS 0X18, 0X1A: RXD1, RXD2 ORIENTED CODE RECEIVER ENABLE.116 REGISTER 0X19, 0X1B: RXD1, RXD2 RECEIVE ORIENTED CODE STATUS .117 REGISTERS 0X1D, 0X1F: TXD1, TXD2 TRANSMIT ORIENTED CODE.118 REGISTER 0X20: MICROPROCESSOR CELL BUFFER INTERRUPT.119 REGISTER 0X21: MICROPROCESSOR INSERT FIFO CONTROL. REGISTER 0X22: MICROPROCESSOR EXTRACT FIFO CONTROL REGISTER 0X23: MICROPROCESSOR INSERT FIFO READY. REGISTER 0X24: MICROPROCESSOR EXTRACT FIFO READY REGISTER 0X25: INSERT CRC-32 ACCUMULATOR (LSB). REGISTER 0X26: INSERT CRC-32 ACCUMULATOR (2ND). REGISTER 0X27: INSERT CRC-32 ACCUMULATOR (3RD). REGISTER 0X28: INSERT CRC-32 ACCUMULATOR (MSB) REGISTER 0X29: EXTRACT CRC-32 ACCUMULATOR (LSB) REGISTER 0X2A: EXTRACT CRC-32 ACCUMULATOR (2ND) REGISTER 0X2B: EXTRACT CRC-32 ACCUMULATOR (3RD) REGISTER 0X2C: EXTRACT CRC-32 ACCUMULATOR (MSB). REGISTER 0X2D: MICROPROCESSOR CELL DATA. REGISTER 0X30: RXD1 EXTRACT FIFO CONTROL REGISTER 0X31: RXD1 EXTRACT FIFO INTERRUPT STATUS. REGISTER 0X34: RXD2 EXTRACT FIFO CONTROL REGISTER 0X35: RXD2 EXTRACT FIFO INTERRUPT STATUS. REGISTER 0X3C: RECEIVE LOGICAL CHANNEL FIFO CONTROL.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
REGISTER 0X3D:RECEIVE LOGICAL CHANNEL FIFO INTERRUPT STATUS REGISTERS 0X40, 0X50: RXD1, RXD2 HIGH-SPEED SERIAL CONFIGURATION REGISTERS 0X41, 0X51: RXD1, RXD2 HIGH-SPEED SERIAL CELL FILTERING CONFIGURATION/STATUS REGISTERS 0X42, 0X52: RXD1, RXD2 HIGH-SPEED SERIAL INTERRUPT ENABLES REGISTERS 0X43,0X53: RXD1, RXD2 HIGH-SPEED SERIAL INTERRUPT STATUS REGISTERS 0X44, 0X54: RXD1, RXD2 HIGH-SPEED SERIAL ERROR COUNT REGISTERS 0X45, 0X55: RXD1, RXD2 HIGH-SPEED SERIAL CELL COUNTER (LSB) REGISTERS 0X46, 0X56: RXD1, RXD2 HIGH-SPEED SERIAL CELL COUNTER REGISTERS 0X47, 0X57: RXD1, RXD2 HIGH-SPEED SERIAL CELL COUNTER (MSB) REGISTER 0X5C: TRANSMIT LOGICAL CHANNEL FIFO CONTROL REGISTER 0X5D: TRANSMIT LOGICAL CHANNEL FIFO INTERRUPT STATUS150 REGISTER 0X5E: TRANSMIT LOGICAL CHANNEL FIFO DEPTH. REGISTER 0X60: TRANSMIT HIGH-SPEED SERIAL CONFIGURATION REGISTER 0X61: TRANSMIT HIGH-SPEED SERIAL CELL COUNT STATUS REGISTER 0X62: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (LSB) REGISTER 0X63: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER REGISTER 0X64: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (MSB)
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
REGISTER 0X68: RECEIVE SERIAL INDIRECT CHANNEL SELECT REGISTER 0X69: RECEIVE SERIAL INDIRECT CHANNEL CONFIGURATION REGISTER 0X6A: RECEIVE SERIAL INDIRECT CHANNEL INTERRUPT ENABLES REGISTER 0X6B: RECEIVE SERIAL INDIRECT CHANNEL INTERRUPT STATUS REGISTER 0X6C: RECEIVE SERIAL INDIRECT CHANNEL ERROR COUNT REGISTER 0X6D: RECEIVE SERIAL COUNT THRESHOLD REGISTER 0X70: TRANSMIT SERIAL INDIRECT CHANNEL SELECT REGISTER 0X71:TRANSMIT SERIAL INDIRECT CHANNEL DATA REGISTER 0X74:TRANSMIT SERIAL ALIGNMENT CONTROL REGISTER 0X80: MASTER TEST REGISTER 0X83: MISCELLANEOUS TEST
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
LIST FIGURES FIG. TYPICAL TARGET APPLICATION FIG. THREE STAGE MULTIPLEX ARCHITECTURE. FIG. CLOCK DATA INTERFACE FIG. S/UNI-DUPLEX S/UNI-DUPLEX APPLICATIONS. FIG. S/UNI-DUPLEX S/UNI-DUPLEX PROTECTION SWITCHING FIG. EIGHT SCI-PHY/UTOPIA/ANY-PHY CELL FORMAT. FIG. SIXTEEN SCI-PHY/UTOPIA/UTOPIA CELL FORMAT. FIG. CELL DELINEATION STATE DIAGRAM. FIG. HIGH-SPEED SERIAL LINK DATA STRUCTURE FIG. DATAPATH LOOPBACK FIG. MICROPROCESSOR CELL FORMAT FIG. INPUT OBSERVATION CELL (IN_CELL) FIG. OUTPUT CELL (OUT_CELL). FIG. BIDIRECTIONAL CELL (IO_CELL). FIG. LAYOUT OUTPUT ENABLE BIDIRECTIONAL CELLS FIG. BOUNDARY SCAN ARCHITECTURE FIG. CONTROLLER FINITE STATE MACHINE FIG. SCI-PHY INTERFACE, INPUT SLAVE TRANSFER TIMING. FIG. SCI-PHY INTERFACE, INPUT MASTER TRANSFER TIMING FIG. ANY-PHY INTERFACE, INPUT SLAVE TRANSFER TIMING. FIG. SCI-PHY INTERFACE, OUTPUT SLAVE TRANSFER TIMING. FIG. SCI-PHY INTERFACE, OUTPUT MASTER TRANSFER TIMING
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
FIG. ANY-PHY INTERFACE, OUTPUT SLAVE TRANSFER TIMING FIG. CLOCKED SERIAL DATA TRANSMIT INTERFACE FIG. CLOCKED SERIAL DATA TRANSMIT INTERFACE, FIG. CLOCKED SERIAL DATA TRANSMIT INTERFACE, FIG. CLOCKED SERIAL DATA RECEIVE INTERFACE. FIG. MICROPROCESSOR INTERFACE READ TIMING FIG. MICROPROCESSOR INTERFACE WRITE TIMING FIG. RSTB TIMING FIG. INGRESS SCI-PHY/ANY-PHY INTERFACE TIMING. FIG. EGRESS SCI-PHY/ANY-PHY INTERFACE TIMING. FIG. CLOCKED SERIAL DATA INTERFACE FIG. JTAG PORT INTERFACE TIMING.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
LIST TABLES TABLE SIGNAL NAME CROSS-REFERENCE TABLE EIGHT SCI-PHY/UTOPIA MASTER, INPUT CONFIGURATION TABLE SIXTEEN SCI-PHY/UTOPIA MASTER, INPUT CONFIGURATION TABLE EIGHT SCI-PHY/UTOPIA MASTER, OUTPUT CONFIGURATION TABLE SIXTEEN SCI-PHY/UTOPIA MASTER, OUTPUT CONFIGURATION TABLE EIGHT SCI-PHY/UTOPIA SLAVE, INPUT CONFIGURATION TABLE SIXTEEN SCI-PHY/UTOPIA SLAVE, INPUT CONFIGURATION TABLE EIGHT SCI-PHY/UTOPIA SLAVE, OUTPUT CONFIGURATION TABLE SIXTEEN SCI-PHY/UTOPIA SLAVE, OUTPUT CONFIGURATION TABLE SCI-PHY/UTOPIA ANY-PHY COMPARISON, INGRESS DIRECTION TABLE EIGHT ANY-PHY SLAVE, INPUT CONFIGURATION TABLE SIXTEEN ANY-PHY SLAVE, INPUT CONFIGURATION TABLE SCI-PHY/UTOPIA ANY-PHY COMPARISON, EGRESS DIRECTION TABLE EIGHT ANY-PHY SLAVE, OUTPUT CONFIGURATION. TABLE SIXTEEN SCI-PHY/UTOPIA SLAVE, OUTPUT CONFIGURATION TABLE PREPENDED FIELDS.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
TABLE ASSIGNED ORIENTED CODES TABLE BOUNDARY SCAN REGISTER TABLE LVDS LINK BYTE CELL CONFIGURATIONS TABLE LVDS LINK BYTE CELL CONFIGURATIONS TABLE LVDS LINK BYTE CELL CONFIGURATIONS TABLE LVDS LINK BYTE CELL CONFIGURATIONS TABLE LVDS LINK BYTE CELL CONFIGURATIONS WITH
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
FEATURES Integrated analog/digital device that interfaces high-speed parallel high speed Voltage Differential Signal (LVDS) serial link with optional protection. framers modems without Utopia interfaces S/UNI-DUPLEX provides cell delineation (I.432) across clock data (bit serial) interfaces. Fault detection, redundancy, protection switching, inserting/removing cards while system running (hot swap). Interface other S/UNI-DUPLEX S/UNI-VORTEX, satisfy full system level requirements backplane interconnect: Transports user data providing inter-card data-path. Inter-processor communication providing integrated inter-card control channel. Exchanges flow control information (back-pressure) prevent data loss. Provides embedded command control signals across backplane: system reset, error indications, protection switching commands, etc. Clock/timing distribution (system clocks well reference clocks such timing references).
When used parallel slave device, configured share with other S/UNI-DUPLEX slave devices. interface another S/UNI-DUPLEX device (via single LVDS link) create simple point-to-point "Utopia extension" capability. interface S/UNI-DUPLEX devices create protected extension. Interworks with PM7351 S/UNI-VORTEX devices implement point-tomultipoint serial backplane architecture, with optional protection common card. LVDS receive direction: selects traffic from LVDS link marked active demultiplexes individual cell streams appropriate device.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Cell read/write both LVDS links available through processor port. Provides optional hardware assisted CRC32 calculation across cells support embedded inter-processor communication channel across LVDS links. Requires external memories. Standard P1149.1 JTAG test port. Low-power, 3.3V CMOS technology. 160-pin high-performance plastic ball grid array (PBGA) package.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
APPLICATIONS Single shelf multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM). ATM, frame relay, switch. Multiservice access multiplexer. Universal Mobile Telecommunication System (UMTS) wireless base stations. channel cell delineation (I.432 transmission convergence processing).
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
REFERENCES PMC-Sierra; "Saturn Compatible Interface APHY Layer ALayer Devices, Level PMC-940212; Dec. 1995 AForum, "Universal Test Operations Interface A(UTOPIA), Level Version 1.0, af-phy-0039.000, June 1995 PMC-Sierra; "Saturn Interface Specification Interoperability Framework Packet Cell Transfer Between Physical Layer Link Layer Devices", PMC-980902, Draft Draft American National Standard Telecommunications T1.413 Issue "Network Customer Installation Interfaces Asymmetric Digital Subscriber Line (ADSL) Metallic Interface", ANSI T1.413-1998, November 1998 ITU-T Recommendation I.432.1, "B-ISDN user-network interface Physical layer specification: General characteristics", 08/96
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
APPLICATION EXAMPLES When designing communication equipment such access switches, multiplexers, wireless base stations, base station controllers equipment architect faced with common problem: efficiently connect large number lower speed ports small number high speed ports? Typically, number line-side ports (analog modems, xDSL modems APHYs, modems) terminated each line card. Numerous line cards then slotted into more shelves backplane traces inter-shelf cables used connect line cards centralized (often protected) common card, hereafter referred core card. core card normally includes more high speed up-link ports that transport traffic from high speed broadband network. block diagram redundant system shown Fig. Fig. Typical Target Application
Modem Modem Modem Line Card S/UNIDUPLEX S/UNIVORTEX Policing OA&M Buffering Discard Scheduling up-link
OA&M
Card
Modem Modem Modem
Line Card S/UNIDUPLEX
S/UNIVORTEX
Policing OA&M
Buffering Discard Scheduling
OA&M
up-link
Card
this type equipment majority (perhaps all) user traffic goes from port line port, from line port port. Although individual ports line cards often relatively speed interfaces such xDSL, there many ports line card many line cards system, resulting hundreds even thousands lines terminating single up-link. upstream direction (from line card up-link), equipment must have capacity buffer intelligently manage bursts upstream traffic simultaneously from numerous line cards.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
downstream direction equipment must handle similar issue, "big pipe feeding little pipe" problem. When large burst traffic destined single line port received high speed port must buffered managed queues waiting much lower speed line port clear. line cards always most numerous cards this type equipment. individual line card, even terminates dozen speed ports, does generate receive enough traffic justify putting complex buffering traffic management devices ideal architecture cost "dumb" line cards feature rich, "smart" core card. order enhance fault tolerance, architecture should also inherently support protection using redundant core card up-link without significantly increasing line card complexity. system architecture that keeps buffering traffic management line card with typically exhibit following features: Connection setup simpler both terms programming during execution because there minimal requirement line intervention during connection setup process. In-service feature upgrades simpler because feature complexity limited common equipment. Component costs reduced, while system reliability increases reduced component count. this type architecture there often three stages signal concentration multiplexing, shown
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Fig. Three Stage Multiplex Architecture
Modem Modem Modem Line Card
S/UNIDUPLEX
Modem Modem Modem
Line Card
S/UNIDUPLEX
S/UNIVORTEX
S/UNIVORTEX
Policing OA&M
Buffering Discard Scheduling
OA&M Card
up-link
Modem Modem Modem
Line Card
S/UNIDUPLEX
first stage resides line card spans only those ports physically terminated that card. Since confined single card, this first stage multiplexing readily lends itself simple parallel based multiplex topology implemented S/UNI-DUPLEX. second stage concentration occurs between core card(s) line cards, including line cards that separate shelf. This second stage best served redundant serial point-to-point technology. third stage multiplexing optional resides core card. This third stage used systems with large number line cards that require several devices terminate second stage aggregation. Since third stage aggregation confined core card, lends itself readily parallel implementation. This three stage approach implemented directly S/UNI-DUPLEX sister device, S/UNI-VORTEX. S/UNI-DUPLEX acts line card's master. implements first stage multiplexing routing traffic from PHYs transmitting traffic simultaneously over high speed (200 Mbps) serial 4-wire LVDS links. serial link attaches active core card, other standby core card. downstream direction S/UNI-DUPLEX demultiplexes traffic from active core card's LVDS serial link routes this traffic appropriate PHYs. active core card LVDS link) should fail, protection switching commands embedded spare LVDS link will direct S/UNI-DUPLEX start receiving traffic from this spare link.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
S/UNI-VORTEX resides core card terminates LVDS links connected S/UNI-DUPLEX devices. S/UNI-VORTEX implements second stage multiplexing. More than S/UNI-VORTEX will required more than links required will case system with more than line cards. S/UNI-VORTEX device(s) share high speed parallel with core card's traffic management OA&M layers, implemented devices such PMC-Sierra's S/UNI-APEX S/UNI-ATLAS. Some applications framer modem devices without integrated I.432 processing1 normally support clock data interface, rely external circuitry detect generate Acell framing overhead. support these applications, S/UNI-DUPLEX provides clock data mode2. this mode, input/output pins that normally interface Utopia configured support clock data serial interfaces. This type line card shown Fig. I.432 processing transparent device, which implies that single S/UNI-VORTEX simultaneously interface line cards that implement Utopia line cards that clock data interfaces. Fig. Clock Data Interface
Line Card
Clock Data
Modem
Clock Data
S/UNIDUPLEX
4-wire LVDS
Modem
Some devices provide 3-line interface consisting clock, data, overhead indication. these PHYs external circuitry used adapt S/UNI-DUPLEX's 2-line interface.
Cell delineation, payload scrambling-descrambling, idle cell generation/discard, etc. Either Utopia mode clock data mode selected, both once.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
clock data receive direction S/UNI-DUPLEX performs level Acell delineation function. transmit direction S/UNI-DUPLEX operate either frame aligned mode. frame mode (also called byte aligned mode) wire transmit interface continuously monitors gaps transmit clock determine where frame byte alignment should occur. circuitry assumes that when transmit clock detected this either framing position (e.g. DS-1 framing bit) overhead byte (e.g. ADSL modem). either case next clock period after assumed represent byte alignment position. multiplexer application discussed previously S/UNI-DUPLEX's LVDS interfaces connected S/UNI-VORTEX devices. also possible interface S/UNI-DUPLEX S/UNI-DUPLEX LVDS link. Since S/UNI-DUPLEX interface configured several ways (clock data, 8/16 bits master, 8/16 slave) there various applications where S/UNI-DUPLEX devices used "back-to-back" order perform more following functions: Interfacing master device another master. Interfacing slave device another slave. Converting between buses. card shelf extension. Cell delineation (I.432 processing). Protection switching. Examples these types configurations shown Fig. Fig.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Fig. S/UNI-DUPLEX S/UNI-DUPLEX Applications master S/UNIDUPLEX
LVDS
S/UNIDUPLEX
master
Example on-card conversion: master master
master
S/UNIDUPLEX
LVDS
S/UNIDUPLEX
slave
Example basic extension between cards
Framer Framer S/UNIDUPLEX
LVDS
S/UNIDUPLEX
master
Framer
Fig. S/UNI-DUPLEX S/UNI-DUPLEX Protection Switching
Clock data 8/16 Example on-card I.432 processing
master
S/UNIDUPLEX
S/UNIDUPLEX
slave
master
S/UNIDUPLEX
S/UNIDUPLEX
slave
Example protection switching between cards
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
BLOCK DIAGRAM Although separated improve clarity, many signals following diagram share physical package pins. SCI-PHY/Any-PHY interfaces clocked serial data interfaces mutually exclusive.
RX8K
OMAS OADD R[4:0] OAVA ODAT[15:0] OSOC OFCLK
SCI-PHY Transm ter/ Receive Slav
LTXD LTXC [15:0] [15:0] IBUS STER [4:0] T[15 A[7:0 [7:0] blocks MicroProcessor Interface
Elastic Store
e-Sliced Trans ission Convergence
per-PH buffers Cell Processor per-PH buffers
XD1+ XD1TXD XD2+ XD2TXD
SCI-PHY eive Master/ Transm Slave
Cell Buffer FIFO
Clock Synthesis
REFC
JTAG Test Access Port
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
DESCRIPTION PM7350 S/UNI-DUPLEX monolithic integrated circuit typically used with sister device, S/UNI-VORTEX, implement point-to-point serial backplane interconnect architecture. primary role S/UNI-DUPLEX interface devices (typically framers PHYs) transfer 52-56 byte data cells serial format to/from backplane. Devices interface S/UNI-DUPLEX 16-bit SCI-PHY/Utopia/Any-PHY bus, optionally port clock data interface. Each S/UNI-DUPLEX connect Mb/s Voltage Differential Signal (LVDS) serial links. microprocessor port provides access internal configuration monitoring registers. microprocessor port also used insert extract cells support embedded microprocessor communication channel. INTERFACE: four modes selected:
bit, Utopia master operating clock frequency. Also supports PMC-Sierra's SCI-PHY standard which compatible with Utopia allows extended length cells supports additional address signal order support devices rather than Utopia's Table comparison these standards. port, clocked serial data interface (Tx, TxClk, RxClk), with integrated I.432 Acell delineation operating serial clock frequency. bit, SCI-PHY/Utopia slave operating clock frequency. slave input port presents itself addressable logical channels. slave output port appears single addressable channel carrying multiplexed traffic from logical channels where each cell's channel number optionally embedded header field (Utopia mode) indicated cell prepend (SCI-PHY mode). bit, Any-PHY slave (bus protocol compatible with PM7351 S/UNI-VORTEX) operating clock frequency. slave input port presents itself addressable logical channels. slave output port appears single addressable channel carrying multiplexed traffic from logical channels. both directions each cell's logical channel number indicated cell prepend.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
LVDS INTERFACES (both directions):
Dual 4-wire LVDS serial transceivers each operating Mbps across backplane traces, across meters 4-wire twisted pair cabling inter-shelf communications. Full integrated LVDS clock synthesis recovery. external analog components required. Usable bandwidth (excludes system overhead) Mbps.
LVDS TRANSMIT DIRECTION
Simple round robin multiplex PHYs clock data interfaces) plus microprocessor port's cell transfer buffer. Multiplexed cell stream broadcast both LVDS simultaneously. port prepended each cell Alayer identify cell source PHYs processor). Back-pressure provided (active link only) prevent overflow receiver.
LVDS RECEIVE DIRECTION
Cells received from active LVDS link forwarded appropriate PHY, serial interface, microprocessor port specified port added each cell device. LVDS link marked "spare" monitored errors, cells discarded, microprocessor port cells accepted. Individual microprocessor FIFO back-pressure indications sent prevent FIFO overflows. stream back-pressure prevents head-of-line blocking.
MICROPROCESSOR INTERFACE
data bus, address bus. Provides read/write access configuration status registers. Provides CRC32 calculation cell transfer registers support embedded microprocessor microprocessor communication channel over LVDS link.
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PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
DIAGRAM S/UNI-DUPLEX packaged 160-pin plastic ball grid array (PBGA) package having body size ball pitch 1.00
TRSTB
A[2]
RSTB
A[6]
BIAS
IMASTER LTXD[15]
IADDR[3] LRXC[15]
IADDR[1] LRXD[14]
LRXC[13]
RSTOB
TX8K
A[0]
A[4]
A[5]
INTB
IAVALID LTXC[15]
IENB LRXD[13]
IPRTY LTXD[13]
IDAT[15] LTXC[13]
D[7]
A[1]
A[7]
SCIANY
IBUS8 LTXD[14]
IADDR[0] LRXC[14]
IDAT[14] LTXD[12]
IDAT[13] LTXC[12]
D[4]
D[6]
D[5]
A[3]
IADDR[4] LRXD[15]
IADDR[2] LTXC[14]
IDAT[11] LRXC[12]
IDAT[12] LRXD[12]
IDAT[10] LTXD[11]
RX8K
RCLK
IDAT[7] LRXC[11]
IDAT[8] LRXD[11]
IDAT[9] LTXC[11]
D[0]
D[2]
D[1]
D[3]
IFCLK LTXC[9]
IDAT[6] LTXD[10]
IDAT[5] LTXC[10]
RXD1+
RXD1-
TAVD
IDAT[3] LTXD[8]
IDAT[1] LTXD[7]
IDAT[4] LTXD[9]
TXD1+
TXD1-
TAVS
RESK
LTXC[6]
IDAT[2] LTXC[8]
ISOC LTXD[6]
IDAT[0] LTXC[7]
RXD2+
RXD2-
RAVS
RAVD
ODAT[15] LRXC[10]
OPRTY LRXD[10]
IANYPHY LTXD[5]
TXD2+
TXD2-
TAVS
TAVD
ODAT[14] LRXD[9]
ODAT[13] LRXC[9]
ATP0
ATP1
CAVS
CAVD
OADDR[1] LRXD[0]
OSOC LRXD[3]
ODAT[2] LRXD[4]
ODAT[4] LRXC[6]
ODAT[12] LTXC[5]
ODAT[11] LRXD[8]
QAVS
QAVD
OMASTER LTXD[1]
OADDR[3] LTXC[1]
OAVALID LRXD[1]
OANYPHY LTXD[2]
ODAT[5] LRXD[6]
ODAT[9] LTXC[4]
ODAT[10] LRXC[8]
Unused LTXD[0]
OADDR[2] LTXC[0]
OADDR[4] LRXC[1]
LRXC[2]
ODAT[1] LRXC[4]
ODAT[3] LRXD[5]
OFCLK LRXC[5]
ODAT[6] LRXC[7]
ODAT[8] LTXC[3]
Unused LTXD[3]
REFCLK
OADDR[0] LRXC[0]
OENB LRXD[2]
LRXC[3]
ODAT[0] LTXC[2]
OBUS8 LTXD[4]
ODAT[7] LRXD[7]
BOTTOM VIEW
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
DESCRIPTION Ball Name RXD1+ RXD1RXD2+ RXD2Ball
Type Diff. LVDS Input
Function High Speed LVDS Links high-speed receive data (RXD1+/-, RXD2+/-) inputs present data from serial backplane. pairs provided redundancy. active link chosen local microprocessor determined simple handshake. RXD1+/- RXD2+/- truly differential inputs offering superior common-mode noise rejection. They have sufficient sensitivity common-mode range support LVDS signals.
TXD1+ TXD1TXD2+ TXD2-
Diff. LVDS Output
transmit differential data (TXD1+/-, TXD2+/-) outputs present encoded data serial backplane. These outputs open drain current sinks which interface directly with twisted-pair cabling board interconnect. Edge rates controlled minimize radiated emissions. Both differential links carry identical traffic except exact phase relationship guaranteed.
REFCLK
Input
reference clock input (REFCLK) must provide jitter-free reference clock. used reference clock both clock recovery clock synthesis circuits. jitter below transferred directly TXD1+/- TXD2+/outputs. high-speed serial interface rate eight times REFCLK frequency. 4.75k resistor must connected between these pins achieve correct LVDS output signal levels. Analog Test Points (ATP) provided production test purposes. mission mode they high impedance should connected ground.
RESK ATP0 ATP1
Analog
Analog
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name TX8K
Type Input
Ball
Function High Speed LVDS Links transmit timing reference (TX8K) input allows traceable signal transmitted high-speed serial links TXD1+/- TXD2+/-. rising edge TX8K encoded next cell transmitted. Although TX8K targeted typical need transporting signal, frequency constrained kHz. frequency less than cell rate permissible.
RX8K
Output
receive timing reference (RX8K) output presents timing extracted from receive high-speed serial links, RXD1+/- RXD2+/-. rising edge RX8K accurate nearest byte boundary high-speed serial link; therefore, small amount jitter present. link rate 155.52 Mb/s, jitter 63ns peak-topeak. Pulses RX8K always high-speed serial link periods wide (two REFCLK periods).
RCLK
Output
Recovered Clock (RCLK) output presents byte clock active receive high-speed serial link. RCLK frequency shall 0.125 RXD1+/- RXD2+/- rate. digital clock recovery technique employed, jitter introduced 12.8 phase steps. active link changed, RCLK guaranteed glitch free. Because these factors, RCLK must cleaned before suitable timing reference.
Clocked Data Serial Interface
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name SCIANY
Type Input
Ball
Function High Speed LVDS Links SCI-PHY/Any-PHY Interface (SCIANY) input selects type device interface. SCIANY logic high, S/UNI-DUPLEX will configured communicate devices shared SCI-PHY Level Utopia Any-PHY cell bus. SCIANY logic low, each device dedicated clocked serial interface. types interfaces share common package pins. Failure present correct logic level this signal application result damage S/UNI-DUPLEX devices. When SCIANY logic high, LTXD[3] LTXD[0] become inputs need tied through pull pull down.
LRXD[15] LRXD[14] LRXD[13] LRXD[12] LRXD[11] LRXD[10] LRXD[9] LRXD[8] LRXD[7] LRXD[6] LRXD[5] LRXD[4] LRXD[3] LRXD[2] LRXD[1] LRXD[0]
(SCIANY=
Input
low-speed receive data (LRXD[15:0]) inputs provide data from individual modem channels. data streams must carry contiguous Acells with valid (Header Check Sequence) bytes. LRXD[n] clocked either rising falling edge corresponding LRXC[n] input, depending value LRXCINV Master Configuration register. default, rising edge used. These inputs only active SCIANY input logic low.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name LRXC[15] LRXC[14] LRXC[13] LRXC[12] LRXC[11] LRXC[10] LRXC[9] LRXC[8] LRXC[7] LRXC[6] LRXC[5] LRXC[4] LRXC[3] LRXC[2] LRXC[1] LRXC[0] LTXD[15] LTXD[14] LTXD[13] LTXD[12] LTXD[11] LTXD[10] LTXD[9] LTXD[8] LTXD[7] LTXD[6] LTXD[5] LTXD[4] LTXD[3] LTXD[2] LTXD[1] LTXD[0]
Type Input (SCIANY
Ball
Function High Speed LVDS Links low-speed receive clock (LRXC[15:0]) inputs provide timing receive links. Each LRXC signal independent others. Each signal LRXD[15:0] sampled either rising falling edge corresponding LRXC[15:0] clock, depending value LRXCINV Master Configuration register. default, rising edge used. active edge each LRXC must only occur during those periods containing Acell data. must suppressed during periods containing transmission overhead. These inputs only active SCIANY input logic low. Maximum clock rate MHz. low-speed transmit data signals (LTXD[15:0]) carry outgoing link data serial format. Each LTXD signal independent other signals. most significant each data byte transmitted first. Each signal LTXD[15:0] updated either rising falling edge corresponding LTXC[15:0] clock, depending value LTXCINV Master Configuration register. default, rising edge used. These outputs only active SCIANY input logic low. When SCIANY logic high, LTXD[3] LTXD[0] become inputs need tied through pull pull down.
Output
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name LTXC[15] LTXC[14] LTXC[13] LTXC[12] LTXC[11] LTXC[10] LTXC[9] LTXC[8] LTXC[7] LTXC[6] LTXC[5] LTXC[4] LTXC[3] LTXC[2] LTXC[1] LTXC[0] IANYPHY
Type Input
Ball
Function High Speed LVDS Links low-speed transmit clock (LTXC[15:0]) inputs provide timing transmit links. Each LTXC signal independent others. Each signal LTXD[15:0] updated either rising falling edge corresponding LTXC[15:0] clock, depending value LTXCINV Master Configuration register. default, rising edge used. option, clock gaps recognized force byte alignment transmission overhead. These outputs only active SCIANY input logic low. Maximum clock rate MHz.
(SCIANY Input
Input Parallel (SCIANY logic high) Input Port Any-PHY configuration (IANYPHY) input determines protocol SCI-PHY/AnyPHY input port interface. IANYPHY only active SCIANY input logic high. IANYPHY logic low, interface complies SCI-PHY/Utopia specification. IANYPHY logic high, interface complies Any-PHY specification. Any-PHY protocol supported only when input port cell interface configured slave (IMASTER input must logic IANYPHY high). IANYPHY asynchronous input expected held static.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name IMASTER
Type Input
Ball
Function High Speed LVDS Links input port master select (IMASTER) determines direction input port cell interface control signals. IMASTER low, input port S/UNIDUPLEX slave complies with SCIPHY/Utopia Any-PHY transmit protocol depending state IANYPHY input. IADDR[4:0], IAVALID, IENB signals inputs. signal output. IMASTER high, input port S/UNIDUPLEX master complies with SCI-PHY/Utopia receive protocol (IANYPHY must IMASTER high). IADDR[4:0], IAVALID, IENB signals outputs. signal input. This input only active SCIANY input logic high.
IBUS8
Input
input port width select (IBUS8) selects interface width. When IBUS8 high, only IDAT[7:0] expected present valid data IDAT[15:8] ignored. When IBUS8 low, IDAT[15:0] inputs used. This input only active SCIANY input logic high.
IFCLK
Input
input FIFO clock (IFCLK) used read words into S/UNI-DUPLEX upstream cell buffer. IFCLK must cycle lower instantaneous rate. SCI-PHY/Any-PHY input port timing relative rising edge IFCLK. This input only active SCIANY input logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name ISOC
Type Input
Ball
Function High Speed LVDS Links This input only active SCI-PHY/Utopia slave master modes (SCIANY ANYPHY= Input Start Cell (ISOC) marks start cell IDAT[15:0] bus. When ISOC high, first word cell structure present IDAT[15:0] stream. necessary ISOC asserted each cell, unless inband addressing being used. interrupt generated ISOC high during word other than first word cell structure. ISOC sampled rising edge IFCLK. IMASTER high, ISOC considered valid only when IENB signal previous cycle. IMASTER low, ISOC considered valid coincident with IENB assertion.
Input
Transmit Start Cell (ISX) indication signal only active Any-PHY slave mode (when IANYPHY=1 IMASTER=0). marks start cell IDAT[15:0] data bus. When high, first word cell structure present IDAT[15:0] stream. must asserted each cell. interrupt generated high during word other than expected first word cell structure. This input only active SCIANY input logic high.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name IDAT[15] IDAT[14] IDAT[13] IDAT[12] IDAT[11] IDAT[10] IDAT[9] IDAT[8] IDAT[7] IDAT[6] IDAT[5] IDAT[4] IDAT[3] IDAT[2] IDAT[1] IDAT[0]
Type Input (SCIANY
Ball
Function High Speed LVDS Links Input Data (IDAT[15:0]) carries Acell words that written upstream cell buffer. Only IDAT[7:0] used IBUS8 input high. IDAT[15:0] sampled rising edge IFCLK. SCI-PHY/Utopia master (IMASTER=1, IANYPHY=0) IDAT[15:0] considered valid only when IENB signal previous cycle. slave (IMASTER IDAT[15:0] considered valid when IENB signal asserted signal asserted high. Any-PHY slave (IMASTER IANYPHY=1) IDAT[15:0] considered valid when autonomous deselection occurs after last word cell. These inputs only active SCIANY input logic high.
IPRTY
Input
Input Parity (IPRTY) signal completes parity (programmable even parity) IDAT[15:0] when IBUS8 IDAT[7:0] when IBUS8 high. maskable interrupt status generated upon parity error; other actions taken. IPRTY signal sampled rising edge IFCLK. SCI-PHY/Utopia master (IMASTER=1, IANYPHY=0) IPRTY considered valid only when IENB signal previous cycle. slave (IMASTER=0) IPRTY considered valid coincident with IENB being asserted being asserted high. Any-PHY slave (IMASTER IANYPHY IPRTY considered valid when autonomous deselection occurs after last word cell. This input only active SCIANY input logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name
Type
Ball
Function High Speed LVDS Links Input Cell Available (ICA) signal provides celllevel flow control. ICA's direction depends state IMASTER input. SCI-PHY/Utopia master (IMASTER IANYPHY S/UNI-DUPLEX polls PHYs using address signals IADDR[4:0]. device being addressed IADDR[4:0] expected indicate whether complete cell available transfer driving during clock cycle following that which addressed. When cell transfer progress, S/UNI-DUPLEX will poll device which sending cell devices need support cell availability indication during cell transfer. selection particular device from which transfer cell indicated state IADDR[4:0] during last cycle IENB high. slave (IMASTER S/UNI-DUPLEX indicates ability accept additional cells output. When IAVALID sampled high SCIPHY Any-PHY configuration, asserted cell FIFO logical channel addressed IADDR[4:0] least empty cell buffer. FIFO full, deasserted. cell transfer progress that will fill logical channel FIFO, will also deasserted. When IAVALID sampled SCI-PHY high AnyPHY configuration, becomes high impedance. delayed additional clock cycle AnyPHY configuration. buffer status particular logical channel involved stale maximum cycles after start cell transfer when using cycles when using bus. Therefore, master should refrain from polling that logical channel interim.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name (Cont'd)
Type
Ball
Function High Speed LVDS Links slave (IMASTER S/UNI-DUPLEX also configured respond subset IADDRESS[4:0] address range. this case, will remain high-impedance when logical channel addressed IADDR[4:0] outside address range specified ICAEN[31:0] Input Cell Available Enable registers. sampled updated rising edge IFCLK. This signal only active SCIANY input logic high.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name IENB
Type
Ball
Function High Speed LVDS Links active input port enable (IENB) signal used initiate reading cells from device into upstream cell buffer. SCI-PHY/Utopia master (IMASTER IANYPHY S/UNI-DUPLEX asserts IENB transfer cell from devices. source selected IADDR[4:0] signals. valid word expected IDAT[15:0] second rising edge IFCLK after enable asserted. slave (IMASTER IENB input IDAT[15:0] word accepted coincident with IENB being sampled low. Any-PHY slave (IMASTER IANYPHY IENB ignored high held upon completion cell transfer, since cell transfer only initiated assertion ISX. IENB deasserted high time pause cell transfer.IENB sampled updated rising edge IFCLK. Any-PHY protocol supports autonomous deselection. Any-PHY slave inputs become high impedance after last word cell transferred until S/UNI-DUPLEX reselected (via ISX) even IENB left asserted. SCIPHY/Utopia slave defined, subsequent cell transferred (provided available) IENB held beyond cell. This signal only active SCIANY input logic high.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name IADDR[4] IADDR[3] IADDR[2] IADDR[1] IADDR[0]
Type
Ball
Function High Speed LVDS Links SCI-PHY/Utopia master (IMASTER IANYPHY IADDR[4:0] signals outputs used address devices purposes polling selection cell transfer. When conducting polling, order avoid contention, S/UNI-DUPLEX inserts cycles during which IADDR[4:0] 0x1F IAVALID logic When this occurs, device should drive during following clock cycle. Polling performed incrementing sequential order. device selected transfer based IADDR[4:0] value present during last cycle IENB high. SCI-PHY/Utopia slave (IMASTER IANYPHY IADDR[4:0] inputs. During polling when IAVALID sampled high SCI-PHY Any-PHY configuration, S/UNIDUPLEX will drive with cell buffer availability status logical channel indexed IADDR[4:0] next IFCLK cycle. logical channel selected cell transfer determined IADDR[4:0] value presented when IENB last sampled high. Cell transfer initiated with ISOC input being asserted. Any-PHY slave (IMASTER IANYPHY IADDR[4:0] inputs used only polling. Cell transfer initiated with inband addressing (prepend Word contains address) input. Polling occurs when IAVALID sampled S/UNI-DUPLEX drives with cell buffer availability status logical channel indexed IADDR[4:0]. There IFCLK cycle between IAVALID sampled ICA.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name IADDR[4] IADDR[3] IADDR[2] IADDR[1] IADDR[0] (Cont'd)
Type
Ball
Function High Speed LVDS Links slave device (either SCI-PHY AnyPHY), S/UNI-DUPLEX configured restricted subset logical channel address range. this case, device polling selection will occur when logical channel addressed IADDR[4:0] inside address range specified ICAEN[31:0] Input Cell Available Enable registers. IADDR[4:0] updated sampled rising edge IFCLK. These signals only active SCIANY input logic high.
IAVALID
Input Port Address Valid (IAVALID) indicates that IADDR[4:0] asserting valid address polling purposes. SCI-PHY/Utopia master (IMASTER IANYPHY IAVALIV output. When IAVALID deasserted, IADDR[4:0] 0x1F defined Utopia standard. therefore IAVALID necessary when less than devices being polled. slave (IMASTER IAVALID input used control output. IAVALID active highin SCI-PHY/Utopia mode (IANYPHY active Any-PHY mode (IANYPHY output only driven when IAVALID sampled active. IAVALID sampled inactive, becomes high impedance. S/UNI-DUPLEX supports polling contiguous cycles IAVALID held active. delayed additional IFCLK cycle.IAVALID sampled updated rising edge IFCLK. This signal only active SCIANY input logic high. Parallel Output
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name OANYPHY
Type Input
Ball
Function High Speed LVDS Links Output Port Any-PHY configuration (OANYPHY) input determines protocol SCI-PHY/Any-PHY output port interface. OANYPHY only active SCIANY input logic high. OANYPHY logic low, interface complies SCI-PHY/Utopia specification. OANYPHY logic high, interface complies Any-PHY specification. Any-PHY protocol supported only when output port cell interface configured slave (IMASTER input must logic OANYPHY high). OANYPHY asynchronous input expected held static.
OMASTER
Input
Output Port Master select (OMASTER) determines direction output port cell interface control signals. OMASTER high OANYPHY must low. output port S/UNI-DUPLEX master that complies with SCI-PHY/Utopia transmit protocol. OADDR[4:0], OAVALID, OENB signals outputs signal input. OMASTER low, output port S/UNIDUPLEX slave complies with SCIPHY/Utopia Any-PHY receive protocol depending state OANYPHY input. OADDR[4:0], OAVALID, OENB signals inputs. signal output. This input only active SCIANY input logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name OBUS8
Type Input
Ball
Function High Speed LVDS Links output port width select (OBUS8) selects output port interface width. When OBUS8 high, only ODAT[7:0] present valid data ODAT[15:8] held low. When OBUS8 low, ODAT[15:0] outputs used. This input only active SCIANY input logic high.
OFCLK
Input
output port FIFO clock (OFCLK) used transfer cells from internal downstream cell buffer devices. OFCLK must cycle lower instantaneous rate, high enough rate avoid FIFO overflow. SCIPHY/Any-PHY output port timing relative rising edge OFCLK. This input only active SCIANY input logic high.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name OSOC
Type Output
Ball
Function High Speed LVDS Links modes, OSOC updated rising edge OFCLK. When presenting valid data, OSOC high impedance. SCI-PHY/Utopia slave mode (OMASTER OANYPHY output port start cell (OSOC) indication signal marks first word cell transfer ODAT[15:0] data bus. OSOC driven immediately upon sampling OENB previous polling cycle resulted this device being selected (see description below). Any-PHY slave mode (OMASTER OANYPHY output port start cell (OSOC) indication signal marks second word cell transfer ODAT[15:0] data bus. OSOC driven after OFCLK cycle delay upon sampling OENB previous polling cycle resulted this device being selected (see description below). Autonomous deselection occurs after last word cell resulting setting OSOC highimpedance until reselection. SCI-PHY/Utopia master mode (OMASTER OANYPHY output port start cell (OSOC) indication signal marks first word cell transfer ODAT[15:0] data bus. OSOC valid coincident with OENB assertion. When OANYPHY high, autonomous deselection occurs after last word cell resulting setting OSOC high-impedance until reselection. This output only active SCIANY input logic high.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name
Type Output
Ball
Function High Speed LVDS Links Output Start Transfer (OSX) only active Any-PHY slave mode (OANYPHY OMASTER When OANYPHY logic low, held during cell transfer highimpedance otherwise. marks start cell ODAT[15:0] bus. When high, first word cell structure present ODAT[15:0] stream. updated rising edge OFCLK considered valid only when OENB signal sampled previous cycle S/UNIVORTEX device selected after polling process. becomes high impedance (with cycle latency) upon sampling OENB high S/UNI-VORTEX device selected transfer. When OANYPHY high, autonomous deselection occurs after last word cell resulting setting high-impedance until reselection. This input only active SCIANY input logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name ODAT[15] ODAT[14] ODAT[13] ODAT[12] ODAT[11] ODAT[10] ODAT[9] ODAT[8] ODAT[7] ODAT[6] ODAT[5] ODAT[4] ODAT[3] ODAT[2] ODAT[1] ODAT[0]
Type Output (SCIANY
Ball
Function High Speed LVDS Links output port cell data (ODAT[15:0]) carries Acell octets that transferred devices. Only ODAT[7:0] used OBUS8 high. ODAT[15:0] updated rising edge OFCLK. SCI-PHY/Utopia master (OMASTER OANYPHY ODAT[15:0] considered valid coincident with OENB assertion. slave (OMASTER ODAT[15:0] considered valid only when S/UNIVORTEX device selected after polling process OENB signal sampled low. SCI-PHY/Utopia slave (OMASTER OANYPHY ODAT[15:0] driven immediately upon sampling OENB additional OFCLK cycle latency. When presenting valid data, ODAT[15:0] high impedance. Autonomous deselection occurs after last word cell resulting setting ODAT[15:0] highimpedance until reselection. These outputs only active SCIANY input logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name OPRTY
Type Output
Ball
Function High Speed LVDS Links output port parity (OPRTY) signal completes parity (programmable even parity) ODAT[15:0] when OBUS8 ODAT[7:0] when OBUS8 high. OPRTY signal updated rising edge OFCLK. SCI-PHY/Utopia master (OMASTER OANYPHY OPRTY considered valid coincident with OENB assertion. slave (OMASTER OPRTY considered valid only when S/UNI-VORTEX device selected after polling process OENB signal sampled low. SCIPHY/Utopia slave (OMASTER OANYPHY OPRTY driven immediately upon sampling OENB low, Any-PHY slave (OMASTER OANYPHY additional cycle latency when OANYPHY logic high. When presenting valid data, OPRTY high impedance. Any-PHY slave autonomous deselection occurs after last word cell resulting setting OPRTY high-impedance until reselection. This output only active SCIANY input logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name
Type
Ball
Function High Speed LVDS Links Output Cell Available (OCA) signal provides cell-level flow control. OCA's direction depends state OMASTER input. SCI-PHY/Utopia master (OMASTER OANYPHY S/UNI-DUPLEX polls PHYs using address signals OADDR[4:0]. device being addressed OADDR[4:0] expected indicate whether accept cell driving during clock cycle following that which addressed. When cell transfer progress, S/UNI-DUPLEX will poll device which receiving cell devices need support cell availability indication during cell transfer. selection particular device which cell will written indicated state OADDR[4:0] during last cycle OENB high. slave (OMASTER S/UNIDUPLEX indicates existence least complete cell within buffers when polled. S/UNI-DUPLEX round-robins between logical channel cell FIFOs autonomously select cells, interface appears single slave. When OAVALID sampled high SCI-PHY Any-PHY configuration sampled OADDR[4:0] matches OAD[4:0] bits Output Address Match register, asserted least cell available transfer. logical channel FIFOs empty, deasserted. cell transfer progress that will read last available cell, will also deasserted. When OAVALID sampled low, becomes high impedance. delayed additional clock cycle Any-PHY configuration. sampled updated rising edge OFCLK. This signal only active SCIANY input logic high.
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RELEASED DATA SHEET PMC-1980581 ISSUE
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK MULTIPLEXER
Ball Name OENB
Type
Ball
Function High Speed LVDS Links active output port enable (OENB) signal used enact cell transfers from output port. OENB's direction depends state OMASTER input. SCI-PHY/Utopia master (OMASTER OANYPHY OENB output valid word output ODAT[15:0] coincidentally with assertion OENB. state OADDR[4:0] during last cycle OENB high selects which cell destined. Once asserted low, OENB will remain until cell transfer complete. slave (OMASTER OENB input. When OENB sampled S/UNIDUPLEX been selected, word output ODAT[15:0]. Selection occurs when OENB last sampled high OADDR[4:0] value equals state OAD[4:0] bits Output Address Match register OAVALID sampled asserted state. OENB must duration cell transfer. SCI-PHY/Utopia slave valid data driven immediately upon sampling OENB low. Any-PHY slave OSX, OSOP, ODAT[15:0] OPRTY outputs have additional cycle latency. permissible pause cell transfer deasserting OENB high. SCI-PHY/Utopia slave S/UNI-DUPLEX's must reselected before cell transfer resume. Any-PHY slave cell transfer resumes unconditionally when OENB asserted again. either case, cell transfer must completed before another device selected.
Any-PHY protocol supports autonomous deselection. Any-PHY slave outputs become high impedance after last word cell transferred until S/UNI-DUPLEX reselected (via OSX) even OENB left asserted. SCIPHY/Utopia slave defined, subsequent cell transferred (provided available) OENB held beyond cell. PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
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Ball Name OENB
Type
Ball
Function High Speed LVDS Links (Continued) When OENB sampled high S/UNIDUPLEX selected, read performed outputs ODAT[15:0], OPRTY, OSOC become high impedance. OENB sampled updated rising edge OFCLK. This signal only active SCIANY input logic high.
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Ball Name OADDR[4] OADDR[3] OADDR[2] OADDR[1] OADDR[0]
Type
Ball
Function High Speed LVDS Links SCI-PHY/Utopia master (OMASTER 0ANYPHY OADDR[4:0] signals used address devices purposes polling selection cell transfer. When conducting polling, order avoid contention, S/UNI-DUPLEX inserts cycles during which OADDR[4:0] 0x1F OAVALID logic When this occurs, device should drive during following clock cycle. polling order based existence cells downstream cell buffer. device selected transfer based OADDR[4:0] value present during last cycle OENB high. slave OADDR[4:0] signals inputs. When OAVALID sampled high SCI-PHY/Utopia Any-PHY configuration sampled OADDR[4:0] matches OAD[4:0] bits Output Address Match register, asserted least cell available transfer. delayed additional OFCLK cycle Any-PHY configuration. OADDR[4:0] value equals state OAD[4:0] bits Output Address Match register when OENB last sampled high, S/UNI-DUPLEX will initiate cell transfer. SCI-PHY/Utopia slave (OMASTER OANYPHY device must reselected resume cell transferred that been halted deasserting OENB high. OADDR[4:0] sampled updated rising edge OFCLK. These signals only active SCIANY input logic high.
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Ball Name OAVALID
Type
Ball
Function High Speed LVDS Links Output Address Valid (OAVALID) indicates that OADDR[4:0] asserting valid address polling purposes. SCI-PHY/Utopia master (OMASTER OANYPHY OAVALID output. When this signal deasserted, OADDR[4:0] also 0x1Fas defined Utopia standard. Therefore. OAVALID necessary when less than devices being polled. slave (OMASTER OAVALID input used control output. output only driven when OAVALID asserted (sampled high SCI-PHY/Utopia sample Any-PHY configuration) sampled OADDR[4:0] value matches OAD[4:0] bits Output Address Match register. OAVALID deasserted (sampled SCI-PHY/Utopia) high Any-PHY configuration) becomes high impedance. S/UNI-DUPLEX supports polling contiguous cycles OAVALID held high. delayed additional OFCLK cycle Any-PHY configuration. OAVALID sampled updated rising edge OFCLK. This signal only active SCIANY input logic high. Microprocessor
Input
active-low chip select (CSB) signal during S/UNI-DUPLEX register accesses. Note that when being used, must tied high. required (i.e., registers accesses controlled using signals only), must connected inverted version RSTB input.
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Ball Name
Type Input
Ball
Function High Speed LVDS Links active-low read enable (RDB) signal during S/UNI-DUPLEX register read accesses. S/UNI-DUPLEX drives D[7:0] with contents addressed register while low. active-low write strobe (WRB) signal during S/UNI-DUPLEX register write accesses. D[7:0] contents clocked into addressed register rising edge while low. bi-directional data D[7:0] used during S/UNI-DUPLEX register read write accesses.
Input
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[7]/TRS A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB
Input
address A[7:0] selects specific registers during S/UNI-DUPLEX register accesses. test register select (TRS) signal selects between normal test mode register accesses. high during test mode register accesses, during normal mode register accesses. active-low reset (RSTB) signal provides asynchronous S/UNI-DUPLEX reset. RSTB Schmitt triggered input with integral pull-up resistor. address latch enable (ALE) active-high latches address A[5:0] when low. When high, internal address latches transparent. allows S/UNI-DUPLEX interface multiplexed address/data bus. integral pull-up resistor.
Input
Input
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Ball Name INTB
Type Output
Ball
Function High Speed LVDS Links
RSTOB
Output
active-low interrupt (INTB) signal goes when S/UNI-DUPLEX interrupt source active that source unmasked. S/UNI-DUPLEX enabled report many alarms events interrupts. INTB tristated when interrupt acknowledged appropriate register access. INTB open drain output. active Reset Output used reset other devices. RSTOB asserted when RSTB low, RESETO Master Configuration register "remote reset activate" oriented code been validated active link. "remote reset deactivate" code sets RSTOB high impedance unless RESETO set. JTAG Boundary Scan Port test clock (TCK) signal provides timing test operations that carried using IEEE P1149.1 test access port. test mode select (TMS) signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. test data input (TDI) signal carries test data into S/UNI-DUPLEX IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. test data output (TDO) signal carries test data S/UNI-DUPLEX IEEE P1149.1 test access port. updated falling edge TCK. tristate output which inactive except when scanning data progress.
Input
Input
Input
Tristate
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Ball Name TRSTB
Type Input
Ball
Function High Speed LVDS Links active-low test reset (TRSTB) signal provides asynchronous S/UNI-DUPLEX test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull-up resistor. Note that when being used, TRSTB must connected RSTB input. Power Ground
BIAS
Power
When tied +5V, BIAS input used bias wells input pads that pads tolerate their inputs without forward biasing internal protection devices. When tied +3.3V, inputs bi-directional inputs will only tolerate 3.3V level inputs. digital power (VDD) pins should connected well-decoupled +3.3 supply.
Power
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Ball Name
Type Ground
Ball
Function High Speed LVDS Links digital ground (VSS) pins should connected GND.
QAVD
Analog Power
Quiet Analog Power (QAVD). QAVD should connected analog +3.3 should electrically isolated much possible) from other power connections. Quiet Analog Ground (QAVS). QAVS should connected analog GND. should electrically isolated much possible) from other ground connections. power (CAVD) analog clock synthesis unit. This should connected analog +3.3V. should electrically isolated much possible) from other power connections. ground (CAVS) analog clock synthesis unit. This should connected analog GND. should electrically isolated much possible) from other ground connections.
QAVS
Analog Ground
CAVD
Analog Power
CAVS
Analog Ground
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Ball Name RAVD
Type Analog Power
Ball
Function High Speed LVDS Links power (RAVD) LVDS receivers. This should connected analog +3.3V. should electrically isolated much possible) from other power connections. ground (RAVS) LVDS receivers. This should connected analog GND. should electrically isolated much possible) from other ground connections. power (TAVD) pins LVDS transmitters. These pins should connected analog +3.3V. These should electrically isolated much possible) from other power connections. ground (TAVS) pins LVDS transmitters. These pins should connected analog GND. These should electrically isolated much possible) from other ground connections. Thermal Vias (GND) used improve thermal conductance device package. They should connected ground plane. pins electrically connected other ground pins package.
RAVS
Analog Ground
TAVD
Analog Power
TAVS
Analog Ground
Thermal Vias
Notes Description: S/UNI-DUPLEX inputs bi-directionals present minimum capacitive loading operate logic levels, except RXD1+/- RXD2+/-. Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors. recommended power supply sequencing follows: During power-up, voltage BIAS must kept equal greater than voltage pins, avoid damage device. power must applied before input pins driven input current limited less than maximum input current specification mA).
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Analog power supplies (QAVD, CAVD, RAVD, TAVD) must applied after have been applied they must current limited maximum latch-up current specification (100 mA). operation, differential voltage measured between supplies must less than relative power sequencing multiple power supplies important. Power down device reverse sequence.
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FUNCTIONAL DESCRIPTION S/UNI-DUPLEX supports distinct methods interconnection modems, PHYs other Adevices: parallel interface clocked serial data interface. either case primary function S/UNIDUPLEX transfer cells between external devices high speed LVDS serial links. LVDS link another S/UNI-DUPLEX device S/UNI-VORTEX device must connected. PMC-Sierra Data Sheet PM7351 S/UNI-VORTEX details that device. LVDS transmit direction, cells read from external devices multiplexed onto LVDS link. Flow control, alarm, identification, other control information added each cell ensure managed link maintained. LVDS receive direction, system overhead stripped each cell before sent appropriate device parallel over clocked serial data interfaces. slave mode, left cell, typically Alayer device such PMC-Sierra's S/UNI-ATLAS that cell source determined. master mode, clocked serial interface mode stripped used direct cell appropriate Utopia slave device appropriate clocked serial interface. discussion overall system architecture issues, reader referred companion document provided PMC-Sierra titled S/UNI-VORTEX S/UNIDUPLEX TECHNICAL OVERVIEW. document number PMC-981025 obtained various means described last page this document. remainder this section focuses interfaces functionality single S/UNI-DUPLEX device, although reader should also view things context attached far-end device (either S/UNI-DUPLEX S/UNIVORTEX).
Parallel Interface S/UNI-DUPLEX's parallel interface. selected when SCIANY input tied high. This interface supports three types bus: Utopia Level SCI-PHY Level Any-PHY. Table provides correspondence between S/UNI-DUPLEX names Utopia Level SCI-PHY Level Any-PHY signals. Any-PHY format enabled when IANYPHY OANYPHY inputs tied high, SCI-PHY Utopia selected when inputs tied low. Input output
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formats need same. When configured SCI-PHY Utopia Level interface S/UNI-DUPLEX either master slave, determined IMASTER OMASTER inputs. When configured Any-PHY interface, S/UNI-DUPLEX only slave. wide interfaces supported configurations, determined IBUS8 OBUS8 inputs. Table Signal Name Cross-Reference
S/UNIDUPLEX Name
IFCLK
IENB IADDR[4:0] IAVALID IDAT[15:0] IPRTY ISOC OFCLK OENB OADDR[4:0] OAVALID ODAT[15:0] OPRTY OSOC
UTOPIA Level Slave
TxClk
TxEnb* TxAddr[4:0] TxData[15:0] TxPrty TxClav TxSOC RxClk RxEnb* RxAddr[4:0] RxData[15:0] RxPrty RxClav RxSOC
UTOPIA Level Master
RxClk
RxEnb* RxAddr[4:0] RxData[15:0] RxPrty RxClav RxSOC TxClk TxEnb* TxAddr[4:0] TxData[15:0] TxPrty TxClav TxSOC
SCI-PHY Level Slave
TFCLK
TWRENB TADDR[4:0] TAVALID TDAT[15:0] TPRTY TSOC RFCLK RWRENB RADDR[4:0] RAVALID RDAT[15:0] RPRTY RSOC
SCI-PHY Any-PHY Level Slave Master
RFCLK
RWRENB RADDR[4:0] RAVALID RDAT[15:0] RPRTY RSOC TFCLK TWRENB TADDR[4:0] TAVALID TDAT[15:0] TPRTY TSOC
TCLK
TENB TADR[4:0] TADR[5] TDAT[15:0] TPRTY TSOP RCLK RENB RADR[4:0] RADR[5] RDAT[15:0] RPRTY RSOP
Utopia SCI-PHY electrically compatible, only difference that Utopia does support optional OAVALID IAVALID pins. Therefore, whether input output buses Utopia SCI-PHY determined inclusion exclusion optional words cell format that transferred across bus. cell formats supported presented Fig. Fig. programmed through register bits, bytes prepended basic Acell support applications where user defined context information carried inband. Also, inclusion H5/UDF fields modes respectively) optional under most configurations. slave configurations,
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identifier inband address included additional prepend word H5/UDF fields, discussed below. default, none optional words prepended, H5/UDF field included. aware that cells transported transparently across LVDS links. There constraints contents. Therefore, data streams other than Acells transferred across parallel interface interface; only timing protocols need respected. also important note that treatment H5/UDF field, address prepend (Word optional User Prepend input output buses independent from their corresponding fields LVDS link configured. Section 12.2 further details. 9.1.1 SCI-PHY Utopia Master SCI-PHY/Utopia master format enabled when IANYPHY OANYPHY inputs tied IMASTER OMASTER inputs tied high. SCI-PHY/Utopia master interface supports entities provided IAVALID OAVALID signals used; otherwise, supported. interface fully Utopia Level compliant when IAVALID OAVALID used. assumed devices perform Transmission Convergence (TC) functions including cell delineation, cell rate decoupling, payload scrambling, insertion cell filtering upon header errors. ingress direction (cells transferred from input LVDS link), S/UNI-DUPLEX uses round robin polling provide equal access devices. directed flow control information LVDS link (and optionally through S/UNI-DUPLEX configuration), device temporarily removed from polling sequence. Data transfers cell based, that entire cell transferred from device before another selected. Polling occurs concurrently with cell transfers ensure maximum throughput. SCI-PHY/Any-PHY Input Configuration register (0x0C) determines cell format input bus. Unlike Any-PHY mode, SCI-PHY/Utopia master does require hence does support embedded cell length options (shown Fig. described Table options (shown Fig. described Table
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Table Eight SCI-PHY/Utopia Master, Input Configuration
Byte
bytes
Register 0x0C H5UDF PRELEN
Notes
Short cell, byte Default, Utopia compatible user byte then H1-H4 user byte then H1-H5 user bytes then H1-H4. user bytes then H1-H5.
Table Sixteen SCI-PHY/Utopia Master, Input Configuration
Word
bytes
Register 0x0C H5UDF PRELEN
Notes
Short cell, H5/UDF field Default, Utopia compatible user word then H1-H4 user word, H1-H4, then H5/UDF
egress direction (cells transferred from LVDS link output bus.), only those devices polled which there cell internal cell buffer. cell buffer organized FIFOs, each associated with single device. This arrangement prevents head-of-line blocking. ingress interface, transfers cell based polling concurrent with cell transfers. SCI-PHY/Any-PHY Output Configuration register (0x14) determines cell format output bus. SCI-PHY/Utopia master neither requires supports embedded cell length options (shown Fig. described Table options (shown Fig. described Table
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Table Eight SCI-PHY/Utopia Master, Output Configuration
Byte
bytes
Register 0x14 INADD
Notes
Short cell, generated Default setting. Utopia compatible, standard byte cell, user byte, H1-H4, user byte, H1-H5, user bytes, H1-H4, user bytes, H1-H5,
Table Sixteen SCI-PHY/Utopia Master, Output Configuration
Word
bytes
Register 0x14 INADD
Notes
Short cell, Default, Utopia compatible, user bytes, H1-H4, user bytes, H1-H4, H5/UDF,
9.1.2 SCI-PHY Utopia Slave SCI-PHY/Utopia slave format enabled when IANYPHY, OANYPHY, IMASTER, OMASTER inputs tied low. ingress direction (cells transferred from parallel input port LVDS links), port presents itself entities fully Utopia Level compatible when fewer PHYs active IAVALID tied high. Cells read from queued dedicated FIFO each virtual (hereafter referred logical channel). ability FIFOs accept additional cells discovered through polling using IADDR[4:0] IAVALID inputs. Upon IAVALID being sampled high output asserted cell FIFO logical channel addressed IADDR[4:0] least empty cell buffer. FIFO full, deasserted. cell transfer progress that will fill logical channel FIFO, will also deasserted. IAVALID sampled SCI-PHY mode) becomes high impedance. When operating SCI-PHY/Utopia interface, cell transfer effected assertion IENB. logical channel FIFO which cell written selected IADDR[4:0] value sampled when IENB last sampled high.
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SCI-PHY/Any-PHY Input Configuration register (0x0C) determines cell format input bus. SCI-PHY/Utopia input slave neither requires supports embedded cell length options (shown Fig. described Table options (shown Fig. described Table Note that these options identical SCIPHY/Utopia input master configuration. Table Eight SCI-PHY/Utopia Slave, Input Configuration
Byte
bytes
Register 0x0C H5UDF PRELEN
Notes
H1-H4, byte Default, Utopia compatible user byte then H1-H4 user byte then H1-H5 user bytes then H1-H4 user bytes then H1-H5
Table Sixteen SCI-PHY/Utopia Slave, Input Configuration
Word
bytes
Register 0x0C H5UDF PRELEN
Notes
H1-H4, H5/UDF field Default, Utopia compatible user word then H1-H4 user word, H1-H4, then H5/UDF
egress direction (cells transferred from LVDS output port), port appears single addressable SCI-PHY/Utopia Level slave. cells received high-speed serial link queued FIFOs dedicated each logical channel. corresponding each cell encoded system prepend bytes sent over LVDS link. S/UNI-DUPLEX autonomously multiplexes traffic from logical channels presents single cell stream output bus. least cell present FIFOs, will drive high when device polled. Polling occurs when OAVALID sampled high sampled OADDR[4:0] matches OAD[4:0] bits Output Address Match register. Utopia compatibility achieved OAVALID tied high OAD[4:0] ones.
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cell transfer will enacted OADDR[4:0] value equals state OAD[4:0] bits Output Address Match register when OENB last sampled high. SCI-PHY mode word prepended transferred Acell identify cell's source (i.e. logical channel number). retain Utopia Level compatibility, word identifying logical channel placed H5/UDF field. three most significant bits channel number 8-bit format most significant bits prepend 16-bit format derived from contents Extended Address Match registers, which default zeros. SCI-PHY/Any-PHY Output Configuration register (0x14) determines cell format output bus. cell length options (shown Fig. described Table options (shown Fig. described Table Table Eight SCI-PHY/Utopia Slave, Output Configuration
Byte
bytes
Register 0x14 INADD
Notes
H1-H4 only, generated Default setting. Utopia compatible, standard byte cell, user byte, H1-H4, user byte, H1-H5, user bytes, H1-H4, user bytes, H1-H5, Most common setting when Utopia compatibility desired. Standard byte cell, embedded user byte, H1-H4, user bytes, H1-H4,
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Table Sixteen SCI-PHY/Utopia Slave, Output Configuration
Word
bytes
Register 0x14 INADD
Notes
H1-H4 only, Default, Utopia compatible, user bytes, H1-H4, user bytes, H1-H4, H5/UDF, Most common setting when Utopia compatibility desired. Standard byte cell, embedded H5/UDF. user bytes, H1-H4, H5/UDF
9.1.3 Any-PHY Slave Any-PHY slave format enabled when IANYPHY OANYPHY inputs high, IMASTER, OMASTER inputs tied low. ingress direction (cells transferred from parallel input port LVDS links), port presents itself entities. Cells read from queued dedicated FIFO each logical channel. SCI-PHY mode, ability FIFOs accept additional cells discovered through polling using IADDR[4:0] IAVALID inputs. Upon IAVALID being sampled (note this opposite SCI-PHY mode) output asserted cell FIFO logical channel addressed IADDR[4:0] least empty cell buffer. FIFO full, deasserted. cell transfer progress that will fill logical channel FIFO, will also deasserted. IAVALID sampled high becomes high impedance. delayed cycle (i.e. IFCLK cycle) Any-PHY configuration. Any-PHY mode cell transfer initiated using inband selection. first word cell, coincident with assertion signal, used logical channel selection. Cells accepted S/UNI-DUPLEX value Extended Address field Word agrees with Extended Address Match registers over range bits specified Extended Address Mask registers. Table summarizes distinctions between SCI-PHY/Utopia Any-PHY protocols ingress direction.
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Table SCI-PHY/Utopia Any-PHY Comparison, Ingress Direction
Attribute Latency SCI-PHY driven high immediately upon sampling IAVALID high becomes high impedance immediately upon sampling IAVALID low. Logical channel selected IADDR[4:0] when IENB last sampled high. Unused. High coincident with first word cell data structure. supported. subsequent cell input (provided space available) IENB held beyond cell. Any-PHY driven becomes high impedance IFCLK rising edge following that samples IAVALID high respectively. extra word (Word prepended cell coincident with assertion signal. Word used logical channel selection High coincident with first word cell data structure. Unused S/UNI-DUPLEX. Supported. Subsequent writes ignored IENB held until input asserted.
Logical Channel Selection ISOC Autonomous deselection
SCI-PHY/Any-PHY Input Configuration register (0x0C) determines cell format input bus. Any-PHY input slave requires embedded present Byte Word cell format options (shown Fig. described Table options (shown Fig. described Table Table Eight Any-PHY Slave, Input Configuration
Byte
bytes
Register 0x0C H5UDF PRELEN
Notes
byte, then H1-H4, byte Default setting. then H1-H5 user byte then H1-H4 user byte then H1-H5 user bytes then H1-H4 user bytes then H1-H5
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Table Sixteen Any-PHY Slave, Input Configuration
Word
bytes
Register 0x0C H5UDF PRELEN
Notes
word, then H1-H4, H5/UDF field Default, H1-H4, then H5/UDF user word, then H1-H4, H5/UDF user word, H1-H4, then H5/UDF
egress direction (cells transferred from LVDS output port), port appears single addressable Any-PHY slave. S/UNI-DUPLEX autonomously multiplexes traffic from logical channels presents single cell stream output bus. least cell present FIFOs, will drive high when device polled. delayed additional clock cycle (one OFCLK) Any-PHY configuration. Polling occurs when OAVALID sampled sampled OADDR[4:0] matches OAD[4:0] bits Output Address Match register. cell transfer will enacted OADDR[4:0] value equals state OAD[4:0] bits Output Address Match register when OENB last sampled high. word prepended transferred Acell identifies logical channel. three most significant bits prepend 8-bit format most significant bits prepend 16-bit format derived from contents Extended Address Match registers, which default zeros. Table summarizes distinctions between protocols egress direction. Table SCI-PHY/Utopia Any-PHY Comparison, Egress Direction
Attribute Latency SCI-PHY/Utopia ODAT[15:0], OPRTY OSOC driven become high impedance immediately upon sampling OENB high, respectively. driven immediately upon sampling OADDR[4:0] value that matches contents Output Address Match register. Undefined. when high impedance. Any-PHY 0DAT[15:0], 0PRTY, 0SOC driven become high impedance OFCLK rising edge following that samples OENB high, respectively. driven OFCLK rising edge following that samples OADDR[4:0] value that matches content Output Address Match register. High coincident with first word cell data structure.
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OSOC Paused transfers
High coincident with first word cell data structure. Permitted deasserting OENB high, S/UNI-DUPLEX address presented OADDR[4:0] must match content Output Address Match register last cycle OENB high reselect device. supported. subsequent cell output (provided available) OENB held beyond cell.
High coincident with second word cell data structure. Permitted deasserting OENB high. cell transfer resumes unconditionally when OENB asserted again.
Autonomous deselection
outputs become high impedance after last word cell transferred until S/UNI-DUPLEX reselected.
SCI-PHY/Any-PHY Output Configuration register (0x14) determines cell format output bus. Byte Word will always contain channel cell length options (shown Fig. described Table options (shown Fig. described Table Table Eight Any-PHY Slave, Output Configuration
Byte
bytes
Register 0x14 INADD
Notes
byte then H1-H4 Default setting. then H1H5 user byte, then H1-H4 user byte, then H1-H5 user bytes, then H1-H4 user bytes, then H1-H5
Table Sixteen SCI-PHY/Utopia Slave, Output Configuration
Word
bytes
Register 0x14 INADD
Notes
word then H1-H4 Default setting. H1-H4, then H5/UDF user bytes, H1-H4 user bytes, H1-H4, H5/UDF
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Fig. Eight SCI-PHY/Utopia/Any-PHY Cell Format
(optional) (optional) (optional) (optional)
Extended Address
PHYID[4:0]
User Prepend User Prepend PAYLO
PAYLOAD48
Note Optionally, field overw ritten Extended Address PHYID[4:0].
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Fig. Sixteen SCI-PHY/Utopia/Utopia Cell Format
(optional) (optional) (optional) PAYLOAD1 PAYLOAD3 Extended Address User Prepend PAYLOAD2 PAYLOAD4
PHYID[4:0]
PAYLO AD47
PAYLOAD48
Note ptionally, H5/UDF fields overwritten Extended Address PHYID[4:0].
Clocked Serial Data Interface some systems devices which S/UNI-DUPLEX interface contain integrated Transmission Convergence function even though level protocol being transported over that interface I.432 compliant Acells. these types devices (typically framers modems) S/UNIDUPLEX provides bi-directional clocked serial data interfaces with fully integrated, I.432 compliant, Transmission Convergence (TC) functions allow cell structured streams exchanged with modems. modems perform Physical Media Dependent (PMD) functions that streams contain only contiguous Acells. S/UNI-DUPLEX requires that clock gapped during overhead locations.
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9.2.1 Upstream Functions upstream direction (input from modems), S/UNI-DUPLEX provides inputs (clock data) channel implements cell delineation, payload descrambling, idle cell filtering header error detection recover valid Acells. These functions performed accordance with ITU-T Recommendation I.432.1. When configuring S/UNI-DUPLEX clocked serial data mode user must modify Transmit Logical Channel FIFO Depth register (0x5E) accordingly. register descriptions details. Cell delineation process framing Acell boundaries using header check sequence (HCS) field found Acell header. CRC-8 calculation over first octets Acell header. accordance with ITU-T Recommendation I.432.1, coset polynomial added (modulo received octet before comparison with calculated result. When performing delineation, correct calculations assumed indicate cell boundaries. cell delineation circuitry performs sequential bit-by-bit hunt correct sequence. This state referred HUNT state. When correct found, particular cell boundary assumed PRESYNC state entered. This state verifies that previously detected pattern false indication. pattern false indication then incorrect should received within next DELTA cells delineation state machine falls back HUNT state. incorrect found this PRESYNC period then transition SYNC state made, cell delineation declared non-idle cells with correct passed SYNC state synchronization relinquished until ALPHA consecutive incorrect patterns found. such event transition made back HUNT state. state diagram cell delineation process shown Fig.
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Fig. Cell delineation State Diagram
correct (bit bit)
HUNT
Incorrect (cell cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell cell)
SYNC
DELTA consecutive correct HCS's (cell cell)
values ALPHA DELTA determine robustness delineation method. ALPHA determines robustness against false misalignments errors. DELTA determines robustness against false delineation synchronization process. ALPHA chosen DELTA chosen loss cell delineation (LCD) alarm declared after programmable threshold incorrect cells occurs while HUNT state. threshold Receive Serial Count Threshold register. threshold default value which translates kbs.All idle cells filtered passed high-speed interface. They identified cells containing zeros VPI, fields bit. Optionally, unassigned cells (like idle cells except zero) also filtered. cells with incorrect octet filtered out. Header correction implemented. option configured Receive Serial Indirect Channel Configuration register (0x69), ATransmission Convergence functions disabled provide clear channel capability. this case, serial data segmented into byte packets independent contents, then transported across highspeed LVDS links.
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9.2.2 Downstream Functions downstream direction (toward modems), S/UNI-DUPLEX uses clock input data output channel produce valid Acell streams with correct octets inserted idle cells adapt clock generated modem. Each modem provides clock, which asynchronous others. S/UNI-DUPLEX responds active edge each transmit clock generating single bit. Idle cells automatically generated interleaved with cells available from high-speed serial interface match channel's rate driven clock input. When needs insert transmission overhead (such framing bits) into data stream provided S/UNI-DUPLEX, modem expected downstream clock provided S/UNI-DUPLEX that data bits output during overhead period(s). Optionally, S/UNI-DUPLEX programmed (using register 0x74) optionally force octet alignment data overhead monitoring clock gaps. support dynamically adaptable modem rate without external intervention, system automatically adapts frequency changes LTXC[15:0]. When byte alignment enabled, clock period monitored each LTXC[15:0] input. period greater than minimum detectable period, most significant data octet output during period, allowing receiving modem receive first clock active edge after gap. S/UNI-DUPLEX detect clock gaps eight clock periods over permitted LTXC[15:0] clock line frequency range. frequency range over which framing detected changes linearly with speed high-speed links. When operating LVDS interface Mb/s (REFCLK frequency MHz), S/UNI-DUPLEX will detect clock line frequency range MHz. minimum frequency Mb/s (REFCLK frequency 12.5 MHz) line frequency range which framing detected MHz. option (see Transmit Serial Indirect Channel Data register 0x71) transmitted data stream provided clear channel disabling generation payload scrambling. responsibility traffic generation entity other LVDS link send traffic sufficient rate keep internal FIFOs from emptying, else clear channel data will interrupted automatically generated Aidle cell pattern.
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High-Speed Serial Interface S/UNI-DUPLEX provides backplane interconnection Mb/s serial links. data destined coming from core cell processing card concentrated these high-speed links. transceivers support UTP-5 cable lengths 10m. avoid clock skew issues, clock transmitted receivers recover local clock from incoming data. bi-directional LVDS links provided redundancy; each link intended routed different core cards. Both LVDS transmitters carry identical traffic except internally generated overhead. Both links frequency locked single input reference clock although their phase guaranteed match. LVDS receivers clock recovery cell delineation always active both receivers allow quick switch redundant core card with minimal cell loss. serial links carry Acells with prepended bytes. cell format illustrated Fig. discussed Section 12.2). S/UNI-DUPLEX appends first four bytes Header Check Sequence (HCS) byte upstream direction strips them parses them downstream direction. remainder bytes data structure transferred transparently. bytes serialized most significant first. stream simple concatenation extended cells. Cell rate decoupling accomplished through introduction stuff cells. transmitter inserts correct CRC-8 that protects both Acell header prepended bytes byte. Cells with errored counted then discarded. receiver also uses byte determining cell delineation. Failure establish cell alignment results loss cell delineation (LCD) alarm. entire stream scrambled with self-synchronous scrambler.Table summarizes contents system prepended bytes.
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Fig. High-Speed Serial Link Data Structure
Byte
User Prepend
User Header bytes
Syste Prepend
APayload bytes
APayload
bytes, where
Table Prepended Fields Byte Bits Mnemonic CA[15:8] CA[7:0] Description CA[15:0] bits carry per-PHY flow control information upstream direction. support PHYs, status each sent every other cell; CASEL indicates which half represented. CASEL logic CA[15:0] corresponds those PHYs with addresses through CASEL logic CA[15:0] corresponds those PHYs with addresses through downstream direction, CA[15:0] communicates congestion upstream entity. encoding identical upstream direction. logic indicates accept more cells specific logical channel. logic indicates S/UNI-DUPLEX free send queued traffic that logical channel immediately. event errored header detected incorrect HCS), bits will assumed zero. This ensures cells transmitted which there buffer space. CASEL state select determines which half devices CA[15:0] bits correspond CASEL toggles with each cell transmitted.
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Byte
Bits
Mnemonic UPCA
Description UPCA carries flow control information microprocessor control channel. this one, control channel cells transferred. event errored header, UPCA will assumed zero. This ensures cells transmitted which there buffer space.
PHYID
identifier determines which cell destined downstream direction from which came upstream direction. also indicates whether cell stuff control channel cell. field encoded follows: "111111" Stuff cell provided cell rate decoupling. payload carries useful data cell shall discarded. "111110" Control channel cell. transmit serial link, PHYID shall equal this value cells inserted Microprocessor Cell Buffer. cells received serial link with this encoding will routed local microprocessor. "100000" "111101" Reserved "000000" "011111" Logical channel index devices.
Oriented Code (BOC) position carries repeating pattern that encodes possible code words used remote control status reporting. Five codes predefined represent remote defect, loopback activate request, loopback deactivate request, reset activate request reset deactivate request. remaining codes either reserved user defined. receiver ensures pattern same (default) repetitions before
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Byte
Bits
Mnemonic
Description validating code word. Refer 9.3.1 section more details. link active indicates which redundant links currently chosen. S/UNI-DUPLEX will switch link which contains this location least consecutive cells. local microprocessor override this selection. both links present this location, selection remains unchanged. confirm which link active, transmitted ACTIVE will associated receive link selected. event errored header, previous ACTIVE value retained.
ACTIVE
TREF[5:0]
timing reference encodes signal inband that independent serial rate. TREF[5:0] binary value represents number high-speed link bytes after this which timing reference inferred. ones value indicates timing mark associated with this cell.
transmitter outputs internally terminated current mode drivers. Correct termination receiver required provide appropriated signal levels. internal transmit clock synthesized from 12.5 clock. resulting data rate eight times frequency REFCLK input. jitter below REFCLK passed unattenuated TXD1+/- TXD2+/outputs. design loop filter optimized minimum intrinsic jitter. With jitter free reference input noise board layout, intrinsic jitter typically less than 0.01 0.10 peak-to-peak when measured using band pass filter with cutoff frequencies. truly differential receivers capable handling signal swings down 100mV. wide common mode range makes them compatible with LVDS signals. External termination resisters must provided match cable impedance.
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receivers monitor loss signal (LOS) links. declared upon 2048 periods (13.2 155.52 Mb/s) without signal transition scrambled data. consequence, status set, maskable interrupt asserted (Remote Defect Indication) codeword sent repetitively corresponding downstream link. indication cleared when signal transition occurred each consecutive intervals periods each. Clock recovery performed digital phase locked loop (DPLL). implementation robust against operating condition variations power supply noise. receive link constrained within eight times REFCLK frequency. shown Fig. datapath loopbacks provided each LVDS link fault isolation continuity verification. metallic loopback routes high-speed serial receive data transmitter. diagnostic loopback replaces downstream data with upstream data. loopbacks enabled individually simultaneously, each link looped back independently other.
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Fig. Datapath Loopback
RSTO RCLK RX8K TX8K
IANY OBUS8 NYPH OMAS OENB OADDR[4:0] OAVALID ODAT[15:0] OSOC OFCLK
SCI-PHY Transm Master/ Receive Slave
LTXD [15:0] LTXC [15:0] LRXD[15:0] LRXC[15:0] IBUS IMASTER IADDR[4:0] IAVALID IDAT[15:0] ISOC IFCLK A[8:0] D[7:0] blocks MicroProcessor Interface
Elastic Store
e-Sliced Transm ission Convergence
per-PHY buffers Cell Processor per-PHY buffers
RXD1+ RXD1TXD 1RXD2+ RXD2TXD
SCI-PHY Receive Master/ Transm Slave
Cell Buffer Cell FIFO
Clock Synthesis
REFCLK
JTAG Test Access Port
diagnostic loopback effected Serial Links Maintenance register (0x05) corresponding active high-speed serial link logic (DLB1 DLB2 depending data being received from RXD1+/- RXD2+/inputs). upstream data clock inserted into downstream datapath
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after clock recovery. Setting corresponding inactive link effect. metallic loopback independently each high-speed serial link. effected three ways: after receipt loopback activate code corresponding RXD1+/- RXD2+/- inputs described Section 9.3.2) when corresponding MLB1 MLB2 Serial Link Maintenance register logic when reset (RSTB) input asserted low. loopback occurs LVDS transceiver after conversion digital before clock recovery. looped back data slightly distorted data slicing (differential single-ended) re-buffering that occurs. Metallic loopback terminated loopback deactivate oriented code received validated, provided corresponding MLB1 MLB2 Serial Links Maintenance register logic 9.3.1 Link Integrity Monitoring Although serial link error rate inferred from accumulated Header Check Sequence (HCS) errors, option exists perform error monitoring over entire stream. When feature enabled second User Prepend byte transmitted shall overwritten CRC-8 syndrome preceding cell. encoding valid cells, including stuff cells. CRC-8 polynomial receiver shall raise maskable interrupt optionally increment error count. Simultaneous cell CRC-8 errors result single increment. 9.3.2 Oriented Codes Oriented Codes (BOCs) carried position System Prepend. possible codes used carry predefined user defined signaling. oriented codes transmitted repeating 16-bit sequence consisting ones, zero, code bits, trailing zero (111111110xxxxxx0). code transmitted independently LVDS links, programmed writing TXD1 Oriented Code TXD2 Oriented Code registers. autonomously generated Remote Defect Indication (RDI) code, which generated upon loss-of-signal loss-of-cell-delineation, takes precedence over programmed code. insertion disabled RDIDIS Serial Links Maintenance register. inserted manually highspeed serial link setting corresponding TXD1 Oriented Code TXD2 Oriented Code register zeros.
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receiver enabled declare received code valid been observed times times, specified Oriented Code Receiver Enable register. Unless fast declaration necessary, recommended that logic improve error tolerance. Valid indicated through RXD1 Oriented Code Status RXD2 Oriented Code Status registers. bits ones (111111) valid code been detected. maskable interrupt generated signal when detected code been validated, optionally, when valid code goes away (i.e. bits ones). When receiver cell delineation (OCD), detection disabled corresponding RXD1 RXD2 Oriented Code Status register will produce ones (111111). valid codes provided Table Reserved codes anticipate future enhanced feature devices should used. User Defined codes used without restriction. Regardless definition, codes validated read microprocessor. Only four codes result autonomous action: loopback activate, loopback deactivate, reset output activate reset output deactivate. Note that processing metallic loopback activate code handled special case. RXD1+/-, RXD2+/- data looped back onto TXD1+/-, TXD2+/- respectively reception loopback activate code corresponding high-speed serial link rather than when code first validated. loopback enabled loopback code must first validated (received times least once) then invalidated, typically reception another code. loopback enable upon initial validation loopback activate code because looped back signal, which still contains original loopback activate command, would cause far-end receiver into metallic loopback, thereby forming undesirable closed loop condition! loopback cleared immediately upon validation loopback deactivate code, assuming corresponding register Serial Links Maintenance register logic produce loopback end, program desired TXD1 Oriented Code TXD2 Oriented Code register with loopback activate code least then revert another (typically idle) code. Upon termination loopback activate code, data transmitted TXD1+/- TXD2+/- expected received verbatim RXD1+/- RXD2+/- inputs. When transmitting loopback activate code high-speed serial link, recommended corresponding RDIDIS1 RDIDIS2 register logic else loss-of-signal loss-of-cell-delineation event would cause premature loopback pre-emptive Remote Defect Indication (RDI) code being sent.
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remote reset activate remote reset deactivate code words used control RSTOB output. remote reset activate code validated, RSTOB output asserted low. remote reset deactivate code validated RSTOB output becomes high impedance. RSTOB also controlled through RESETO Master Configuration register. Remote Defect Indication (RDI) sent whenever Loss Signal (LOS) Loss Cell Delineation (LCD) declared. This code word takes precedence over others. Table Assigned Oriented Codes Function Remote Defect Indication (RDI) Loopback activate Loopback deactivate Remote reset activate Remote reset deactivate Reserved Reserved User Defined User Defined Idle Code 9.3.3 Cell Delineation Process S/UNI-DUPLEX performs cell delineation, payload descrambling, idle cell filtering header error detection recover valid cells from receive high-speed links. These functions performed with similar algorithm upstream Clocked Serial Data interface described Section 9.2.1 support byte cell headers. loss cell delineation (LCD) alarm declared after 1318 consecutive cell periods (4.0 155.52Mb/s) HUNT PRESYNC states. alarm cleared after 1318 consecutive cells SYNC state. Codeword (left transmitted first) 11111111 00000000 11111111 01000000 11111111 00100000 11111111 01100000 11111111 00010000 11111111 01010000 11111111 00000100 11111111 01000100 11111111 00111110 11111111 01111110
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9.3.4 Protection Switching Protocol S/UNI-DUPLEX sister device, S/UNI-VORTEX inherently support system architectures requiring fault tolerance redundancy system's common equipment. point-to-point backplane architectures such these, protection also includes associated LVDS links connecting common equipment line cards. S/UNI-VORTEX S/UNI-DUPLEX perform clock recovery, cell delineation, header error monitoring receive high-speed serial links simultaneously. maintained error counts alarm status indications used control system determine state viability each LVDS link. S/UNI-VORTEX data sheet additional details. these architectures, each S/UNI-DUPLEX will connected S/UNIVORTEXs (see Fig. S/UNI-DUPLEXs (see Fig. Upon failure active card, spare card becomes conduit traffic. S/UNIVORTEX S/UNI-DUPLEX facilitate link selection upon start-up well switching between links upon failure conditions. Typically centralized resource cooperating distributed microprocessor subsystems will determine which common card considered active each downstream S/UNI-DUPLEX sets active indication accordingly. current state link's active sent downstream once transmitted cell. active status debounced acted upon far-end S/UNIDUPLEX. S/UNI-DUPLEX will only accept data traffic from LVDS links, normally link marked active that considered working link (although this overridden locally discussed below). Thus, although far-end S/UNI-VORTEX S/UNI-DUPLEX indicate desired active spare links, actually local S/UNI-DUPLEX that must enforce protection switching. link switching mechanism preserves cell integrity high-speed serial link that becomes active. other words, switching occurs between cells. reset Link marked active link. also important note that Loss Signal (LOS) active LVDS link does automatically affect value ACTIVE bit. ACTIVE value prior condition maintained unless other link's active indication asserted (after debouncing) until local override (described below) device reset invoked. value extracted ACTIVE forced logic when corresponding link Loss Cell Delineation (LCD state. S/UNI-DUPLEX auto-selecting active link status (Master Configuration register 0x01, RXAUTOSEL active transmitted LVDS links
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will indicate which link currently chosen active. This reflected ACTIVE have direct affect S/UNI-VORTEX S/UNI-DUPLEX, status typically debounced (must remain same received cells) then stored device. reflected status normally monitored control system determine when protection switching been completed. S/UNI-DUPLEX stores LVDS active indication ACTIVE Master Configuration register (0x01). S/UNI-DUPLEX override active link selection receive direction force link selection transmit direction (this applies S/UNI-DUPLEX S/UNI-DUPLEX type configuration) using Master Configuration register (0x01). S/UNI-DUPLEX forcing ACTIVE link status (Master Configuration register 0x01, RXAUTOSEL active receive link transmitted ACTIVE LVDS links will reflect status Master Configuration register ACTIVE bit. ACTIVE then LVDS link receiver will active link transmitter will indicate active, while LVDS link transmitter will indicate inactive. ACTIVE opposite indications will occur. Cell Buffering Flow Control possibility congestion inherent access multiplexer. downstream direction, link generate burst cells particular device rate exceeding modem's bandwidth capacity. Therefore, feedback core card required cause buffer smooth cell bursts prevent downstream buffer overflow. upstream direction, subscribed aggregate bandwidth exceed that accommodated uplink. Flow control required ensure fair access uplink, minimize cell loss minimize impact greedy users others. 9.4.1 LVDS Receive Traffic Flow Control LVDS receive direction primary task S/UNI-DUPLEX accept cells from active high speed link, inspect PHYID field determine destination cell, then route cell appropriate parallel PHY, clocked serial data interface, microprocessor port. Because LVDS link typically supports much higher transfer bandwidth than external devices, rate decoupling flow control implemented. Flow control signaling implemented using in-band system overhead appended each cell sent over LVDS link (see Table 16). currently active link user cells (those destined parallel clocked serial data interfaces) inter-processor communication channel cells (those destined microprocessor port) processed. inactive link only inter-processor communication cells (hereafter called control cells)
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processed user cells discarded. Both links discard stuff cells after extracting system overhead. active link uses fields system overhead each cell. inactive link monitors PHYID (only identify control channel cells), ACTIVE, BOC, TREF fields. Both links monitor loss signal loss cell delineation conditions. Cells received with incorrect Header Check Sequence (HCS) (due errors during transmission) counted discarded. system overhead fields errored cells ignored. User control channel cells received from high-speed serial link temporarily stored shallow buffer partitioned into separate FIFO each logical channel. discussed below, cells read this buffer under control parallel bus, clocked serial data, microprocessor interface. buffer logically partitioned into FIFO each logical channel. Each FIFO associated flow control user cells, UPCA control channels) embedded within prepended bytes upstream highspeed serial link. P
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