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PM73123 AAL1GATOR-8 LINK CES/DBCES AAL1 PM73123 AAL1GAT


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PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
PM73123
AAL1GATOR-8
AADAPTATION LAYER SEGMENTATION REASSEMBLY PROCESSOR-8
DATASHEET
PROPRIETARY CONFIDENTIAL PRELIMINARY ISSUE JANUARY 2000
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
REVISION HISTORY Issue Issue Date January 2000 Details Change Document created.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
CONTENTS FEATURES APPLICATIONS APPLICATION EXAMPLES INTEGRATED ACCESS DEVICE UNSTRUCTURED OVER A.24
REFERENCES BLOCK DIAGRAM DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION UTOPIA INTERFACE BLOCK (UI) 9.1.1 UTOPIA SOURCE INTERFACE (SRC_INTF) 9.1.2 UTOPIA SINK INTERFACE (SNK_INTF) 9.1.3 UTOPIA BLOCK (UMUX) AAL1 PROCESSING BLOCK (A1SP) 9.2.1 AAL1 TRANSMIT SIDE (TXA1SP).74 9.2.2 AAL1 RECEIVE SIDE (RXA1SP).105 AAL1 CLOCK GENERATION CONTROL .139 9.3.1 DESCRIPTION.139 9.3.2 BLOCK DIAGRAM.141 9.3.3 FUNCTIONAL DESCRIPTION .141
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
PROCESSOR INTERFACE BLOCK (PROCI).155 9.4.1 INTERRUPT DRIVEN ERROR/STATUS REPORTING .160 9.4.2 QUEUE FIFO .163
INTERFACE BLOCK (RAMI).166 LINE INTERFACE BLOCK (AAL1_LI).167 9.6.1 CONVENTIONS .167 9.6.2 FUNCTIONAL DESCRIPTION .167 9.6.3 TRANSMIT DIRECTION .172
JTAG TEST ACCESS PORT .177
MEMORY MAPPED REGISTER DESCRIPTION .178 10.1 10.2 INITIALIZATION .179 A1SP LINE CONFIGURATION STRUCTURES.180 10.2.1 HS_LIN_REG .181 10.3 TRANSMIT STRUCTURES SUMMARY .186 10.3.1 P_FILL_CHAR.188 10.3.2 T_SEQNUM_TBL.188 10.3.3 T_COND_SIG .189 10.3.4 T_COND_DATA .191 10.3.5 RESERVED (TRANSMIT SIGNALING BUFFER) .192 10.3.6 T_OAM_QUEUE .193 10.3.7 T_QUEUE_TBL.194 10.3.8 RESERVED (TRANSMIT DATA BUFFER).205 10.4 RECEIVE DATA STRUCTURES SUMMARY.207
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
10.4.1 R_OAM_QUEUE_TBL .208 10.4.2 R_OAM_CELL_CNT .209 10.4.3 R_DROP_OAM_CELL .210 10.4.4 R_SRTS_CONFIG .210 10.4.5 R_CRC_SYNDROME .211 10.4.6 R_CH_TO_QUEUE_TBL .215 10.4.7 R_COND_SIG .217 10.4.8 R_COND_DATA.219 10.4.9 RESERVED (RECEIVE SRTS QUEUE).220 10.4.10 RESERVED (RECEIVE SIGNALING BUFFER).221 10.4.11 R_QUEUE_TBL .222 10.4.12 R_OAM_QUEUE.239 10.4.13 RESERVED (RECEIVE DATA BUFFER).240 NORMAL MODE REGISTER DESCRIPTION .242 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 COMMAND REGISTERS .243 INTERFACE REGISTERS.250 UTOPIA INTERFACE REGISTERS .252 LINE INTERFACE REGISTERS .262 DIRECT SPEED MODE REGISTERS .262 INTERRUPT STATUS REGISTERS .266 IDLE CHANNEL DETECTION CONFIGURATION STATUS REGISTERS .282 CONTROL STATUS REGISTERS.297
OPERATION .302
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
12.1 12.2
HARDWARE CONFIGURATION .302 START-UP .302 12.2.1 LINE CONFIGURATION.303 12.2.2 QUEUE CONFIGURATION .303 12.2.3 ADDING QUEUES .303 12.2.4 LINE CONFIGURATION DETAILS .304
12.3 12.4
UTOPIA INTERFACE CONFIGURATION.305 JTAG SUPPORT .305 12.4.1 CONTROLLER .307
FUNCTIONAL TIMING.312 13.1 13.2 13.3 13.4 SOURCE UTOPIA.313 SINK UTOPIA .318 PROCESSOR .325 EXTERNAL CLOCK GENERATION CONTROL (CGC).327 13.4.1 SRTS DATA OUTPUT.327 13.4.2 CHANNEL UNDERRUN STATUS OUTPUT .328 13.4.3 ADAPTIVE STATUS OUTPUT .329 13.5 13.6 FREQ SELECT INTERFACE .330 LINE INTERFACE TIMING.332 13.6.1 LINE MODE.332 13.6.2 H-MVIP TIMING .335 13.6.3 DS3/E3 TIMING.341
ABSOLUTE MAXIMUM RATINGS .342
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
D.C. CHARACTERISTICS.343 A.C. TIMING CHARACTERISTICS .345 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 RESET TIMING.345 SYSCLK TIMING.346 NCLK TIMING .347 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS .348 EXTERNAL CLOCK GENERATION CONTROL INTERFACE .353 INTERFACE .354 UTOPIA INTERFACE .356 LINE TIMING.359 16.8.1 DIRECT SPEED TIMING .359 16.8.2 H-MVIP TIMING .361 16.8.3 HIGH SPEED TIMING .363 16.9 JTAG TIMING .365
ORDERING THERMAL INFORMATION.367 MECHANICAL INFORMATION.368 DEFINITIONS .370
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
LIST FIGURES FIGURE AAL1GATOR-8 INTEGRATED ACCESS DEVICE (IAD) APPLICATION. FIGURE AAL1GATOR- UNSTRUCTURED OVER AAPPLICATION. FIGURE AAL1GATOR-8 INTERNAL BLOCK DIAGRAM FIGURE DATA FLOW BUFFERING A1SP BLOCKS FIGURE BLOCK DIAGRAM FIGURE A1SP BLOCK DIAGRAM.72 FIGURE CAPTURE SIGNALING BITS FIGURE CAPTURE SIGNALING BITS.75 FIGURE TRANSMIT FRAME TRANSFER CONTROLLER.75 FIGURE SDF-MF FORMAT T_DATA_BUFFER FIGURE SF-SDF-MF FORMAT T_DATA_BUFFER FIGURE SDF-FR FORMAT T_DATA_BUFFER FIGURE SDF-MF FORMAT T_DATA_BUFFER.79 FIGURE SDF-MF WITH SIGNALING FORMAT T_DATA_BUFFER.79 FIGURE SDF-FR FORMAT T_DATA_BUFFER FIGURE UNSTRUCTURED FORMAT T_DATA_BUFFER.80 FIGURE SDF-MF FORMAT T_SIGNALING_BUFFER.81 FIGURE SDF-MF FORMAT T_SIGNALING BUFFER FIGURE SDF-MF FORMAT T_SIGNALING_BUFFER
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
FIGURE SDF-MF WITH SIGNALING FORMAT T_SIGNALING_BUFFER FIGURE TRANSMIT SIDE SRTS FUNCTION FIGURE IDLE DETECTION CONFIGURATION REGISTER STRUCTURE.84 FIGURE IDLE DETECTION INTERRUPT WORD FIGURE BAND SIGNALING IDLE DETECTION INTERRUPT WORD FIGURE BAND SIGNALING CONFIGURATION REGISTER STRUCTURE.86 FIGURE CHANNEL ACTIVE/IDLE TABLE STRUCTURE FIGURE PAT_MTCH_CFG REGISTER STRUCTURE.88 FIGURE PATTERN MATCH IDLE DETECTION REGISTER STRUCTURE FIGURE PATTERN MATCH IDLE DETECTION INTERRUPT WORD FIGURE FRAME ADVANCE FIFO OPERATION FIGURE PAYLOAD GENERATION FIGURE 32-LOCAL LOOPBACK .104 FIGURE CELL HEADER INTERPRETATION .106 FIGURE FAST ALGORITHM .112 FIGURE RECEIVE CELL PROCESSING FAST SN.113 FIGURE ROBUST ALGORITHM .116 FIGURE CELL RECEPTION.118 FIGURE SDF-MF FORMAT R_DATA_BUFFER .119 FIGURE SDF-MF FORMAT R_DATA_BUFFER.119 FIGURE SDF-FR FORMAT R_DATA_BUFFER.120
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
viii
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
FIGURE SDF-MF FORMAT R_DATA_BUFFER .120 FIGURE SDF-MF WITH SIGNALING FORMAT R_DATA_BUFFER .121 FIGURE SDF-FR FORMAT R_DATA_BUFFER .121 FIGURE UNSTRUCTURED FORMAT R_DATA_BUFFER .122 FIGURE SDF-MF FORMAT R_SIG_BUFFER.122 FIGURE SDF-MF FORMAT R_SIG_BUFFER .123 FIGURE SDF-MF FORMAT R_SIG_BUFFER .123 FIGURE SDF-MF WITH SIGNALING FORMAT R_SIG_BUFFER .124 FIGURE POINTER/STRUCTURE STATE MACHINE.129 FIGURE OVERRUN DETECTION .131 FIGURE OUTPUT SIGNALING BITS .135 FIGURE OUTPUT SIGNALING BITS .135 FIGURE CHANNEL-TO-QUEUE TABLE OPERATION .137 FIGURE RECEIVE SIDE SRTS SUPPORT.138 FIGURE SRTS DATA.143 FIGURE CHANNEL STATUS FUNCTIONAL TIMING .143 FIGURE ADAPTIVE DATA FUNCTIONAL TIMING .145 FIGURE 58-EXT FREQ SELECT FUNCTIONAL TIMING.146 FIGURE RECEIVE SIDE SRTS SUPPORT.147 FIGURE DIRECT ADAPTIVE CLOCK OPERATION.149 FIGURE MEMORY MAP.155 FIGURE A1SP SRAM MEMORY .155
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
FIGURE CONTROL REGISTERS MEMORY MAP.156 FIGURE TRANSMIT DATA STRUCTURES MEMORY .157 FIGURE RECEIVE DATA STRUCTURES .158 FIGURE NORMAL MODE REGISTERS MEMORY .160 FIGURE INTERRUPT HIERARCHY .161 FIGURE ADDQ_FIFO WORD STRUCTURE .163 FIGURE LINE INTERFACE BLOCK ARCHITECTURE.169 FIGURE CAPTURE SIGNALING BITS .172 FIGURE CAPTURE SIGNALING BITS.172 FIGURE OUTPUT SIGNALING BITS .174 FIGURE OUTPUT SIGNALING BITS .174 FIGURE SDF-MF FORMAT T_SIGNALING BUFFER.193 FIGURE R_CRC_SYNDROME MASK TABLE LEGEND.212 FIGURE BOUNDARY SCAN ARCHITECTURE.306 FIGURE CONTROLLER FINITE STATE MACHINE.308 FIGURE PIPELINED SSRAM .312 FIGURE PIPELINED SSRAM .312 FIGURE 80SRC_INTF START TRANSFER TIMING (UTOPIA AMODE) FIGURE 81SRC_INTF END-OF-TRANSFER TIMING (UTOPIA AMODE) FIGURE 82-UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE UI_SRC_INTF END-OF-TRANSFER (UTOPIA MODE) .315
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
FIGURE 84UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE UI_SRC_INTF END-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE 86UI_SRC_INTF START-OF-TRANSFER TIMING (ANY-PHY MODE) FIGURE UI_SRC_INTF END-OF-TRANSFER TIMING (ANY-PHY MODE) FIGURE 88SNK_INTF START-OF-TRANSFER TIMING (UTOPIA AMODE) FIGURE .SNK_INTF END-OF-TRANSFER TIMING (UTOPIA AMODE)320 FIGURE 90SNK_INTF START-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE SNK_INTF START-OF-TRANSFER UTOPIA .321 FIGURE SNK_INTF CLAV DISABLE UTOPIA .322 FIGURE SNK_INTF END-OF-TRANSFER UTOPIA .322 FIGURE 94SNK_INTF START-OF-TRANSFER (ANY-PHY MODE) .323 FIGURE .SNK_INTF END-OF-TRANSFER (ANY-PHY MODE)324 FIGURE MICROPROCESSOR WRITE ACCESS .325 FIGURE MICROPROCESSOR READ ACCESS .326 FIGURE MICROPROCESSOR WRITE ACCESS WITH .326 FIGURE MICROPROCESSOR READ ACCESS WITH ALE.326 FIGURE SRTS DATA327 FIGURE CHANNEL STATUS FUNCTIONAL TIMING328 FIGURE ADAPTIVE DATA FUNCTIONAL TIMING330 FIGURE .-EXT FREQ SELECT FUNCTIONAL TIMING331
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
FIGURE RECEIVE LINE SIDE TIMING(RL_CLK 1.544 MHZ)332 FIGURE RECEIVE LINE SIDE TIMING(RL_CLK 2.048 MHZ)333 FIGURE MVIP-90 RECEIVE FUNCTIONAL TIMING333 FIGURE TRANSMIT LINE SIDE TIMING(TL_CLK 1.544 MHZ)334 FIGURE -TRANSMIT LINE SIDE TIMING(TL_CLK 2.048 MHZ)334 FIGURE MVIP-90 TRANSMIT FUNCTIONAL TIMING335 FIGURE RECEIVE H-MVIP TIMING, CLOSE-UP VIEW336 FIGURE RECEIVE H-MVIP TIMING, EXPANDED VIEW337 FIGURE TRANSMIT H-MVIP TIMING, CLOSE-UP VIEW338 FIGURE .TRANSMIT H-MVIP TIMING, EXPANDED VIEW340 FIGURE RECEIVE HIGH-SPEED FUNCTIONAL TIMING341 FIGURE TRANSMIT HIGH-SPEED FUNCTIONAL TIMING341 FIGURE EXTERNAL CLOCK GENERATION CONTROL INTERFACE TIMING FIGURE INTERFACE TIMING.355 FIGURE SINK UTOPIA INTERFACE TIMING .357 FIGURE SOURCE UTOPIA INTERFACE TIMING .358 FIGURE TRANSMIT SPEED INTERFACE TIMING.359 FIGURE RECEIVE SPEED INTERFACE TIMING .360 FIGURE 122: H-MVIP SINK DATA FRAME PULSE TIMING .362 FIGURE 123: H-MVIP INGRESS DATA TIMING.362 FIGURE TRANSMIT HIGH SPEED TIMING363 FIGURE RECEIVE HIGH SPEED INTERFACE TIMING .364 FIGURE 126: JTAG PORT INTERFACE TIMING.366
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
FIGURE 127: PBGA 23X23MM BODY .368
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
xiii
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE LINE INTERFACE SIGNAL TABLE SELECTION.46 LINE INTERFACE SUMMARY.52 CFG_ADDR PHY_ADDR USAGE DIRECTION CFG_ADDR PHY_ADDR USAGE DIRECTION CHANNEL STATUS.144 BUFFER DEPTH .145 FREQUENCY SELECT MODE .152 FREQUENCY SELECT MODE .154 LINE_MODE ENCODING.168
TABLE AAL1GATOR-8 MEMORY .179 TABLE A1SP LINE CONFIGURATION STRUCTURES SUMMARY180 TABLE TRANSMIT STRUCTURES SUMMARY .186 TABLE R_CRC_SYNDROME MASK TABLE .212 TABLE R_QUEUE_TBL FORMAT .223 TABLE REGISTER MEMORY MAP.242 TABLE -COMMAND REGISTER MEMORY MAP.243 TABLE -RAM INTERFACE REGISTERS MEMORY .250 TABLE UTOPIA INTERFACE REGISTERS MEMORY .252 TABLE TABLE CFG_ADDR PHY_ADDR USAGE DIRECTION259 CFG_ADDR PHY_ADDR USAGE DIRECTION260
TABLE LINE INTERFACE REGISTER MEMORY SUMMARY.262 TABLE DIRECT SPEED MODE REGISTER MEMORY .262
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
TABLE INTERRUPT STATUS REGISTERS MEMORY .266 TABLE IDLE CHANNEL DETECTION CONFIGURATION STATUS REGISTERS MEMORY .282 TABLE CONTROL STATUS REGISTERS MEMORY .297 TABLE CHANNEL STATUS.328 TABLE FRAME DIFFERENCE .330 TABLE ABSOLUTE MAXIMUM RATINGS.342 TABLE AAL1GATOR-8 D.C. CHARACTERISTICS .343 TABLE RTSB TIMING .345 TABLE SYSCLK TIMING .346 TABLE NCLK TIMING .347 TABLE MICROPROCESSOR INTERFACE READ ACCESS.348 TABLE MICROPROCESSOR INTERFACE WRITE ACCESS .350 TABLE EXTERNAL CLOCK GENERATION CONTROL INTERFACE .353 TABLE INTERFACE.354 TABLE UTOPIA SOURCE SINK INTERFACE .356 TABLE TRANSMIT SPEED INTERFACE TIMING .359 TABLE RECEIVE SPEED INTERFACE TIMING .360 TABLE H-MVIP SINK TIMING.361 TABLE H-MVIP SOURCE TIMING.362 TABLE TRANSMIT HIGH SPEED INTERFACE TIMING .363 TABLE RECEIVE HIGH SPEED INTERFACE TIMING.363 TABLE JTAG PORT INTERFACE.365 TABLE AAL1GATOR-8 (PM73123) ORDERING INFORMATION .367
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
TABLE AAL1GATOR-8 (PM73123) THERMAL INFORMATION .367
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
FEATURES AAL1gator-8 AAL1 Segmentation Reassembly (SAR) Processor monolithic single chip device that provides DS1, DS3, STS-1 STM-0 line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator-8 device. Compliant with AForum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), ITU-T I.363.1 Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with AForum's DBCES specification (AF-VTOA0085). Supports idle channel detection processor intervention, signaling, data pattern detection. Provides idle channel indication channel basis. Supports non-DBCES idle channel detection activating queue when constituent time slots active, deactivating queue when constituent time slots inactive. Provides AAL1 segmentation reassembly individual lines, H-MVIP lines MHz, DS3, STS-1 unstructured lines. Provides standard UTOPIA level Interface which optionally supports parity runs MHz. Only Cell Level Handshaking supported. MPHY mode, like single port port device. following modes supported: 8/16-bit Level Multi-Phy Mode (MPHY) 8/16-bit Level SPHY 8-bit Level AMaster
Provides optional 8/16-bit Any-PHY slave interface. Supports Virtual Channels (VC).
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Supports (consecutive channels) (non-consecutive channels) structured data format. Provides transparent transmission Common Channel Signaling (CCS) Channel Associated Signaling (CAS). Provides termination signaling. Provides per-VC data signaling conditioning transmit cell direction data signaling conditioning transmit line direction. Data signaling conditioning individually enabled. Includes conditioning support both directions. Transmit line conditioning options include programmable byte pattern, pseudo-random pattern data. Conditioning automatically occurs underruns. Cell Transmit direction, provides per-VC configuration time slots allocated, signaling support, partial cell size, data signaling conditioning, ACell header definition. Generates AAL1 sequence numbers, pointers SRTS values accordance with ITU-T I.363.1. Multicast connections supported. Cell Transmit direction provides counters for: Conditioned cells transmitted each queue Cells which were suppressed each queue Total number cells transmitted each queue
Cell Receive direction, provides per-VC configuration time slots allocated, signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers accordance with ITU-T I.363.1. Cell Receive direction, supports Fast Sequence Number processing algorithm types connections Robust Sequence Number processing Unstructured Data Format (UDF) connections. Cells inserted/dropped maintain integrity lost misinserted cells. integrity maintained through single errored cell lost cells, even underrun occurs. Pointer bytes taken into account. Cell insertion options include programmable single byte pattern, pseudo-random data, data
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Cell Receive direction provides counters following events which include counters required AForum's CES-IS MIB: Incorrect sequence numbers queue Incorrect sequence number protection fields queue Total number received cells queue Total number dropped cells queue Total number underruns queue Total number lost cells queue Total number overruns queue Total number reframes queue Total number pointer parity errors queue Total number misinserted cells queue Total number non-data cells received Total number non-data cells dropped.
each receive queue following sticky bits maintained: Cell received Structured pointer rule error detected DBCES bitmask parity error Cell dropped blank allocation table Cells dropped pointer search Cell dropped forced underrun Cell dropped sequence number processing algorithm Valid pointer received
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Pointer parity error detected SRTS resume from underrun condition SRTS underrun occurred Resume occurred from underrun condition Pointer reframe occurred Overrun condition detected Cell received while underrun
Supports AAL0 mode, selectable basis. Provides system side loopback support. When enabled incoming matches programmable loopback VCI, cell received Receive UTOPIA interface looped back Transmit UTOPIA interface. Alternatively UTOPIA interface into remote loopback mode where incoming cells looped back out. Provides line side loopback, enabled queue basis, which loop single channel group channels which mapped single queue. Provides patented frame based calendar queue service algorithm with anti-clumping add-queue mechanism that produces minimal Cell Delay Variation (CDV). mode uses non-frame based scheduling optimize CDV. Queues added making entries into add-queue FIFO minimize queue activation overhead. offset configured when queue added distribute cell build times minimize clumping. Provides single maskable, open-collector interrupt with master interrupt register facilitate interrupt processing. master interrupt register indicates following conditions each which masked: Error/status condition with AAL1 block parity error
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
UTOPIA parity error Transmit UTOPIA FIFO full Transmit UTOPIA transfer error UTOPIA loopback FIFO full UTOPIA runt cell detected
AAL1 block following conditions cause interrupt, each which masked. entry FIFO used track receive transmit status. receive queue sticky just (individual mask sticky bit) Receive queue entered underrun statex Receive queue exited underrun state DBCES bitmask changed. Receive Status FIFO overflow Transmit Frame Advance FIFO full Reception cells Change idle state channel enabled idle channel detection Transmit Channel Idle State change FIFO overflow Line frame resync event Transmit ALayer Processor (TALP) FIFO full
Provides 16-bit microprocessor interface internal registers external 128K 16(18) Synchronous SRAM RAM. Provides transmit buffer which used Operations, Administration Maintenance (OAM) cells well other usergenerated cells such AAL5 cells Asignaling.
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PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
corresponding receive buffer exists reception cells non-AAL1 data cells. Includes internal E1/T1 clock synthesizer each line which generate nominal E1/T1 clock controlled Synchronous Residual Time Stamp (SRTS) clock recovery method Unstructured Data Format (UDF) mode programmable weighted moving average adaptive clocking algorithm. clock synthesizers also controlled externally provide customization SRTS adaptive algorithms. SRTS also disabled hardware input. Adaptive SRTS information output port external processing both speed high speed mode, needed. Buffer depth provided units bytes. synthesizer discrete frequencies between either +/100 +/-200 Low-power Volt CMOS technology with Volt, Volt tolerant I/O. 324-pin fine pitch plastic ball grid array (PBGA) package.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
APPLICATIONS Multi-service ASwitch AAccess Concentrator Digital Cross Connect Computer Telephony Chassis with Ainfrastructure Wireless Local Loop Back Haul APassive Optical Network (APON) Equipment Integrated Access Device (IAD) Unstructured DS3/E3/STS-1/STM-0 over A
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
APPLICATION EXAMPLES Integrated Access Device Integrated Access Device (IAD) consolidates voice, data, Internet, video wide-area network services using Aover shared T1/E1 lines. IADs also unify functions many different types equipment including CSUs, DSUs multiplexers. Figure shows AAL1gator-8 connected eight PM4351 COMETs, PM7326 S/UNI-APEX Traffic Manager, Inverse Multiplexing over Adevice, PM7344 S/UNIMPH T1/E1 UNIs eight PM4351 COMETs uplink.
ATraffic Management
UTOPIA Any-PHY UTOPIA
Service Adaptation
PBX, Videoconferencing Terminal
APHY with
T1/E1
PM4351 PM4351 COMET PM4351 COMET COMET
PM73123 AAL1gator-8
PM7326 S/UNI-APEX
Inverse Multiplexing over A
Router
Packet Processor
AAL5
Cell FIFO
M7734 S/UNI-MPH S/UNI-MPH
PM4351 COMET PM4351 COMET
AIMA
T1/E1
Figure AAL1gator-8 Integrated Access Device (IAD) Application.
Unstructured over AApplications requiring high speed unstructured data transfer DS3, STS-1, STM-0 rates suited AAL1gator-8 shown Figure PM5342 SPECTRA-155 provides SONET/SDH overhead processing OC-3 rate 155.52 Mbps. Three streams into three AAL1gator-8s. AAL1gator-8 also connected directly LIU. Aside each AAL1gator-8 configured either UTOPIA Level Any-PHY interconnecting PM7326 S/UNI-APEX ATraffic Manager Switch device. S/UNI-155-TETRA provides four Aover SONET OC-3c PHYs.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
UTOPIA
UTOPIA/ Any-PHY
PM73123 AAL1gator-8 PM5342 SPECTRA155 PM73123 AAL1gator-8 PM73123 AAL1gator-8
PM7326 S/UNI-APEX
PM5351 S/UNI-155TETRA
PM73123 AAL1gator-8
Cell FIFO
Figure AAL1gator- Unstructured over AApplication.
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PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
REFERENCES Applicable Recommendations Standards. ANSI Recommendation T1.403, Network-to-Customer Installation Metallic Interface, 1995. ANSI Recommendation T1.630, Broadband ISDN-AAdaptation Layer Constant Rate Services, Functionality Specification, 1993. AForum, AUser Network Interface (UNI) Specification, 3.1, Foster City, USA, September 1994. AForum, Circuit Emulation Service Interoperability Specification (CES-IS), 2.0, Foster City, USA, August 1996. AForum, Specifications (DBCES) Dynamic Bandwidth Utilization 64Kbps Time Slot Trunking Over Using CES, Foster City, USA, (AF-VTOA-0085) July 1997. AForum, UTOPIA, ATM-PHY Layer Specification, Level 2.01, Foster City, USA, March 1994. AForum, UTOPIA, ATM-PHY Layer Specification, Level 1.0, Foster City, USA, June 1995. ITU-T Recommendation G.703, Physical/Electrical Characteristics Hierarchical Digital Interfaces, April 1991. ITU-T Recommendation I.363.1, B-ISDN AAdaptation Layer (AAL) Specification, July 1995. ITU-T Recommendation G.823, Control Jitter Wander within Digital Networks Which Based 2048 kbit/s Hierarchy, March 1993. ITU-T Recommendation G.824 Control Jitter Wander within Digital Networks Which Based 1544 kbit/s Hierarchy, March 1993. GO-MVIP "MVIP-90 Standard" Release 1.1, October 1994. GO-MVIP "H-MVIP Standard" Release 1.1a, January 1997.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
BLOCK DIAGRAM AAL1gator-8 contains AAL1 Processor (A1SP) which performs segmentation re-assembly AAL1 cells. A1SP block interfaces common UTOPIA interface side Line Interface block other side which configured support several different line protocols. A1SP block connects interface. processor Interface block, which also contains external clock control interface shared blocks. Figure AAL1gator-8 Internal Block Diagram
RL_CLK[7:0] TL_CLK_OE TL_CLK[7:0] CRL_CLK
RSTB SCAN_ENB SCAN_MODEB TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0]
CTL_CLK
SYSCLK
NCLK
Clock
Line Interface
LINE_MODE
H-MVIP UTOPIA Interface
TL_DATA[7:0] TL_SYNC[7:0] TL_SIG[7:0] RL_DATA[7:0] RL_SYNC[7:0] RL_SIG[7:0]
A1SP
Direct Mode
JTAG
Interface
Processor Interface
External Clock Interface
CGC_DOUT[3:0]
RAM_ADSCB
RAM_PAR[1:0]
D[15:0]
A[19:0]
TRST
ADAP_STB
ACKB
RAM_WEB[1:0]
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CGC_LINE[3:0]
CGC_SER_D
RAM_D[15:0]
RAM_CSB
RAM_A[16:0]
CGC_VALID
SRTS_STB
RAM_OEB
INTB
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
DESCRIPTION AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator8) monolithic single chip device that provides DS1, DS3, STS-1, STM-0 line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator-8 device.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
DIAGRAM
AAL1gator-8 manufactured pin, fine pitch, plastic ball grid array (PBGA) package. Bottom View PBGA Package (23mm
RL_CLK
TL_CLK
TL_SYNC
RAM1_D
RAM1_OE
RAM1_D
SCAN_EN
RAM1_D
RAM1_WE
RAM1_PA
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
SYSCLK
[15]
[10]
[14]
[10]
TL_SYNC
RL_SYNC
RL_SIG
TL_DATA
LINE_MO
RAM1_D
RAM1_D
RAM1_D
RAM1_D
RAM1_D
RAM1_D
RAM1_AD
RAM1_WE
RAM1_AD
RAM1_CS
RAM1_AD
RAM1_AD
TCLK
TATM_DA
[14]
[11]
[13]
[14]
RL_SIG
TL_CLK
RL_SYNC
TL_SIG
CTL_CLK
RAM1_D
RAM1_D
RAM1_D
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
TATM_DA
RPHY_AD
[13]
[16]
[12]
[15]
D_RSX
TL_SIG
RL_DATA
CRL_CLK
RAM1_D
RAM1_D
RAM1_D
RAM1_D
RAM1_PA
RAM1_AD
RAM1_AD
RAM1_AD
TATM_PA
TATM_DA
TATM_DA
[12]
[15]
[11]
[13]
[11]
RL_DATA
RL_CLK
TL_DATA
TL_CLK
TATM_DA
TATM_DA
[12]
[10]
TL_DATA
TL_SYNC
RL_SYNC
TATM_CL
TATM_DA
TATM_DA
RL_CLK
RL_SIG
TL_SIG
RPHY_AD
RPHY_AD
RPHY_AD
TL_CLK
TL_SYNC
RL_DATA
TL_SIG
TATM_DA
TATM_EN
TATM_SO
RPHY_AD
RL_CLK
RL_SIG
TL_DATA
RL_SYNC
TATM_CL
TATM_DA
TATM_DA
TATM_DA
TL_CLK
TL_SYNC
RL_DATA
TL_SIG
TATM_DA
TATM_DA
TATM_DA
RL_CLK
TL_DATA
TATM_DA
RATM_DA
RL_SIG
RL_SYNC
RATM_DA
RATM_EN
RATM_DA
TL_SYNC
TL_CLK
TL_SIG
RL_DATA
RATM_DA
RATM_DA
RATM_DA
RATM_DA
RL_SIG
RL_CLK
RL_SYNC
TL_DATA
RATM_DA
TPHY_AD
RATM_CL
RATM_SO
TL_CLK
TL_SIG
RL_DATA
RATM_PA
TPHY_AD
RATM_CL
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
RL_SIG
RL_CLK
RL_DATA
TL_SYNC
TPHY_AD
RATM_DA
TPHY_AD
RL_SYNC
TL_CLK
TL_DATA
RATM_DA
RATM_DA
RATM_DA
[12]
[11]
TL_DATA
TL_SYNC
RATM_DA
RATM_DA
TPHY_AD
[10]
[15]
RL_SYNC
CGC_LINE
CGC_VALI
INTB
[10]
SCAN_MO
[19]
RATM_DA
[13]
TL_SIG
RL_SIG
TRSTB
TL_CLK_O
CGC_DOU
[13]
[15]
[12]
[18]
RATM_DA
[14]
RL_CLK
RSTB
SRTS_ST
ADAP_ST
CGC_LINE
CGC_SER
NCLK
CGC_DOU
ACKB
[10]
[14]
[13]
[17]
RL_DATA
CGC_LINE
CGC_LINE
CGC_DOU
CGC_DOU
[11]
[11]
[15]
[12]
[14]
[16]
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
DESCRIPTION UTOPIA Interface Signals (52) Name Type
Function
Note signals have different meanings depending whether UTOPIA Amaster mode, mode Any-PHY mode. mode controlled UTOP_MODE ANY-PHY_EN fields UI_SRC_CFG UI_SNK_CFG registers. outputs tri-state when chip reset when UI_EN disabled UI_COMN_CFG register. outputs have maximum output current (IMAX) TATM_CLK/RPHY_CLK Input ATM: Transmit UTOPIA ALayer Clock synchronization clock input TAinterface. PHY: Receive UTOPIA/Any-PHY Layer Clock synchronization clock input RPHY interface Maximum frequency MHz. TATM_SOC/RPHY_SOC /RSOP Output ATM: Transmit UTOPIA ALayer Start-Of-Cell active high signal asserted AAL1gator-8 when TATM_D contains first valid byte cell. PHY: Receive Any-PHY/UTOPIA Layer Start-Of-Cell active high signal asserted AAL1gator-8 when RPHY_D[15:0] contains first valid word cell. AAL1gator-8 drives this signal only when Alayer selected cell transfer. Any-PHY: This Receive Start Packet (RSOP) signal which functions just like RPHY_SOC.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name TATM_D[15]/RPHY_D[15] TATM_D[14]/RPHY_D[14] TATM_D[13]/RPHY_D[13] TATM_D[12]/RPHY_D[12] TATM_D[11]/RPHY_D[11] TATM_D[10]/RPHY_D[10] TATM_D[9]/RPHY_D[9] TATM_D[8]/RPHY_D[8] TATM_D[7]/RPHY_D[7] TATM_D[6]/RPHY_D[6] TATM_D[5]/RPHY_D[5] TATM_D[4]/RPHY_D[4] TATM_D[3]/RPHY_D[3] TATM_D[2]/RPHY_D[2] TATM_D[1]/RPHY_D[1] TATM_D[0]/RPHY_D[0]
Type Output
Function ATM: Transmit UTOPIA ALayer Data Bits form byte-wide data driven layer. Least Significant (LSB). Most Significant (MSB) should transmitted first. Note that only lower used Amaster mode. PHY: Receive UTOPIA/Any-PHY Layer Data Bits form word-wide data driven Alayer. Drives this only when Alayer selected cell transfer. upper byte only used 16_BIT_MODE UI_SRC_CFG register. Otherwise upper byte tristate. LSB. first byte should transmitted first. ATM: Transmit UTOPIA ALayer Parity byte parity covering TATM_D(7:0). PHY: Receive UTOPIA/Any-PHY Layer Parity either byte parity covering RPHY_D(7:0) word parity covering RPHY_D(15:0) depending value 16_BIT_MODE.
TATM_PAR/ RPHY_PAR
Output
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name TATM_ENB/RPHY_ENB /RENB
Type Bidi
Function ATM: Transmit UTOPIA ALayer Enable active signal asserted AAL1gator-8 during cycles when TATM_D contains valid data. asserted until AAL1gator-8 ready send full cell. PHY: Receive UTOPIA/Any-PHY Layer Enable active signal asserted Alayer indicate RPHY_D RPHY_SOC will sampled next cycle. UTOP_MODE UI_SRC_CFG UTOPIA Level Mode then AAL1gator-8 will drive data only RPHY_ADD matches CFG_ADDR UI_SRC_ADD_CFG register cycle before RPHY_ENB goes low. Any-PHY: This RENB input signal, which functions same RPHY_ENB. only difference that data driven cycles after selection instead just cycle.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name TATM_CLAV/RPHY_CLAV /RPA
Type Bidi
Function ATM: Transmit UTOPIA ALayer Cell Available active high signal from layer device indicate that there sufficient room accept cell. PHY: Receive UTOPIA/Any-PHY Layer Cell Available active high signal asserted AAL1gator-8 indicate ready deliver complete cell. Utopia Level mode, this signal driven only when MPHY_ADD matches CFG_ADDR UI_SRC_ADD_CFG register previous cycle. Any-PHY: This Receive Packet Available (RPA) signal which functions same RPHY_CLAV except activated cycles after matching address instead one.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name RPHY_ADD[4]/RSX RPHY_ADD[3]/RCSB RPHY_ADD[2] RPHY_ADD[1] RPHY_ADD[0]
Type Input Input Input Input
Function ATM: These signals used Amode. PHY: Receive UTOPIA Layer Address (Bits which selects UTOPIA receiver. These inputs used output enable RPHY_CLAV validate activation RPHY_ENB. There internal pull-up resistors. These pins compared with CFG_ADDR[5:0] UI_SRC_CFG_ADDR register. ANY-PHY: Receive Start Transfer(RSX) active high output which indicates start Any-PHY packet which identifies location prepended address. ANY-PHY_EN UI_SRC_CFG register needs this function. Receive Chip Select (RCSB) active input which used select AAL1gator-8 when polling Any-PHY mode. This input used decode Any-PHY address bits greater than RPHY_ADD[2]. This input goes cycle after Any-PHY address valid. ANY-PHY_EN CS_MODE_EN UI_SRC_CFG register needs this function. Otherwise this functions RPHY_ADD[3]. RPHY_ADD[2:0] bottom three bits Any-PHY address used select device when polling. These pins compared with CFG_ADDR[2:0] UI_SRC_CFG_ADDR register. Note these pins must tied ground when used.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name RATM_CLK/ TPHY_CLK
Type Input
Function ATM: Receive UTOPIA ALayer Clock synchronization clock input synchronizing RAinterface. PHY: Transmit UTOPIA/Any-PHY Layer Clock synchronization clock input synchronizing TPHY interface. Maximum frequency MHz.
RATM_SOC/ TPHY_SOC /TSOP
Input
This signal definitions depending whether UTOPIA Amode mode. ATM: Receive UTOPIA ALayer Start-Of-Cell active high signal asserted layer when RATM_D contains first valid byte cell. PHY: Transmit UTOPIA/Any-PHY Layer Start-Of-Cell active high signal asserted Alayer when TPHY_D contains first valid byte cell. Any-PHY: This Transmit Start Packet (TSOP) signal which functions just like TPHY_SOC. This signal optional this mode. unused, low.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name RATM_D[15]/TPHY_D[15] RATM_D[14]/TPHY_D[14] RATM_D[13]/TPHY_D[13] RATM_D[12]/TPHY_D[12] RATM_D[11]/TPHY_D[11] RATM_D[10]/TPHY_D[10] RATM_D[9]/TPHY_D[9] RATM_D[8]/TPHY_D[8] RATM_D[7]/TPHY_D[7] RATM_D[6]/TPHY_D[6] RATM_D[5]/TPHY_D[5] RATM_D[4]/TPHY_D[4] RATM_D[3]/TPHY_D[3] RATM_D[2]/TPHY_D[2] RATM_D[1]/TPHY_D[1] RATM_D[0]/TPHY_D[0] RATM_PAR/ TPHY_PAR
Type Input
Function ATM: Receive UTOPIA ALayer Data Bits form byte-wide data from layer device. LSB. should received first. upper byte used Amode. PHY: Transmit UTOPIA/Any-PHY Layer Data Bits form word-wide data from Alayer device. LSB. first byte should received first. upper byte only used 16_BIT_MODE UI_SNK_CFG register.
Input
ATM: Receive UTOPIA ALayer Parity byte parity covering RATM_D(7:0) word parity covering RATM_D(15:0) depending value 16_BIT_MODE. PHY: Transmit UTOPIA/Any-PHY Layer Parity either byte parity covering TPHY_D(7:0) word parity covering TPHY_D(15:0) depending value 16_BIT_MODE.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name RATM_ENB/TPHY_ENB
Type Bidi
Function ATM: Receive UTOPIA ALayer Enable active signal asserted AAL1gator-8 indicate RATM_D RATM_SOC will sampled next cycle. will asserted until AAL1gator-8 ready receive full cell. PHY: Transmit UTOPIA/Any-PHY Layer Enable active signal asserted Alayer device during cycles when TPHY_D[15:0] contain valid data. AAL1gator-8 will accept data only TPHY_ADD matches CFG_ADDR UI_SNK_CFG register cycle before TPHY_ENB goes Any-PHY: This TENB input signal, which functions same TPHY_ENB. only difference that data expected cycles after selection instead just cycle.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name RATM_CLAV/TPHY_CLAV
Type Bidi
Function ATM: Receive UTOPIA ALayer Cell Available active high signal asserted layer indicate that there cell available send. PHY: Receive UTOPIA/Any-PHY Layer Cell Available active high signal asserted AAL1gator-8 indicate there cell-space available. AAL1gator8 drives this signal only when TPHY_ADD matches CFG_ADDR UI_SNK_CFG register previous cycle. Any-PHY: This Transmit Packet Available (TPA) signal which functions same TPHY_CLAV except activated cycles after matching address instead one.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name TPHY_ADD[4]/TSX TPHY_ADD[3]/TCSB TPHY_ADD[2] TPHY_ADD[1] TPHY_ADD[0]
Type Input
Function ATM: These signals used Amode. PHY: Transmit UTOPIA Layer Address (Bits which selects UTOPIA transmitter. These inputs used output enable TPHY_CLAV validate activation TPHY_ENB. There internal pull-up resistors. These pins compared with CFG_ADDR[5:0] UI_SNK_CFG_ADDR register. ANY-PHY: Transmit Start Transfer(TSX) active high input which indicates start AnyPHY packet which identifies location prepended address. ANY-PHY_EN UI_SNK_CFG register needs this function. Transmit Chip Select (TCSB) active input which used select AAL1gator-8 when polling Any-PHY mode. This input used decode Any-PHY address bits greater than TPHY_ADD[2]. This input goes cycle after Any-PHY address valid. ANY-PHY_EN CS_MODE_EN UI_SNK_CFG register needs this function. Otherwise this functions TPHY_ADD[3]. TPHY_ADD[2:0] bottom three bits Any-PHY address used select device when polling. These pins compared with CFG_ADDR[2:0] UI_SNK_CFG_ADDR register. Note these pins must tied ground when used.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Microprocessor Interface Signals (43) Name D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Type AB11 AA10 AB10 AA12 Function bi-directional data signals (D[15:0]) provide data allow AAL1gator-8 device interface external microprocessor. Both read write transactions supported. microprocessor interface used configure monitor AAL1gator-8 device.
Input
address signals (A[19:0]) provide address allow AAL1gator-8 device interface external micro-processor.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name
Type Input
AB13
Function address latch enable signal (ALE) latches A[19:0] signals during address phase transaction. When high, address latches transparent. When low, address latches hold address provided A[19:0]. internal pull-up resistor. write strobe signal (WRB) qualifies write accesses AAL1gator-8 device. When low, D[15:0] contents clocked into addressed register rising edge WRB. Note that CSB, low, chip outputs tristated. Therefore should never active same time during functional operation.
Input
AA13
Input
read strobe signal (RDB) qualifies read accesses AAL1gator-8 device. When low, AAL1gator-8 device drives D[15:0] with contents addressed register falling edge RDB. Note that CSB, low, chip outputs tristated. Therefore should never active same time during functional operation.
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name
Type Input
Function chip select signal (CSB) qualifies read/write accesses AAL1gator-8 device. signal must during read write accesses. When high, microprocessor interface signals ignored AAL1gator-8 device. required (register accesses controlled only RDB) then should connected inverted version RSTB signal. Note that CSB, low, chip outputs tristated.
ACKB
OpenDrain Output
AA14
ACKB active signal which indicates when processor read data valid when processor write operation completed. When inactive this signal tristated. ACKB open drain output should pulled high externally with fast resistor. Maximum output current (IMAX)
INTB
OpenDrain Output
interrupt signal (INTB) active signal indicating that enabled MSTR_INTR_REG register set. When INTB low, interrupt active enabled. When INTB tristate, there interrupt pending disabled. INTB open drain output should pulled high externally with fast resistor. Maximum output current (IMAX)
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Interface Signals(41) Name RAM1_D[15] RAM1_D[14] RAM1_D[13] RAM1_D[12] RAM1_D[11] RAM1_D[10] RAM1_D[9] RAM1_D[8] RAM1_D[7] RAM1_D[6] RAM1_D[5] RAM1_D[4] RAM1_D[3] RAM1_D[2] RAM1_D[1] RAM1_D[0] RAM1_A[16] RAM1_A[15] RAM1_A[14] RAM1_A[13] RAM1_A[12] RAM1_A[11] RAM1_A[10] RAM1_A[9] RAM1_A[8] RAM1_A[7] RAM1_A[6] RAM1_A[5] RAM1_A[4] RAM1_A[3] RAM1_A[2] RAM1_A[1] RAM1_A[0] RAM1_OEB Type Function bi-directional data signals (RAM1_D[15:0]) provide data allow AAL1gator-8 device access external 256Kx16(18) RAM. RAM1 used A1SP blocks
Output
address signals (RAM1_A[16:0]) provide address allow AAL1gator-8 device address external 256Kx16(18)
Output
RAM1 Output Enable active signal that enables SRAM drive data. Maximum output current (IMAX)
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Name RAM1_WEB[1]
Type Output
Function RAM1 Write Enable active signal high-byte write. Maximum output current (IMAX) RAM1 Write Enable Zero active signal low-byte write. Maximum output current (IMAX) RAM1 Chip Select active chip-select signal external memory. Maximum output current (IMAX) This signal different meanings depending upon type SRAM that AAL1gator-8 programmed interface SSRAM: RAM1 Address Status Control active output external memory used cause external address loaded into RAM. ZBT: RAM1 indicates direction transfer. Maximum output current (IMAX)
RAM1_WEB[0]
Output
RAM1_CSB
Output
RAM1_ADSCB /RAM1_R/WB
Output
RAM1_PAR[1] RAM1_PAR[0]
RAM1 Parity bi-directional signal that indicates parity upper lower byte RAM1_D[15:0].
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
NOTE: different modes line interface redefined. Direct mode there separate bi-directional lines which support lines Mbps each with aggregate bandwidth Mbps.Or line into highspeed mode support data rates Mbps. H-MVIP mode there Mbps lines which compatible with H-MVIP specification. Table defines which signal tables need used each possible mode. Select mode line interface that will used refer tables listed. Table page shows pins shared between different modes.
Table Line Mode Direct H-MVIP
Line Interface Signal Table Selection Line Interface Table Direct H-MVIP
Line Interface Signals(Direct)(68) Name LINE_MODE Type Input Function Determines mode operation line interface: 0)Direct Mode 1)H-MVIP Mode
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PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
TL_SYNC[7] TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3] TL_SYNC[2] TL_SYNC[1] TL_SYNC[0]
Transmit Line Synchronization transmit frame synchronization indicators used SDF-MF SDFFR modes. Depending value MF_SYNC_MODE LI_CFG_REG register line, these signals either indicate frame boundary multi-frame boundary. Depending value GEN_SYNC LIN_STR_MODE register that line, sync signal either received from corresponding framer device generated internally Default mode this signal frame sync input. Transmit Line Serial Data carry received data corresponding framer devices.
TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0]
Output
Output
Transmit Line Signal signaling outputs corresponding framer devices SDFMF mode. This default function this pin.
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TL_CLK[7]/TSM[7] TL_CLK[6]/TSM[6] TL_CLK[5]/TSM[5] TL_CLK[4]/TSM[4] TL_CLK[3]/TSM[3] TL_CLK[2]/TSM[2] TL_CLK[1]/TSM[1] TL_CLK[0]/TSM[0]
Transmit Line Channel Clock clock lines sixteen lines. They clock data from AAL1gator-8 corresponding framer devices. Depending value TL_CLK_OE CLK_SOURCE_TX field LIN_STR_MODE memory register, these pins either outputs inputs. TL_CLK_OE high, these pins outputs clock sourced internally power This later changed CLK_SOURCE_TX field. Transmit Signaling Mirror copy TL_SIG output. Direct Speed mode, CLK_SOURCE_TX="111" then signaling output this pin. This option used with devices that share same clock signaling. this mode CTL_CLK used line clock. Maximum output current (IMAX)
CTL_CLK
Input
Common Transmit Line Clock transmit line clock which shared across lines. Whether this clock used given line dependent value CLK_SOURCE_TX LINE_STR_MODE memory register that line.
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RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0]
Input
Receive Line Synchronization receive frame synchronization indicators used SDF-MF SDFFR modes. Depending value MF_SYNC_MODE LI_CFG_REG register line, these signals either indicate frame boundary multi-frame boundary. ground unused.
RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0]
Input
AB22 AA22
Receive Line Serial Data carries receive data from corresponding framer devices.
Input
Receive Line Signaling carries data from corresponding framer devices.
Input
Receive Line Clock clock received from corresponding framer device used clock RL_DATA, RL_SIG, RL_SYNC.
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CRL_CLK
Input
Common Receive Line Clock receive line clock which shared across lines. Whether this clock used given line dependent value CLK_SOURCE_RX LIN_STR_MODE memory register that line.
Line Interface Signals(H-MVIP)(13) Name LINE_MODE Type Input Function Determines mode operation line interface: 0)Direct Mode 1)H-MVIP Mode (TL_SYNC[0]) Input Frame Sync active frame synchronization input signal used indicate start frame. Transmit Line Serial Data carry received data corresponding framer devices. H_MVIP backplane. Transmit Line Signal signaling outputs corresponding framer devices SDF-MF mode. H-MVIP does support signaling directly, these signals used transport signaling needed. Clock clock used transfer data across H-MVIP bus. clock runs twice fast data rate. This common clock used both receive transmit direction.
TL_DATA[1] TL_DATA[0]
Output
TL_SIG[1] TL_SIG[0]
Output
C16B (CTL_CLK)
Input
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Name RL_DATA[1] RL_DATA[0]
Type Input
AB22
Function Receive Line Serial Data carries receive data from corresponding framer devices H-MVIP backplane. Receive Line Signaling carries data from corresponding framer devices. H-MVIP does support signaling directly, these signals used transport signaling needed.
RL_SIG[1] RL_SIG[0]
Input
(CRL_CLK)
Input
Clock clock used generating sampling F0B. This common clock used both receive transmit direction.
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following table shows modes same time shows pins redefined different modes. Table Direct Speed TL_SYNC[7] TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3] TL_SYNC[2] TL_SYNC[1] TL_SYNC[0] TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0] TL_SIG[1] TL_SIG[0] TL_DATA[1] TL_DATA[0] Line Interface Summary H-MVIP
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Direct Speed TL_CLK[7] TL_CLK[6] TL_CLK[5] TL_CLK[4] TL_CLK[3] TL_CLK[2] TL_CLK[1] TL_CLK[0] CTL_CLK RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0] RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RL_SIG[7] RL_SIG[6]
H-MVIP
C16B
RL_DATA[1] RL_DATA[0]
AB22
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Direct Speed RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0] CRL_CLK
H-MVIP
RL_SIG[1] RL_SIG[0]
AA22
Clock Generation Control Interface(18) Name CGC_DOUT[3] CGC_DOUT[2] CGC_DOUT[1] CGC_DOUT[0] Type Output AB16 AB14 AA15 Function External Clock Generation Control Data Bits form SRTS correction code when SRTS_STBH asserted; otherwise CGC_DOUT[3:0] bits form channel status frame difference when ADAP_STBH asserted. Line Bits form line CGC_DOUT corresponds when SRTS_STBH asserted; otherwise CGC_LINE[3:0] bits form adaptive state machine index when ADAP_STBH asserted.
CGC_LINE[3] CGC_LINE[2] CGC_LINE[1] CGC_LINE[0]
Output
AB19 AA18 AB18
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Name SRTS_STBH
Type Output
AA20
Function SRTS Strobe indicates that SRTS value present CGC_DOUT[3:0]. CGC_LINE[4:0] indicates line SRTS code controls. Adaptive Strobe indicates that channel status byte difference being played CGC_DOUT[3:0]. nibbles identified values CGC_LINE[4:0]. Network Clock network-derived clock used SRTS. this signal tied low, SRTS disabled. Internally this clock divided independently each A1SP block. Transmit Line Clock Output Enable controls whether TL_CLK lines inputs outputs between time hardware reset when CLK_SOURCE_TX bits read. high, TL_CLK pins outputs. low, TL_CLK pins inputs. There internal pull-down resistor, TL_CLK pins inputs connected. value this input overwritten CLK_SOURCE_TX bits LIN_STR_MODE memory register. External Clock Generation Control Serial Data input used allow external clock control circuitry pass frequency information into internal clock synthesizer. External Clock Generation Control Valid signal active high input indicating that data CGC_SER_D valid. This signal must transition from high first valid data CGC_SER_D must stay high through whole clock control word.
ADAP_STBH
Output
AA19
NCLK/ SRTS_DISB
Input
AA16
TL_CLK_OE
Input
CGC_SER_D
Input
AA17
CGC_VALID
Input
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JTAG/TEST Signals(5) Name TCLK Type Input Function test clock signal provides timing test operations carried using JTAG test access port. test mode select signal controls test operations that carried using JTAG test access port. test data input signal JTAG serial input data test data output signal JTAG serial output data. active signal which, SCAN mode, used shift data. This signal should tied high normal operation. When tied enable SCAN mode. This signal should tied high normal operation. active test reset signal asynchronous reset JTAG circuitry. This signal must tied ground during normal operation. used, leave unconnected
Input Internal Pull-up
Input Internal Pull-up
SCAN_ENB
Output Input Internal Pull-up
SCAN_MODEB
Input Internal Pull-up
TRSTB
Schmitt Trigger Input Internal Pull-up
Reserved
AB20
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General Signals(3+power/gnd) Name RSTB Type Schmitt Trigger Input Internal Pull-up SYS_CLK Input AA21 Function Reset active asynchronous hardware reset. When RSTB forced low, AAL1gator's internal registers reset their default states. System Clock. maximum frequency MHz. This clock used clock majority logic inside chip also determines speed memory interface external clock control interface. This clock also used clock synthesis. When clock synthesis enabled this clock must 38.88 MHz. Power (VDD3.3). VDD3.3 pins should connected well decoupled +3.3V power supply. These pins power output ports device. pins "quiet" power pads.
VDD3.3 (PPH, PQH)
Power
AB17
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Name VDD2.5 (PCH)
Type Power
AA11
Function Power (VDD2.5). VDD2.5 pins should connected well decoupled +2.5V power supply. These pins power core device.
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Name (PPL, PQL, PCL)
Type Ground
AB12 AB15 AB21
Function Ground (VSS). pins should connected GND. pins ground pins ports. pins "quiet" ground pins ports. pins core ground pins. grounds should connected together.
Notes Description: AAL1gator-8 inputs bi-directionals present minimum capacitive loading tolerant.
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AAL1gator-8 UTOPIA/Any-PHY outputs bi-directional pins have drive capability. drive capability. other outputs bi-directional pins have drive capability. AAL1gator-8 outputs tristated under control IEEE P1149.1 test access port, even those which tristate under normal operation. outputs bi-directionals tolerant when tristated. clock inputs Schmitt triggered. Inputs RPHY_ADDR, TPHY_ADR, RL_CLK, RL_SYNC, RATM_DATA, RATM_CLK, TATM_CLK, micro processor data, RAM_PAR, WRB, CSB, RDB, NCLK, CRL_CLK, CTL_CLK, SCAN_ENB, RSTB, ALE, TMS, TRSTB have internal pull-up resistors. Power VDD3.3 pins should applied before power VDD2.5 pins applied. Similarly, power VDD2.5 pins should removed before power VDD3.3 pins removed.
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FUNCTIONAL DESCRIPTION AAL1gator-8 divided into following major blocks, which explained this section: UTOPIA Interface Block (UTOPIAI) AAL1 Processing Block (A1SP) Processor Interface Block (PROCI) Interface Block (RAMI) Line Interface Block (LINEI) JTAG
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UTOPIA Interface Block (UI) manages responds control signals UTOPIA passes cells from UTOPIA A1SP block. Both 8-bit 16-bit UTOPIA interfaces with optional single parity supported. Each direction configured independently address configuration register. following UTOPIA modes supported. UTOPIA Level Master (8-bit only) UTOPIA Level UTOPIA Level Any-PHY
sink direction, uses 4-cell deep FIFO buffering cells they wait sent Dual A1SP blocks. addition, A1SP contains 8-cell deep FIFO with separate interface allow A1SP process data pace. source direction, uses 4cell deep FIFO holding cells before they sent onto UTOPIA bus. Also, A1SP contains 8-cell deep FIFO, again with separate interface. data flow showing FIFOs shown Figure Figure Data Flow Buffering A1SP Blocks
UTOPIAI A1SP
TUFIFO cells) TXA1SP cell FIFO)
Cell FIFO
Cell FIFO
RXA1SP cell FIFO) RUFIFO cells)
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UTOPIA Level mode, AAL1gator-8 responds UTOPIA single port device. UTOPIA UTOPIA loopback, there 3-cell FIFO Block. Line-side Line-side loopback done A1SP Block. UI_EN UI_COMN_CFG register enables both source side sink side UTOPIA interface. This resets disabled state that chip resets with UTOPIA outputs tristated. Once modes have been configured interface enabled, then outputs will drive their correct values. block consists functions: Data Source Interface (SRC_INTF), Data Sink Interface(SNK_INTF), 4-cell FIFO (FF4CELL), 3-cell FIFO (FF3CELL), UMUX, UI_REG. Figure block diagram AAL1_UI block. Figure Block Diagram
UTOPIA Interface (UI) Block UMUX SRC_INTF FF4CELL
Signals to/from each A1SP block
TXUTOPIA SIGNALS
UTOPIA Interface FIFO Output Logic
FF3CELL
Prioritization FIFO Input Logic
SNK_INTF FF4CELL UTOPIA Interface FIFO Input Logic
Signals to/from each A1SP block
RXUTOPIA SIGNALS
DEMUX FIFO Output Logic UI_REG
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9.1.1 UTOPIA Source Interface (SRC_INTF) SRC_INTF block (shown Figure conveys cells received from UMUX block UTOPIA interface. Depending value UTOP_MODE field UI_SRC_CFG register, UTOPIA interface will either UTOPIA master (controls write enable signal) UTOPIA device (controls cell available signal). device SRC_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device SRC_INTF only function UTOPIA Level device. 16_BIT_MODE UI_SRC_CFG register then bits UTOPIA data used. 16_BIT_MODE must UTOPIA master mode. master mode, SRC_INTF block sources TATM_D, TATM_PAR, TATM_SOC, TATM_ENB while receiving TATM_CLAV. Start-OfCell (SOC) indication generated coincident with first word (only 8-bit mode supported) each cell that transmitted TATM_D. TATM_D, TATM_PAR TATM_SOC driven times. TATM_ENB signal indicates which clock cycles contain valid data UTOPIA bus. device will assert TATM_ENB signal until full cell send target device activated TATM_CLAV. TATM_CLAV signal indicates whether target device able accept cells not. Only cell level handshaking supported. target device unable accept additional cells must deactivate TATM_CLAV later than byte current cell. additional cells will sent until TATM_CLAV activated. mode, SRC_INTF block sources RPHY_D[15:0], RPHY_PAR, RPHY_SOC, RPHY_CLAV, while receiving RPHY_ENB. indication generated coincident with first word (8-bit 16-bit) each cell that transmitted RPHY_D[15:0]. mode, RPHY_D[15:0], RPHY_PAR, RATM_SOC signals driven only when valid data being sent; otherwise they tristated. UTOPIA Level mode, RPHY_CLAV activated whenever complete cell available sent. remains active until last byte been read last available complete cell. cell sent cycle after RPHY_ENB goes low. RPHY_ENB goes high during cell transfer, data sent each cycle following where RPHY_ENB high.
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RPHY_ADD[4:0] input used only UTOPIA Level mode. cycle following where RPHY_ADD[4:0] matches CFG_ADDR(4:0) UI_SRC_ADD_CFG register, Block will drive RPHY_CLAV. Otherwise RPHY_CLAV tri-stated. addition, during previous cycle RPHY_ENB high current cycle, then device selected SRC_INTF begins transmitting cell next cycle. Parity driven TATM_PAR (RPHY_PAR) whenever TATM_D(RPHY_D[15:0]) driven. EVEN_PAR will determine whether even parity parity generated. Since parity required AForum, EVEN_PAR intended used error checking only. AAL1gator-8 tolerate temporary de-assertions TATM_CLAV (RPHY_ENB), assumed that enough UTOPIA bandwidth present accept cells that AAL1gator-8 produce timely manner. Once 4-Cell FIFO fills cells will begin filling 8-cell FIFO each A1SP block. Anytime UTOPIA FIFO fills T_UTOP_FULL interrupt will active MSTR_INTR_REG enabled. This FIFO fill during normal operation usually indication error. However A1SP FIFO should normally fill. they fill indicates there some congestion, which impacting UTOPIA interface TALP_FIFO_FULL will active A1SP_INTR_REG. When TALP FIFO fills, then TALP longer able build cells data will start building transmit buffer frame_advance_fifo will fill. this continues that FR_ADV_FIFO_FULL goes active then data been lost transmit queues need reset. T_UTOP_FULL indicator used determine when UTOPIA Interface clears. also desirable disable UI_EN that stored cells flushed. SRC_INTF circuit controls when cell transmitted from internal cell FIFO. Since UTOPIA transmit cells higher speeds than TALP since expected applications shared UTOPIA environment, cell transmission from SRC_INTF commences only when there full cell worth data available transmit. cell then transmitted interface UTOPIA TATM_CLK rate, accordance with TATM_FULLB (RPHY_ENB) input. maximum supported clock rate MHz. 9.1.1.1 Any-PHY Mode ANY-PHY_EN UI_SRC_CFG register then SRC_INTF operates single port Any-PHY slave device. Any-PHY mode
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RPHY_ADDR(4) becomes depending value CS_MODE_EN, RPHY_ADDR(3) become RCSB signal instead. Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address sending cell. SRC_INTF uses CFG_ADDR(15:0) UI_SRC_ADD_CFG register address prepend. 16_BIT_MODE then only lower bits used. During cycle that prepend address active pulses high. Because large number possible ports, source direction, device addresses used polling device selection, instead port addresses (each device control many ports). When device selected send cell, device prepends port address front cell. Since, this direction AAL1gator-8 only single port, device address port address same. However AAL1gator-8 only limited number address pins. accommodate systems, which using different port density Any-PHY devices, RCSB signal available handle additional external decoding that required. Any-PHY mode, devices respond with RPHY_CLAV cycles after their address instead cycle required UTOPIA mode. However timing RCSB matches UTOPIA timing that full cycle external decoding available. Table shows CFG_ADDR field used different modes.
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Table
CFG_ADDR PHY_ADDR Usage direction Polling Selection CFG_ADDR [4:0]=device [2:0]=device PHY_ADDR Pins [4:0]=device [2:0]=device CFG_ADDR prepended [3:0]=device [3:0]=device [3:0]=device CFG_ADDR prepended [15:0]=device CFG_ADDR [4:0]=device [15:0]=device
MODE UTOPIA-2 Single-Addr Any-PHY with Any-PHY without NOTES:
PHY_ADDR Pins [4:0]=device [2:0]=device
Any-PHY mode, direction AAL1gator-8 will prepend cell with CFG_ADDR[15:0]. 8-bit mode cell will prepended with CFG_ADDR[7:0] Any-PHY mode, CS_MODE_EN='1' then CFG_ADDR[4:3] "00". Any-PHY mode, CS_MODE_EN='0' then CFG_ADDR[3]="0". 9.1.2 UTOPIA Sink Interface (SNK_INTF) SNK_INTF block receives cells from UTOPIA interface sends them UMUX interface. Depending value UTOP_MODE field UI_SNK_CFG register, UTOPIA interface acts either UTOPIA master (controls read enable signal) UTOPIA device (controls cell available signal). device SNK_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device SNK_INTF only function UTOPIA Level device. 16_BIT_MODE UI_SNK_CFG register then bits UTOPIA data used. 16_BIT_MODE must UTOPIA master mode.
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master mode, SNK_INTF block receives RATM_D, RATM_PAR, RATM_SOC, RATM_CLAV while driving RATM_ENB. Once enabled this mode, and, RATM_CLAV input signal asserted, SNK_INTF block waits RATM_SOC signal from layer. Once RATM_SOC signal arrives, cell accepted soon possible. Start-Of-Cell (SOC) indication received coincident with first word (only 8-bit mode supported) each cell that received RATM_D. 4-cell FIFO allows interface accept data maximum rate. FIFO fills, RATM_ENB signal will asserted again until device ready accept entire cell. RATM_ENB signal depends only cell space independent state RATM_CLAV signal. RATM_CLAV signal indicates whether target device cell send not. Only cell level handshaking supported. mode, SNK_INTF block receives TPHY_D[15:0], TPHY_SOC, TPHY_ENB while driving TPHY_CLAV. cell available (TPHY_CLAV) signal indicates when device ready receive complete cell. UTOPIA Level mode, TPHY_CLAV always driven. UTOPIA Level mode, SNK_INTF responds single address device. When polling A1SP full indication will given when A1SP FIFO reaches half full state (room more cells). This will always allow room cells that still queued sink UTOPIA FIFO. TPHY_CLAV driven cycle following ones which TPHY_ADDR(4:0) matches CFG_ADDR(4:0) UI_SNK_ADD_CFG register. Otherwise TPHY_CLAV tri-stated. addition address match, during previous cycle TPHY_ENB high current cycle, then device selected SRC_INTF begins accepting cell that being received. SNK_INTF block waits SOC. When signal arrives, counter started, bytes received. occurs within cell, counter reinitializes. This means that corrupted cell will dropped second good cell will received. SNK_INTF block stores cell receive FIFO. receive FIFO becomes full, stops receiving cells. bytes written FIFO with RATM_CLK. RATM_CLK input AAL1gator-8. maximum supported clock rate MHz. Parity always checked parity error will cause interrupt UTOP_PAR_ERR_EN MSTR_INTR_EN_REG.
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FORCE_EVEN_PARITY will determine whether even parity parity checked. Since parity required AForum, FORCE_EVEN_PARITY intended used error checking only. error detected UTOP_PAR_ERR MSTR_INTR_REG set, corresponding enable MSTR_INTR_EN_REG then INTB will active. cell received with parity will still processed normal. 9.1.2.1 Any-PHY Mode ANY-PHY_EN UI_SNK_CFG register then SNK_INTF operates multi port Any-PHY slave device. Any-PHY mode TPHY_ADDR[4] becomes depending value CS_MODE_EN, TPHY_ADDR(3) become TCSB signal instead. Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address receive cell. SNK_INTF uses CFG_ADDR(15:2) UI_SNK_ADD_CFG register match with address prepend. 16_BIT_MODE then CFG_ADDR(7:2) used. During cycle that prepend address active bus, input pulses high. sink direction, port addresses used polling device selection, instead device addresses. Since, this direction AAL1gator-8 port, AAL1gator-8 will upper bits UI_SNK_ADD_CFG register address compares lower bits determine when A1SP being polled selected. However AAL1gator-8 only limited number address pins. accommodate systems, which using different port density Any-PHY devices, TCSB signal available handle additional external decoding that required. Any-PHY mode, devices respond with TPHY_CLAV cycles after their address instead cycle required UTOPIA mode. However timing TCSB matches UTOPIA timing that full cycle external decoding available. Table shows CFG_ADDR field used different modes.
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Table
CFG_ADDR PHY_ADDR Usage direction Polling Selection CFG_ADDR [4:0]=device [2]=device PHY_ADDR Pins [4:0]=device [2]=device addr prepended [3:2]=device [3:2]=device [3:2]=device addr prepended [15:2]=device CFG_ADDR [4:0]=device [15:2]=device
MODE UTOPIA-2 Single-Addr Any-PHY with Any-PHY without NOTES:
PHY_ADDR Pins [4:0]=device [2]=device
Any-PHY mode, CS_MODE_EN='1' then CFG_ADDR[4:3] "00". Else CS_MODE_EN='0' then CFG_ADDR[3]="0". Any-PHY mode upper bits prepended address compared with CFG_ADDR[15:2]. 8-bit mode CFG_ADDR[7:2] used instead. 9.1.3 UTOPIA Block (UMUX) UMUX serves bridge between A1SP block SNK_INTF SRC_INTF blocks. source direction, UMUX polls A1SP block Loopback FIFO using least recently serviced algorithm determine cell availability. this algorithm, once particular source serviced, lowest priority sources then moves priority other higher priority source ahead serviced. SRC_INTF FIFO room cell, A1SP block selected, cell read from A1SP block, cell placed SRC_INTF FIFO. A1SP block 8-cell FIFO. sink direction, UMUX waits until SNK_INTF FIFO cell send. Once SNK_INTF FIFO cell send, UMUX polls A1SP availability. Once A1SP room cell, UMUX reads cell SNK_INTF FIFO places A1SP FIFO.
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UMUX also supports forms UTOPIA UTOPIA loopback; global loopback, where cells looped, based loopback, where only specific used loopback cells. global loopback cells received UTOPIA block sent back onto UTOPIA bus. Global loopback enabled setting U2U_LOOP UI_COMN_CFG register. based loopback mode, cell received with that matches loopback sent back onto UTOPIA bus. based loopback enabled setting VCI_U2U_LOOP UI_COMN_CFG register. loopback programmable writing U2U_LOOP_VCI register. 3-cell FIFO used loopback. AAL1 Processing Block (A1SP) A1SP block main AAL1 processing block. Each block processes E1/T1 lines. This block following major components. Transmit Frame Transfer Controller (TFTC) block Cell Service Decision (CSD) block Transmit Adaptation Layer Processor (TALP) block TALP FIFO (TFIFO) block Local Loopback Block (LOC_LPBK) block Receive Frame Transfer Controller (RFTC) block Receive Adaptation Layer Processor (RALP) block RALP FIFO (RFIFO) block
Figure shows block diagram A1SP sequence events used segment reassemble data.
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Figure
A1SP Block Diagram
Cell Service Decision (CSD)
Input from Block
Transmit Frame Transfer Controller (TFTC)
Transmit Adaptation Layer Processor (TALP)
TALP FIFO Block (TFIFO)
Output Block
External Memory
Local Loopback Block (LOC_LPBK)
Output Block
Receive Frame Transfer Controller (RFTC)
Internal
Receive Adaptation Layer Processor (RALP)
RALP FIFO Block (RFIFO)
Input from Block
Microprocessor Control
TFTC stores line data into memory bits time. When TFTC finishes writing complete frame into memory, notifies frame completion writing line frame number into FIFO. Idle channel detection processed here enabled. checks frame-based table queues having sufficient data generate cell. each queue with enough data generate cell, schedules next cell generation occurrence table. commands TALP generate cell from available data each ready queues identified step TALP generates cell from data signaling buffers writes cell into TALP FIFO. TFIFO block buffers cells which will transmitted UTOPIA Interface block. local loopback enabled cell looped RALP
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RFIFO block buffers cells received from UTOPIA Interface block. RALP performs pointer searches, checks overrun underrun conditions, detects mismatches, checks cells, extracts line data from cells, places data into receive buffer. RFTC plays receiver buffer data onto lines.
Four types data supported A1SP UDF-ML (Unstructured Data Format- Multi-Line). Unstructured stream line speeds Mbps. (supports lines A1SP) under Mbps). UDF-HS (Unstructured Data Format- High Speed). Unstructured stream line speeds under Mbps. (Only line supported A1SP). SDF-FR (Structured Data Format- Frame). Channelized data without signaling. (Frame based structure). SDF-MF (Structured Data Format- Multi-Frame). Channelized data with signaling. (Multi-Frame based structure).
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9.2.1 AAL1 Transmit Side (TxA1SP) 9.2.1.1 Transmit Frame Transfer Controller (TFTC) TFTC accepts deframed data from Line Interface Block. structured data, TFTC uses synchronization supplied Line Interface Block perform serial-to-parallel conversion incoming data then places this data into multiframe buffer order which arrives. TFTC monitors frame sync signals will realign when edge seen these signals that does correspond where expects occur. necessary provide edge beginning every frame multiframe. AAL1gator-8 reads signaling during last frame every multiframe. mode, AAL1gator-8 reads signaling 24th frame multiframe. mode, AAL1gator-8 reads signaling 16th frame multiframe. special case mode exists that permits signaling with framing. Normally multiframe consists frames timeslots, where signaling changes multiframe boundaries. When E1_WITH_T1_SIG LIN_STR_MODE line mode, TFTC will multiframe consisting frames timeslots. this mode, AAL1gator-8 reads signaling 24th frame multiframe. AAL1gator-8 reads signaling nibble each channel when reads last nibble each channel's data. Figure example frame. Figure example frame.
Figure
Capture Signaling Bits
Line Signals During Last Frame Multiframe
(timeslots)
RL_SER
ABCD RL_SIG XXXX ABCD XXXX Channel XXXX ABCD Channel
Channel
ABCD ABCD ABCD XXXX Channel XXXX Channel XXXX Channel
XXXX indicates signaling ignored
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Figure
Capture Signaling Bits
Line Signals During Last Frame Multiframe
(timeslots)
RL_SER
ABCD RL_SIG XXXX ABCD XXXX Channel XXXX ABCD Channel
Channel
ABCD ABCD ABCD XXXX Channel XXXX Channel XXXX Channel
XXXX indicates signaling ignored
NOTE: AAL1gator-8 treats timeslots identically. Although data streams contain timeslots channel data timeslots control (timeslots 16), data signaling timeslots stored memory sent received cells.
Unstructured data received without regard byte alignment data within frame placed frame buffer order which arrives. Figure shows basic components TFTC. Figure
Line Line
Transmit Frame Transfer Controller
Line
ATTN0
Interface
Line Line
Receive Line Interface
DATA0
Line Encoder Line Number
Line Receive Line Interface
ATTN7
Channel Pair
Line-to-Memory Interface
DATA7
Interface
Data
receive line interface primarily serial-to-parallel converter. Serial data, which derived from RL_DATA signal from Block, supplied shift register. shift register clock RL_CLK input from external framer. When data been properly shifted transferred 2-byte holding register internally derived channel clock. This clock derived from line clock framing information.
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channel clock also informs line-to-memory interface that data bytes available from line. When bytes available, line attention signal sent line encoder block. However, because channel clock asynchronous input line-to-memory interface, passed through synchronizer before supplied line encoder. Since there eight potential lines each them provides channel clock, they synchronized before being submitted line encoder. TFTC accommodates Super Frame (SF) mode treating like Extended Super Frame (ESF) format. TFTC ignores every other frame pulse captures signaling data only last frame multiframes. formatting data signaling buffers highly dependent operating mode. Refer section 7.6.6 "RESERVED (Transmit Signaling Buffer)" page more information transmit signaling buffer. Figure shows format transmit data buffer ESF-formatted data lines that SDF-MF mode. Figure SDF-MF Format T_DATA_BUFFER
DS0s
Frame Buffer umber
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Figure shows format transmit data buffer SF-formatted data lines that SDF-MF mode. Figure SF-SDF-MF Format T_DATA_BUFFER
Frame Buffer Number
DS0s
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Figure shows format transmit data buffer data lines that SDF-FR mode. Figure SDF-FR Format T_DATA_BUFFER
Frame Buffer Number DS0s
Frame
Frame Frame
Frame
Frame Frame
Frame
Frame Frame
Frame
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Figure shows format transmit data buffer data lines that SDF-MF mode. Figure SDF-MF Format T_DATA_BUFFER
Frame Buffer Number DS0s
Figure shows format transmit data buffer data using signaling, lines that SDF-MF mode Figure SDF-MF with Signaling Format T_DATA_BUFFER
DS0s Frame Buffer Number
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Figure shows format transmit data buffer data lines that SDF-FR mode. Figure SDF-FR Format T_DATA_BUFFER
Frame Buffer Number DS0s Frame Frame Frame Frame
Figure shows format transmit data buffer lines that UDF-ML mode. Figure Unstructured Format T_DATA_BUFFER
Data Bits
rame Buffer Number
256-Bit Internal Frame 256-Bit Internal Frame 256-Bit Internal Frame
Figure through Figure show contents transmit signaling buffer different signaling modes. cases upper nibble each byte "0000".
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Figure
SDF-MF Format T_SIGNALING_BUFFER
Byte Address
Channel ABCD
Channel Used
Channel ABCD
Channel ABCD
Channel ABCD
Channel Used
Multiframe
Figure
SDF-MF Format T_SIGNALING BUFFER
Byte Address
Channel ABAB
Channel Used
Channel ABAB
Channel ABAB
Channel ABAB
Channel Used
Multiframe/2
Figure
SDF-MF Format T_SIGNALING_BUFFER
Byte Address
Multiframe
Channel ABCD Channel ABCD
Channel ABCD
Channel ABCD
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Figure SDF-MF with Signaling Format T_SIGNALING_BUFFER
Byte Address Multiframe
Channel ABCD Channel ABCD
Channel ABCD
Channel ABCD
9.2.1.1.1 Transmit Conditioning T_COND_DATA structure allows conditional data defined per-DS0 basis T_COND_SIG structure allows conditioned signaling defined per-DS0 basis. TX_COND T_QUEUE_TBL allows cell building logic (described section 9.2.1.3 Transmit Adaptation Layer Processor (TALP) page directed build cells from conditioned data signaling. control whether conditioned data, conditioned signaling, both used, TX_COND_MODE TX_CONFIG register appropriate value. TX_COND TX_COND_MODE bits per-queue basis. having independent control over whether signaling data conditioned, possible substitute signaling which carried bits across Anetwork while still passing data received line. This useful applications that receiving signaling with data. HS_UDF mode HS_TX_COND needs HS_LIN_REG register. When this cells with ones pattern will generated. CMD_REG_ATTN needs written after HS_TX_COND this function take affect. Under certain alarm conditions such Loss Signal (LOS), Alarm Indication Signal (AIS) needs transmitted downstream. This means that cells need generated which carry pattern. AAL1gator-8 does alarm processing dependent external framer this functionality. framer would notify processor alarm conditions then processor would switch particular
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queue from normal mode conditioned mode setting TX_COND T_QUEUE_TBL. Most signals ones pattern, cells with this pattern generated setting T_COND_DATA "FF"x T_COND_SIG "F"x. mode this done setting HS_TX_COND `1'. However signal framed "1010" pattern. This signal generated setting HS_GEN_DS3_AIS HS_LIN_REG register. CMD_REG_ATTN needs written after HS_GEN_DS3_AIS HS_TX_COND this function take affect. 9.2.1.1.2 Transmit Signaling Freezing Signaling freezing required function when transporting CAS. This function holds signaling unchanged when incoming line fails. PMC-Sierra framers provide this function. framer used that does support signaling freezing, this function must provided externally. 9.2.1.1.3 SRTS Transmit Side transmit side supports SRTS only unstructured data formats per-line basis. SRTS support requires input reference clock, NCLK. input reference frequency defined 155.52/2n MHz, where chosen such that reference clock frequency greater than frequency being transmitted, less than twice frequency being transmitted RL_CLK NCLK RL_CLK). implementation, input reference clock frequency must 2.43 MHz. transmit side accept reference clock speed 77.76 MHz, which required applications. Figure page shows process implemented each line enabled SRTS, regardless reference frequency. resulting 4-bit SRTS code then inserted into each numbered cells that line. There four cells each cell sequence, each carries different SRTS bit. line does supply SRTS, then bits 3008 divider number data bits eight cells 47). divider aligned first cell generation after reset resynchronization cell generation process.
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Figure
Transmit Side SRTS Function
SRTS Code
Serve Freq
Divide 3008
4-Bit Latch
Reset Cell eneration Resync
Bits fere Freq (For 2.43 MHz.
4-Bit Counter
9.2.1.1.4 Idle Detection Idle detection will performed queue basis using following three methods: channel associated signaling (CAS), band signaling (processor controlled), pattern matching. status each channel stored Active/Idle table. mode each channel controlled value IDLE_CFG_n Idle Detection Configuration Table. lower channels upper channels line must pattern matching mode with processor controlled mode. This avoid contention updating active channel table. 9.2.1.1.4.1 Idle Detection idle detection looks ABCD bits both receive transmit direction compares them values programmed channel basis processor. consecutive values match both receive transmit direction channel considered idle. format register (AUTO_CONFIG_n) CAS/Pattern Matching Configuration Table which processor programs with idle ABCD patterns pictured below Figure register also provides mask fields receive transmit directions which allow ABCD bits ignored when looking match. Figure
MASK
Idle Detection Configuration Register Structure
MASK ABCD ABCD
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During idle detection, word written Transmit Idle Interrupt FIFO every time status changes from active->idle idle->active. TIDLE_FIFO_EMPB long this FIFO contains unread entries, which will result maskable interrupt. structure word contained FIFO shown Figure upper eight bits indicate channel that encountered status change indicates status channel (Active Idle processor accesses FIFO reading A1SPn_TIDLE_FIFO register which will contain element FIFO. Figure
Idle Detection Interrupt Word
Line Channel Unused
Status
9.2.1.1.4.2 Band Signaling Idle Detection band signaling mode, responsibility processor drop channels. This mode used conjunction with common channel signaling (CCS) processor wants make determination channel activity based bits. During band signaling idle detection, word written Transmit Idle Interrupt FIFO every time value nibble changes then remains stable additional multiframe. TIDLE_FIFO_EMPB long this FIFO contains unread entries, which will result maskable interrupt. structure word contained FIFO shown Figure first eight bits indicate channel, which encountered change value CAS. next four bits indicate value final four bits indicate value. Based these values processor make determination channel should marked active idle. values de-bounced internally time, additional debounce must done external chip. Figure
Band Signaling Idle Detection Interrupt Word
Line Channel
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processor will also able mask portions therefore receive interrupts only when particular bits change. Figure shows structure AUTO_CONFIG_n field CAS/Pattern Matching Configuration Table. lower byte reserved used detecting changes values. Therefore, avoid contention, upper byte should only written when idle detection disabled. Figure
MASK
Band Signaling Configuration Register Structure
MASK Reserved Reserved
Once processor determines that status channel should change, processor should then write Channel Active Table. processor does this accessing table bits time. most situations processor will want change subset channels accessed. Therefore read-modify-write will have performed. Figure shows structure Active/Idle table. index represents value that needs added base address table order access status channels located that index. Note that since processor writes bits time recommended that processor intervention automatic mode mixed within group channels avoid contention problems.
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Figure
Index
Channel Active/Idle Table Structure
Channel Status
Line
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9.2.1.1.4.3 Pattern Match Idle Detection Pattern match idle detection compares received byte with programmed pattern mask. there mismatch received data with programmed pattern during programmable length time, then channel considered active. Otherwise, received channel bytes match unmasked pattern bits over programmable length time, channel considered idle state cell transmission will suppressed. Interval length refers amount time that patterns must match considered match event. This value programmed Pattern Matching Line Configuration register associated line. Interval length programmed units units Since this field, maximum length time (+/12 seconds (+/- seconds Figure PAT_MTCH_CFG Register Structure
Rsvd
Interval Length
Internal Length Duration time data must match before declaring idle condition
Figure shows structure AUTO_CONFIG_n field CAS/Pattern Matching Configuration Table. lower byte contains pattern received byte should compared against. upper byte mask field that used control which bits monitored. Since chip will updating this field during normal operation, best processor writes lower byte register only during reset order avoid contention. allow chip support various error rates length interval selectable line basis.
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Figure
Pattern Match Idle Detection Register Structure
PATTERN_MASK IDLE_PATTERN
During pattern match idle detection, word written TIDLE_FIFO every time status changes from active->idle idle->active. interrupt generated long this FIFO contains unread entries. structure word contained FIFO shown Figure upper eight bits indicate channel that encountered status change indicates status channel (Active Idle processor accesses FIFO reading Status Interrupt register which will contain element FIFO. Figure
Line
Pattern Match Idle Detection Interrupt Word
Channel Unused Status
9.2.1.2 Cell Service Decision (CSD) Circuit circuit determines which cells sent when. determines this implementing Transmit Calendar tables Active/Idle tables. When TALP builds cell, circuit performs complex calculation using credits determine frame which next cell from that queue should sent. circuit schedules cell only when cell built TALP SUPPRESS_TRANSMISSION TX_CONFIG word set, then cell scheduled, however, cell transmitted. non-DBCES mode, queue placed idle detection mode setting IDLE_DET_ENABLE TRANSMIT_CONFIG word within queue table. When queue idle detection mode channels given queue inactive, cells scheduled, cells actually sent. This mode also requires that idle detection methods enabled channels given queue. This done programming A1SP Idle Detection Configuration Table.
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following steps well Figure page describe circuit schedules cells TALP build. Once TFTC writes complete frame into external memory, writes line number frame number this frame into FR_ADVANCE_FIFO. circuit reads line-frame number pair from FR_ADVANCE_FIFO uses index into Transmit Calendar. Transmit Calendar composed eight-bit tables, line. Each table consists entries, frame buffer. Each entry consists bits, queue. each indexed entry Transmit Calendar, will schedule frame which next cell built corresponding queue, notify TALP that enough data available build cell that queue. circuit processes queues from Transmit Calendar entry starting with lowest queue number proceeding highest. processing steps follows: circuit obtains QUE_CREDITS, subtracts average number credits cell from average number credits, AVG_SUB_VALU, number credits that will spent sending current cell. structured lines, average number credits cell 7/8. unstructured lines, average number credits cell Next, circuit computes frame location next service subtracting remaining credits from divides result number channels, NUM_CHAN, dedicated that queue. number channels calculated based upon Active/Idle table channels allocated queue. chip non-DBCES mode, NUM_CHAN equal number channels allocated queue. chip DBCES mode, NUM_CHAN equal number allocated channels that active, which determined from Active/Idle table. result frame differential. then adds this frame differential present frame location determine frame number next frame which TALP build cell. circuit then sets corresponding entry Transmit Calendar writes QUEUE_CREDITS. circuit then adds credits back credit total frame increment number. number credits equal
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frame differential computed earlier, multiplied number channels that queue. Once queue identified requiring service, identity written NEXT_SERV location. circuit obtains next queue that frame repeats steps through circuit continues this process until there more active queues that frame. After servicing queues that frame, circuit advances next active line located line queue. there active lines, circuit returns idle state wait next line request service. Figure shows assigns credits determine which frames cells should sent. Figure
Frame Boundaries
Frame Advance FIFO Operation
TFTC RL_DATA(0 RL_FSYNC(0) TFTC sees frame advance records this FR_ADVANCE_FIFO FR_ADVANCE_FIFO reads frame advances determines cells sent NEXT_ SERV
RL_DATA(1 RL_FSYNC(1)
following example calculations circuit performs. This example assumes structured line with four channels allocated queue non-DBCES mode. TFTC writes Line Frame FR_ADVANCE_FIFO.
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circuit determines queue which cell ready finding Transmit Calendar. this example, queue number 100. circuit reads number credits queue number 100. number credits always greater than because ready service. this example, QUE_CREDITS 59.375. circuit subtracts AVG_SUB_VALU, average number credits spent cell. (Remember: structured lines, average number credits cell 46-7/8. unstructured lines, average number credits cell 47.) Credits 59.375 46.875 Credits 12.5 frame differential next service computed from number credits needed exceed NUM_CHAN, number channels allocated frame. 12.5 34.5 34.5 8.625 Round 8.625 frame differential Therefore, next cell will sent nine frames ahead current cell. Next frame present frame number circuit computes number credits those nine frames adds result total. credits QUE_CREDITS 12.5 48.5 queue line SDF-MF mode, makes signaling adjustment QUE_CREDITS before writing this value memory. queue SDF-MF mode, signaling adjustment made QUE_CREDITS calculated Step written memory.)
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calculation determines number signaling bytes structure, then generates average number signaling bytes inserted into cells frame, finally multiplies this average number frame differential adjust QUE_CREDITS. converts frame differential from units frames units one-eighth multiframes. performing this calculation, also uses FRAME_REMAINDER value from QUE_CREDITS location T_QUEUE_TBL. This example assumes that FRAME_REMAINDER from previous calculation this queue. Frame differential eighths multiframe) (frame differential FRAME_REMAINDER) Frame differential eighths multiframe) (frame differential FRAME_REMAINDER) Frame differential three-eighths multiframe, remainder writes remainder this division into FRAME_REMAINDER location next calculation this queue. calculates signaling credit adjustment multiplying frame differential expressed eighths multiframe number signaling bytes structure. Number signaling bytes structure channels bytes channel bytes multiframe Signaling adjustment three eighths 0.75 bytes Then adds signaling credit adjustment total writes result memory, preparation next service this queue. QUEUE_CREDITS 48.5 0.75 49.25 bytes Unstructured lines different procedure. case unstructured lines, cell will sent every time bytes received. This assumes that partial cells used mode.
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DBCES algorithm similar. main change that time channel activated deactivated, scheduling next bitmask cell dynamically update account change number active channels. channels active cell with Inactive structure will sent every mode mode. DBCES only supported full cells. 9.2.1.2.1 Transmit (The performance numbers this section examples only subject change) following items affect transmit CDV: Cell scheduling Contention with other cells scheduled same time Actual cell build time UTOPIA contention cell generation
scheduler resolution other words, works frame-based clock determine whether cell should sent during current frame. Therefore, ideal rate cell transmission multiple there will CDV. scheduler will never more than CDV. example, single queue with signaling using full cells, will need build cell every frames. Therefore, cell will scheduled every frames, scheduler will CDV. Also mode cells sent every time bytes received added. However, signaling were added single queue, extra byte that occurs every bytes (assuming mode) requires compensation. this case, cell will sent every frames. Therefore, there will scheduler. Note that lines there LOW_CDV which LIN_STR_MODE memory register which will cause cells scheduled every bytes instead frame based. This eliminates caused scheduler. This mode only used UDF-ML mode when BYTES_PER_CELL High Speed mode cells always
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scheduled every bytes which assumes that partial cells never used mode. Only cell built time. Thus multiple queues scheduled send cells during same frame, additional delay will incurred. queues activated deactivated that number queues scheduled ahead specific queue same frame changes, resulting change delay translates CDV. scheduling multiple cells same time known clumping. takes approximately build cell normally take under worst case traffic processor activity (Note this assumes 38.88 SYS_CLK). Therefore each cell that waited could delay. When multiple queues scheduled send cells same time, cells will built sequential order, starting with going 256. Therefore, system that will adding dropping queues, higher number queues will experience more than lower number queues, depending many queues active time, scheduled within same frame. AAL1gator-8 minimizes effects clumping offsetting schedule point each line frame. Also when queues added, offset field supplied which will force multiple cells same line scheduled different times. Queue FIFO section Processor Interface section more details. configurations that will require sending cell every frames where integer divisor (for (for T1), cells will always scheduled same frame unless offset field differently each cell. actual build time cell depends microprocessor activity contention with other internal state machines AAL1gator-8 memory bus. Therefore there will some minor that added cell basis, based current microprocessor/memory traffic. This usually less than very noticeable. there backpressure UTOPIA bus, cells will able sent which also causes CDV. Since cells have higher priority than data cells transmission cells should distributed. cell assuming 38.88 SYS_CLK under worst case processor load.
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9.2.1.3 Transmit Adaptation Layer Processor (TALP) 9.2.1.3.1 Cell Generation When cell transmission requested, sent first available opportunity. Transmit cells have higher priority than cells scheduled circuit. Because this, care should taken ensure that cells overwhelm transmitter such extent that data cells starved adequate opportunities. rate cells must limited AAL1gator-8 maintain maximum data rate. send cell, microprocessor writes cells into dedicated cell buffers located external memory. When cell assembled buffer, microprocessor must appropriate Command register TALP sends cell soon possible, then clears appropriate attention indicate requested cell been sent. requests both cells active time command register read AAL1gator-8, cell will always sent because assigned higher priority. Therefore, control order cell transmission, microprocessor should only attention time wait until cleared before setting other attention bit. cells optionally have 48-byte payload CRC-10 protected. This accomplished circuit that monitors cell sent TUTOPIA computes fly. then substitutes resultant CRC, preceded last bytes cell. generation enabled setting Word T_OAM_CELL. 9.2.1.3.2 Data Cell Generation TALP receives request send CSD-scheduled data cell there cell requests pending, will soon free. will look predefined Aheader from T_QUEUE_TBL (refer section 7.6.8 "T_QUEUE_TBL" page 122). will then obtain sequence number that queue from memory, structure pointer necessary. After these bytes written TUTOPIA interface, TALP will then data signaling frame buffers, locate data bytes correct channels, write them correct order
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UTOPIA interface. This cell building process described more detail following section. 9.2.1.3.2.1 Header Construction entire header fixed queue. Headers maintained memory, queue. These headers include Header Error Check (HEC) character fifth byte. queue should deactivated during header replacement prevent cells from being constructed with incorrect header values. queue paused setting SUPPRESS_TRANSMISSION TX_CONFIG register. Emissions still scheduled, transmissions suppressed. cells that suppressed, T_SUPPRESSED_CELL_CNT incremented. 9.2.1.3.2.2 Payload Construction Payload construction most complex task TALP circuit performs. signaling requirements define much process, which follows: first byte payload provided lookup into T_QUEUE_TBL. This first byte consists bit, 3-bit sequence number, 4-bit sequence number protection field. depending SRTS pointer requirements. sequence number incremented every time cell sent same VPI/VCI. queue been configured AAL0 mode, this step done additional data byte loaded instead. line structured modes, structure pointer needed even-numbered cells. TALP inserts structure pointers according following rules: Only pointer inserted each 8-cell sequence. pointer inserted first possible even-numbered cell every 8cell sequence. pointer value inserted when structure starts byte directly after pointer itself. pointer value inserted when structure coincides with 93-octet block AAL-user information.
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dummy pointer value inserted cell number startof-structure end-of-structure occurs within 8-cell sequence.
This algorithm supplies constant number structure pointers and, therefore, data bytes, regardless structure size. pointer inserted seventh byte location cell. force TALP build structure consisting single with signaling nibble pointer, T_CHAN_UNSTRUCT QUEUE_CONFIG word T_QUEUE_TBL. TALP fills rest cell payload with data and/or signaling information. T_CHAN_ALLOC table transmit queue table determines which channels dedicated which queue. set, channel represented that assigned that queue. TALP successively writes data from marked channels into UTOPIA interface. LOOPBACK_ENABLE TX_CONFIG register then cell written into separate FIFO looped back RALP queue-based parameter, BYTES_PER_CELL, decides when enough payload bytes have been obtained. this number fewer than then remaining bytes cell loaded with P_FILL_CHAR. This implies that because presence structure pointer, number fill bytes will constant structured data queues. DBCES mode requires some additional adjustments. bitmask must placed beginning structure that pointed structure pointer. This bitmask four bytes length. Also active status channels must factored Only T_CHAN_ALLOC table corresponding channel active does TALP write data from channel into UTOPIA interface. none channels active cell will filled with null bitmask. structure used signaling determined mode line value E1_WITH_T1_SIG. Normally signaling structure will follow mode line. However, line mode E1_WITH_T1_SIG set, then signaling structure used. This means that single DS0, signaling inserted after data bytes instead after data bytes. data sent from data queue, this process continues byte-by-byte while updating pointers counters until following occurs: cell complete. last data byte last frame multiframe been set.
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When signaling information sent, data obtained from signaling locations multiframe, with help channel allocation table (T_CHAN_ALLOC). This process proceeds byte-by-byte until following occurs: cell complete. signaling nibbles channels assigned queue have been sent.
Figure shows example payload generation process. Figure Payload Generation
Channel builds (segments) cell from T_DATA_BUFFER. this case from DS0s
writes bytes pairs into T_DATA_BUFFER RL_SER
T_DATA_BUFF
rames
AAL0 mode cell build process takes bytes line data does AAL1 overhead bytes. DBCES mode, anytime pointer generated, subsequent start structure will contain bitmask field with number channels currently active. Changes bitmask only occur this time. 9.2.1.3.3 Peak Cell Rates (PCRs) purposes discussion, following information assumed:
PRELIMINARY STANDARD PRODUCT DATASHEET PMC-200-0097 ISSUE
PM73123 AAL1GATOR-8
LINK CES/DBCES AAL1
Full cells used, numbers line, SYS_CLK 38.88 MHz.
9.2.1.3.3.1 Peak Cell Rates (PCRs) Structured Cell Formats cells second where (assuming completely filled cells). Each AAL1 cell either bytes, depending upon whether cell contains structure pointer.
9.2.1.3.3.2 Peak Cell Rates (PCRs) Unstructured Cell Formats 4,107 cells second (assuming bytes each AAL1 cell). 5,447 cells second (assuming bytes each AAL1 cell). 118,980 cells second (assuming bytes each AAL1 cell). 91,405 cells second (assuming bytes each AAL1 cell). lines same rate, aggregate 53,191 cells second multiple-line unstructured data format (assuming bytes each AAL1 cell). lines same rate, aggregate 46,542. 1,000 cells second cells. This rate cells calculated basis four cells second Transmitting receiving cells this rate consumes microprocessor accesses.
9.2.1.3.3.3 Peak

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