DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE PM7

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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE PM7

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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
PM7346 S/UNI
QJET
S/UNI-QJET
SATURN QUAD USER NETWORK INTERFACE J2/E3/T3
DATASHEET
PROPRIETARY CONFIDENTIAL ISSUE 1999
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REVISION HISTORY Issue Issue Date 1999 Details Change S/UNI-QJET requires software initialization sequence order guarantee proper device operation long term reliability. Please refer Section 12.1 this document details program this sequence. Updated RFCLK TFCLK descriptions reflect that these pins tolerant. Both pins 3.3V only input pins. Documentation clarifications.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
CONTENTS FEATURES APPLICATIONS REFERENCES APPLICATION EXAMPLES BLOCK DIAGRAM. DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION FRAMER. FRAMER FRAMER 9.3.1 FRAME FIND ALGORITHMS. 9.10 9.11 PMON PERFORMANCE MONITOR ACCUMULATOR. RBOC BIT-ORIENTED CODE DETECTOR RDLC FACILITY DATA LINK RECEIVER. SPLR PLCP LAYER RECEIVER ATMF ACELL DELINEATOR RXCP-50 RECEIVE CELL PROCESSOR RXFF RECEIVE FIFO. CPPM CELL PLCP PERFORMANCE MONITOR
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23
PRGD PSEUDO-RANDOM SEQUENCE GENERATOR/DETECTOR TRANSMITTER. TRANSMITTER TRANSMITTER. XBOC ORIENTED CODE GENERATOR TDPR FACILITY DATA LINK TRANSMITTER SPLT SMDS PLCP LAYER TRANSMITTER TXCP-50 TRANSMIT CELL PROCESSOR TXFF TRANSMIT FIFO. TRAIL TRACE BUFFER JTAG TEST ACCESS PORT MICROPROCESSOR INTERFACE
NORMAL MODE REGISTER DESCRIPTION. TEST FEATURES DESCRIPTION 11.1 11.2 TEST MODE DETAILS JTAG TEST PORT.
OPERATION 12.1 12.2 12.3 SOFTWARE INITIALIZATION SEQUENCE REGISTER SETTINGS BASIC CONFIGURATIONS PLCP FRAME FORMATS 12.3.1 PLCP PATH OVERHEAD OCTET PROCESSING 12.4 12.5 FRAME FORMAT G.751 FRAME FORMAT.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
12.6 12.7 12.8 12.9
G.832 FRAME FORMAT. FRAME FORMAT S/UNI-QJET CELL DATA STRUCTURE. RESETTING RXFF TXFF FIFOS
12.10 SERVICING INTERRUPTS. 12.11 USING PERFORMANCE MONITORING FEATURES 12.12 USING INTERNAL TRANSMITTER 12.13 USING INTERNAL DATA LINK RECEIVER 12.14 PRGD PATTERN GENERATION. 12.14.1 GENERATING DETECTING REPETITIVE PATTERNS 12.14.2 COMMON TEST PATTERNS
12.15 JTAG SUPPORT FUNCTIONAL TIMING ABSOLUTE MAXIMUM RATINGS. D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS A.C. TIMING CHARACTERISTICS ORDERING THERMAL INFORMATION MECHANICAL INFORMATION.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
LIST REGISTERS REGISTER 000H, 100H, 200H, 300H: S/UNI-QJET CONFIGURATION REGISTER 001H, 101H, 201H, 301H: S/UNI-QJET CONFIGURATION REGISTER 002H, 102H, 202H, 302H: S/UNI-QJET TRANSMIT CONFIGURATION REGISTER 003H, 103H, 203H, 303H: S/UNI-QJET RECEIVE CONFIGURATION REGISTER 004H, 104H, 204H, 304H: S/UNI-QJET DATA LINK FERF/RAI CONTROL REGISTER 005H, 105H, 205H, 305H: S/UNI-QJET INTERRUPT STATUS. REGISTER 006H: S/UNI-QJET IDENTIFICATION, MASTER RESET, GLOBAL MONITOR UPDATE. REGISTER 007H, 107H, 207H, 307H: S/UNI-QJET CLOCK ACTIVITY MONITOR INTERRUPT IDENTIFICATION REGISTER 008H, 108H, 208H, 308H: SPLR CONFIGURATION REGISTER 009H, 109H, 209H, 309H: SPLR INTERRUPT ENABLE REGISTER 00AH, 10AH, 20AH, 30AH: SPLR INTERRUPT STATUS. REGISTER 00BH, 10BH, 20BH, 30BH: SPLR STATUS. REGISTER 00CH, 10CH, 20CH, 30CH: SPLT CONFIGURATION. REGISTER 00DH, 10DH, 20DH, 30DH: SPLT CONTROL. REGISTER 00EH, 10EH, 20EH, 30EH: SPLT DIAGNOSTICS OCTET REGISTER 00FH, 10FH, 20FH, 30FH: SPLT OCTET REGISTER 010H, 110H, 210H, 310H: CHANGE PMON PERFORMANCE METERS.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REGISTER 011H, 111H, 211H, 311H: PMON INTERRUPT ENABLE/STATUS REGISTER 014H, 114H, 214H, 314H: PMON LINE CODE VIOLATION EVENT COUNT REGISTER 015H, 115H, 215H, 315H: PMON LINE CODE VIOLATION EVENT COUNT REGISTER 016H, 116H, 216H, 316H: PMON FRAMING ERROR EVENT COUNT REGISTER 017H, 117H, 217H, 317H: PMON FRAMING ERROR EVENT COUNT REGISTER 018H, 118H, 218H, 318H: PMON EXCESSIVE ZERO COUNT REGISTER 019H, 119H, 219H, 319H: PMON EXCESSIVE ZERO COUNT REGISTER 01AH, 11AH, 21AH, 31AH: PMON PARITY ERROR EVENT COUNT LSB. REGISTER 01BH, 11BH, 21BH, 31BH: PMON PARITY ERROR EVENT COUNT MSB. REGISTER 01CH, 11CH, 21CH, 31CH: PMON PATH PARITY ERROR EVENT COUNT REGISTER 01DH, 11DH, 21DH, 31DH: PMON PATH PARITY ERROR EVENT COUNT REGISTER 01EH, 11EH, 21EH, 31EH: PMON FEBE/J2-EXZS EVENT COUNT LSB. REGISTER 01FH, 11FH, 21FH, 31FH: PMON FEBE/J2-EXZS EVENT COUNT MSB. REGISTER 021H, 121H, 221H, 321H: CPPM CHANGE CPPM PERFORMANCE METERS. REGISTER 022H, 122H, 222H, 322H: CPPM ERROR COUNT
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REGISTER 023H, 123H, 223H, 323H: CPPM ERROR COUNT REGISTER 024H, 124H, 224H, 324H: CPPM FRAMING ERROR EVENT COUNT REGISTER 025H, 125H, 225H, 325H: CPPM FRAMING ERROR EVENT COUNT REGISTER 026H, 126H, 226H, 326H: CPPM FEBE COUNT LSB. REGISTER 027H, 127H, 227H, 327H: CPPM FEBE COUNT MSB. REGISTER 030H, 130H, 230H, 330H: FRMR CONFIGURATION REGISTER 031H, 131H, 231H, 331H: FRMR INTERRUPT ENABLE (ACE=0). REGISTER 031H, 131H, 231H, 331H: FRMR ADDITIONAL CONFIGURATION REGISTER (ACE=1) REGISTER 032H, 132H, 232H, 332H: FRMR INTERRUPT STATUS REGISTER 033H, 133H, 233H, 333H: FRMR STATUS. REGISTER 034H, 134H, 234H, 334H: TRAN CONFIGURATION REGISTER 035H, 135H, 235H, 335H: TRAN DIAGNOSTIC REGISTER 038H, 138H, 238H, 338H: FRMR FRAMING OPTIONS. REGISTER 039H, 139H, 239H, 339H: FRMR MAINTENANCE OPTIONS REGISTER 03AH, 13AH, 23AH, 33AH: FRMR FRAMING INTERRUPT ENABLE REGISTER 03BH, 13BH, 23BH, 33BH: FRMR FRAMING INTERRUPT INDICATION STATUS. REGISTER 03CH, 13CH, 23CH, 33CH: FRMR MAINTENANCE EVENT INTERRUPT ENABLE REGISTER 03DH, 13DH, 23DH, 33DH: FRMR MAINTENANCE EVENT INTERRUPT INDICATION
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REGISTER 03EH, 13EH, 23EH, 33EH: FRMR MAINTENANCE EVENT STATUS REGISTER 040H, 140H, 240H, 340H: TRAN FRAMING OPTIONS REGISTER 041H, 141H, 241H, 341H: TRAN STATUS DIAGNOSTIC OPTIONS REGISTER 042H, 142H, 242H, 342H: TRAN BIP-8 ERROR MASK REGISTER 043H, 143H, 243H, 343H: TRAN MAINTENANCE ADAPTATION OPTIONS. REGISTER 044H, 144H, 244H, 344H: J2-FRMR CONFIGURATION REGISTER 045H, 145H, 245H, 345H: J2-FRMR STATUS. REGISTER 046H, 146H, 246H, 346H: J2-FRMR ALARM INTERRUPT ENABLE REGISTER 047H, 147H, 247H, 347H: J2-FRMR ALARM INTERRUPT STATUS REGISTER 048H, 148H, 248H, 348H: J2-FRMR ERROR/XBIT INTERRUPT ENABLE REGISTER 049H, 149H, 249H, 349H: J2-FRMR ERROR/XBIT INTERRUPT STATUS REGISTER 04CH, 14CH, 24CH, 34CH: J2-TRAN CONFIGURATION REGISTER 04DH, 14DH, 24DH, 34DH: J2-TRAN DIAGNOSTIC. REGISTER 04EH, 14EH, 24EH, 34EH: J2-TRAN TS97 SIGNALING. REGISTER 04FH, 14FH, 24FH, 34FH: J2-TRAN TS98 SIGNALING. REGISTER 050H, 150H, 250H,350H: RDLC CONFIGURATION. REGISTER 051H, 151H, 251H, 351H: RDLC INTERRUPT CONTROL. REGISTER 052H, 152H, 252H, 352H: RDLC STATUS REGISTER 053H, 153H, 253H, 353H: RDLC DATA.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REGISTER 054H, 154H, 254H, 354H: RDLC PRIMARY ADDRESS MATCH. REGISTER 055H, 155H, 255H, 355H: RDLC SECONDARY ADDRESS MATCH REGISTER 058H, 158H, 258H, 358H: TDPR CONFIGURATION REGISTER 059H, 159H, 259H, 359H: TDPR UPPER TRANSMIT THRESHOLD REGISTER 05AH, 15AH, 25AH, 35AH: TDPR LOWER INTERRUPT THRESHOLD REGISTER 05BH, 15BH, 25BH, 35BH: TDPR INTERRUPT ENABLE REGISTER 05CH, 15CH, 25CH, 35CH: TDPR INTERRUPT STATUS/UDR CLEAR. REGISTER 05DH, 15DH, 25DH, 35DH: TDPR TRANSMIT DATA. REGISTER 060H, 160H, 260H, 360H: RXCP-50 CONFIGURATION REGISTER 061H, 161H, 261H, 361H: RXCP-50 CONFIGURATION REGISTER 062H, 162H, 262H, 362H: RXCP-50 FIFO/UTOPIA CONTROL CONFIG. REGISTER 063H, 163H, 263H, 363H: RXCP-50 INTERRUPT ENABLES COUNTER STATUS. REGISTER 064H, 164H, 264H, 364H: RXCP-50 STATUS/INTERRUPT STATUS REGISTER 065H, 165H, 265H, 365H: RXCP-50 COUNT THRESHOLD (MSB) REGISTER 066H, 166H, 266H, 366H: RXCP-50 COUNT THRESHOLD (LSB) REGISTER 067H, 167H, 267H, 367H: RXCP-50 IDLE CELL HEADER PATTERN.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REGISTER 068H, 168H, 268H, 368H: RXCP-50 IDLE CELL HEADER MASK REGISTER 069H, 169H, 269H, 369H: RXCP-50 CORRECTED ERROR COUNT. REGISTER 06AH, 16AH, 26AH, 36AH: RXCP-50 UNCORRECTED ERROR COUNT REGISTER 06BH, 16BH, 26BH, 36BH: RXCP-50 RECEIVE CELL COUNTER (LSB) REGISTER 06CH, 16CH, 26CH, 36CH: RXCP-50 RECEIVE CELL COUNTER REGISTER 06DH, 16DH, 26DH, 36DH: RXCP-50 RECEIVE CELL COUNTER (MSB) REGISTER 06EH, 16EH, 26EH, 36EH: RXCP-50 IDLE CELL COUNTER (LSB) REGISTER 06FH, 16FH, 26FH, 36FH: RXCP-50 IDLE CELL COUNTER REGISTER 070H, 170H, 270H, 370H: RXCP-50 IDLE CELL COUNTER (MSB) REGISTER 080H, 180H, 280H, 380H: TXCP-50 CONFIGURATION REGISTER 081H, 181H, 281H, 381H: TXCP-50 CONFIGURATION REGISTER 082H, 182H, 282H, 382H: TXCP-50 CELL COUNT STATUS. REGISTER 083H, 183H, 283H, 383H: TXCP-50 INTERRUPT ENABLE/STATUS REGISTER 084H, 184H, 284H, 384H: TXCP-50 IDLE CELL HEADER CONTROL REGISTER 085H, 185H, 285H, 385H: TXCP-50 IDLE CELL PAYLOAD CONTROL REGISTER 086H, 186H, 286H, 386H: TXCP-50 TRANSMIT CELL COUNT (LSB) REGISTER 087H, 187H, 287H, 387H: TXCP-50 TRANSMIT CELL COUNT.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REGISTER 088H, 188H, 288H, 388H: TXCP-50 TRANSMIT CELL COUNT (MSB) REGISTER 090H, 190H, 290H, 390H: CONTROL REGISTER 091H, 191H, 291H, 391H: TRAIL TRACE IDENTIFIER STATUS REGISTER 092H, 192H, 292H, 392H: INDIRECT ADDRESS REGISTER 093H, 193H, 293H, 393H: INDIRECT DATA REGISTER 094H, 194H, 294H, 394H: EXPECTED PAYLOAD TYPE LABEL267 REGISTER 095H, 195H, 295H, 395H: PAYLOAD TYPE LABEL CONTROL/STATUS REGISTER 098H, 198H, 298H, 398H: RBOC CONFIGURATION/INTERRUPT ENABLE REGISTER 099H, 199H, 299H, 399H: RBOC INTERRUPT STATUS REGISTER 09AH, 19AH, 29AH, 39AH: XBOC CODE. REGISTER 09BH, 19BH, 29BH, 39BH: S/UNI-QJET MISC. REGISTER 09CH, 19CH, 29CH, 39CH: S/UNI-QJET FRMR STATUS. REGISTER 0A0H, 1A0H, 2A0H, 3A0H: PRGD CONTROL. REGISTER 0A1H, 1A1H, 2A1H, 3A1H: PRGD INTERRUPT ENABLE/STATUS REGISTER 0A2H, 1A2H, 2A2H, 3A2H: PRGD LENGTH REGISTER 0A3H, 1A3H, 2A3H, 3A3H: PRGD TAP. REGISTER 0A4H, 1A4H, 2A4H, 3A4H: PRGD ERROR INSERTION REGISTER REGISTER 0A8H, 1A8H, 2A8H, 3A8H: PATTERN INSERTION REGISTER 0A9H, 1A9H, 2A9H, 3A9H: PATTERN INSERTION
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
REGISTER 0AAH, 1AAH, 2AAH, 3AAH: PATTERN INSERTION REGISTER 0ABH, 1ABH, 2ABH, 3ABH: PATTERN INSERTION REGISTER 0ACH, 1ACH, 2ACH, 3ACH: PRGD PATTERN DETECTOR REGISTER 0ADH, 1ADH, 2ADH, 3ADH: PRGD PATTERN DETECTOR REGISTER 0AEH, 1AEH, 2AEH, 3AEH: PRGD PATTERN DETECTOR REGISTER 0AFH, 1AFH, 2AFH, 3AFH: PRGD PATTERN DETECTOR REGISTER 400H: S/UNI-QJET MASTER TEST
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
LIST FIGURES FIGURE S/UNI-QJET, APHY, ASWITCH. FIGURE S/UNI-QJET, QUAD FRAMER DEVICE, FRAME RELAY EQUIPMENT FIGURE S/UNI-QJET, CELL PROCESSOR, DSLAM EQUIPMENT FIGURE NORMAL OPERATING MODE. FIGURE DS3/E3/J2 FRAMERS BYPASSED. FIGURE DS3/E3/J2 TRANSCEIVER MODE FIGURE LOOPBACK MODES. FIGURE FRAMING ALGORITHM (CRC_REFR FIGURE FRAMING ALGORITHM (CRC_REFR FIGURE CELL DELINEATION STATE DIAGRAM. FIGURE VERIFICATION STATE DIAGRAM FIGURE PLCP FRAME FORMAT FIGURE PLCP FRAME FORMAT FIGURE G.751 PLCP FRAME FORMAT. FIGURE PLCP FRAME FORMAT FIGURE FRAME STRUCTURE FIGURE G.751 FRAME STRUCTURE. FIGURE G.832 FRAME STRUCTURE. FIGURE FRAME STRUCTURE FIGURE 16-BIT WIDE, WORD STRUCTURE. FIGURE 16-BIT WIDE, WORD STRUCTURE.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
FIGURE 8-BIT WIDE, WORD STRUCTURE. FIGURE 8-BIT WIDE, WORD STRUCTURE. FIGURE TYPICAL DATA FRAME. FIGURE EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE FIGURE PRGD PATTERN GENERATOR FIGURE BOUNDARY SCAN ARCHITECTURE. FIGURE CONTROLLER FINITE STATE MACHINE FIGURE INPUT OBSERVATION CELL (IN_CELL) FIGURE OUTPUT CELL (OUT_CELL). FIGURE BI-DIRECTIONAL CELL (IO_CELL). FIGURE LAYOUT OUTPUT ENABLE BI-DIRECTIONAL CELLS FIGURE RECEIVE STREAM. FIGURE RECEIVE STREAM FIGURE RECEIVE BIPOLAR STREAM FIGURE RECEIVE UNIPOLAR STREAM FIGURE RECEIVE BIPOLAR STREAM. FIGURE RECEIVE UNIPOLAR STREAM FIGURE RECEIVE BIPOLAR STREAM FIGURE RECEIVE UNIPOLAR STREAM. FIGURE GENERIC RECEIVE STREAM FIGURE RECEIVE OVERHEAD. FIGURE RECEIVE G.832 OVERHEAD.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
FIGURE RECEIVE G.751 OVERHEAD. FIGURE RECEIVE OVERHEAD FIGURE RECEIVE PLCP OVERHEAD FIGURE TRANSMIT STREAM FIGURE TRANSMIT STREAM FIGURE TRANSMIT BIPOLAR STREAM. FIGURE TRANSMIT UNIPOLAR STREAM FIGURE TRANSMIT BIPOLAR STREAM FIGURE TRANSMIT UNIPOLAR STREAM. FIGURE TRANSMIT BIPOLAR STREAM FIGURE TRANSMIT UNIPOLAR STREAM FIGURE GENERIC TRANSMIT STREAM. FIGURE TRANSMIT OVERHEAD FIGURE TRANSMIT G.832 OVERHEAD FIGURE TRANSMIT G.751 OVERHEAD FIGURE TRANSMIT OVERHEAD. FIGURE TRANSMIT PLCP OVERHEAD FIGURE FRAMER MODE TRANSMIT INPUT STREAM FIGURE FRAMER MODE TRANSMIT INPUT STREAM WITH TGAPCLK FIGURE FRAMER MODE RECEIVE OUTPUT STREAM FIGURE FRAMER MODE RECEIVE OUTPUT STREAM WITH RGAPCLK FIGURE FRAMER MODE G.751 TRANSMIT INPUT STREAM.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
FIGURE FRAMER MODE G.751 TRANSMIT INPUT STREAM WITH TGAPCLK FIGURE FRAMER MODE G.751 RECEIVE OUTPUT STREAM FIGURE FRAMER MODE G.751 RECEIVE OUTPUT STREAM WITH RGAPCLK FIGURE FRAMER MODE G.832 TRANSMIT INPUT STREAM. FIGURE FRAMER MODE G.832 TRANSMIT INPUT STREAM WITH TGAPCLK FIGURE FRAMER MODE G.832 RECEIVE OUTPUT STREAM FIGURE FRAMER MODE G.832 RECEIVE OUTPUT STREAM WITH RGAPCLK FIGURE FRAMER MODE TRANSMIT INPUT STREAM FIGURE FRAMER MODE TRANSMIT INPUT STREAM WITH TGAPCLK FIGURE FRAMER MODE RECEIVE OUTPUT STREAM FIGURE FRAMER MODE RECEIVE OUTPUT STREAM WITH RGAPCLK FIGURE MULTI-PHY POLLING ADDRESSING TRANSMIT CELL INTERFACE FIGURE MULTI-PHY POLLING ADDRESSING RECEIVE CELL INTERFACE FIGURE MICROPROCESSOR INTERFACE READ TIMING. FIGURE MICROPROCESSOR INTERFACE WRITE TIMING FIGURE RSTB TIMING FIGURE TRANSMIT ACELL INTERFACE TIMING. FIGURE RECEIVE ACELL INTERFACE TIMING FIGURE TRANSMIT INTERFACE TIMING
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
FIGURE 100. RECEIVE INTERFACE TIMING FIGURE 102. JTAG PORT INTERFACE TIMING
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LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE SUPPORTED OPERATING FORMATS. REGISTER MEMORY STATSEL[2:0] OPTIONS TFRM[1:0] TRANSMIT FRAME STRUCTURE CONFIGURATIONS LOF[1:0] INTEGRATION PERIOD CONFIGURATION RFRM[1:0] RECEIVE FRAME STRUCTURE CONFIGURATIONS SPLR FORM[1:0] CONFIGURATIONS. PLCP DECLARATION/REMOVAL TIMES SPLT FORM[1:0] CONFIGURATIONS
TABLE FRMR EXZS/LCV COUNT CONFIGURATIONS TABLE FRMR CONFIGURATIONS TABLE FRMR FORMAT[1:0] CONFIGURATIONS TABLE TRAN FORMAT[1:0] CONFIGURATIONS TABLE FRMR THRESHOLD CONFIGURATIONS TABLE RDLC PBS[2:0] DATA STATUS TABLE RXCP-50 FILTERING CONFIGURATIONS. TABLE RXCP-50 CELL DELINATION ALGORITHM BASE TABLE RXCP-50 INTEGRATION PERIODS TABLE TXCP-50 FIFO DEPTH CONFIGURATIONS. TABLE PAYLOAD TYPE MATCH CONFIGURATIONS. TABLE PRGD PATTERN DETECTOR REGISTER CONFIGURATION
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
TABLE PRGD GENERATED ERROR RATE CONFIGURATIONS TABLE TEST MODE REGISTER MEMORY MAP. TABLE TEST MODE INPUT READ ADDRESS LOCATIONS. TABLE TEST MODE OUTPUT WRITE ADDRESS LOCATIONS TABLE INSTRUCTION REGISTER. TABLE BOUNDARY SCAN REGISTER TABLE REGISTER SETTINGS BASIC CONFIGURATIONS TABLE PLCP OVERHEAD PROCESSING TABLE PLCP PATH OVERHEAD IDENTIFIER CODES TABLE PLCP TRAILER LENGTH TABLE PLCP TRAILER LENGTH TABLE FRAME OVERHEAD OPERATION TABLE G.751 FRAME OVERHEAD OPERATION TABLE G.832 FRAME OVERHEAD OPERATION TABLE FRAME OVERHEAD OPERATION. TABLE PSEUDO RANDOM PATTERN GENERATION TABLE REPETITIVE PATTERN GENERATION TABLE RECEIVE OVERHEAD BITS. TABLE TRANSMIT OVERHEAD BITS TABLE ABSOLUTE MAXIMUM RATINGS. TABLE CHARACTERISTICS. TABLE MICROPROCESSOR INTERFACE READ ACCESS (FIGURE
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
TABLE MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE TABLE RSTB TIMING (FIGURE 92). TABLE TRANSMIT ACELL INTERFACE TIMING (FIGURE TABLE RECEIVE ACELL INTERFACE TIMING (FIGURE TABLE TRANSMIT INTERFACE TIMING (FIGURE TABLE RECEIVE INTERFACE TIMING (FIGURE 100). TABLE JTAG PORT INTERFACE (FIGURE 102) TABLE PACKAGING INFORMATION TABLE THERMAL INFORMATION
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
FEATURES Single chip quad AUser Network Interface operating 44.736 Mbit/s, 34.368 Mbit/s, 6.312 Mbit/s conforming ATMF-95-1207R1, ATMF-940406R5, AF-PHY-0029.000. Each line individually configured desired rate. Implements ADirect Cell Mapping into DS1, DS3, transmission systems according ITU-T Recommendation G.804. Provides UTOPIA Level compatible ATM-PHY Interface. Implements Physical Layer Convergence Protocol (PLCP) transmission systems according AForum User Network Interface Specification ANSI TA-TSY-000773, TA-TSY-000772, transmission systems according ETSI 300-269 ETSI 300270. Support provided SMDS Amappings into various rate transmission systems follows: Supported Operating Formats Framer Only external external external external bypass SMDS PLCP Mapping ADirect Mapping
Table
Rate
(44.736 Mbit/s) (34.368 Mbit/s) (6.312 Mbit/s) (2.048 Mbit/s) (1.544 Mbit/s) Arbitrary Cell Rate Mbit/s)
Format
C-bit Parity G.751 G.832 G.704 CRC-4 PCM30
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Implements Aphysical layer Broadband ISDN according ITU-T Recommendation I.432. Provides on-chip DS3, (G.751 G.832), framers. configured used solely DS3, Framer. When configured operate DS3, Framer, gapped transmit receive clocks optionally generated interface devices which only need access payload data bits. Provides support arbitrary rate external transmission system interface maximum rate Mbit/s which enables S/UNI-QJET used quad Acell delineator. Uses PMC-Sierra PM4341 T1XC, PM4344 TQUAD, PM6341 E1XC, PM6344 EQUAD framer/line interface chips applications. Provides programmable pseudo-random test pattern generation, detection, analysis features. Provides integral transmit receive HDLC controllers with 128-byte FIFO depths. Provides performance monitoring counters suitable accumulation periods second. Provides 8-bit microprocessor interface configuration, control status monitoring. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. power 3.3V CMOS technology with tolerant inputs. Available high density 256-pin SBGA package (27mm 27mm).
receiver section: Provides frame synchronization C-bit parity applications, alarm detection, accumulates line code violations, framing errors, parity errors, path parity errors FEBE events. addition, alarm channel
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
codes detected, integral HDLC receiver provided terminate path maintenance data link. Provides frame synchronization G.751 G.832 applications, alarm detection, accumulates line code violations, framing errors, parity errors, FEBE events. addition, G.832, Trail Trace detected, integral HDLC receiver provided terminate either Network Requirement General Purpose data link. Provides frame synchronization G.704 6.312 Mbit/s applications, alarm detection, accumulates line code violations, framing errors, parity errors. integral HDLC receiver provided terminate data link. Provides frame synchronization, cell delineation extraction DS3, G.751 G.832 G.704 Adirect-mapped formats. Provides PLCP frame synchronization, path overhead extraction, cell extraction PLCP PLCP PLCP G.751 PLCP formatted streams. Provides 8-bit wide 16-bit wide Utopia FIFO buffer receive path with parity support, multi-PHY (Level control signals. Provides Aframing using cell delineation. Acell delineation optionally disabled allow passing cell bytes regardless cell delineation status. Provides cell descrambling, header check sequence (HCS) error detection, idle cell filtering, header descrambling (for with packets), accumulates number received idle cells, number received cells written FIFO, number errors. Provides four cell FIFO rate decoupling between line, higher layer processing entity. FIFO latency reduced changing number operational cell FIFOs. Provides receive HDLC controller with 128-byte FIFO accumulate data link information. Provides detection yellow alarm loss frame (LOF), accumulates BIP-8 errors, framing errors FEBE events.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Provides programmable pseudo-random test-sequence detection 2321 length patterns conforming ITU-T O.151 standards) analysis features.
transmitter section: Provides frame insertion C-bit parity applications, alarm insertion, diagnostic features. addition, alarm channel codes inserted, integral HDLC transmitter provided insert path maintenance data link. Provides frame insertion G.751 G.832 applications, alarm insertion, diagnostic features. addition, G.832, Trail Trace inserted, integral HDLC transmitter provided insert either Network Requirement General Purpose data link. Provides frame insertion G.704 6.312 Mbit/s applications, alarm insertion, diagnostic features. integral HDLC transmitter provided insert path maintenance data link. Provides frame insertion path overhead insertion DS1, DS3, based PLCP formats. addition, alarm insertion diagnostic features provided. Provides 8-bit wide 16-bit wide Utopia FIFO buffer transmit path with parity support multi-PHY (Level control signals. Provides optional Acell scrambling, header scrambling (for with packets), generation/insertion, programmable idle cell insertion, diagnostics features accumulates transmitted cells read from FIFO. Provides four cell FIFO rate decoupling between line higher layer processing entity. FIFO latency reduced changing number operational cell FIFOs. Provides transmit HDLC controller with 128-byte FIFO. Provides reference input locking transmit PLCP frame rate externally applied frame reference. Provides programmable pseudo-random test sequence generation 232-1 length sequences conforming ITU-T O.151 standards).
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Diagnostic abilities include single error insertion error insertion error rates ranging from 10-1 10-7. Bypass Loopback features: Allows bypassing DS3, framers enable transmission system sublayer processing external device (for example, PM4344 Quad Framer used DS1-based services, PM6344 Quad Framer used E1-based services). Allows bypassing PLCP Afunctions enable S/UNI-QJET quad DS3, framer. Provides diagnostic loopbacks, line loopbacks, payload loopbacks.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
APPLICATIONS SMDS Switches, Multiplexers, Routers SONET/SDH E3/DS3 Tributary Interfaces J2/E3/DS3 Line Interfaces DS3/E3/J2 Digital Cross Connect Interfaces DS3/E3/J2 Internet Access Interfaces DS3/E3/J2 Frame Relay Interfaces
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PM7346 S/UNI-QJET
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REFERENCES
ANSI T1.627 1993, "Broadband ISDN ALayer Functionality Specification". ANSI T1.107a 1990, "Digital Hierarchy Supplement Formats Specifications (DS3 Format Applications)". ANSI T1.107 1995, "Digital Hierarchy Formats Specifications". ANSI T1.646 1995, "Broadband ISDN Physical Layer Specification UserNetwork Interfaces Including DS1/ATM". AForum AUser-Network Interface Specification, V3.1, October, 1995. AForum "UTOPIA, APHY Interface Specification, Level Version June, 1995. AForum, 94-0406R5, (34,368 kbps) Physical Layer Interface", Dec. 1994. AForum, 95-1207R1, "DS3 Physical Layer Interface Specification", December 1995. AForum, af-phy-0029.000, "6,312 Kbps Specification, Version 1.0", June 1995. Bell Communications Research, TA-TSY-000773 "Local Access System Generic Requirements, Objectives, Interface Support Switched Multi-megabit Data Service" Issue March 1990 Supplement December 1990. Draft Standard T/NA(91)17 "Metropolitan Area Network Physical Layer Convergence Procedure 2.048 Mbit/s", April 1994. Draft Standard T/NA(91)18 "Metropolitan Area Network Physical Layer Convergence Procedure 34.368 Mbit/s", April 1994. ITU-T Recommendation O.151 "Error Performance Measuring Equipment Operating Primary Rate Above", October, 1992. ITU-T Recommendation I.432 "B-ISDN User-Network Interface Physical Layer Specification", 1993 ITU-T Recommendation G.703 "Physical/Electrical Characteristics Hierarchical Digital Interfaces", 1991.
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ITU-T Recommendation G.704 "General Aspects Digital Transmission Systems; Terminal Equipments Synchronous Frame Structures Used 1544, 6312, 2048, 8488 kbit/s Hierarchical Levels", July, 1995. ITU-T Recommendation G.751 CCITT Blue Book Fasc. III.4, "Digital Multiplex Equipments Operating Third Order Rate 34,368 kbit/s Fourth Order Rate 139,264 kbit/s Using Positive Justification", 1988. ITU-T Draft Recommendation G.775 "Loss Signal (LOS) Alarm Indication Signal (AIS) Defect Detection Clearance Criteria", October 1993. ITU-T Recommendation G.804 "ACell Mapping into Plesiochronous Digital Hierarchy (PDH)", 1993. ITU-T Recommendation G.832 "Transport Elements Networks: Frame Multiplexing Structures", 1993. ITU-T Recommendation Q.921 "ISDN User-Network Interface Data Link Layer Specification", March, 1993. Technical Reference, "NTT Technical Reference High-Speed Digital Leased Circuit Services", 1991.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
APPLICATION EXAMPLES S/UNI-QJET configured Aphysical layer device. line side, connects more J2/E3/T3 line interface units system side, S/UNI-QJET interfaces Alayer device, such PM7322 RCMP-800, over wide UTOPIA Level interface shown Figure Figure S/UNI-QJET, APHY, ASwitch
5355
4314 QDSX
7344
5346 5355
7346 5355 7346
7322
7348 7348 5347 5355
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
S/UNI-QJET configured quad J2/E3/T3 framer router, frame relay switch multiplexer applications shown Figure unchannelized J2/E3/T3 line card, S/UNI-QJET interfaces directly more PM7366 FREEDM-8 HDLC controllers. Each FREEDM-8 process highspeed links, such process eight lower speed links such S/UNI-QJET overhead bits such that only payload data passed from FREEDM-8. line side, S/UNI-QJET connected more J2/E3/T3 line interface units. system side, S/UNI-QJET interfaces with data link device over serial interface. PPP-Over-SONET application, S/UNI-QJET interfaces PM5342 SPECTRA-155 three data streams onto three corresponding STS-1 services that collectively carried over OC-3 link. Figure S/UNI-QJET, Quad Framer Device, Frame Relay Equipment
lize
lize
PM43 PPM431144 PMM43114 QDSSX QQDSXX QDDSX
PPM736665 FREEEDM FSREEEI-PM-8 DM-8H FRRENDDM
itch
lize QDSX QDSX
lize PPM43 PPM43 8888 M43888 TTOCTTL TTOCT OCTLL D3MX D3MX
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Packet
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
S/UNI-QJET configured cell processor provide cell mapping functions xDSL modems Abased Digital Subscriber Loop Access Multiplexer (DSLAM) equipment. shown Figure each S/UNI-QJET provides four cell processors. S/UNI-QJETs required port xDSL line card. Figure S/UNI-QJET, Cell Processor, DSLAM Equipment
7346 7346 5355
5346 5355 7348 7348
7346 7346 5355
7322
5347 5347
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
BLOCK DIAGRAM Figure Normal Operating Mode
[4:1] I[4:1] I[4:1] [4:1] [4:1] LL[4:1]
[4:1] [4:1] [4:1] [4:1]
XBOC
TDPR
rail ccess uffer
1149.1 ccess
TRSTB
[4:1] [15:0] TPRTY TSOC [4:0] TENB FCLK ystem [2:0] ATM8 RENB [4:0] RSOC RPRTY [15:0] [4:1]
[4:1] TNEG/TOHM[4:1]` [4:1]
Line ncode
[4:1] TI[4:1] [4:1]
Line eceive ecode Fram
ester
ransm Fram
ransm Fram
rocessor
FIFO
eceiv Fram
RXCP_50 rocessor
RXFF FIFO
RBOC
RDLC erf. rail onitor ccess uffer
CPPM /cell erf. onitor
icroprocess
[4:1] [4:1]] [4:1] [4:1] [4:1]
[4:1] [4:1] [4:1]
[10:0]
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[7:0]
RSTB
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Figure
DS3/E3/J2 Framers Bypassed
[4:1] [4:1] [4:1] [4:1] [4:1] FP[4:1] EF8KI
XBOC
TDPR
rail Access Buffer
1149.1 ccess
[4:1] [15:0] TPRTY TSOC [4:0] TENB FCLK ystem [2:0] ATM8 RENB R[4:0] RSOC RPRTY [15:0] A[4:1]
[4:1] TOHM[4:1]` [4:1]
Line Encode
[4:1] I[4:1] M[4:1]
Line ecode
eceive Fram
eceive Fram
ester
ransm Fram
ransm Fram
rocessor
Cell FIFO
RXCP_50 rocessor
Cell FIFO
RDLC Perf. rail onitor Access uffer
CPPM /cell erf. onitor
icroprocessor
D[4:1] H[4:1] P[4:1] LK[4:1]
[4:1]
A[10:0]
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[7:0]
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Figure
DS3/E3/J2 Transceiver Mode
LK/TC ELL[4:1]
I[4:1] FPI/FPI[4:1] ICLK[4:1]
S[4:1] [4:1] CLK[4:1] FP[4:1]
XBOC
TDPR
rail Access Buffer
IEEE 1149.1 Access Port
POS/T [4:1] TNEG/TOHM[4:1]` LK[4:1]
Line Encode
Tester
ransm Fram
ransm Fram
Processor
FIFO
System
Processor FIFO
CLK[4:1] I[4:1] [4:1]
FRMR Line eceiv ecode Fram
eceiv PLCP Fram
Perf. rail onitor Access Buffer
CPPM P/cell Perf. onitor
icroprocessor
[4:1] [4:1] EF8KO FPO[4:1] LK/R LK[4:1] [4:1]
H[4:1] LK[4:1] [4:1]
A[10:0]
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[7:0]
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Figure
Loopback Modes
[4:1] LL[4:1]
[4:1] [4:1] [4:1] [4:1]
[4:1] I[4:1] I[4:1] [4:1]
Line
iagnostic
XBOC
TDPR
rail ccess uffer ayload
1149.1 ccess
TRSTB
[4:1] [15:0] TPRTY TSOC [4:0] TENB FCLK ystem [2:0] ATM8 RENB [4:0] RSOC RPRTY [15:0] [4:1]
[4:1] TNEG/TOHM[4:1]` [4:1]
Line ncode
[4:1] I[4:1] [4:1]
Line ecode
eceive Fram
ester
ransm Fram
ransm Fram
rocessor
FIFO
eceiv Fram
RXCP_50 rocessor
RXFF FIFO
RBOC
RDLC PMON erf. Trail onitor ccess uffer
CPPM /cell erf. onitor
icroprocessor
[4:1] [4:1] [4:1] [4:1] [4:1]
[4:1] [4:1] [4:1]
[10:0]
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[7:0]
RSTB
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
DESCRIPTION PM7346 S/UNI-QJET quad Aphysical layer processor with integrated DS3, framers. PLCP sublayer DS1, DS3, processing supported Acell delineation. S/UNI-QJET contains integral framers, which provide framing error accumulation accordance with ANSI T1.107, T1.107a, integral framers, which provide framing accordance with ITU-T Recommendations G.832 G.751, integral framers, which provide framing accordance with ITU-T Recommendation G.704 I.432. When configured transmission system sublayer processing, S/UNI-QJET accepts outputs both digital B3ZS-encoded bipolar unipolar signals compatible with C-bit parity applications. When configured transmission system sublayer processing, S/UNI-QJET accepts outputs both HDB3-encoded bipolar unipolar signals compatible with G.751 G.832 applications. When configured transmission system sublayer processing, S/UNI-QJET accepts outputs both B8ZS-encoded bipolar unipolar signals compliant with G.704 6.312 Mbit/s applications. When configured DS1, transmission system sublayer processing, S/UNI-QJET accepts outputs unipolar signals with appropriate clock frame pulse signals physical sublayer processing. When configured other transmission systems, S/UNI-QJET provides generic interface physical sublayer processing. receive direction, S/UNI-QJET frames signals with maximum average reframe time detects line code violations, loss signal, framing errors, parity errors, path parity errors, AIS, receive failure idle code. overhead bits extracted presented serial outputs. When C-bit parity mode, Path Maintenance Data Link Alarm Control (FEAC) channels extracted. HDLC receivers provided Path Maintenance Data Link support. addition, valid bitoriented codes FEAC channels detected available through microprocessor port. receive direction, S/UNI-QJET frames G.751 G.832 signals with maximum average reframe times 135µs G.751 frames 250µs G.832 frames. Line code violations, loss signal, framing errors,
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AIS, remote alarm indication detected. Further, when processing G.832 formatted data, parity errors, receive failure, block errors also detected; Trail Trace message extracted made available through microprocessor port. HDLC receivers provided either G.832 Network Requirement G.832 General Purpose Data Link support. receive direction, S/UNI-QJET frames G.704 6.312 signals with maximum average reframe time 5.07ms. alternate framing algorithm which uses CRC-5 bits rule 99.9% static mimic framing patterns available with maximum average reframe time 10.22ms when operating with 10-4 error rate. alternate framing algorithm selected CRC_REFR J2-FRMR Configuration Register. Line code violations, loss signal, loss frame, framing errors, physical layer AIS, payload AIS, CRC-5 errors, Remote Alarm, Remote Alarm Indication detected. HDLC receivers provided Data Link support. Error event accumulation also provided S/UNI-QJET. Framing errors, line code violations, parity errors, path parity errors block errors accumulated, when appropriate, saturating counters DS3, frames. Loss Frame detection DS3, provided recommended ITU-T G.783 with integration times 1ms, 2ms, 3ms. transmit direction, S/UNI-QJET inserts framing, bits. When enabled C-bit parity operation, bit-oriented code transmitters HDLC transmitters provided insertion FEAC channels Path Maintenance Data Links into appropriate overhead bits. Alarm Indication Signals inserted using internal register bits; other status signals such idle signal inserted when enabled internal register bits. When operation selected, C-bit Parity (the first C-bit first subframe) forced toggle that downstream equipment will confuse M23-formatted stream with stuck-at C-bits C-bit Parity application. transmit direction, S/UNI-QJET inserts framing either G.832 G.751 format. When enabled G.832 operation, HDLC transmitter provided insertion either Network Requirement General Purpose Data Link into appropriate overhead bits. Alarm Indication Signal other status signals inserted internal register bits. transmit direction, S/UNI-QJET inserts 6.312 Mbit/s G.704 framing. HDLC transmitter provided insertion Data Links. CRC-5 check bits calculated inserted into multiframe. External pins provided enable overwriting overhead bits within frame.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
S/UNI-QJET also supports diagnostic options which allow insert, when appropriate transmit framing format, parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, Remote Alarms. S/UNI-QJET provides cell delineation Acells using PLCP framing format, using header check sequence octet Acell header specified ITU-T Recommendation I.432. DS1, DS3, based PLCP frame formats processed. Non-PLCP-based cell delineation accomplished with either bit, nibble, byte-wide search algorithms, depending line interface used. interface consistent with generic physical interface defined ITU-T Recommendation I.432 provided arbitrary rates Mbit/s. This interface used provide physical layer support transmission systems that have associated PLCP sublayer, provide efficient means directly mapping Acells existing transmission system formats (such DS1). PLCP receive direction, framing, path overhead extraction cell extraction provided. BIP-8 error events, frame octet error events block error events accumulated. PLCP transmit direction, S/UNI-QJET provides overhead insertion using inputs internal registers, nibble byte stuffing, automatic BIP8 octet generation insertion automatic block error insertion. Diagnostic features BIP-8 error, framing error block error insertion also supported. cell receive path, idle cells dropped according programmable filter. default, incoming cells with single errors corrected written FIFO buffer. Optionally, cells dropped upon detection error. Cell delineation optionally disabled allow passing cells, regardless cell delineation status. Acell payloads optionally descrambled. Acell headers optionally descrambled (for with packets). Assigned cells containing detectable errors written FIFO buffer. Cells data read from FIFO using synchronous 8bit wide 16-bit wide SCI-PHYand Utopia Level compatible interface. Cell data parity also provided. Counts error-free assigned cells, cells containing errors accumulated independently performance monitoring purposes. cell transmit path, cell data written FIFO buffer using synchronous 8-bit wide 16-bit wide SCI-PHYcompatible interface. Cell data parity also examined errors. Idle cells automatically inserted when FIFO contains less than full cell. generation, cell payload scrambling,
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cell header scrambling (for with packets) optionally provided. Counts transmitted cells accumulated performance monitoring purposes. Both receive transmit cell FIFOs provide buffering four cells. FIFOs provide rate matching interface between higher layer Aentity S/UNI-QJET. S/UNI-QJET configured, controlled monitored generic 8-bit microprocessor through which internal registers accessed. sources interrupts identified, acknowledged, masked this interface.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
DIAGRAM S/UNI-QJET packaged 256-pin SBGA package having body size 27mm 27mm pitch 1.27
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PM7346 S/UNI-QJET
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DESCRIPTION Name TPOS[4] TPOS[3] TPOS[2] TPOS[1] Type Output Function Transmit Digital Positive Pulse (TPOS[4:1]). TPOS[4:1] contains positive pulses transmitted B3ZSencoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail output format selected. Transmit Data (TDATO[4:1]). TDATO[4:1] contains transmit data stream when single-rail (unipolar) output format enabled when non-DS3/E3/J2 based transmission system selected. TPOS/TDATO[4:1] function selection controlled TFRM[1:0] TUNI bits S/UNI-QJET Transmit Configuration Registers. Output signal polarity control provided TPOSINV S/UNI-QJET Transmit Configuration Registers. Both TPOS[4:1] TDATO[4:1] updated falling edge TCLK[4:1] default, configured updated rising edge TCLK[4:1] through TCLKINV S/UNI-QJET Transmit Configuration Registers. Finally, both TPOS[4:1] TDATO[4:1] updated rising edge TICLK[4:1], enabled TICLK S/UNI-QJET Transmit Configuration Registers. TNEG[4] TNEG[3] TNEG[2] TNEG[1] Output Transmit Digital Negative Pulse (TNEG[4:1]). TNEG[4:1] contains negative pulses transmitted B3ZSencoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail output format selected.
TDATO[4] TDATO[3] TDATO[2] TDATO[1]
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Name TOHM[4] TOHM[3] TOHM[2] TOHM[1]
Type Output
Function Transmit Overhead Mask (TOHM[4:1]). TOHM[4:1] indicates position overhead bits (non-payload bits) transmission system stream aligned with TDATO[4:1]. TOHM[4:1] indicates location M-frame boundary DS3, position frame boundary position multi-frame boundary when single-rail (unipolar) input format enabled. When PLCP formatted signal transmitted, TOHM[4:1] logic once transmission frame, indicates frame alignment. When non-PLCP non-DS3, non-E3, non, based signal transmitted, TOHM[4:1] delayed version TIOHM[4:1] input, indicates position each overhead transmission frame. TOHM[4:1] updated falling edge TCLK[4:1]. TNEG/TOHM[4:1] function selection controlled TFRM[1:0] TUNI bits S/UNI-QJET Transmit Configuration Registers. Output signal polarity control provided TNEGINV S/UNI-QJET Transmit Configuration Registers. Both TNEG[4:1] TOHM[4:1] updated falling edge TCLK[4:1] default, enabled updated rising edge TCLK[4:1]. This sampling controlled TCLKINV S/UNI-QJET Transmit Configuration Registers. Finally, both TNEG[4:1] TOHM[4:1] updated rising edge TICLK[4:1], enabled TICLK S/UNI-QJET Transmit Configuration Registers.
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Name TCLK[4] TCLK[3] TCLK[2] TCLK[1]
Type Output
Function Transmit Output Clock (TCLK[4:1]). TCLK[4:1] provides transmit direction timing. TCLK[4:1] buffered version TICLK[4:1] enabled update TPOS/TDATO[4:1] TNEG/TOHM[4:1] outputs rising falling edge. Receive Digital Positive Pulse (RPOS[4:1]). RPOS[4:1] contains positive pulses received B3ZSencoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail input format selected. Receive Data (RDATI[4:1]). RDATI[4:1] contains data stream when singlerail (unipolar) input format enabled when non-DS3/E3/J2 based transmission system being processed (for example RDATI contain stream). RPOS/RDATI[4:1] function selection controlled RFRM[1:0] bits S/UNI-QJET Configuration Registers bits FRMR, FRMR, FRMR Configuration Registers. Both RPOS[4:1] RDATI[4:1] sampled rising edge RCLK[4:1] default, enabled sampled falling edge RCLK[4:1]. This sampling controlled RCLKINV S/UNI-QJET Receive Configuration Registers. addition, signal polarity control provided RPOSINV S/UNI-QJET Receive Configuration Registers.
RPOS[4] RPOS[3] RPOS[2] RPOS[1]
Input
RDATI[4] RDATI[3] RDATI[2] RDATI[1]
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Name RNEG[4] RNEG[3] RNEG[2] RNEG[1]
Type Input
Function Receive Digital Negative Pulse (RNEG[4:1]). RNEG[4:1] contains negative pulses received B3ZS encoded DS3, HDB3-encoded B8ZS-encoded transmission system when dual-rail input format selected. Receive Line Code Violation (RLCV[4:1]). RLCV[4:1] contains line code violation indications when single-rail (unipolar) input format enabled DS3, applications. Each line code violation represented RCLK[4:1] period-wide pulse.
RLCV[4] RLCV[3] RLCV[2] RLCV[1]
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Name ROHM[4] ROHM[3] ROHM[2] ROHM[1]
Type Input
Function Receive Overhead Mask (ROHM[4:1]). When PLCP Adirectmapped signal received, ROHM[4:1] pulsed once transmission frame, indicates frame alignment relative RDATI[4:1] data stream. When alternate frame-based signal received, ROHM[4:1] indicates position each overhead transmission frame. RNEG/RLCV/ROHM[4:1] function selection controlled RFRM[1:0] bits S/UNI-QJET Receive Configuration Registers, bits FRMR, FRMR, FRMR Configuration Registers, PLCPEN bits SPLR Configuration register. RNEG[4:1], RLCV[4:1], ROHM[4:1] sampled rising edge RCLK[4:1] default, enabled sampled falling edge RCLK[4:1]. This sampling controlled RCLKINV S/UNI-QJET Receive Configuration Registers. addition, signal polarity control provided RNEGINV S/UNI-QJET Receive Configuration Registers.
RCLK[4] RCLK[3] RCLK[2] RCLK[1]
Input
Receive Clock (RCLK[4:1]). RCLK[4:1] provides receive direction timing. RCLK[4:1] externally recovered transmission system baud rate clock that samples RPOS/RDATI[4:1] RNEG/RLCV/ROHM[4:1] inputs rising falling edge.
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Name TOHINS[4] TOHINS[3] TOHINS[2] TOHINS[1]
Type Input
Function Transmit DS3/E3/J2 Overhead Insertion (TOHINS[4:1]). TOHINS[4:1] controls insertion DS3, overhead bits from TOH[4:1] input. When TOHINS[4:1] high, associated overhead TOH[4:1] stream inserted transmitted DS3, frame. When TOHINS[4:1] low, DS3, overhead generated inserted internally. TOHINS[4:1] sampled rising edge TOHCLK[4:1]. TOHINS[4:1] logic TOH[4:1] input precedence over internal datalink transmitter, internal register setting.
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Name TOH[4] TOH[3] TOH[2] TOH[1]
Type Input
Function Transmit DS3/E3/J2 Overhead Data (TOH[4:1]). When configured operation, TOH[4:1] contains overhead bits that inserted transmit stream. When configured G.832 operation, TOH[4:1] contains overhead bytes (FA1, FA2, mask, that inserted transmit G.832 stream. When configured G.751 operation, TOH[4:1] contains overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) that inserted transmit G.751 stream. When configured operation, TOH[4:1] contains overhead bits (TS97, TS98, Framing, X1-3, E1-5) that inserted transmit stream. TOHINS[4:1] logic TOH[4:1] input precedence over internal datalink transmitter, other internal register setting. TOH[4:1] sampled rising edge TOHCLK[4:1].
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name TOHFP[4] TOHFP[3] TOHFP[2] TOHFP[1]
Type Output
Function Transmit DS3/E3/J2 Overhead Frame Position (TOHFP[4:1]). TOHFP[4:1] used align individual overhead bits transmit overhead data stream, TOH[4:1], M-frame frame. DS3, TOHFP[4:1] high during overhead position TOH[4:1] stream. G.832 TOHFP[4:1] high during first byte. G.751 TOHFP[4:1] high during overhead position TOH[4:1] stream. TOHFP[4:1] high during first timeslot first frame 4-frame multiframe). TOHFP[4:1] updated falling edge TOHCLK[4:1]. Transmit DS3/E3/J2 Overhead Clock (TOHCLK[4:1]). TOHCLK[4:1] active when DS3, stream being processed. TOHCLK[4:1] nominally clock DS3, 1.072 clock G.832 1.074 clock G.751 gapped 6.312 clock with average frequency TOHFP[4:1] updated falling edge TOHCLK[4:1]. TOH[4:1], TOHINS[4:1] sampled rising edge TOHCLK[4:1].
TOHCLK[4] TOHCLK[3] TOHCLK[2] TOHCLK[1]
Output
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name REF8KI
Type Input
Function Reference Input (REF8KI). PLCP frame rate locked external reference applied this input internal phase-frequency detector compares transmit PLCP frame rate with externally applied reference adjusts PLCP frame rate. REF8KI input must transition high once every correct operation. REF8KI input treated asynchronous signal must "glitchfree". LOOPT register logic PLCP frame rate locked RPOHFP[x] signal instead REF8KI input.
TPOHINS[4] TPOHINS[3] TPOHINS[2] TPOHINS[1]
Input
Transmit Path Overhead Insertion (TPOHINS[4:1]). TPOHINS[4:1] controls insertion PLCP overhead octets TPOH[4:1] input. When TPOHINS[4:1] logic associated overhead TPOH[4:1] stream inserted transmit PLCP frame. When TPOHINS[4:1] logic PLCP path overhead generated inserted internally. TPOHINS[4:1] sampled rising edge TPOHCLK[4:1]. Note, when operating G.751 PLCP mode, bits octet should manipulated.
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Name TPOH[4] TPOH[3] TPOH[2] TPOH[1]
Type Input
Function Transmit PLCP Overhead Data (TPOH[4:1]). TPOH[4:1] valid when FRMRONLY S/UNI-QJET Configuration registers logic TPOH[4:1] contains PLCP path overhead octets (Zn, which inserted transmit PLCP frame. octet data TPOH[4:1] shifted order from most significant (bit least significant (bit TPOH[4:1] sampled rising edge TPOHCLK[4:1]. Framer Transmit Data (TDATI[4:1]). TDATI[4:1] contains serial data transmitted when S/UNI-QJET configured DS3, framer device non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Register. TDATI[4:1] sampled rising edge TICLK[4:1] TXGAPEN register S/UNI-QJET Configuration register logic TXGAPEN logic then TDATI[4:1] sampled falling edge TGAPCLK[4:1].
TDATI[4] TDATI[3] TDATI[2] TDATI[1]
TPOHFP[4] TPOHFP[3] TPOHFP[2] TPOHFP[1]
Output
Transmit Path Overhead Frame Position (TPOHFP[4:1]). TPOHFP[4:1] valid when FRMRONLY S/UNI-QJET Configuration Registers logic TPOHFP[4:1] output locates individual PLCP path overhead bits transmit overhead data stream, TPOH[4:1]. TPOHFP[4:1] logic while (the most significant bit) path user channel octet (F1) present TPOH[4:1] stream. TPOHFP[4:1] updated falling edge TPOHCLK[4:1].
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name TFPO[4] TFPO[3] TFPO[2] TFPO[1]
Type Output
Function Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO[4:1]). TFPO/TMFPO[4:1] valid when S/UNI-QJET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Registers logic TXGAPEN S/UNI-QJET Configuration Registers logic TFPO[4:1] pulses high every clock cycles when configured DS3, giving free-running mark overhead bits frame. TFPO[4:1] pulses high every 1536 clock cycles when configured G.751 giving freerunning reference G.751 indication. TFPO[4:1] pulses high every 4296 clock cycles when configured G.832 giving free-running reference G.832 frame indication. TFPO[4:1] pulses high every clock cycles when configured giving freerunning reference frame indication.
TMFPO[4] TMFPO[3] TMFPO[2] TMFPO[1]
TMFPO[4:1] pulses high every 4760 clock cycles when configured DS3, giving free-running reference Mframe indication. TMFPO[4:1] pulses high every 3156 clock cycles when configured giving free-running reference multi-frame indication. TMFPO[4:1] behaves same TFPO[4:1] applications. TFPO/TMFPO[4:1] updated rising edge TICLK[4:1] RCLK[4:1] loop-timed.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name TGAPCLK[4] TGAPCLK[3] TGAPCLK[2] TGAPCLK[1]
Type Output
Function Framer Gapped Transmit Clock (TGAPCLK[4:1]). TGAPCLK[4:1] valid when S/UNI-QJET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Registers TXGAPEN S/UNI-QJET Configuration Registers. TGAPCLK[4:1] derived from transmit reference clock TICLK[4:1] from receive clock loop-timed. overhead (gapped) positions generated internal device. TGAPCLK[4:1] held high during overhead positions. This clock useful interfacing devices which source payload data only. TGAPCLK[4:1] used sample TDATI[4:1].
TCELL[4] TCELL[3] TCELL[2] TCELL[1]
Transmit Cell Indication (TCELL[4:1]). TCELL[x] valid when TCELL S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH) set. TCELL[x] pulses once every cell (idle assigned) transmitted. TCELL[x] updated using timing derived from transmit input clock (TICLK[x]), active minimum TICLK[x] periods RCLK[x] periods loop-timed).
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name TPOHCLK[4] TPOHCLK[3] TPOHCLK[2] TPOHCLK[1]
Type Output
Function Transmit PLCP Overhead Clock (TPOHCLK[4:1]). TPOHCLK[4:1] active when PLCP processing enabled. TPOHCLK[4:1] nominally 26.7 clock PLCP frame, clock PLCP frame, 33.7 clock based PLCP frame, clock G.751 based PLCP frame. TPOHFP[4:1] updated falling edge TPOHCLK[4:1]. TPOH[4:1], TPOHINS[4:1] sampled rising edge TPOHCLK[4:1]. Transmit Input Overhead Mask (TIOHM[4:1]). TIOHM[4:1] valid only FRMRONLY S/UNI-QJET Configuration register logic TIOHM[4:1] indicates position overhead bits when configured DS1, DS3, transmission system streams. TIOHM[4:1] delayed internally produce TOHM[4:1] output. When configured operation over DS1, DS3, transmission system sublayer, TIOHM[4:1] required, should logic When configured other transmission systems, TIOHM[4:1] logic each overhead position. TIOHM[4:1] logic transmission system contains overhead bits. TIOHM[4:1] sampled rising edge TICLK[4:1].
TIOHM[4] TIOHM[3] TIOHM[2] TIOHM[1]
Input
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name TFPI[4] TFPI[3] TFPI[2] TFPI[1]
Type Input
Function Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI[4:1]). TFPI/TMFPI[4:1] valid when S/UNI-QJET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Register logic TFPI[4:1] indicates position overhead bits each M-subframe, first each G.751 G.832 frame, first framing each frame. TFPI[4:1] required pulse every frame boundary modes.
TMFPI[4] TMFPI[3] TMFPI[2] TMFPI[1]
TMFPI[4:1] indicates position first each M-frame, first each frame, first framing each multiframe. TMFPI[4:1] required pulse every multiframe boundary. TFPI/TMFPI[4:1] sampled rising edge TICLK[4:1].
TICLK[4] TICLK[3] TICLK[2] TICLK[1]
Input
Transmit Input Clock (TICLK[4:1]). TICLK[4:1] provides transmit direction timing. TICLK[4:1] externally generated transmission system baud rate clock. internally buffered produce transmit clock output, TCLK[4:1], enabled update TPOS/TDATO[4:1] TNEG/TOHM[4:1] outputs TICLK[4:1] rising edge. TICLK[4:1] maximum frequency MHz.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name ROHFP[4] ROHFP[3] ROHFP[2] ROHFP[1]
Type Output
Function Receive DS3/E3/J2 Overhead Frame Position (ROHFP[4:1]). ROHFP[4:1] locates individual overhead bits received overhead data stream, ROH[4:1]. ROHFP[4:1] high during overhead position ROH[4:1] stream when processing stream. ROHFP[4:1] high during first byte when processing G.832 stream. ROHFP[4:1] high during overhead position when processing G.751 stream. ROHFP[4:1] high during first Timeslot first frame 4-frame multiframe when processing stream. ROHFP[4:1] updated falling edge ROHCLK[4:1]. Receive DS3/E3/J2 Overhead Data (ROH[4:1]). ROH[4:1] contains overhead bits extracted from received stream; ROH[4:1] contains overhead bytes (FA1, FA2, extracted from received G.832 stream; ROH[4:1] contains overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) extracted from received G.751 stream; ROH[4:1] contains overhead bits (Framing, X1-3, E1-5) extracted from received stream. ROH[4:1] updated falling edge ROHCLK[4:1].
ROH[4] ROH[3] ROH[2] ROH[1]
Output
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name ROHCLK[4] ROHCLK[3] ROHCLK[2] ROHCLK[1]
Type Output
Function Receive DS3/E3/J2 Overhead Clock (ROHCLK[4:1]). ROHCLK[4:1] active when DS3, stream being processed. ROHCLK[4:1] nominally clock when processing DS3, 1.072 clock when processing G.832 1.074 clock when processing G.751 gapped 6.312 clock with average frequency ROH[4:1], ROHFP[4:1] updated falling edge ROHCLK[4:1]. Reference 8kHz Output (REF8KO[4:1]). REF8KO[4:1] 8kHz reference derived from receive clocks RCLK[4:1]. free-running divide-down counter used generate REF8KO[4:1] will glitch reframe actions. REF8KO[4:1] will pulse high approximately RCLK[4:1] cycle every REF8KO[4:1] should treated glitch-free asynchronous signal. Receive PLCP Overhead Frame Position (RPOHFP[4:1]). RPOHFP[4:1] locates individual PLCP path overhead bits receive overhead data stream, RPOH[4:1]. RPOHFP[4:1] logic while (the most significant bit) path user channel octet (F1) present RPOH[4:1] stream. RPOHFP[4:1] updated falling edge RPOHCLK[4:1]. RPOHFP[4:1] available when PLCPEN register logic SPLR Configuration Register.
REF8KO[4] REF8KO[3] REF8KO[2] REF8KO[1]
Output
RPOHFP[4] RPOHFP[3] RPOHFP[2] RPOHFP[1]
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name RFPO[4] RFPO[3] RFPO[2] RFPO[1]
Type Output
Function Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO[4:1]). RFPO/RMFPO[4:1] valid when S/UNI-QJET configured framer only mode. 8KREFO must logic S/UNI-QJET Configuration Register. RFPO[4:1] aligned RDATO[4:1] indicates position first each M-subframe, first each G.751 G.832 frame, first framing each frame
RMFPO[4] RMFPO[3] RMFPO[2] RMFPO[1]
RMFPO[4:1] aligned RDATO[4:1] indicates position first each M-frame, first each G.751 G.832 multiframe, first framing each multiframe. RFPO/RMFPO[4:1] updated either falling rising edge RSCLK[4:1] depending setting RSCLKR S/UNI-QJET Receive Configuration register.
RPOH[4] RPOH[3] RPOH[2] RPOH[1]
Output
Receive PLCP Overhead Data (RPOH[4:1]). RPOH[4:1] contains PLCP path overhead octets (Zn, extracted from received PLCP frame when PLCP layer in-frame. When PLCP layer loss frame state, RPOH[4:1] forced ones. octet data RPOH[4:1] shifted order from most significant (bit least significant (bit RPOH[4:1] updated falling edge RPOHCLK[4:1].
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Name ROVRHD[4] ROVRHD[3] ROVRHD[2] ROVRHD[1]
Type Output
Function Framer Receive Overhead Indication (ROVRHD[4:1]). ROVRHD[4:1] valid when S/UNI-QJET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Registers. ROVRHD[4:1] will high whenever data RDATO[4:1] corresponds overhead position. ROVRHD[4:1] updated either falling rising edge RSCLK[4:1] depending setting RSCLKR S/UNI-QJET Receive Configuration register. Receive PLCP Overhead Clock (RPOHCLK[4:1]). RPOHCLK[4:1] active when PLCP processing enabled. frequency this signal depends selected PLCP format. RPOHCLK[4:1] nominally 26.7 clock PLCP frame, clock PLCP frame, 33.7 clock based PLCP frame, clock G.751 based PLCP frame. RPOHFP[4:1] RPOH[4:1] updated falling edge RPOHCLK[4:1]. Framer Recovered Clock (RSCLK[4:1]). RSCLK[4:1] valid when S/UNI-QJET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Register. RSCLK[4:1] recovered clock timing reference RDATO[4:1], RFPO/RMFPO[4:1], ROVRHD[4:1].
RPOHCLK[4] RPOHCLK[3] RPOHCLK[2] RPOHCLK[1]
Output
RSCLK[4] RSCLK[3] RSCLK[2] RSCLK[1]
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name RGAPCLK[4] RGAPCLK[3] RGAPCLK[2] RGAPCLK[1]
Type Output
Function Framer Recovered Gapped Clock (RGAPCLK[4:1]). RGAPCLK[4:1] valid when S/UNI-QJET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Register RXGAPEN S/UNI-QJET Configuration Register. RGAPCLK[4:1] recovered clock timing reference RDATO[4:1]. RGAPCLK[4:1] held high positions which correspond overhead.
LCD[4] LCD[3] LCD[2] LCD[1]
Output
Loss Cell Delineation (LCD[4:1]). LCD[4:1] active high signal which asserted while Acell processor detected Loss Cell Delineation defect. FRMRONLY S/UNI-QJET Configuration Register must logic LCD[4:1] valid. Framer Receive Data (RDATO[4:1]). RDATO[4:1] valid when S/UNI-QJET configured DS3, framer non-Aapplications setting FRMRONLY S/UNI-QJET Configuration Register. RDATO[4:1] received data aligned RFPO/RMFPO[4:1] ROVRHD[4:1]. RDATO[4:1] updated active edge RSCLKR register bit) RSCLK[4:1] RGAPCLK[4:1].
RDATO[4] RDATO[3] RDATO[2] RDATO[1]
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Name FRMSTAT[4] FRMSTAT[3] FRMSTAT[2] FRMSTAT[1]
Type Output
Function Framer Status (FRMSTAT[4:1]). FRMSTAT[4:1] active high signal which configured show when DS3, PLCP framers have detected certain conditions. FRMSTAT[4:1] outputs programmed STATSEL[2:0] bits S/UNI-QJET Configuration Register indicate: E3/DS3 Loss Frame extended Loss Frame, E3/DS3 Frame Loss Frame, PLCP Loss Frame, PLCP Frame, AIS, Loss Signal, Idle. FRMSTAT[4:1] should treated glitch free asynchronous signal. AInterface Width Selection (ATM8). ATM8 input determines whether S/UNI-QJET works with 8bit wide interface (RDAT[7:0] TDAT[7:0]) 16-bit wide interface (RDAT[15:0] TDAT[15:0]). ATM8 logic then 8-bit wide interface chosen. ATM8 logic then 16-bit wide interface chosen.
ATM8
Input
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Name TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]
Type Input
Function Transmit Cell Data (TDAT[15:0]). This carries Acell octets that written selected transmit FIFO. TDAT[15:0] sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-QJET been selected TADR[4:2] PHY_ADR[2:0] inputs. S/UNI-QJET configured operate with 8-bit wide 16-bit wide Adata interface ATM8 input pin. When configured 8-bit wide interface, TDAT[15:8] used should tied ground.
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Name TPRTY
Type Input
Function Transmit parity (TPRTY). transmit parity (TPRTY) signal indicates parity TDAT[15:0] TDAT[7:0] bus. configured 8-bit (via ATM8 input pin), then parity calculated over TDAT[7:0]. configured 16-bit bus, then parity calculated over TDAT[15:0]. parity error indicated status maskable interrupt. Cells with parity errors inserted transmit stream, TPRTY input unused. even parity selection made using TPTYP register bit. TPRTY sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-QJET been selected TADR[4:0] PHY_ADR[2:0] inputs.
TSOC
Input
Transmit Start Cell (TSOC). transmit start cell (TSOC) signal marks start cell TDAT bus. When TSOC high, first word cell structure present TDAT bus. necessary TSOC present each cell. interrupt generated TSOC high during word other than first word cell structure. TSOC sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-QJET been selected TADR[4:2] PHY_ADR[2:0] inputs.
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Name TENB
Type Input
Function Transmit Multi-Phy Write Enable (TENB). TENB signal active input which used along with TADR[4:0] inputs initiate writes transmit FIFOs. When sampled using rising edge TFCLK, word TDAT written into transmit FIFO selected TADR[4:0] address bus. When sampled high using rising edge TFCLK, write performed, TADR[4:0] address latched identify transmit FIFO accessed. complete octet cell must written transmit FIFO before inserted into transmit stream. Idle cells inserted when complete cell available. Transmit Address (TADR[4:0]). TADR[4:0] used select FIFO (and hence port) that written using TENB signal FIFO whose cellavailable signal visible output. TADR[4:0] sampled rising edge TFCLK together with TENB. Note that null-PHY address invalid address will identified port S/UNI-QJET.
TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]
Input
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name
Type Output
Function Transmit Multi-Phy Cell Available (TCA). signal indicates when cell available transmit FIFO port selected TADR[4:0]. When high, indicates that corresponding transmit FIFO full complete cell written. When goes low, configured indicate either that corresponding transmit FIFO near full that corresponding transmit FIFO full. will transition rising edge TFCLK which samples Payload byte (TCALEVEL0=0) (TCALEVEL0=1) 8-bit interface (ATM8=1), rising edge TFCLK which samples Payload word (TCALEVEL0=0) (TCALEVEL0=1) 16-bit interface (ATM8=0) being polled same use. reduce FIFO latency, FIFO depth which indicates "full" one, two, three four cells. Note that regardless what fill level indicate "full" transmit cell processor store complete cells. tri-stated when either null-PHY address (1FH) address matching address space PHY_ADR[2:0] latched TFCLK) from TADR[4:2] inputs. polarity (with respect description above) inverted when TCAINV register logic
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name TFCLK
Type Input
Function Transmit FIFO Write Clock (TFCLK). This signal used write Acells four cell transmit FIFOs. TFCLK cycles lower instantaneous rate. Please note that TFCLK input tolerant, only input pin.
DTCA[4] DTCA[3] DTCA[2] DTCA[1]
Output
Direct Access Transmit Cell Available (DTCA[4:1]). These output signals indicate when cell available transmit FIFO corresponding port. When high, DTCA[x] indicates that corresponding transmit FIFO full complete cell written. DTCA[x] configured indicate either that corresponding transmit FIFO near full accept more than four writes that corresponding transmit FIFO full. DTCA[x] will thus transition rising edge TFLCK which samples Payload byte (TCALEVEL0=0) (TCALEVEL0=1) 8-bit interface (ATM8=1), rising edge TFCLK which samples Payload word (TCALEVEL0=0) (TCALEVEL0=1) 16-bit interface (ATM8=0). reduce FIFO latency, FIFO depth which DTCA[x] indicates "full" one, two, three four cells. Note that regardless what fill level DTCA[x] indicate "full" transmit cell processor store complete cells. polarity DTCA[x] (with respect description above) inverted when TCAINV register logic DTCA[4:1] outputs used support Utopia Direct Access mode.
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DATASHEET PMC-960835 ISSUE SATURN QUAD USER NETWORK INTERFACE
Name RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] RPRTY
Type Output
Function Receive Cell Data (RDAT[15:0]). This carries Acell octets that read from receive AFIFO selected RADR[4:0]. RDAT[15:0] tri-stated when RENB high. RDAT[15:0] updated rising edge RFCLK. S/UNI-QJET configured operate with 8-bit wide 16-bit wide Adata interface ATM8 input pin. RDAT[15:8] will remain tri-stated ATM8 logic RDAT[15:0] tri-stated when either null-PHY address (1FH) address matching address space PHY_ADR[2:0] latched from RADR[4:2] inputs when RENB high.
Output
Receive Parity (RPRTY). receive parity (RPRTY) signal indicates parity RDAT bus. S/UNI-QJET configured operate with 8-bit wide 16-bit wide Adata interface ATM8 input pin. 8-bit mode, RPRTY reflects parity RDAT[7:0]. 16-bit mode, RPRTY reflects parity RDAT[15:0]. even parity selection made using RXPTYP register bit. RPRTY tri-stated when either nullPHY address (1FH) address matching address space PHY_ADR[2:0] latched from RADR[4:2] inputs when RENB high.
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Name RSOC
Type Output
Function Receive Start Cell (RSOC). This signal marks start cell RDAT bus. RSOC marks start cell RDAT bus. RSOC tri-stated when either nullPHY address (1FH) address matching address space PHY_ADR[2:0] latched from RADR[4:0] inputs when RENB high.
RENB
Input
Receive Multi-Phy Read Enable (RENB). RENB signal used initiate reads from receive FIFOs. When sampled using rising edge RFCLK, byte read available) from receive FIFO selected RADR[4:0] address output RDAT bus. When sampled high using rising edge RFCLK, read performed RDAT[15:0], RPRTY, RSOC tristated, address RADR[4:0] latched select device port next AFIFO access. RENB must operate conjunction with RFCLK access FIFOs high enough rate prevent FIFO overflows. Alayer device de-assert RENB anytime unable accept another byte.
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Name RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]
Type Input
Function Receive Address (RADR[4:0]). RADR[4:1] signal used select FIFO (and hence port) that read from using RENB signal FIFO whose cell-available signal visible output. RADR[4:0] sampled rising edge RFCLK together with RENB. Note that null-PHY address invalid address will identified port S/UNI-QJET.
Output
Receive Multi-Phy Cell Available (RCA). signal indicates when cell available receive FIFO port selected RADR[4:0]. configured de-asserted when either zero four bytes remain selected/addressed FIFO. will thus transition rising edge RFCLK after Payload byte (RCALEVEL0=1) (RCALEVEL0=0) output 8-bit interface (ATM8=1), after Payload word (RCALEVEL0=1) (RCALEVEL0=0) output 16-bit interface (ATM8=0) being polled same use. tri-stated when either null-PHY address (1FH) address matching address space PHY_ADR[2:0] latched RFCLK) from RADR[4:2] inputs. polarity (with respect description above) inverted when RCAINV register logic
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Name RFCLK
Type Input
Function Receive FIFO Read Clock (RFCLK). This signal used read Acells from receive FIFOs. RFCLK must cycle lower instantaneous rate, high enough rate avoid FIFO overflows. Please note that RFCLK input tolerant, only input pin.
DRCA[4] DRCA[3] DRCA[2] DRCA[1]
Output
Direct Access Receive Cell Available (DRCA[4:1]). These output signals indicate when cell available receive FIFO corresponding port. DRCA[4:1] configured deasserted when either zero four bytes remain FIFO. DRCA[4:1] will thus transition rising edge RFCLK after Payload byte (RCALEVEL0=1) (RCALEVEL0=0) output 8-bit interface (ATM8=1), after Payload word (RCALEVEL0=1) (RCALEVEL0=0) output 16-bit interface (ATM8=0). DRCA[4:1] outputs used support Utopia Direct Access mode.
PHY_ADR[2] PHY_ADR[1] PHY_ADR[0]
Input
Device Identification Address (PHY_ADR[2:0]). PHY_ADR[2:0] inputs most-significant bits address space which this S/UNI-QJET occupies. When PHY_ADR[2:0] inputs match TADR[4:2] RADR[4:2] inputs, then four quadrants determined TADR[1:0] RADR[1:0] inputs) this S/UNI-QJET selected transmit receive Aaccess. Note that null-PHY address invalid address will identified port S/UNI-QJET.
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Name
Type Input
Function Active Chip Select (CSB). This signal must enable S/UNI-QJET register accesses. used, (RDB determine register reads writes) then should tied inverted version RSTB. Active Write Strobe (WRB). This signal pulsed enable S/UNI-QJET register write access. D[7:0] clocked into addressed register rising edge while low. Active Read Enable (RDB). This signal pulsed enable S/UNI-QJET register read access. S/UNI-QJET drives D[7:0] with contents addressed register while both low. Bi-directional Data (D[7:0]). bidirectional data D[7:0] used during S/UNI-QJET register read write accesses.
Input
Input
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
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Name A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB
Type Input
Function Address (A[10:0]). address A[10:0] selects specific registers during S/UNI-QJET register accesses.
Input
Active Reset (RSTB). This signal asynchronously reset S/UNI-QJET. RSTB Schmitt-trigger input with integral pull-up resistor. Address Latch Enable (ALE). address latch enable (ALE) active-high latches address A[10:0] when low. When high, internal address latches transparent. allows S/UNI-QJET interface multiplexed address/data bus. integral pull-up resistor. Active Open-Drain Interrupt (INTB). This signal goes when unmasked interrupt event detected internal interrupt sources. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source. Test Clock (TCK). This signal provides timing test operations that carried using IEEE P1149.1 test access port.
Input
INTB
Output
Input
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Name
Type Input
Function Test Mode Select (TMS). This signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Input (TDI). This signal carries test data into S/UNI-QJET IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Output (TDO). This signal carries test data S/UNI-QJET IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress. Active Test Reset (TRSTB). This signal provides asynchronous S/UNI-QJET test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull resistor. TRSTB must asserted during power sequence. Note that used, TRSTB must connected RSTB input.
Input
Output
TRSTB
Input
BIAS
Input
Bias (BIAS). When tied +5V, BIAS input used bias wells input pads that pads tolerate their inputs without forward biasing internal protection devices. When tied VDD, inputs bidirectional inputs will only tolerate input levels VDD.
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Name VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15] VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28]
Type Power
Function Power. Power pins should connected well-decoupled +3.3V supply.
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Name VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29]
Type Ground
Function Ground. Ground pins should connected GND.
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Name VSS[30] VSS[31] VSS[32]
Type Ground
Function Ground. Ground pins should connected GND.
Notes Description: S/UNI-QJET inputs bi-directionals present minimum capacitive loading operate logic levels. S/UNI-QJET outputs bi-directionals have least drive capability. data outputs, D[7:0], have drive capability. FIFO interface outputs, RDAT[15:0], RPRTY, RCA, DRCA[4:1], RSOC, TCA, DTCA[4:1], have drive capability. outputs TCLK[4:1], TPOS/TDATO[4:1], TNEG/TOHM[4:1], TPOHFP/TFPO/TMFPO/TGAPCLK[4:1], LCD/RDATO[4:1], RPOH/ROVRHD[4:1], RPOHCLK/RSCLK/RGAPCLK[4:1], REF8KO/RPOHFP/RFPO/RMFPO[4:1] have drive capability. other outputs have drive capability. Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors. RSTB, TRSTB, TMS, TDI, TCK, REF8KI, TFCLK, RFCLK, TICLK[4:1], RCLK[4:1] schmitt trigger input pads. RFCLK TFCLK only input pins they tolerant. Connecting signal these inputs result damage part. [32:1] ground pins internally connected together. Failure connect these pins externally cause malfunction damage S/UNI-QJET. VDD[28:1] power pins internally connected together. Failure connect these pins externally cause malfunction damage device. These power supply connections must utilized must connect common +3.3 ground rail, appropriate. During power-up power-down, voltage BIAS must kept equal greater than voltage [28:1] pins, avoid damage device.
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FUNCTIONAL DESCRIPTION Framer Framer (T3-FRMR) Block integrates circuitry required decoding B3ZS-encoded signal framing resulting stream. T3-FRMR directly compatible with C-bit parity applications. T3-FRMR decodes B3ZS-encoded signal provides indications line code violations. B3ZS decoding algorithm definition independently chosen through software. loss signal (LOS) defect also detected B3ZS encoded streams. declared when inputs RPOS RNEG contain zeros consecutive RCLK cycles. removed when ones density RPOS and/or RNEG greater than RCLK cycles. framing algorithm examines five F-bit candidates simultaneously. When least discrepancy occurred each candidate, algorithm examines next five candidates. When single F-bit candidate remains set, first supposed M-subframe examined M-frame alignment signal (i.e., M-bits, following pattern). Framing declared, out-of-frame removed, M-bits correct three consecutive M-frames while discrepancies have occurred F-bits. During examination M-bits, X-bits P-bits ignored. algorithm gives maximum average reframe time While T3-FRMR synchronized M-frame, F-bit M-bit positions stream examined. out-of-frame defect detected when F-bit errors consecutive F-bits observed selected M3O8 FRMR Configuration Register), when more M-bit errors detected consecutive M-frames. M-bit error criteria disabled MBDIS Framer Configuration register. consecutive F-bits out-of-frame ratio provides more robust operation, presence high error rate, than consecutive F-bits ratio. Either out-of-frame criteria allows out-offrame defect detected quickly when M-subframe alignment patterns optionally, when M-frame alignment pattern lost. Also while in-frame, line code violations, M-bit F-bit framing errors, Pbit parity errors indicated. When C-bit parity mode enabled, both C-bit parity errors block errors indicated. These error indications, well line code violation excessive zeros indication, accumulated
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over second intervals with Performance Monitor (PMON). Note that framer off-line framer, indicating both COFA events. Even indicated, framer will continue indicating performance monitoring information based previous frame alignment. Three maintenance signals alarm condition, alarm indication signal, idle signal) detected T3-FRMR. maintenance detection algorithm employs simple integrator with slope that based occurrence "valid" M-frame intervals. alarm, M-frame said "valid" interval contains defect, defined occurrence event during that M-frame. IDLE, M-frame interval "valid" contains IDLE, defined occurrence less than discrepancies expected signal pattern (1010. AIS, 1100. IDLE) while valid frame alignment maintained. This discrepancy threshold ensures detection algorithms operate presence 10-3 error rate. AIS, expected pattern selected framed "1010" signal; framed arbitrary signal C-bits zero; framed "1010" signal Cbits zero; framed all-ones signal (with overhead bits ignored); unframed all-ones signal (with overhead bits equal ones). Each "valid" Mframe causes associated integration counter increment; "invalid" M-frames cause decrement. With "slow" detection option, RED, AIS, IDLE declared when respective counter saturates 127, which results detection time 13.5 With "fast" detection option, RED, AIS, IDLE declared when respective counter saturates which results detection time 2.23 (i.e., times maximum average reframe time). RED, AIS, IDLE removed when respective counter decrements Loss Frame detection provided recommended ITU-T G.783 with programmable integration periods 1ms, 2ms, 3ms. While integrating assert LOF, counter will integrate when framer asserts Frame condition integrates down when framer de-asserts Frame condition. Once asserted, framer must assert entire integration period before de-asserted. Valid X-bits extracted T3-FRMR provide indication receive failure (FERF). FERF defect detected extracted X-bits equal logic (X1=X2=0); defect removed extracted X-bits equal logic (X1=X2=1). X-bits equal, FERF status remains previous state. extracted FERF status buffered M-frames before being reported within FRMR Status register. This buffer ensures better than 99.99% chance freezing FERF status correct value during occurrence frame.
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When C-bit parity application enabled, both alarm control (FEAC) channel path maintenance data link extracted. Codes FEAC channel detected Oriented Code Detector (RBOC). HDLC messages Path Maintenance Data Link received Data Link Receiver (RDLC). T3-FRMR enabled automatically assert indication outgoing transmit stream upon detection combination LOS, RED, AIS. T3-FRMR also enabled automatically insert C-bit Parity FEBE upon detection receive C-bit parity error. T3-FRMR extracts entire overhead bits M-frame) using output, along with ROHCLK, ROHFP outputs. T3-FRMR configured generate interrupts error events status changes. sources interrupts masked acknowledged internal registers. Internal registers also used configure T3-FRMR. Access these registers generic microprocessor bus. Framer Framer (E3-FRMR) Block integrates circuitry required decoding HDB3-encoded signal framing resulting stream. E3-FRMR directly compatible with G.751 G.832 applications. E3-FRMR searches frame alignment incoming serial stream based either G.751 G.832 formats. G.751 format, E3-FRMR expects selected framing pattern error-free three consecutive frames before declaring INFRAME. G.832 format, E3-FRMR expects selected framing pattern error-free consecutive frames before declaring INFRAME. Once frame alignment established, incoming data continuously monitored framing errors byte interleaved parity errors G.832 format). While in-frame, E3-FRMR also extracts various overhead bytes processes them according framing format selected: G.832 format, E3-FRMR extracts: Trail Trace bytes outputs them serial stream further processing Trail Trace Buffer (TTB) block;
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FERF indicates alarm when FERF logic consecutive frames. FERF indication removed when FERF logic consecutive frames; FEBE outputs accumulation PMON; Payload Type bits buffers them that they read microprocessor; Timing Marker asserts Timing Marker indication when value extracted been same state consecutive frames; Network Operator byte presents serial stream further processing RDLC block when RNETOP S/UNI-QJET Data Link FERF Control register logic byte also brought ROH[x] output with associated clock ROHCLK[x]. bits Network Operator byte extracted presented overhead output and, optionally, presented RDLC. General Purpose Communication Channel byte presents RDLC when RNETOP S/UNI-QJET Data Link FERF Control register logic byte also brought ROH[x] output with associated clock ROHCLK[x].
G.751 mode, E3-FRMR extracts: Remote Alarm Indication (bit frame) indicates Remote Alarm when logic consecutive frames. Similarly, Remote Alarm removed when logic consecutive frames; National reserved (bit frame) presents serial stream further processing RDLC when RNETOP S/UNI-QJET Data Link FERF Control register logic also brought ROH[x] output with associated clock ROHCLK[x]. Optionally, interrupt generated when National changes state.
Further, while in-frame, E3-FRMR indicates position overhead bits incoming digital stream ATMF/SPLR block. G.751 mode, tributary justification bits optionally identified either overhead payload payload mappings that take advantage full bandwidth.
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E3-FRMR declares frame alignment framing pattern error four consecutive frames. E3-FRMR "off-line" framer, where frame alignment indications, overhead indications, overhead processing continue based previous alignment. Once framer determined frame alignment, out-of-frame indication removed COFA indication declared alignment differs from previous alignment. E3-FRMR detects presence incoming data stream when less than zeros frame detected while framer G.832 mode, when less than zeros frame detected while G.751 mode. This algorithm provides probability detecting presence 10-3 92.9% G.832 98.0% G.751. Loss signal declared when marks have been received consecutive periods. Loss signal de-asserted after periods during which there sequence four consecutive zeros. Loss Frame detection provided recommended ITU-T G.783 with programmable integration periods 1ms, 2ms, 3ms. While integrating assert LOF, counter will integrate when framer asserts Frame condition integrates down when framer de-asserts Frame condition. Once asserted, framer must assert entire integration period before de-asserted. E3-FRMR also enabled automatically assert RAI/FERF indication outgoing transmit stream upon detection combination LOS, AIS. E3-FRMR also enabled automatically insert G.832 FEBE upon detection receive BIP-8 errors. Framer J2-FRMR integrates circuitry decode unipolar B8ZS encoded signal frame resulting 6312 kbps stream. Having found frame, J2FRMR extracts variety overhead datalink information from stream. format consists 789-bit frames, each 125µs long, consisting bytes payload, reserved bytes, F-bits. frames grouped into 4frame multiframes. multiframe format follows:
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Frm. Frm. Frm. Frm.
TS1[1:8] TS1[1:8] TS1[1:8] TS1[1:8]
761-768 TS96[1:8] TS96[1:8] TS96[1:8] TS96[1:8]
769-776 TS97[1:8] TS97[1:8] TS97[1:8] TS97[1:8]
777-784 TS98[1:8] TS98[1:8] TS98[1:8] TS98[1:8]
TS96 TS97, TS98:
Byte interleaved payload Reserved channels signaling represented binary ones zeroes
Frame Alignment Signal: e1.e5:
4-kHz datalink Spare bits, usually logic Remote Loss Frame alarm bit, active high CRC-5 check sequence. entire 3156-bit multiframe, including CRC-5 check sequence, should have remainder when divided
J2-FRMR frames signal with average reframe time 5.07 alternate framing algorithm that uses CRC-5 check detect static mimic patterns available. Once frame, J2-FRMR provides indications frame multiframe boundaries, marks overhead bits, x-bits, m-bits, reserved channels (TS97 TS98). Indications loss signal, bipolar violations, excessive zeroes, change frame alignment, framing errors, errors provided, accumulated PMON (with exception change frame alignment); maskable interrupts available alert microprocessor occurrence these events. addition marking x-bit values, J2-FRMR provides microprocessor access x-bits, will optionally generate interrupt when x-bits changes state. m-bits associated clock either extracted through RDLC through ROH[x] ROHCLK[x] output pins S/UNI-QJET. m-bits also presented RBOC detection generic bit-oriented codes. Status signals such Physical AIS, Payload AIS, Remote Alarm Indication
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m-bits, Remote Loss Frame (a-bit) detected J2-FRMR. addition providing indication signals these states, J2-FRMR will optionally generate interrupt when these status signals changes. declared when marks have been received consecutive periods. cleared when either consecutive periods have passed without excessive zeros more consecutive zeros) detection required ITU-T G.775. declared when more consecutive multiframes with errored framing patterns received. cleared when more consecutive multiframes with correct framing patterns received. framing algorithm which takes into account calculation also available. framing algorithms described following text. Physical Layer declared when less zeros detected sequence 3156 bits. cleared when more zeros detected sequence 3156 bits required ITU-T G.775. Payload detected when incoming payload less zeros sequence 3072 bits. cleared when more zeros detected sequence 3072 bits. J2-FRMR forced re-frame microprocessor control. Similarly, microprocessor disable J2-FRMR from reframing framing errors. J2-FRMR configured, sources interrupts masked acknowledged, internal registers. These internal registers accessed generic microprocessor bus. 9.3.1 Frame Find Algorithms J2-FRMR searches frame alignment using algorithms, selected CRC_REFR J2-FRMR Configuration Register. When CRC_REFR logic J2-FRMR uses only frame alignment sequence find frame, searching three consecutive correct frame alignment sequences. frame find block searches entire 9-bit sequence (spread over multiframes) same time, greatly reducing time required find frame alignment. framing process with CRC-REFR cleared illustrated Figure
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Figure
Framing algorithm (CRC_REFR
Fram
Fram Pattern Matched Mark multiframe alignment
Fail
onfirm Fram Pattern next ultifra
Fail
onfirm Pattern next ultifram
Declare in-frame
Using this algorithm, J2-FRMR will average find frame 5.07ms when starting search worst possible position, given error rate static mimic patterns. When CRC_REFR logic addition requiring three consecutive correct framing patterns, J2-FRMR requires that first CRC-5 checks correct, reframe initiated. speed process, CRC-5 frame alignment checks concurrently, illustrated Figure
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Figure
Framing Algorithm (CRC_REFR
eset Fram
Fram Pattern Matc Mark multiframe alignment
Fail
onfirm Pattern next ultifram
Fail
Sequence
Fail
onfirm Pattern next ultifram
Fail
Sequenc
Declare in-frame
Using this algorithm, J2-FRMR will find frame 10.22ms, average when starting search worst possible position, given error rate static mimic patterns. algorithm will reject 99.90% mimic patterns. Further protection against mimic patterns available monitoring rate CRC-5 errors. Once frame alignment found, block sets indication low, indicates change frame alignment occurred). block declares loss frame alignment consecutive FASs have been received error. presence random 10-3 error rate frame loss criteria provides mean time falsely lose frame alignment 1.65 years. Frame Find Block forced initiate frame search time when REFRAME J2-FRMR Configuration. Conversely, when FLOCK logic J2-FRMR
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will never declare Loss Frame search frame alignment excess framing errors. extended Loss Frame detection provided recommended ITU-T G.783 with programmable integration periods 1ms, 2ms, 3ms. While integrating assert LOF, counter will integrate when framer asserts Frame condition integrates down when framer deasserts Frame condition. Once asserted, framer must assert entire integration period before de-asserted. PMON Performance Monitor Accumulator Performance Monitor (PMON) Block interfaces directly with either Framer (T3-FRMR) accumulate line code violation (LCV) events, parity error (PERR) events, path parity error (CPERR) events, block error (FEBE) events, excess zeros (EXZS), framing error (FERR) events using saturating counters; Framer (E3-FRMR) accumulate LCV, PERR G.832 mode), FEBE FERR events; Framer (J2-FRMR) accumulate LCVs, errors PERR counter), Framing errors (FERR), excess zeros (EXZS). PMON stops accumulating error signal from DS3, Framers once frame synchronization lost. When accumulation interval signaled write PMON register address space write S/UNI-QJET Identification, Master Reset, Global Monitor Update register, PMON transfers current counter values into microprocessor accessible holding registers resets counters begin accumulating error events next interval. counters reset such manner that error events occurring during reset period missed. When counter data transferred into holding registers, interrupt generated, providing interrupt enabled. holding registers have been read since last interrupt, overrun status set. addition, register provided indicate changes PMON counters since last accumulation interval. RBOC Bit-Oriented Code Detector Bit-Oriented Code Detector only used C-bit Parity mode. Bit-Oriented Code Detector (RBOC) Block detects presence possible bit-oriented codes (BOCs) contained C-bit parity far-end alarm control (FEAC) channel datalink signal stream. 64th code ("111111") similar HDLC flag sequence ignored.
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Bit-oriented codes (BOCs) received FEAC channel 16-bit sequences each consisting ones, zero, code bits, trailing zero ("111111110xxxxxx0"). BOCs validated when repeated least times. RBOC enabled declare code valid been observed times times, specified RBOC Configuration/Interrupt Enable Register. RBOC declares that code removed code sequences containing code values different from detected code received moving window code periods. Valid BOCs indicated through RBOC Interrupt Status Register. bits ones ("111111") when valid code detected. RBOC programmed generate interrupt when detected code been validated when code removed. RDLC Facility Data Link Receiver RDLC microprocessor peripheral used receive LAPD/HDLC frames serial HDLC stream that provides data clock information such C-bit parity Path Maintenance Data Link, G.832 Network Requirement byte General Purpose data link (selectable using RNETOP S/UNI-QJET Data Link FERF/RAI Control register), G.751 Network bit, m-bit Data Link. RDLC detects change from flag characters first byte data, removes stuffed zeros incoming data stream, receives packet data, calculates CRC-CCITT frame check sequence (FCS). address matching mode, only those packets whose first data byte matches programmable bytes universal address (all ones) stored FIFO. least significant bits address comparison masked LAPD SAPI matching. Received data placed into 128-level FIFO buffer. interrupt generated when programmable number bytes stored FIFO buffer. Other sources interrupt detection terminating flag sequence, abort sequence, FIFO buffer overrun. Status Register contains bits which indicate overrun empty FIFO status, interrupt status, occurrence first flag message bytes written into FIFO. Status Register also indicates abort, flag, message status data just read from FIFO. message, Status Register indicates status packet contained non-integer number bytes.
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SPLR PLCP Layer Receiver PLCP Layer Receiver (SPLR) Block integrates circuitry support DS1, DS3, G.751 PLCP frame processing. SPLR provides framing PLCP based transmission formats. SPLR frames DS1, DS3, G.751 based PLCP frames with maximum average reframe times respectively. Framing declared (out frame removed) upon finding valid, consecutive sets framing octets valid sequential path overhead identifier (POHID) octets. While framed, POHID octets examined. declared when error detected both octets when consecutive POHID octets found error. declared when state persists more than DS1, DS3, G.751 PLCP formats respectively. events intermittent, counter decremented rate 1/12 (DS3 PLCP), 1/10 (E1, PLCP) 1/9(G.751 PLCP) incrementing rate. thus removed when in-frame state persists more than signal, signal, signal, G.751 signal. When declared, PLCP reframe initiated. When frame, SPLR extracts path overhead octets outputs them serially output RPOH, along with RPOHCLK RPOHFP outputs. Framing octet errors path overhead identifier octet errors indicated frame errors. interleaved parity errors block errors indicated. yellow signal extracted accumulated indicate yellow alarms. Yellow alarm declared when consecutive yellow signal bits logical removed when consecutive received yellow signal bits logical octet examined maintain nibble alignment with incoming transmission system sublayer stream.
ATMF ACell Delineator ACell Delineator (ATMF) Block integrates circuitry support HCS-based cell delineation non-PLCP based transmission formats. ATMF block accepts serial cell stream from upstream transmission system sublayer entity (such T3-FRMR, E3-FRMR, J2-FRMR Block) performs cell delineation locate cell boundaries. PLCP applications, Acell positions fixed relative PLCP frame, ATMF still performs cell delineation locate cell boundaries. Cell delineation process framing Acell boundaries using header check sequence (HCS) field found Acell header.
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CRC-8 calculation over first octets Acell header. When performing delineation, correct calculations assumed indicate cell boundaries. ATMF performs sequential bit-by-bit, nibble-by-nibble (DS-3 direct mapped), byte-by-byte direct-mapped) hunt correct sequence. This state referred HUNT state. When receiving serial cell stream from upstream transmission system sublayer entity, bit, nibble, byte boundaries determined from location overhead. When correct found, ATMF locks particular cell boundary assumes PRESYNC state. This state verifies that previously detected pattern false indication. pattern false indication then incorrect should received within next DELTA cells. that point transition back HUNT state executed. incorrect found this PRESYNC period then transition SYNC state made. this state synchronization relinquished until ALPHA consecutive incorrect patterns found. such event transition made back HUNT state. state diagram cell delineation process shown Figure Figure Cell delineation State Diagram
rrec
PRESYNC
tive rrec SYNC
values ALPHA DELTA determine robustness delineation method. ALPHA determines robustness against false misalignments errors. DELTA determines robustness against false delineation
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synchronization process. ALPHA chosen DELTA chosen recommended ITU-T Recommendation I.432. These values result maximum average time frame stream carrying Acells directly mapped into information payload. Loss cell delineation (LCD) detected counting number incorrect cells while HUNT state. counter value stored RXCP-50 Count Threshold register. threshold default value which results application detection time G.832 application detection time G.751 application detection time application time 24.8ms, application detection time application detection time counter value zero, output signal asserted every incorrect cell. RXCP-50 Receive Cell Processor Receive Cell Processor (RXCP-50) Block integrates circuitry support scrambled unscrambled cell payloads, scrambled unscrambled cell headers, header check sequence (HCS) verification, idle cell filtering, performance monitoring. RXCP-50 operates upon delineated cell stream. PLCP based transmissions systems, cell delineation performed SPLR. nonPLCP based transmission systems, cell delineation performed ATMF. Framing status indications from these blocks ensure that cells written RXFF while SPLR loss frame state, cells written RXFF while ATMF HUNT PRESYNC states. RXCP-50 descrambles cell payload field using self synchronizing descrambler with polynomial header portion cells optionally descrambled also. Note that cell payload scrambling enabled default S/UNI-QJET required ITU-T Recommendation I.432, disabled ensure backwards compatibility with older equipment. CRC-8 calculation over first octets Acell header. RXCP-50 verifies received using accumulation polynomial, coset polynomial added (modulo received octet before comparison with calculated result required AForum specification, ITU-T Recommendation I.432. RXCP-50 programmed drop cells containing error filter cells based cell header. Filtering according particular GFC, PTI, bits Acell header (the bits must logic programmable through RXCP-50 registers.
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More precisely, filtering performed when filtering enabled when errors found when checking enabled. Otherwise, cells passed regardless error conditions. Cells blocked pattern invalid filtering 'Match Pattern' 'Match Mask' registers programmed with certain blocking pattern. AIdle cells filtered default. Acells, Null cells (Idle cells) identified standardized header pattern 'H00, 'H00, 'H00 'H01 first octets followed valid octet. While cell delineation state machine SYNC state, verification circuit implements state machine shown Figure normal operation, verification state machine remains 'Correction' state. Incoming cells containing errors passed receive FIFO. Incoming single-bit errors corrected, resulting cell passed FIFO. Upon detection single-bit error multi-bit error, state machine transitions 'Detection' state. programmable hysteresis provided when dropping cells based errors. When cell with error detected, RXCP-50 programmed continue discard cells until (where cells received with correct HCS. cell discarded (see Figure 11). Note that dropping cells errors only occurs while ATMF SYNC state. Cell delineation optionally disabled, allowing RXCP-50 pass data bytes receives.
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Figure
Verification State Diagram
ell)
consec utiv incorrect CS's state)
aren ulti-B rror
MODE ingle orrect error cell)
MODE
consec utiv correct CS's (From state)
cutive Last ell)
9.10 RXFF Receive FIFO Receive FIFO (RXFF) provides FIFO management S/UNI-QJET receive cell interface. receive FIFO contains four cells. FIFO provides cell rate decoupling function between transmission system physical layer Alayer. general, management functions include filling receive FIFO, indicating when receive FIFO contains cells, maintaining receive FIFO read write pointers, detecting FIFO overrun underrun conditions. FIFO interface "UTOPIA Level compliant accepts read clock (RFCLK) read enable signal (RENB). receive FIFO output (RDAT[15:0]) tri-stated when RENB logic device address (RADR[4:0]) selected does match this device's address. interface indicates start cell (RSOC) receive cell ava

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