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Data Sheet PMC-980620
Issue
PM73121 AAL1gator AAL1 Processor
PM73121 AAL1gator AAL1 Segmentation Reassembly Processor DATA SHEET
Issue January 1999
Data Sheet PMC-980620
Issue
PM73121 AAL1gator AAL1 Processor
AAL1gator trademark PMC-Sierra, Inc. AT&T registered trademark AT&T ECLIPTEK registered trademark ECLIPTEK Corporation Level registered trademark Level Communications, Inc. SyncFIFO trademark Integrated Device Technology, Inc. MITEL registered trademark MITEL Corporation other brand product names trademarks registered trademarks their respective companies organizations.
NOTE:
AAL1gator device contains SRTS logic that Bellcore holds patent Please refer NOTE page more information regarding Bellcore's SRTS patent.
Data Sheet
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PM73121 AAL1gator
PMC-980620
AAL1 Processor
Long Form Data Sheet
WHAT'S THIS DATA SHEET?
This revision history documents changes that occur from data sheet version next version.
From Version Version Issue Major Changes Corrected Function description section 7.8.12 "R_OAM_QUEUE", page 163. Removed "Preliminary" from headers. Removed suffix from part number Appendix "Ordering Information", page 205. Changed following timing parameters: Interrupt Timing: PROC_INTR Tq(max) from 16.5 Microprocessor Read Cycle: /MEM_CS Tq(max) from 17.7 Microprocessor Read Cycle: Tqmoe(max) from 24.7 Microprocessor Write Cycle: /PROC_ACK Tq(max) from 17.5 Microprocessor Write Cycle: /MEM_CS Tq(max) from 17.7 Microprocessor Write Command Register: /PROC_ACK Tq(max) from 17.5 Transmit Side Interface: RL_SER Th(min) from Transmit Side High-Speed Interface: RL_SER Th(min) from Transmit UTOPIA ATiming: TATM_DATA Tq(max) from 12.7 TUTOPIA SPHY Timing: RPHY_DATA Tq(max) from 12.7 TUTOPIA MPHY Timing: RPHY_DATA Tq(max) from 12.7
Issue
Data Sheet
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PM73121 AAL1gator
PMC-980620
AAL1 Processor
Long Form Data Sheet
From Version
Version Issue
Major Changes Removed 237, P_OUT, from Pinout Table. T_QUEUE_TBL, added clarifications QUEUE_CREDITS AVG_SUB_VALU fields single pointer mode. Changed ItypE3 ItypDS3 Operating Conditions Table. Changed following timing parameters: Interrupt Timing: PROC_INTR Tq(max) from 16.5 Microprocessor Read Cycle: /MEM_CS Tq(max) from 17.7 Microprocessor Read Cycle: Tqmoe(max) from 24.7 Tzsu, Tded, Tzen specified typical, instead minimum maximum. Microprocessor Write Cycle: /PROC_ACK Tq(max) from 17.5 Microprocessor Write Cycle: /MEM_CS Tq(max) from 17.7 Microprocessor Write Command Register: /PROC_ACK Tq(max) from 17.5 Write Cycle: /MEM_WE Twp(min) from 1.3, Twp(max) from +0.3. Receive Side Speed Interface: TL_SER, TL_SIG Tq(max) from Transmit Side Interface: RL_SER Th(min) from Transmit Side High-Speed Interface: RL_SER Th(min) from Transmit UTOPIA ATiming: TATM_DATA Tq(max) from 12.7 TUTOPIA SPHY Timing: RPHY_DATA Tq(max) from 12.7 TUTOPIA MPHY Timing: RPHY_DATA Tq(max) from 12.7 Added Operating Conditions: ITYPE1(max)=420mA ITYPDS3(max)=482mA. Absolute Maximum Ratings section, removed undershoot/ overshoot specification, replaced with absolute maximum voltage range inputs. Moved timing requirements external logic Microprocessor interface from section section 8.11.
Issue
Data Sheet
,VVXH
PM73121 AAL1gator
PMC-980620
AAL1 Processor
Long Form Data Sheet
From Version
Version Issue
Major Changes Changed from WAC-121-A PM73121. Changed from User's Manual Long Form Data Sheet. Deleted references BT_Mode default mode. Added part numbers Figure page Figure page Figure page Figure page 168. Under "R_LINE_STATE Word Format" section page 156, added "Not used UDF-HS mode." R_UNDERRUN R_RESUME field descriptions. Under section 7.11 "Activating Queue Active Line", page 167, changed from "CMD_REG_ATTN" "CSD_REG_ATTN bit".
04/17/98
01/21/98
04/17/98
Changed references from SRTS_PORT SRTS_LINE throughout manual. Added sixth bullet page Under "Potential System Impacts" page added "Hardware Considerations". Deleted first paragraph page Replaced section 3.7.1 "SRTS Receive Side" starting page with section 3.7.1 "Generation TL_CLK" starting page Added section 3.7.1.1 "Recovered Mode" starting page section 3.7.1.2 "Synthesize Nominal Clock" starting page section 3.7.1.3 "Synthesize Clock based SRTS" starting page Table page changed last sentence "SYS_CLK" description read "The maximum frequency MHz. Table page added note description SCAN_TRST" page Under section "RAM Microprocessor Timing" starting page 104, changed first sentence third paragraph from "running 38.88 MHz" "running near maximum speed". first sentence fourth paragraph changed from "(38.88 MHz)" "(40.00 MHz)". Figure page 105, changed SYS_CLK from "38.88 MHz" "40.00 MHz". Table page 105, changed maximum value Number from "7".
Data Sheet
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PM73121 AAL1gator
PMC-980620
AAL1 Processor
Long Form Data Sheet
From Version
Version 04/17/98
Major Changes Under section 6.5.1 "RAM Timing" starting page 103, changed from SRAMs" SRAMs", changed from "data setup time "data setup time ns", changed from "SYS_CLK 38.88 MHz" "SYS_CLK MHz". table after Figure page 119, changed maximum value from "38.89" "40.00". Under "QUEUE_CONFIG Word Format" section starting page 135, added second third bullet note "FRAMES_PER_CELL" description note "BYTES_PER_CELL" description. Under section 7.8.6 "R_CH_TO_QUEUE_TBL", page 148, added sixth sentence Function description. Under section "Board Requirements SRAM Interface" starting page 174, changed third paragraph from "SRAMs must faster" "SRAMS must faster", changed from "data setup "data setup deleted following four sentences. Added section "UDF-HS Mode SRTS-Based Clock Recovery Application DS3" starting page 180, section "Interfacing with Mitel MT8980 Digital Switch", page 182, section "Interfacing with ACell Multiplexer (WAC185-B-X)", page 183, section 8.10 "Jitter Characteristics Clock Synthesis Logic" page 185. first sentence under "Description" page added list lines supported. Under section "Circuit Interface Features" starting page added Dallas Semiconductor part DS2152 second bullet, added Dallas Semiconductor part DS2154 third bullet, deleted Framer (TAC-030-A), deleted Dallas part number DS2180A. Under section "Receive Interface Features" page changed fourth bullet text from ms". Under section "Statistics" starting page deleted text from fourth bullet added fourth sentence first paragraph page Under section "SRTS Transmit Line Interface Clock Configurations" page section 3.1. "SRTS Transmit Side" added NOTE regarding Bellcore's SRTS patent.
01/21/98
10/17/97 (first version WAC-121-A User's Manual)
01/21/98
Data Sheet
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PM73121 AAL1gator
PMC-980620
AAL1 Processor
Long Form Data Sheet
From Version
Version 01/21/98
Major Changes Under section 2.8.3 "Peak Cell Rates Partial Cells", page changed formula TCGTOAM. Under section 3.1.2 "Transmit Signaling Freezing", page added Dallas Semiconductor part numbers DS2152 DS2154. Changed signal name text parentheses Figure page Added step page step page step page Deleted NOTE after step page added more paragraphs. Added section 3.2.1 "Transmit CDV" starting page Under section 3.3.2.1 "Header Construction", page revised fourth sentence. Under section "Transmit UTOPIA Interface Block (TUTOPIA)" starting page added last sentences first paragraph page Under section "Receive Adaptation Layer Processor (RALP)" starting page changed last sentence third paragraph page added text second, sixth, eight bullets page Under section 3.6.2 "Underrun" starting page added text third paragraph page Under section 3.6.3 "Pointer Processing", page added text third paragraph. Under section 3.6.4 "Overrun" starting page added text first third paragraphs. Added step NOTES Figure page Under section 3.6.5 "Counters Sticky Bits", page revised first paragraph. Under section "Receive Frame Transfer Controller (RFTC)" starting page Under section 3.7.1 "SRTS Receive Side" starting page revised first second paragraphs page headings first columns Table page Table page changed "SRTS_PORT(3:0)" "SRTS_LINE(3:0)". Under section "Memory Interface Arbitration Controller (MIAC)" starting page added last sentence third paragraph. Added section "Configuration", page
10/17/97 (first version WAC-121-A User's Manual)
Data Sheet
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PM73121 AAL1gator
PMC-980620
AAL1 Processor
Long Form Data Sheet
From Version
Version 01/21/98
Major Changes Table starting page deleted last sentences from description "RPHY_CLAV" page description "TPHY_CLAV" page Under Figure page changed Maximum value from "12" "13". Under section 6.4.1 "RUTOPIA ALayer Device", page 100, added second paragraph. Table page 105, changed Maximum value number from number from "6". Under Figure page 104, changed Minimum value from "Tp-1" "Tp-2", Twsu from "1", added text second bullet under NOTES. Revised Figure page corresponding table. Under Figure page 107, changed Maximum value Tded from "24" "25" Taed from "19" "20". Under Figure page 109, changed Maximum value Taed from "19" "20". Under Figure page 112, changed Maximum value Tded from "24" "25". Under Figure page 117, changed Maximum value from "12" "16". Deleted section "Boundary Scan" starting page renumbered remaining sections. Under "QUE_CREDITS Word Format" section page 137, changed from "Reserved" "FRAME_REMAINDER" added description. Under "CMDREG Word Format" section page 165, revised description "CSD_ATTN". Added second bullet NOTES page 166. Under section 7.11 "Activating Queue Active Line", page 167, added third bullet NOTES. Added section "External FIFO Application" starting page 171. Under section "External SRTS-Based Clock Recovery Application", page 172, added last paragraphs.
10/17/97 (first version WAC-121-A User's Manual)
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Table Contents
Revision History. What's this Data Sheet? Description
Features Potential System Impacts Hardware Considerations Software Considerations PM73121 Required Board Modifications
System Applications
Replacing Digital Access Cross-connect System (DACS) with ASystem Replacing Multiplexer Level Level (M13) with ASystem Access Multiplexer Application Using AAL1gator Enterprise ASwitch Application.
System Features.
Data Formats 2.1.1 Structured Cell Formats. 2.1.2 Unstructured Cell Formats. Circuit Interface Features. Transmit Interface Features Receive Interface Features. Statistics Interrupts SRTS Transmit Line Interface Clock Configurations. Peak Cell Rates (PCRs) 2.8.1 Peak Cell Rates (PCRs) Structured Cell Formats 2.8.2 Peak Cell Rates (PCRs) Unstructured Cell Formats 2.8.3 Peak Cell Rates Partial Cells. 2.8.3.1 SDF-MF Mode 2.8.3.1.1 Mode 2.8.3.1.2 Mode 2.8.3.2 SDF-FR Mode 2.8.3.3 UDF-ML Mode
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Theory Operations
Transmit Frame Transfer Controller (TFTC) 3.1.1 Transmit Conditioning. 3.1.2 Transmit Signaling Freezing 3.1.3 SRTS Transmit Side Cell Service Decision (CSD) Circuit 3.2.1 Transmit Transmit Adaptation Layer Processor (TALP) 3.3.1 Cell Generation 3.3.2 Data Cell Generation 3.3.2.1 Header Construction 3.3.2.2 Payload Construction. Transmit UTOPIA Interface Block (TUTOPIA). Receive UTOPIA Interface Block (RUTOPIA) Receive Adaptation Layer Processor (RALP) 3.6.1 Handling Data Signaling Bytes Structure 3.6.2 Underrun 3.6.3 Pointer Processing 3.6.4 Overrun 3.6.5 Counters Sticky Bits 3.6.6 Cells. 3.6.7 Interrupt Handling Receive Frame Transfer Controller (RFTC) 3.7.1 Generation TL_CLK 3.7.1.1 Recovered Mode 3.7.1.2 Synthesize Nominal Clock 3.7.1.3 Synthesize Clock based SRTS 3.7.2 Adaptive Clock Operation Memory Interface Arbitration Controller (MIAC) Configuration
Descriptions
Package Diagram Pinout 4.2.1 Pinout Diagram 4.2.2 Pinout Table. Descriptions 4.3.1 UTOPIA Interface Signals. 4.3.2 Memory Interface Signals 4.3.3 T1/E1 Interface Signals 4.3.4 Microprocessor Interface Signals 4.3.5 JTAG Process Test Signals.
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Physical Characteristics Timing Diagrams
Transmit Side Line Interface Timing. Receive Side Line Interface Timing Transmit UTOPIA Timing. 6.3.1 TUTOPIA ALayer Device 6.3.2 TUTOPIA Layer Device Single (SPHY) Mode 6.3.3 TUTOPIA Layer Device Multi-PHY (MPHY) Mode Receive UTOPIA Timing 6.4.1 RUTOPIA ALayer Device 6.4.2 RUTOPIA Layer Device Single-PHY (SPHY) Mode 6.4.3 RUTOPIA Layer Device Multi-PHY (MPHY) Mode Microprocessor Timing. 6.5.1 Timing 6.5.2 Microprocessor Timing 6.5.2.1 Microprocessor Write Cycle Timing. 6.5.2.2 Microprocessor Read Cycle Timing 6.5.2.3 Microprocessor Write Command Register Timing 6.5.2.4 Microprocessor Read Command Register Timing 6.5.3 Microprocessor Holdoff Timing Interrupt Timing. SRTS Timing Miscellaneous Timing 6.8.1 SYS_CLK Timing 6.8.2 RESET Timing 6.8.3 JTAG Timing.
Control Registers Data Structures
General. Initialization Control Registers Summary. Control Register Descriptions 7.4.1 DEVICE_REV. 7.4.2 COMP_LIN_REG 7.4.3 LIN_STR_MODE Transmit Data Structures Summary. Transmit Data Structures Descriptions 7.6.1 P_FILL_CHAR 7.6.2 T_ADD_QUEUE. 7.6.3 T_SEQNUM_TBL 7.6.4 T_COND_SIG 7.6.5 T_COND_DATA
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
7.6.6 RESERVED (Transmit Signaling Buffer). 7.6.7 T_OAM_QUEUE 7.6.8 T_QUEUE_TBL 7.6.9 RESERVED (Transmit Data Buffer). 7.6.10 MATH_TBL Receive Data Structures Summary Receive Data Structures Descriptions 7.8.1 R_OAM_QUEUE_TBL 7.8.2 R_OAM_CELL_CNT 7.8.3 R_DROPPED_OAM_CELL_CNT 7.8.4 R_SRTS_CONFIG 7.8.5 R_CRC_SYNDROME 7.8.6 R_CH_TO_QUEUE_TBL. 7.8.7 R_COND_SIG. 7.8.8 R_COND_DATA 7.8.9 RESERVED (Receive SRTS Queue) 7.8.10 RESERVED (Receive Signaling Buffer) 7.8.11 R_QUEUE_TBL 7.8.12 R_OAM_QUEUE 7.8.13 RESERVED (Receive Data Buffer) CMDREG (Command Register) 7.10 Activating Line After Reset 7.11 Activating Queue Active Line 7.12 Making Changes Active Queue
Application Notes.
Application Interface Circuit with Typical Framer Application External FIFO Application External SRTS-Based Clock Recovery Application Board Requirements SRAM Interface 8.6.1 SRAM with Write Data Setup Clock 8.6.2 SRAM with Write Data Setup CMOS Clock 8.6.3 SRAM with Write Data Setup Clock 8.6.4 SRAM with Write Data Setup CMOS Clock 8.6.5 Layout UDF-HS Mode SRTS-Based Clock Recovery Application Interfacing with Mitel MT8980 Digital Switch Interfacing with ACell Multiplexer (WAC-185-B-X) 8.10 Jitter Characteristics Clock Synthesis Logic 8.10.1 Nominal Clock 8.10.2 Nominal Clock
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
8.10.3 SRTS Clock 8.10.4 SRTS Clock 8.11 Timing Requirements External Logic Microprocessor Interface
Appendix Nomenclature
Definitions. Signal Name Prefixes Numbers Glossary Abbreviation
Appendix References
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
List Figures
AAL1gator Block Diagram Block Diagram AAL1gator Connected Eight Mbit/s Data Streams Block Diagram AAL1gator Connected Mbit/s Data Stream Using AAL1gator Part DACS Replacement Using AAL1gator Part Replacement Using AAL1gator AAccess Multiplexer Application Using AAL1gator Enterprise ASwitch Application Examples Structured Cell Formats Examples Unstructured Cell Formats AAL1gator Block Diagram Capture Signaling Bits Capture Signaling Bits Transmit Frame Transfer Controller SDF-MF Format T_DATA_BUFFER SDF-MF Format T_DATA_BUFFER SDF-FR Format T_DATA_BUFFER SDF-MF Format T_DATA_BUFFER SDF-MF with Signaling Format T_DATA_BUFFER SDF-FR Format T_DATA_BUFFER Unstructured Format T_DATA_BUFFER SDF-MF Format T_SIGNALING_BUFFER Modes) Transmit Side SRTS Support Frame Advance FIFO Operation Payload Generation Transmit UTOPIA Timing (AMode) TUTOPIA Start-of-Transfer Timing (PHY Mode) TUTOPIA End-of-Transfer Timing (PHY Mode) Receive UTOPIA Timing (AMode) RUTOPIA Start-of-Transfer Timing RUTOPIA End-of-Transfer Timing Cell Header Interpretation Fast Algorithm Receive Cell Processing Cell Reception SDF-MF Format R_DATA_BUFFER SDF-MF Format R_DATA_BUFFER SDF-FR Format R_DATA_BUFFER
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
SDF-MF Format R_DATA_BUFFER SDF-MF with Signaling Format R_DATA_BUFFER SDF-FR Format R_DATA_BUFFER Unstructured Format R_DATA_BUFFER SDF-MF Format R_SIG_BUFFER SDF-MF Format R_SIG_BUFFER SDF-MF Format R_SIG_BUFFER SDF-MF Mode with Signaling Format R_SIG_BUFFER Pointer/Structure State Machine Overrun Detection Output Signaling Bits Output Signaling Bits Channel-to-Queue Table Operation Receive Side SRTS Support Direct Adaptive Clock Operation 240-Pin Physical Dimensions Diagram (Part 240-Pin Physical Dimensions Diagram (Part AAL1gator Pinout Diagram Transmit Side Interface Timing Transmit Side Interface Frame Timing Transmit Side Interface Frame Timing Transmit Side High-Speed Interface Timing Receive Side Low-Speed Interface Timing Receive Side Interface Frame Timing Receive Side Interface Timing Receive Side High-Speed Interface Timing Transmit UTOPIA ATiming TUTOPIA SPHY Timing TUTOPIA MPHY Timing Receive UTOPIA ATiming RUTOPIA SPHY Timing RUTOPIA MPHY Timing Write Cycle Timing Read Cycle Timing Microprocessor Write Cycle Timing Microprocessor Read Cycle Timing Microprocessor Write Command Register Timing Microprocessor Read Command Register Timing Microprocessor Holdoff Timing Microprocessor Output Delay Timing Interrupt Timing Low-Speed SRTS Timing
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112.
High-Speed SRTS Timing SYS_CLK Timing Reset Timing JTAG Timing Transmit Receive Data Structures SDF-MF Format T_SIGNALING_BUFFER Math Operation Results Typical Application Typical Quad Framer Interface Typical Application Typical External FIFO Application SRTS-Based Clock Recovery Circuitry Suggested AAL1gator Memory Interface SRTS-Based Clock Recovery Circuit Interfacing with Mitel MT8980 Interfacing Timing with Mitel MT8980 Connecting Eight AAL1gator WAC-185-B-X Nominal Clock with Jitter Attenuator Nominal Clock with Jitter Attenuator Nominal Clock with Jitter Attenuator Nominal Clock with Jitter Attenuator Maximum SRTS Jitter with Jitter Attenuator Maximum SRTS Jitter with Jitter Attenuator SRTS Clock with Jitter Attenuator SRTS Clock with Jitter Attenuator Maximum SRTS Jitter with Jitter Attenuator Maximum SRTS Jitter with Jitter Attenuator SRTS Clock with Jitter Attenuator SRTS Clock with Jitter Attenuator Suggested AAL1gator Memory Interface Address Buffer (FCT244) Timing Bidirectional Data Latch (FCT646) Timing Read Timing Write Timing
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Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Data Formats AAL1gator Modes Support Them Statistics Counters Channel Status Frame Difference AAL1gator Pinout UTOPIA Interface Signals Memory Interface Signals T1/E1 Interface Signals Microprocessor Interface Signals JTAG Process Test Signals Absolute Maximum Ratings Recommended Operating Conditions Operating Conditions Capacitance Signaling Format Mode Signaling Format Mode Transmit Signal Names Corresponding UTOPIA Designations Receive Signal Names Corresponding UTOPIA Designations Receive Signal Names Corresponding UTOPIA Designations Transmit Signal Names Corresponding UTOPIA Designations Control Register Summary Transmit Data Structures Summary Receive Data Structures Summary Delay Values Different Resistors Memory Interface System Clock Operating Conditions Recommended Worst-Case Parameters Suggested Memory Interface Prefixes Associated Functional Layers Standard Abbreviations Ordering Information
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
WAC-121-A
Description
AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator IITM) provides DS1, line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator device. FEATURES
Circuit Interface Features
Provides AAL1 segmentation reassembly eight Mbit/s data streams Mbit/s less data stream. Supports Virtual Channels (VCs) line). Supports structured data format. Supports arbitrary timeslot-to-VC mappings, including alternating timeslots. Provides Common Channel Signaling (CCS) Channel Associated Signaling (CAS) configuration options. Provides per-VC data signaling conditioning both transmit receive directions. Arbitrates 16-bit microprocessor interface 128K SRAM. Supports multicast connections, AMonitoring (AMON), Remote Monitoring (RMON), ACircuit Steering (ACS). Supports adaptive clocking Structured Data Format, Frame-based (SDF-FR), Structured Data Format, Multiframe-based (SDF-MF), Unstructured Data Format, Multiple Line (UDF-ML) modes. Provides ATM-layer PHY-layer UTOPIA interface. Both Single (SPHY) Multi-PHY (MPHY) modes supported. Provides per-VC transmit queueing. Provides calendar queue service algorithm that produces minimal Cell Delay Variation (CDV). Provides supervisory transmit buffer Operations, Administration, Maintenance (OAM), Asignaling. Generates pointers structured data transmission. Provides sequence number sequence number protection generation. Provides partially filled cell generation with length configurable per-VC basis. Generates transmits Synchronous Residual Time Stamp (SRTS) values unstructured modes. Built-in transmit line clock generation based received SRTS values, receive line clock, nominal frequency.
Transmit Cell Interface Features
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
Receive Cell Interface Features
Provides ATM-layer PHY-layer UTOPIA interface. Both SPHY MPHY modes supported. Provides per-VC queues. Provides per-VC tolerance settings. Provides per-VC partially filled cell length settings. Provides supervisory receive queue cells. Verifies corrects sequence numbers accordance with ITU-T Recommendation I.363.1. Processes sequence numbers accordance with "Fast Algorithm", specified ITU-T Recommendation I.363.1. Maintains integrity through individual errored cells lost cells. Takes into account pointer bytes. During underruns, output fixed, pseudorandom, data. Provides processor interrupts cell receptions. Provides multiplexed interface external receive Phase-Locked Loops (PLLs) SRTS clock recovery unstructured modes adaptive clock recovery. Counts invalid Cyclic Redundancy Check (CRC) values sequence numbers. Counts cells dropped cells. Counts data cells transmitted Counts conditioned data cells transmitted Counts cells transmitted line resynchronization Counts cells received, dropped, lost, misinserted Counts cells with incorrect Sequence Number (SN) incorrect Sequence Number Protection (SNP). Counts underrun occurrences Counts overrun occurrences Counts pointer reframes pointer parity errors
Statistics Features
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
Figure shows simple block diagram AAL1gator
Cell Service Decision (CSD)
Input from Line
Transmit Frame Transfer Controller (TFTC) Memory Interface Arbitration Controller (MIAC) Receive Frame Transfer Controller (RFTC)
Microprocessor Control
Transmit Adaptation Layer Processor (TALP)
Transmit UTOPIA Interface Block (TUTOPIA)
Output UTOPIA
External Memory
Output Line
Receive Adaptation Layer Processor (RALP)
Receive UTOPIA Interface Block (RUTOPIA)
Input from UTOPIA
Figure AAL1gator Block Diagram
Figure shows system block diagram AAL1gator connected eight Mbit/s data streams.
UTOPIA Interface SRAM T1/E1 Framer Mbit/s AAL1gator (PM73121) Address/Data Buffer Control Buffers
Microprocessor Strobes
Microprocessor Address Data
Figure Block Diagram AAL1gator Connected Eight Mbit/s Data Streams
Figure shows system block diagram AAL1gator connected Mbit/s data stream.
UTOPIA Interface SRAM DS3/E3 Framer Mbit/s AAL1gator (PM73121) Address/Data Buffer Control Buffers
Microprocessor Strobes
Microprocessor Address Data
Figure Block Diagram AAL1gator Connected Mbit/s Data Stream
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
FEATURES Changes AAL1gator (PM73121) version from WAC-021-C-X version follows: After power-up, setting CMD_REG_ATTN register (refer page 166) causes device revision register loaded with code 121Ah. Supports "Fast Algorithm" method processing SNs, specified ITU-T Recommendation I.363.1. This method maintains integrity through single corrupted cell, single misinserted cell, missing cells determined value field. However, integrity cannot maintained underrun occurs. structured cells used, adjustments missing errored pointer cells considered. Pointer cells will predicted cells that should contain pointers determined ITU-T Recommendation I.363.1. value inserted cells FFh, data, byte conditioned data, pseudorandom data that uses conditioned data replaces with pseudorandom pattern pseudorandom option available UDF-HS mode. pattern used selectable per-VC basis. maximum number cells, (MAX_INSERT) R_SN_CONFIG word six) inserted queue programmable per-queue basis (refer "R_SN_CONFIG Word Format" page 160). There bit, DISABLE_SN R_SN_CONFIG register (refer "R_SN_CONFIG Word Format" page 160), optionally disable processing queue. been added disable automatic dropping first cell received, would normally required ITU-T Recommendation I.363.1 (refer "NODROP_IN_START" page 161). UTOPIA interface operate SPHY MPHY device, addition current Amode. When queue underruns, data, byte conditioned data, pseudorandom data that uses conditioned data replaces with pseudorandom pattern (x18 will automatically inserted. choice selectable DS0. Pseudorandom options available UDF-HS mode. Added following seven counters queue: number dropped cells number lost cells number pointer reframes number underruns
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
number overruns number pointer parity errors number misinserted cells SUPPRESS_TRANSMISSION been added (refer section "IDLE_CONFIG Word Format" page 139) temporarily disable transmission while continuing schedule cells. control bits have been added allow queues SDF-MF line configured SDF-FR mode. (refer "T_CHAN_NO_SIG" page 136) transmit direction, (refer "R_CHAN_NO_SIG" page 157) receive direction. This same setting individual queues SDF-FR mode. mode been added allow 24-frame multiframe instead 16-frame multiframe. this mode, signaling updated every frames. When processing cells, signaling data will appear after bytes data, where number DS0s queue. SRTS code from Field Programmable Gate Array (FPGA) been incorporated into chip each line. There also clock multiplexer that enables AAL1gator generate TL_CLK based either RL_CLK, nominal clock, synthesized clock based received SRTS. R_INCORRECT_SNP counter (refer "R_INCORRECT_SNP Word Format" page 158) been changed conform Circuit Emulation Service (CES) MIB. That cells with incorrect will counted, regardless whether corrected. R_SEQUENCE_ERR counter (refer "R_SEQUENCE_ERR Word Format" page 157) been changed conform MIB. That only transitions from SYNC state OUT_OF_SEQUENCE state counted, specified ITU-T Recommendation I.363.1. Both lines supported same time. scan string current scan order changed. following four pins have been added: PHY_ENABLE (refer page TPHY_ADDR (refer page RPHY_ADDR (refer page TLCLK_OUTPUT_EN (refer page following software fields have been added expanded: COMP_LIN_REG (refer section 7.4.2 "COMP_LIN_REG" starting page 125), added following fields:
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
Long Form Data Sheet
MIXED_MODE_EN SPHY_EN LIN_STR_MODE word (refer section 7.4.3 "LIN_STR_MODE" starting page 126), added following fields: TL_MODE R1_WITH_T1_SIG CLK_SOURCE QUEUE_CONFIG word (refer "QUEUE_CONFIG Word Format" starting page 135), added following field: T_CHAN_NO_SIG CH_TO_QUEUE word (refer "CH_TO_QUEUE Word Format" starting page 148), expanded following fields: RX_COND_H RX_COND_L R_MAX_BUF word (refer "R_MAX_BUF Word Format" page 157), added following field: R_CHAN_NO_SIG Added following nine registers queue: IDLE_CONFIG (refer "IDLE_CONFIG Word Format" page 139) R_SN_CONFIG (refer "R_SN_CONFIG Word Format" page 160) R_DROPPED_CELLS (refer "R_DROPPED_CELLS Word Format" page 161) R_UNDERRUNS (refer "R_UNDERRUNS Word Format" page 162) R_LOST_CELLS (refer "R_LOST_CELLS Word Format" page 162) R_OVERRUNS (refer "R_OVERRUNS Word Format" page 162) R_POINTER_REFRAMES (refer "R_POINTER_REFRAMES Word Format" page 162) R_PTR_PAR_ERR (refer "R_PTR_PAR_ERR Word Format" page 162) R_MISINSERTED (refer "R_MISINSERTED Word Format" page 163) maximum system clock frequency MHz.
Data Sheet PMC-980620
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POTENTIAL SYSTEM IMPACTS
Hardware Considerations
AAL1gator device pin-for-pin compatible with WAC-021-CX. However, following hardware issues items consider. mode requires system clock maintain throughput. Power consumption AAL1gator about higher than WAC-021CX device.
Software Considerations
first issues addressed PMC-Sierra's AAL1gator software Device Control Package. math table modified support lines same time. This required since WAC-021-CX different math table lines than lines. PM73121 configure some lines mode some lines mode. result, only math table required anyone using SDF-MF mode needs math table. counters have been added support MIB. These count values will automatically written into memory previously unused locations. PM73121 calculates buffer overflow data written into memory. WAC-021CX calculates buffer overflow only start cell being written into memory. Because this difference calculating buffer overflow, possible that queue configured with certain MAX_BUF size with WAC-021-CX show overflow with PM73121. algorithm been changed conform with "Fast Algorithm", specified ITU-T Recommendation I.363.1. algorithm more tolerant single errors lost cells slightly different behavior. Typically this transparent users, unless they injecting errors. However, side effect algorithm that first cell received queue always dropped. This issue most applications since there always start-up period before real data contained cells. However, application exists that sensitive loss first cell, control been added disable dropping first cell (refer "NODROP_IN_START" page 161). This defaults off. INCORRECT_SNP counter (refer "R_INCORRECT_SNP Word Format" page 158) been changed conform Management Information Base (MIB). That cells with incorrect field will counted, regardless whether corrected. WAC-021-CX only non-correctable SNPs were counted.)
Data Sheet PMC-980620
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R_SEQUENCE_ERR counter (refer "R_SEQUENCE_ERR Word Format" page 157) been changed conform MIB. That only transitions from SYNC OUT_OF_SEQUENCE counted, specified ITU-T Recommendation I.363.1. revision code chip been changed "121A".
When using AAL1gator will have make software updates take advantage features (refer "New Features" starting page These features require setting control bits writing fields that used WAC-021-CX. default these bits off.
PM73121 Required Board Modifications
PM73121 pin-for-pin backward compatible with WAC-021-CX. allow AAL1gator drop into board developed WAC-021-CX, following hooks need implemented take advantage internal clock synthesis UTOPIA mode.
Internal Clock Synthesis
Provide means tristate TL_CLK PM73121. Provide pads terminate TL_CLK correctly when sourced PM73121. need remove termination used when AAL1gator does source TL_CLK. aware skew issues that arise when AAL1gator sources TL_CLK instead being externally generated, such external clock multiplexer.
NOTE: With respect TL_CLK, AAL1gator timing remains same whether sources clock not. TLCLK_OUTPUT_EN pin. AAL1gator synthesize nominal clock, loop RL_CLK, SRTS generate TL_CLK. select clock type, configure LIN_STR_MODE register (refer "LIN_STR_MODE" starting page 126). Since there period time between reset when this register read, there TL_CLK. account this, TLCLK_OUTPUT_EN high. This will cause RL_CLK looped TL_CLK pins until value been read. Then each line TL_CLK will switch proper value. (Each line different). want clock drive between reset when this register read, TLCLK_OUTPUT_EN low. summary, provide means pull pull down will default pull down internal pull-down resistor.
Data Sheet PMC-980620
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UTOPIA Mode
Provide means pull (PHY_EN) high. will default internal pulldown resistor). using MPHY mode, will /TPHY_ADDR will /RPHY_ADDR. These address pins work like active chip select follow MPHY timing. mode, TAsignals will become RPHY signals (/TATM_EN becomes RPHY_CLAV /TATM_FULL becomes /RPHY_EN). RAsignals will become TPHY signals (/RATM_EN becomes TPHY_CLAV /RATM_EMPTY becomes TPHY_EN).
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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SYSTEM APPLICATIONS essential function Aswitches emulate existing Time Division Multiplexing (TDM) circuits. Since most voice data services currently provided circuits, seamless interworking between Ahas become system requirement. AForum standardized internetworking function that satisfies this requirement Circuit Emulation Service (CES) Specification. AAL1gator direct implementation that service specification silicon, including complex channelized service support CAS.
Replacing Digital Access Cross-connect System (DACS) with ASystem
public network application, DACS replaced with Asystem containing AAL1gator When backbone trunk network changed from ATM, DACSs will probably converted from ATM. existing leased line services provided DACSs must then provisioned with ADACS. this manner, TDM, frame relay, Acircuits provided single network, shown Figure
Service
Fractional Service DACS
Backbone
Digital Data Service
Service Circuit Emulation Card Fractional Service AAL1gator (PM73121) Service ADACS ABackbone
Figure
Using AAL1gator Part DACS Replacement
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Replacing Multiplexer Level Level (M13) with ASystem
second public network application, replaced with Asystem containing AAL1gator M13s often used provide services. Figure shows, these circuits must emulated ADACS AM13 when backbone converted ATM.
Line
Line
Line
Line
QDSX (PM4314)
TQUAD (PM4344)
AAL1gator (PM73121)
ACell Multiplexer (WAC-185-X)
S/UNI-PDH (PM7345)
ADS3 Line
Figure
Using AAL1gator Part Replacement
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Access Multiplexer Application
access multiplexer must allow voice circuits made across single Aservice interface. circuit emulation interface card supports circuit connection Private Branch Exchange (PBX). Figure shows, signaling needed support wide variety legacy PBXs.
Private Branch Exchange (PBX) Circuit Emulation Card
AAL1gator (PM73121)
Workstation
SONET
OC-3 Interface
AAccess Multiplexer
S/UNI-LITE PM5346
AService
Figure
Using AAL1gator AAccess Multiplexer Application
Data Sheet PMC-980620
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Using AAL1gator Enterprise ASwitch Application
Circuit emulation become requirement enterprise switches. Figure shows complete solution Aswitches.
OC-3
S/UNI-LITE (PM5346)
RCMP-200
(PM7323)
ARouting Table
(WAC-187-X)
Interface
ARouting Table
(WAC-187-X)
ASwitch Element S/UNI
(PM7345)
ASwitch Element
(WAC-188-X)
ASwitch Element
(WAC-188-X)
RCMP-200
(PM7323)
ARouting Table
(WAC-187-X)
(WAC-188-X)
S/UNIULTRA
(PM5350)
ASwitch Element
(WAC-188-X)
ASwitch Element
(WAC-188-X)
ASwitch Element
(WAC-188-X)
UTP-PHY
QDSX
(PM4314)
TQUAD
(PM4344)
AAL1gator
(PM73121)
ACell Multiplexer
(WAC-185-X)
ARouting Table
(WAC-187-X)
Figure Using AAL1gator Enterprise ASwitch Application
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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SYSTEM FEATURES AAL1gator provides DS1, DS3, other high-speed line interface access AAL1 Anetwork. uses external SRAM temporary storage data statistical data. device provides microprocessor interface configuration, management, statistics gathering. Atechnology handle different types traffic, including voice video, within same network structure. Voice traffic some kinds video traffic classified traffic. AAL1 defined carrying traffic.
Data Formats
AAL1gator supports data formats described Table
Table Data Formats AAL1gator Modes Support Them Corresponding AAL1gator Mode UDF-ML UDF-HS SDF-MF SDF-FR Signaling Number Lines
Format
Channelization
Unstructured Data Format, Multiple Line Unstructured Data Format, High-Speed Structured Data Format, Multiframe-based Structured Data Format, Frame-based
These modes selectable per-line basis. structured mode, each line support either interfaces. Line also support high-speed that compatible with specified framer. UDFs more appropriate services that require framing structure transport data across network. Unframed point-to-point clear channel examples such services. AAL1gator uses simplified algorithms unstructured data, placing data into appropriate line buffers without regard frames. byte locations used. Cell Service Decision (CSD) credit assigning algorithm (refer section "Cell Service Decision (CSD) Circuit" starting page also simplified. Since there only eight queues, algorithm needs identify only which line requires service. When UDF-HS used line only line monitored activity. Many installed networks, however, look framing structure octet alignment transport data streams. Carriers have large installed bases fractional Digital Data Service (DDS) leased line services that must still supported when backbone over ATM. Many private networks have same support issue; backbone either circuit-switched, both. ATM, then existing switched circuits must migrated onto Abackbone through circuit emulation. Because extensive support Digital Signal Level
Data Sheet PMC-980620
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(DS0s), which Kbit/s channels, AAL1gator ideal vehicle constructing ATM-based DACS other circuit emulation devices. Structured data format suited these types networks underlying services. SDF-MF mode primarily used applications that need pass CAS, which carries ABCD signaling bits. still common many networks. SDF-FR mode, which transfers signaling, also supported. SDF-MF mode, individual queues configured transfer signaling. This equivalent SDF-FR mode given queue.
2.1.1 Structured Cell Formats
Figure shows examples four structured cell formats. partially filled cell examples, partially filled level been payload bytes.
Payload Payload Payload Cell without Pointer Payload Bytes Partially Filled Cell with Pointer Payload Bytes Partially Filled Cell without Pointer Payload Bytes GFC/VPI Pointer Payload
GFC/VPI
GFC/VPI
GFC/VPI
Pointer
Payload Payload
Payload
Payload
Payload
Payload
Cell with Pointer Payload Bytes
Figure
Examples Structured Cell Formats
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2.1.2
Unstructured Cell Formats
Figure shows unstructured cell formats. partially filled cell, partially filled level been payload bytes.
GFC/VPI Payload Payload Payload Cell without Pointer Partial Cell without Pointer Payload Payload
GFC/VPI
Payload
Figure
Examples Unstructured Cell Formats
Circuit Interface Features
Provides convenient interface following line circuit types: eight framers (PMC-Sierra part number PM4341A T1XC Base-2part number UGA-360). eight framers (PMC part number PM6341 E1XC Base-2 part number UGA-510). quad framers (PMC part number PM4344 TQUAD). quad framers (PMC part number PM6344 EQUAD). Framer (EAC-030-X)-compatible device (clear channel). Supports following VCs: channelized T1/E1 line line T1). eight multiple-line unstructured data format (UDF-ML mode). DS3. Compatible with AForum Circuit Emulation Service (CES) standard (refer Appendix "References", page 203).
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Allows outgoing Virtual Path Identifier (VPI)/Virtual Channel Identifier (VCI) value each Maps selectable 8-bit field into possible receive queues. Provides count integrity replacing lost Service Data Units (SDUs). Allows combination timeslots within T1/E1 line mapped VCI. Supports arbitrary rates Mbit/s aggregate throughput. Provides per-line CCS/CAS configuration option. Individual lines configured lines configured signaling rates. Provides transmit data signaling conditioning Provides receive signaling freezing underrun, overrun, pointer mismatch errored cells. Provides receive data signaling conditioning Provides SRTS generation collection internal clock synthesizer drive external receive PLLs unstructured data formats. Provides 16-bit microprocessor interface 128K SRAM external device. Provides statistics interrupts microprocessor.
Transmit Interface Features
AAL1gator accepts deframed data serial stream from multiple external deframer devices. AAL1gator then stores data external SRAM, creates AAL1 Acells from data. AAL1gator allows configurations line) that transmit from DS0s Kbit/s channels) within line with arbitrary sequential mapping (including alternating timeslots). queues serviced with calendar scheduling mechanism. transmit side transmit queue controller also supports transmission cells generated microprocessor. addition, variety statistics maintained 16-bit counters. Other transmit interface features include: Provides per-VC transmit queuing. Provides calendar queue service algorithm that produces minimal CDV. Provides layer UTOPIA interface. side either SPHY MPHY. Provides supervisory transmit buffer OAM/signaling with Cyclic Redundancy Check-10 (CRC-10) generation. Generates sequence numbers sequence number protection bits. Provides partially filled cells with lengths configured per-VC basis.
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Supports Synchronous Residual Time Stamp (SRTS) unstructured data formats. transmit interface generates 4-bit SRTS code that reflects difference between network clock transmitting service clock. enabled, this SRTS code inserted into Convergence Sublayer Indication (CSI) cells with sequence numbers. Provides data signaling conditioning per-VC basis. Provides 2-cell UTOPIA First-In, First-Out (FIFO). Transmit delay defined following three components: time schedule cell, time build cell, time transmit cell. time schedule cell from structured data from times unstructured data. time seconds) build cell with full payload approximately divided bps). time send cell depends number cells queued transmission, amount traffic being inserted microprocessor, speed which cells accepted device connected UTOPIA transmitter. Once payload available, each cell takes about prepare. Provides optionally generated transmit line clock based received SRTS values, looped RL_CLK, synthesized nominal clock.
Receive Interface Features
When cells arrive, AAL1gator places them multiframe buffer based channel allocation. cells then transmitted line interface proper time. Other receive interface features include: Provides layer UTOPIA interface. side either SPHY MPHY. Provides per-VC queues. Provides receive buffer using signaling), receive buffer receive buffer receive buffer DS3. Provides per-VC Cell Delay Variation Tolerance (CDVT) setting using signaling); provides per-VC CDVT setting increments Provides CDVT setting CDVT setting DS3. Provides overrun underrun protection. Provides pointer misalignment protection. Receives, verifies, corrects sequence numbers accordance with ITU-T Recommendation I.363.1. (refer Appendix "References", page 203). Processes sequence numbers accordance with I.363.1 "Fast Algorithm" (refer Appendix "References", page 203). Sequence number processing optionally disabled queue basis.
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Provides 256-cell receive queue. Provides processor interrupt cell reception. Provides sample SRTS CDVT setting. Supports SRTS collecting queueing SRTS values, calculating local SRTS value derived from local transmit clock local network reference clock, driving difference between incoming value local value multiplexed interface. This difference then used drive eight external digital analog PLLs. Application support available 8-line SRTS/adaptive digital frequency synthesizer, which added externally. Clock synthesis logic, internal chip, optionally configured synthesize TL_CLK based received SRTS values. modes except UDF-HS, supports adaptive clocking calculating receive frame difference providing external adaptive digital frequency synthesizer. Provides 2-cell UTOPIA FIFO. Defines receive delay primarily following components: buffering handle internal cell processing time. internal cell processing time less than
Statistics
AAL1gator gathers statistical information transmitted received cells. These statistics maintained 16-bit counters (which implemented rollover counters never cleared) external memory. Table lists provided statistics counters.
Table Counter Name Number Counters Statistics Counters Counter Description Count cells received. Count cells received dropped lack space receive FIFO. Count number occurrences when and/or parity correct. Both correctable noncorrectable errors reported. Count errors. Counts transitions from SYNC OUT_OF_ SEQUENCE. Count billable data cells received from UTOPIA interface. Count cells that were received dropped. Count number underruns this queue account lost cells. Count cells detected lost this queue. Count overruns this queue.
R_OAM_CELL_CNT R_DROPPED_OAM_CELL_CNT R_INCORRECT_SNP
R_SEQUENCE_ERR R_CELL_CNT R_DROPPED_CELLS R_UNDERRUNS R_LOST_CELLS R_OVERRUNS
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Statistics Counters (Continued) Counter Description Count pointer reframes. Count pointer parity errors. Count misinserted cells. Count billable data cells transmitted UTOPIA interface. Counts data conditioned cells transmitted UTOPIA interface. Counts cells sent because line resynchronization, device UDF-HS mode, because TX_ACTIVE set. Also SUPPRESS_TRANSMISSION set, cells sent will increment this counter.
Number Counters
R_POINTER_REFRAMES R_PTR_PAR_ERR R_MISINSERTED T_CELL_CNT T_COND_CELL_CNT T_SUPPRESSED_CELL_CNT
Sticky bits following events also maintained per-queue basis memory (refer "R_ERROR_STKY Word Format" page 158): cell received while queue underrun. Receive overrun: cell received, causing maximum buffer depth exceeded. This event causes forced underrun condition. resume function occurred: cell received placed receive buffer causing underrun condition. cell dropped accordance with Recommendation I.363.1 "Fast Algorithm". This event causes forced underrun condition. cell dropped because forced underrun. cell dropped because blank allocation table disabled receiver. cell received. cell dropped because valid pointer found while queue underrun condition. valid pointer received. errored pointer received (parity check failed). SRTS resume occurred. cell received while SRTS queue underrun. cell dropped because pointer mismatch occurred causing forced underrun condition. AAL1gator sets status bits every time detects events listed previously. microprocessor clears status bits after recognizes event. Because these bits will polled rate, relative their occurrence, possible determine exact number
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occurrences each type event. count required, counters should used instead. status bits receive error conditions each queue maintained single-data word. When detected, this single-data word should cleared immediately. NOTE: events occur between read status bits write clear status bits, status bits should used statistics gathering only.
Interrupts
AAL1gator asserts interrupt line whenever cell arrives interrupt mask deasserted. interrupt cleared asserting OAM_INT_MASK asserting CLR_ RX_OAM_LATCH. Refer section "CMDREG (Command Register)" page 165.
SRTS Transmit Line Interface Clock Configurations
AAL1gator provides following transmit line interface clock configurations per-line basis: Drives TL_CLK(i) with looped-back RL_CLK(i). Drives TL_CLK(i) with SRTS-derived clock. Drives TL_CLK(i) with nominal T1/E1 clock 1.544 2.048 MHz. Accepts TL_CLK(i) input. NOTE: AAL1gator uses Bellcore's patented SRTS clock recovery technique. Refer NOTE page additional information regarding Bellcore's SRTS patent.
AAL1gator also provides following external TL_CLK generation options through multiplexed SRTS output port. These options used when AAL1gator accepts CLK(i) input: AAL1gator drives SRTS information SRTS port. external circuit this information synthesize SRTS-based TL_CLK. (Provided backward compatibility with WAC-021-C-X.) AAL1gator drives adaptive clocking information SRTS port. external circuit this information synthesize adaptive (based receive-buffer-centering) TL_CLK.
Peak Cell Rates (PCRs)
purposes discussion, following information assumed: Full cells used, numbers line, SYS_CLK 38.88 MHz.
2.8.1 Peak Cell Rates (PCRs) Structured Cell Formats
cells second where (assuming completely filled cells).
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Each AAL1 cell either bytes, depending upon whether cell contains structure pointer.
Peak Cell Rates (PCRs) Unstructured Cell Formats
2.8.2
4,107 cells second (assuming bytes each AAL1 cell). 5,447 cells second (assuming bytes each AAL1 cell). 118,980 cells second (assuming bytes each AAL1 cell). 91,405 cells second (assuming bytes each AAL1 cell). lines same rate, aggregate 53,191 cells second multiple-line unstructured data format (assuming bytes each AAL1 cell). lines same rate, aggregate 46,542. 1,000 cells second cells. This rate cells calculated basis four cells second Transmitting receiving cells this rate consumes microprocessor accesses.
Peak Cell Rates Partial Cells
2.8.3
Partial Cells used minimize amount delay required assemble cell. However, amount overhead required same amount data increases when partial cells used. This overhead increases number data bytes cell decreases. following equations used determine when partial cells used. First, maximum average cell generation time (MACGT) calculated. MACGT value equal maximum average number cycles generate cell, times length clock cycle. Second, maximum average cell generation time multiplied number cells required second give total cell generation time (TCGT). following equations given different modes operation. Each equation calculated per-queue basis. queues configured same, then total queue multiplied number queues. Otherwise, calculations each queue needs totaled. must less than one. following variables used: data bytes cell number timeslots assigned queue length clock cycle NOTE: cells used, following equation cells:
TCGTOAM (maximum number cells second)
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2.8.3.1
SDF-MF Mode
MACGTSDFMF [208
2.8.3.1.1 Mode TCGTSDFMFE1 MACGTSDFMF (8000
queues SDF-MF same size, timeslots used, SYS_CLK= 38.88 MHz, then minimum number bytes cell
2.8.3.1.2 Mode TCGT SDFMFT1 MACGTSDFMF (8000
queues SDF_MF same size, timeslots used, SYS_CLK= 38.88 MHz, then minimum number bytes cell
2.8.3.2 SDF-FR Mode
MACGTSDFFR [202
TCGTSDFFR MACGTSDFFR (8000
mode, queues same size, timeslots used, SYS_CLK= 38.88 MHz, then minimum number bytes cell mode, queues same size timeslots used SYS_CLK= 38.88 MHz, then minimum number bytes cell
2.8.3.3 UDF-ML Mode
MACGTUDFML [202
TCGTUDFML MACGTUDFML (8000
queues unstructured lines used SYS_CLK= 38.88 MHz, then minimum number bytes cell
TCGTSDFMFE1 TCGT SDFMFT1 TCGTSDFFR TCGTUDFML queues TCGTOAM must less than second.
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THEORY OPERATIONS AAL1gator divided into following major blocks, which explained this section: Transmit Frame Transfer Controller (TFTC) block Cell Service Decision (CSD) block Transmit Adaptation Layer Processor (TALP) block Transmit UTOPIA Interface (TUTOPIA) block Memory Interface Arbitration Controller (MIAC) block Receive Frame Transfer Controller (RFTC) block Receive Adaptation Layer Processor (RALP) block Receive UTOPIA Interface (RUTOPIA) block Figure shows block diagram AAL1gator sequence events used segment reassemble data.
AAL1gator (PM73121)
Cell Service Decision (CSD)
Input from Line
Transmit Frame Transfer Controller (TFTC)
Transmit Adaptation Layer Processor (TALP) Memory Interface Arbitration Controller (MIAC) Transmit UTOPIA Interface Block (TUTOPIA)
Output UTOPIA
External Memory
Output Line
Receive Frame Transfer Controller (RFTC)
Microprocessor Control
Receive Adaptation Layer Processor (RALP)
Receive UTOPIA Interface Block (RUTOPIA)
Input from UTOPIA
Figure
AAL1gator Block Diagram
TFTC stores line data into memory, bits time. When TFTC finishes writing complete frame into memory, notifies
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frame completion writing line frame number into FIFO.
checks frame-based table queues having sufficient data generate cell. each queue with enough data generate cell, schedules next cell generation occurrence table. commands TALP generate cell from available data each ready queues identified step TALP generates cell from data signaling buffers writes cell into UTOPIA FIFO. TUTOPIA interface transmits cells UTOPIA port. RUTOPIA interface receives cell from UTOPIA port. RALP performs pointer searches, checks overrun underrun conditions, detects mismatches, checks cells, extracts line data from cells, places data into receive buffer. RFTC plays receiver buffer data onto lines. MIAC provides arbitration memory transaction requests various processes.
Transmit Frame Transfer Controller (TFTC)
TFTC accepts deframed data from external framer device. structured data, TFTC uses synchronization signals (RL_FSYNC RL_MSYNC) supplied framer perform serial-to-parallel conversion incoming data then places this data into multiframe buffer order which arrives. rising edge RL_FSYNC indicates beginning frame, rising edge MSYNC indicates beginning multiframe. TFTC will realign when edge seen these signals. necessary provide edge beginning every frame multiframe. AAL1gator reads signaling during last frame every multiframe. mode, AAL1gator reads signaling 24th frame multiframe. mode, AAL1gator reads signaling 16th frame multiframe. special case mode exists that permits signaling with framing. Normally multiframe consists frames timeslots, where signaling changes multiframe boundaries. When E1_WITH_T1_SIG LIN_STR_MODE line mode, TFTC will multiframe consisting frames timeslots. this mode, AAL1gator reads signaling 24th frame multiframe. AAL1gator reads signaling nibble each channel when reads last nibble each channel's data. Figure page example frame. Figure page example frame.
Data Sheet PMC-980620
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Line Signals During Last Frame Multiframe
RL_SER (timeslots
ABCD ABCD RL_SIG XXXX ABCD XXXX Channel XXXX Channel
Channel
ABCD ABCD ABCD XXXX Channel XXXX Channel XXXX Channel
XXXX indicates signaling ignored
Figure
Capture Signaling Bits
Line Signals During Last Frame Multiframe
RL_SER
(timeslots
ABCD ABCD RL_SIG XXXX ABCD XXXX Channel XXXX Channel
Channel
ABCD ABCD ABCD XXXX Channel XXXX Channel XXXX Channel
XXXX indicates signaling ignored
Figure
Capture Signaling Bits
NOTE: AAL1gator treats timeslots identically. Although data streams contain timeslots channel data timeslots control (timeslots 16), data signaling timeslots stored memory sent received cells.
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Unstructured data received without regard byte alignment data within frame placed frame buffer order which arrives. Figure shows basic components TFTC.
Line External Framer Line
ATTN0
Receive Line Interface
DATA0
Line Encoder Line Number
Line External Framer
Line
ATTN7
Channel Pair Number Line-to-Memory Interface Data
Receive Line Interface
DATA7
Figure
Transmit Frame Transfer Controller
receive line interface primarily serial-to-parallel converter. Serial data, which derived from RL_SER pin, supplied shift register. shift register clock RL_CLK input from external framer. When data been properly shifted transferred 2-byte holding register internally derived channel clock. This clock derived from line clock framing information. channel clock also informs line-to-memory interface that data bytes available from line. When bytes available, line attention signal sent line encoder block. However, because channel clock asynchronous input line-to-memory interface, passed through synchronizer before supplied line encoder. Since there eight potential lines each them provides channel clock, they synchronized before being submitted line encoder. TFTC accommodates Super Frame (SF) mode treating like Extended Super Frame (ESF) format. TFTC ignores every other frame pulse captures signaling data only last frame multiframes. formatting data signaling buffers highly dependent operating mode. Refer section 7.6.6 "RESERVED (Transmit Signaling Buffer)" page more information transmit signaling buffer.
Data Sheet PMC-980620
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Figure shows format transmit data buffer ESF-formatted data lines that SDF-MF mode.
Frame Buffer Number
DS0s
Figure
SDF-MF Format T_DATA_BUFFER
Figure shows format transmit data buffer SF-formatted data lines that SDF-MF mode.
Frame Buffer Number
DS0s
Figure
SDF-MF Format T_DATA_BUFFER
Data Sheet PMC-980620
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Figure shows format transmit data buffer data lines that SDF-FR mode.
Frame Buffer Number DS0s
Frame Frame
Frame
Frame Frame
Frame
Frame Frame
Frame
Frame Frame
Frame
Figure SDF-FR Format T_DATA_BUFFER
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Figure shows format transmit data buffer data lines that SDF-MF mode.
Frame Buffer Number DS0s
Figure SDF-MF Format T_DATA_BUFFER
Figure shows format transmit data buffer data using signaling, lines that SDF-MF mode.
DS0s Frame Buffer Number
Figure SDF-MF with Signaling Format T_DATA_BUFFER
Data Sheet PMC-980620
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Figure shows format transmit data buffer data lines that SDF-FR mode.
Frame Buffer Number DS0s Frame Frame Frame Frame
Figure SDF-FR Format T_DATA_BUFFER
Figure shows format transmit data buffer lines that UDF-ML mode.
Frame Buffer Number
Data Bits 256-Bit Internal Frame 256-Bit Internal Frame 256-Bit Internal Frame
Figure
Unstructured Format T_DATA_BUFFER
Data Sheet PMC-980620
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Figure shows contents transmit signaling buffer different signaling modes.
Word
CH31
CH30
NOTE: upper nibble each byte format uses word addresses
Figure
SDF-MF Format T_SIGNALING_BUFFER Modes)
3.1.1
Transmit Conditioning
T_COND_DATA structure allows conditional data defined per-DS0 basis. structure T_COND_SIG allows conditioned signaling defined per-DS0 basis. COND T_QUEUE_TBL allows cell building logic (described section "Transmit Adaptation Layer Processor (TALP)" page directed build cells from conditioned data signaling. TX_COND per-queue basis.
3.1.2 Transmit Signaling Freezing
Signaling freezing required function when transporting CAS. This function holds signaling unchanged when incoming line fails. PMC-Sierra framers provide this function. framer used that does support signaling freezing, this function must provided externally.
3.1.3 SRTS Transmit Side
NOTE: AAL1gator uses Bellcore's patented SRTS clock recovery technique. Refer NOTE page additional information regarding Bellcore's SRTS patent.
Data Sheet PMC-980620
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transmit side supports SRTS only unstructured data formats per-line basis. SRTS support requires input reference clock, N_CLK. input reference frequency defined 155.52/2^n MHz, where chosen such that reference clock frequency greater than frequency being transmitted, less than twice frequency being transmitted RL_CLK N_CLK RL_CLK). implementation, input reference clock frequency must 2.43 MHz. transmit side accept reference clock speed MHz, which required applications. Figure page shows process implemented each line enabled SRTS, regardless reference frequency. resulting 4-bit SRTS code then inserted into numbered cells that line. line does supply SRTS, then bits 3008 divider number data bits eight cells 47). divider aligned first cell generation after reset resynchronization cell generation process.
Server Clock Frequency RL_CLK
4-bit SRTS Code
Divide 3008
Latch
4-Bit Latch
Bits
Reset Cell Generation Resync
Bits Input Reference Clock Frequency N_CLK (For T1/E1, 2.43 MHz. 77.76 MHz.)
4-Bit Counter
Figure Transmit Side SRTS Support
Cell Service Decision (CSD) Circuit
circuit determines which cells sent when. determines this implementing Transmit Calendar tables. When TALP builds cell, circuit performs complex calculation using credits determine frame which next cell from that queue should sent. circuit schedules cell only when cell built TALP. SUPPRESS_ TRANSMISSION IDLE_CONFIG word set, then cell scheduled, however, cell transmitted. following steps well Figure page describe circuit schedules cells TALP build. Once TFTC writes complete frame into external memory, writes line number frame number this frame into FR_ADVANCE_FIFO. circuit reads line-frame number pair from FR_ADVANCE_FIFO uses index into Transmit Calendar. Transmit Calendar composed eight-bit tables, line. Each table consists entries, frame buffer. Each entry consists bits, queue. each indexed entry Transmit Calendar, will schedule frame which next cell built corresponding queue, notify TALP
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that enough data available build cell that queue. circuit processes queues from Transmit Calendar entry starting with lowest queue number proceeding highest. processing steps follows: circuit obtains QUE_CREDITS, subtracts average number credits cell from average number credits, AVG_SUB_VALU, number credits that will spent sending current cell. structured lines, average number credits cell 46-7/8. unstructured lines, average number credits cell Next, circuit computes frame location next service subtracting remaining credits from divides result number channels, NUM_CHAN, dedicated that queue. result frame differential. then adds this frame differential present frame location determine frame number next frame which TALP build cell. circuit then sets corresponding entry Transmit Calendar writes QUEUE_ CREDITS. circuit then adds credits back credit total frame increment number. number credits equal frame differential computed earlier, multiplied number channels that queue. Once queue identified requiring service, identity written NEXT_SERV location. circuit obtains next queue that frame repeats steps through circuit continues this process until there more active queues that frame. After servicing queues that frame, circuit advances next active line located line queue. there active lines, circuit returns idle state wait next line request service.
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Figure shows assigns credits determine which frames cells should sent.
Frame Boundaries
TFTC FR_ADVANCE_FIFO TFTC sees frame advance records this FR_ADVANCE_FIFO reads frame advances determines cells sent NEXT_ SERV
RL_SER(0)
RL_FSYNC(0)
RL_SER(1)
RL_FSYNC(1)
Figure Frame Advance FIFO Operation
following example calculations circuit performs. This example assumes structured line with four channels allocated queue. TFTC writes Line Frame FR_ADVANCE_FIFO. circuit determines queue which cell ready finding Transmit Calendar. this example, queue number 100. circuit reads number credits queue number 100. number credits always greater than because ready service. this example, QUE_CREDITS 59.375. circuit subtracts AVG_SUB_VALU, average number credits spent cell. (Remember: structured lines, average number credits cell 46-7/8. unstructured lines, average number credits cell 47.) Credits 59.375 46.875 Credits 12.5 frame differential next service computed from number credits needed exceed NUM_CHAN, number channels allocated frame. 12.5 34.5 34.5 8.625 Round 8.625 frame differential Therefore, next cell will sent nine frames ahead current cell. Next frame present frame number
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circuit computes number credits those nine frames adds result total. credits QUE_CREDITS 12.5 48.5 queue line SDF-MF mode, makes signaling adjustment QUE_CREDITS before writing this value memory. queue SDF-MF mode, signaling adjustment made QUE_CREDITS calculated Step written memory.) calculation determines number signaling bytes structure, then generates average number signaling bytes inserted into cells frame, finally multiplies this average number frame differential adjust QUE_CREDITS. converts frame differential from units frames units one-eighth multiframes. performing this calculation, also uses FRAME_REMAINDER value from QUE_CREDITS location T_QUEUE_TBL. This example assumes that FRAME_ REMAINDER from previous calculation this queue. Frame differential eighths multiframe) (frame differential FRAME_ REMAINDER) Frame differential eighths multiframe) (frame differential FRAME_ REMAINDER) Frame differential three-eighths multiframe, remainder
writes remainder this division into FRAME_REMAINDER location next calculation this queue. calculates signaling credit adjustment multiplying frame differential expressed eighths multiframe number signaling bytes structure. Number signaling bytes structure channels bytes channel bytes multiframe Signaling adjustment three eighths 0.75 bytes Then adds signaling credit adjustment total writes result memory, preparation next service this queue. QUEUE_CREDITS 48.5 0.75 49.25 bytes Unstructured lines same procedure. case unstructured lines, number channels allocated queue Because there never pointer, average number credits spent cell always
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3.2.1
Transmit
following items affect transmit CDV: Cell scheduling, Contention with other cells scheduled same time, Actual cell build time, UTOPIA contention. scheduler resolution other words, works frame-based clock determine whether cell should sent during current frame. Therefore, ideal rate cell transmission multiple there will CDV. scheduler will never more than CDV. example, single queue with signaling using full cells, will need build cell every frames. Therefore, cell will scheduled every frames, scheduler will CDV. However, signaling were added single queue, extra byte that occurs every bytes (assuming mode) requires compensation. this case, cell will sent every frames. Therefore, there will scheduler.
Only cell built time. Thus multiple queues scheduled send cells during same frame, additional will incurred. Since takes approximately build cell, each cell that waited adds delay. When multiple queues scheduled send cells same time, cells will built sequential order, starting with going 256. Therefore, system that will adding dropping queues, higher number queues will experience more than lower number queues, depending many queues active time, scheduled within same frame. Theoretically, possible have queues scheduled same time, however, this will occur adequate steps taken. Minimize clumping following actions: queues time (PMC-Sierra's driver does this automatically). When queues added same time with same configuration, they clumped together. adding queues time, clumping avoided cell scheduling points evenly distributed. Also, queues only added frame Since transmit buffer frames (for frames (for T1), this equates (for (for T1). Queues should added more than apart (for (for prevent them from being clumped together. Avoid configurations that will require sending cell every frames where integer divi-
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(for (for T1). these configurations queues will always scheduled same frame. Therefore, even these queues added different times they will still scheduled same time. Staggering clocks different lines also help. Since cells scheduled when frame completes, staggering lines offset frame completion point different lines with respect each other.
actual build time cell depends microprocessor activity contention with other internal state machines AAL1gator memory bus. Therefore there will some minor that added cell basis, based current microprocessor/memory traffic. This usually less than very noticeable. there backpressure UTOPIA bus, cells will able sent which also causes CDV.
Transmit Adaptation Layer Processor (TALP) Cell Generation
3.3.1
When cell transmission requested, sent first available opportunity. Transmit cells have higher priority than cells scheduled circuit. Because this, care should taken ensure that cells overwhelm transmitter such extent that data cells starved adequate opportunities. rate cells must limited AAL1gator maintain maximum data rate. send cell, Supervisory Processor (SP) writes supervisory cells into dedicated cell buffers located external memory. When cell assembled buffer, must appropriate command register (refer section "CMDREG (Command Register)" page 165). TALP sends cell soon possible, then clears appropriate attention indicate requested cell been sent. requests both cells active time command register read AAL1gator cell will always sent because assigned higher priority. Therefore, control order cell transmission, should only attention time wait until cleared before setting other attention bit. cells optionally have 48-byte payload CRC-10 protected. This accomplished circuit that monitors cell sent TUTOPIA computes fly. then substitutes 10-bit resultant CRC, preceded last bytes cell.
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3.3.2
Data Cell Generation
TALP receives request send CSD-scheduled data cell there cell requests pending, will soon free. will look predefined Aheader from T_QUEUE_TBL (refer section 7.6.8 "T_QUEUE_TBL" page 134). will then obtain sequence number that queue from memory, structure pointer necessary. After these bytes written TUTOPIA interface, TALP will then data signaling frame buffers, locate data bytes correct channels, write them correct order UTOPIA interface. This cell building process described more detail following section.
3.3.2.1 Header Construction
entire header fixed queue. Headers maintained memory, queue. These headers include Header Error Check (HEC) character fifth byte. queue should deactivated during header replacement prevent cells from being constructed with incorrect header values. queue paused setting SUPPRESS_TRANSMISSION IDLE_ CONFIG register. Emissions still scheduled, just transmissions suppressed. cells that suppressed, T_SUPPRESSED_CELL_CNT incremented.
3.3.2.2 Payload Construction
Payload construction most complex task TALP circuit performs. signaling requirements define much process, which follows: first byte payload provided lookup into T_QUEUE_TBL. This first byte consists bit, 3-bit sequence number, 4-bit sequence number protection field. depending SRTS pointer requirements. sequence number incremented every time cell sent same VPI/VCI. line structured modes, structure pointer needed even-numbered cells. TALP inserts structure pointers according following rules: Only pointer inserted each 8-cell sequence. pointer inserted first possible even-numbered cell every 8-cell sequence. pointer value inserted when structure starts byte directly after pointer itself. pointer value inserted when structure coincides with 93-octet block AAL-user information. dummy pointer value inserted cell number start-of-structure end-of-structure occurs within 8-cell sequence. This algorithm supplies constant number structure pointers and, therefore, data bytes, regardless structure size. pointer inserted seventh byte location cell. force TALP build structure consisting single with signaling nibble
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pointer, T_CHAN_UNSTRUCT QUEUE_CONFIG word T_QUEUE_ TBL. TALP fills rest cell payload with data and/or signaling information. CHAN_ALLOC table (refer section 7.6.8 "T_QUEUE_TBL" page 134) determines which channels dedicated which queue. set, channel represented that assigned that queue. TALP successively writes data from marked channels into UTOPIA interface. queue-based parameter, BYTES_PER_CELL, decides when enough payload bytes have been obtained. this number fewer than then remaining bytes cell loaded with P_FILL_CHAR. This implies that because presence structure pointer, number fill bytes will constant structured data queues. structure used signaling determined mode line value E1_WITH_T1_SIG. Normally signaling structure will follow mode line. However, line mode E1_WITH_T1_SIG set, then signaling structure used. This means that single DS0, signaling inserted after data bytes instead after data bytes. data sent from data queue, this process continues byte-by-byte while updating pointers counters until following occurs: cell complete. last data byte last frame multiframe been set. When signaling information sent, data obtained from signaling locations multiframe, with help channel allocation table (T_CHAN_ALLOC). This process proceeds byte-by-byte until following occurs: cell complete. signaling nibbles channels assigned queue have been sent.
Data Sheet PMC-980620
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Figure shows example payload generation process.
TFTC writes bytes pairs into T_DATA_BUFFER RL_SER TALP builds (segments) cell from T_DATA_BUFFER. this case from DS0s
Channel
T_DATA_BUFFER
Frames
Figure
Payload Generation
Transmit UTOPIA Interface Block (TUTOPIA)
TUTOPIA block (shown Figure page conveys cells emitted TALP UTOPIA interface. Depending value PHY_ENABLE input (refer "PHY_ ENABLE" page 81), UTOPIA interface will either Aside (controls write enable signal) side (controls cell available signal). PHY-side device, TUTOPIA block also SPHY device MPHY device (refer Appendix "References", page UTOPIA Level specification version), depending value SPHY_EN COMP_LIN_REG. SPHY_EN will default off, UTOPIA interface being used MPHY environment, there will contention while device software reset. Amode, TUTOPIA block sources TATM_DATA(7:0), TATM_SOC, /TATM_EN while receiving /TATM_FULL. Start-Of-Cell (SOC) indication generated coincident with first byte each cell that transmitted TATM_DATA. TATM_DATA TATM_SOC driven times. write enable signal indicates which clock cycles contain valid data UTOPIA bus. device will assert /TATM_EN signal until full cell send.
Data Sheet PMC-980620
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TUTOPIA responds /TATM_FULL signal. signal asserted, TUTOPIA data send, will asserting /TATM_EN. /TATM_FULL asserted, then data flow will paused exactly clock cycles, until /TATM_FULL signal allows cell completed. timing diagram Figure page
TATM_CLK(i) /TATM_FULL(i) /TATM_EN(o) TATM_SOC(o) TATM_DATA(o)
Figure Transmit UTOPIA Timing (AMode)
mode, TUTOPIA block sources RPHY_DATA(7:0), RPHY_SOC, RPHY_ CLAV, while receiving /RPHY_EN. indication generated coincident with first byte each cell that transmitted RPHY_DATA. mode, RATM_DATA RATM_SOC signals driven only when valid data being sent; otherwise they tristated. /RPHY_ADDR input used only MPHY mode. cell available (RPHY_CLAV) signal indicates when device complete cell send. SPHY mode, RPHY_CLAV always driven. MPHY mode, output enable this signal /RPHY_ADDR input delayed cycle. MPHY mode, /RPHY_ADDR tied address signals RPHY_CLAV driven only when polled. UTOPIA standard defines 5-bit address. Since AAL1gator only single active address bit, multiple AAL1gator devices connected parallel same MPHY interface connecting each separate address bit. this manner, five AAL1gator connected MPHY interface using following addresses: "0Fh", "17h", "1Bh", "1Dh", "1Eh" with additional logic. other addresses needed additional devices connected same interface, additional logic required. cell being read SPHY mode, being read from channel that being polled MPHY mode, value RPHY_CLAV will until cell been read FIFO there more cells send. mode, TUTOPIA block dependent Adevice read data asserting /RPHY_EN input. SPHY mode, data placed RPHY_DATA cycle following which /RPHY_EN asserted. MPHY mode,
Data Sheet PMC-980620
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order output data, TUTOPIA block also selected, which done when /RPHY_ ADDR falling edge /RPHY_EN. Figure page Figure page TUTOPIA transfer timing diagrams.
RPHY_CLK(i)
RPHY_ADDR(i)*
RPHY_CLAV(o)*** RPHY_CLAV(o)** RPHY_SOC(o)
RPHY_DATA(o) /RPHY_EN(i)
Used only MPHY mode MPHY mode SPHY mode
Figure TUTOPIA Start-of-Transfer Timing (PHY Mode)
RPHY_CLK(i)
RPHY_ADDR(i)*
RPHY_CLAV(o)**
RPHY_CLAV(o)*** RPHY_SOC(o)
RPHY_DATA(o) /RPHY_EN(i)
Used only MPHY mode MPHY mode SPHY mode
Figure
TUTOPIA End-of-Transfer Timing (PHY Mode)
AAL1gator tolerate temporary deassertions /TATM_FULL(/RPHY_EN), assumed that enough UTOPIA bandwidth present accept cells that AAL1gator produce timely manner. AAL1gator tolerate deassertion /TATM_ FULL(/RPHY_EN) line interface frames, this would cause excessive CDV. TALP circuit writes cells byte time into FIFO. also placed into FIFO.
Data Sheet PMC-980620
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Clocking read side derived from system clock. FIFO full, cell building process stalls until space becomes available. FIFO remains full, additional queues will able added. This will indicated processor CSD_ATTN being cleared after setting that bit. TUTOPIA circuit controls when cell transmitted from FIFO. Since UTOPIA transmit cells higher speeds than TALP, since expected applications shared UTOPIA environment, cell transmission from TUTOPIA commences only when there full cell worth data available transmit. cell then transmitted interface UTOPIA TATM_CLK rate, accordance with /TATM_FULL (/RPHY_EN) input. maximum supported clock rate MHz.
Receive UTOPIA Interface Block (RUTOPIA)
RUTOPIA block receives cells from UTOPIA interface sends them RALP interface. Depending value PHY_ENABLE input pin, UTOPIA interface acts either Aside (controls read enable signal) side (controls cell available signal). PHY-side device, RUTOPIA block also SPHY device MPHY device (refer UTOPIA Level specification Appendix "References", page 203) depending value SPHY_EN COMP_LIN_REG. SPHY_EN defaults MPHY mode, device MPHY environment, there will contention while chip software reset. Amode, RUTOPIA block receives RATM_DATA(7:0), RATM_SOC, /RATM_ EMPTY while driving /RATM_EN. reset RUTOPIA block activates /RATM_EN prevent excessive queueing system. After reset, /RATM_EMPTY input signal asserted, RUTOPIA block waits RATM_SOC signal from layer. Once RATM_SOC signal arrives, cell accepted soon possible. small intermediate FIFO allows interface accept data maximum rate. FIFO fills, /RATM_EN signal will asserted again until device ready accept entire cell. /RATM_EN signal depends only cell space independent state /RATM_EMPTY signal. Figure RUTOPIA timing diagram.
RATM_CLK(i) /RATM_EMPTY(i) RATM_DATA(i) RATM_SOC(i) /RATM_EN(o)
Figure
Receive UTOPIA Timing (AMode)
Data Sheet PMC-980620
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RUTOPIA block waits SOC. When RATM_SOC signal arrives, counter started, bytes received. RATM_SOC occurs within cell, counter reinitializes. This means that corrupted cell will dropped good cell will received. RUTOPIA block stores Acell receive FIFO. receive FIFO becomes full, stops receiving Acells from layer. /RATM_EMPTY signal also turn time, even /RATM_EN signal result, incoming byte valid only when /RATM_EN active /RATM_EMPTY inactive. bytes written FIFO with RATM_CLK. RATM_CLK input AAL1gator maximum supported clock rate MHz. mode, RUTOPIA block receives TPHY_DATA(7:0), TPHY_SOC, /TPHY_EN while driving TPHY_CLAV. cell available (TPHY_CLAV) signal indicates when device ready receive complete cell. SPHY mode, TPHY_CLAV always driven. MPHY mode, output enable this signal /TPHY_ADDR input delayed cycle. MPHY mode, /TPHY_ADDR tied address signals that TPHY_CLAV driven only when polled. UTOPIA standard defines 5-bit address. Since AAL1gator only single active address bit, multiple AAL1gator devices connected parallel same MPHY interface connecting each separate address bit. this manner, five AAL1gator connected MPHY interface using following addresses: "0Fh", "17h", "1Bh", "1Dh", "1Eh" with additional logic. other addresses needed additional devices connected same interface, additional logic required. reset, RUTOPIA block tristates TPHY_CLAV. After reset, RUTOPIA block waits /TPHY_EN asserted, SPHY mode, will accept data long /TPHY_EN asserted. MPHY mode, /TPHY_ADDR must falling edge /TPHY_EN order RUTOPIA block accept data. When detected, counter started bytes received. TPHY_SOC occurs within cell, counter reinitializes. This means that corrupted cell will dropped good cell will received. small intermediate FIFO allows interface accept data maximum rate. FIFO fills, TPHY_
Data Sheet PMC-980620
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CLAV signal will asserted again until device ready accept entire cell. FIFO filling, TPHY_CLAV will deasserted when there room only four more bytes data. Figure Figure RUTOPIA transfer timing diagrams.
TPHY_CLK(i)
TPHY_ADDR(i)*
TPHY_CLAV(o)** TPHY_CLAV*** TPHY_DATA(i) TPHY_SOC(i) /TPHY_EN(i)
Only used MPHY mode MPHY mode SPHY mode
Figure
RUTOPIA Start-of-Transfer Timing
TPHY_CLK(i)
TPHY_ADDR(i)*
TPHY_CLAV(o)** TPHY_CLAV*** TPHY_SOC TPHY_DATA(i) /TPHY_EN(i)
Only used MPHY mode MPHY mode SPHY mode
Figure RUTOPIA End-of-Transfer Timing
Receive Adaptation Layer Processor (RALP)
RALP moves data from receive FIFO Acells RUTOPIA interface block external memory. RALP does verify because expects layer device verify before presenting cell AAL1gator SHIFT_VCI cells received with VCI(8) Payload Type Indicator (PTI) sent queue stored using pointers located receive queue table. head pointer address first cell received each queue, usually maintained
Data Sheet PMC-980620
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microprocessor. tail pointer address last cell queue, maintained RALP. RALP updates tail pointer upon each cell arrival. Figure shows interpretation incoming cell header.
Ignored Line Ignored
SHIFT_VCI
Ignored
Data
Queue
Ignored Data
SHIFT_VCI Line
Queue
Ignored
Figure
Cell Header Interpretation
SHIFT_VCI cells received with VCI(8) interpreted data cells sent queue with VCI(7:0). Bits determine line, bits determine queue. receiver ignores VCI(15:9) VPI(11:0). SHIFT_VCI interpretation bits shifted four bits. When cell data cell, RALP verifies CRC. does verify, RALP attempts correct specified ITU-T Recommendation I.363.1 increments R_INCORRECT_SNP counter (refer "R_INCORRECT_SNP Word Format" page 158). RALP cannot correct cell, identifies cell invalid. DISABLE_SN (refer "DISABLE_SN" page 160) been this queue, then sequence number processing done accordance with "Fast Algorithm" described ITU-T Recommendation I.363.1. Based value current previous SNP, RALP either accepts current cell, drops current cell, accepts current cell inserts cells. Inserted cells have following properties: queue unstructured mode queue structured mode inserted cell should contain pointer, each inserted cell contains number payload bytes determined R_BYTES_CELL R_MP_CONFIG (refer "R_MP_ CONFIG Word Format" page 155). queue structured mode inserted cell should contain pointer BYTES_CELL equal then inserted cell contains payload bytes. queue structured mode inserted cell should contain pointer BYTES_CELL less than then inserted cell contains R_BYTES_CELL payload bytes.
Data Sheet PMC-980620
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determination whether inserted cell should contain pointer based pointer generation rules defined ITU-T Recommendation I.363.1. pointer will assumed queue structured following conditions met: even there been other pointer group eight cells (the sequence number structure ends within current inserted cell next cell). queue SDF-MF mode inserted cell should contain signaling data, number payload bytes adjusted signaling information written signaling buffer. Therefore, signaling information will played out.
NOTE: SDF-FR mode, specification states that queue contains data only DS0, pointer used. queue configured this manner, CHAN_UNSTRUCT R_MAX_BUF word (refer "R_MAX_BUF Word Format" page 157). value payload data depends value INSERT_DATA R_SN_ CONFIG (refer "R_SN_CONFIG Word Format" page 160). default load value 0xFF. Other options conditioned data defined R_CONDQ_ DATA, data, pseudorandom data. data chosen, data will written data receive buffer will used. receive buffer write pointer will adjusted correct location. pseudorandom data option chosen, data played will value R_CONDQ_DATA with replaced current value pseudorandom number generator
NOTES: DS0s within replaced cell will same algorithm. minimize overhead generating inserted cells, data option whenever possible. data option still needs internal processing byte-by-byte basis, since does have write data, about twice fast other options. "Fast Algorithm" will, under certain situations, allow cells pass through. When this occurs cells marked potentially bad. cells marked will have pointer verification done them signaling data SRTS information they contain will written. However, these cells should contain pointers signaling data, adjustments made amount payload data written integrity maintained. pseudorandom option available UDF-HS mode.
RALP will maintain integrity there more than consecutive errored cells, there lost cells queue does underrun. maximize tolerance RALP errored cells, R_CDVT R_MAX_BUF values should increased little
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guarantee that queue does underrun situations that could handled sequence number processing algorithm. integrity lost, then queue will forced into underrun condition realign with structure exists. NOTE: processing takes place independent whether queue underrun. cells detected lost while transitioning through underrun state, into forced underrun state, cells will inserted.
MAX_INSERT controls maximum number cells that will inserted when cells lost. more cells than MAX_INSERT lost, then queue will forced into underrun condition. default value MAX_INSERT, "000", equivalent "111" which means that seven cells will inserted. MAX_INSERT R_SN_CONFIG register specified per-queue basis. seven cells lost, this will appear misinserted cell will handled correctly. Likewise, more than seven cells lost, will appear fewer than seven cells were lost because repeats every eight cells. seven more cells were lost, there high probability that queue will underrun. queue underrun, RALP takes following steps minimize impact: time cells inserted, next received pointer mismatches, will immediately create forced underrun realign structure instead waiting consecutive mismatches. signaling information will updated until valid correct pointer received.
DISABLE_SN (refer "DISABLE_SN" page 160) set, processing occurs. That cells will inserted dropped statistics will kept.
RALP begins START state. Once cell received with valid OUT_OF_ SYNC state entered. cells received while START state, including with valid dropped, unless NODROP_IN_START (refer "NODROP_IN_START" page 161) set. this cell valid cell will accepted. NOTE: important dump first cell received, make sure NODROP_IN_ START set.
While OUT_OF_SYNC state, another cell received with valid correct sequence, then SYNC state entered cell accepted. Otherwise, cell with invalid received, then START state re-entered cell dropped. Otherwise, cell valid incorrect sequence, then cell dropped RALP remains OUT_OF_SYNC state.
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While SYNC state, another cell received with valid correct RALP remains SYNC state. Otherwise, invalid received, RALP goes INVALID state; valid incorrect received, OUT_OF_SEQUENCE state entered. cells received while SYNC state accepted. While INVALID state, four possibilities occur. cell received invalid START state re-entered cell dropped. cell received valid sequence with last valid then misinserted cell detected RALP returns SYNC state, cell dropped keep integrity because previous cell already been sent. cell received valid equal with respect last valid then RALP returns SYNC state cell accepted. Otherwise, valid does meet previous criteria, then cell dropped OUT_OF_SYNC state entered. While OUT_OF_SEQUENCE state, five possibilities occur. cell received invalid START state re-entered cell dropped. valid sequence with last valid, sequence then misinserted cell detected RALP returns SYNC state, cell dropped keep integrity because previous cell already been sent. valid sequence with previous cell, RALP assumes cells were lost; inserts number dummy cells identical number lost cells, accepts cell returns SYNC. number lost cells greater than MAX_INSERT, then cells inserted forced underrun occurs. underrun occurred when cells were lost, cells inserted. received valid value equal with respect last received sequence, then cell accepted RALP returns SYNC state. finally, valid does meet previous criteria, then cell dropped RALP enters OUT_OF_SYNC state. Figure page flow "Fast Algorithm". Anytime cell dropped, R_DROPPED_CELLS counter (refer "R_DROPPED_CELLS Word Format" page 161) incremented SN_CELL_DROP sticky (refer "SN_ CELL_DROP" page 158) set. Anytime cell detected lost, R_LOST_CELLS counter (refer "R_LOST_CELLS Word Format" page 162) incremented number lost
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cells. Anytime state machine transitions from SYNC state OUT_OF_ SEQUENCE state, R_SEQUENCE_ERR counter (refer "R_SEQUENCE_ERR Word Format" page 157) incremented. Anytime misinserted cell detected R_MISINSERTED counter (refer "R_SEQUENCE_ERR Word Format" page 157) incremented.
invalid SN/discard START
invalid SN/discard, force underrun seq/discard, force underrun
invalid SN/discard
valid SN/discard (unless NODROP_IN_START set) seq/discard
invalid SN/discard, force underrun
SYNC seq/accept
seq/discard, force underrun invalid SN/accept seq-1/discard seq-1+1/accept seq/accept
SEQUENCE
seq/accept seq-1+1/accept seq/insert cells/accept seq-1/discard
SYNC
INVALID
Figure
Fast Algorithm
cells received while SYNC state accepted whether they good. errored cells received while SYNC state marked potentially cells. These marked cells will have their pointers checked, they contain one; they contain signaling data, signaling data will written memory.
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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cell accepted, RALP then transfers cell external memory using CHAN_ALLOC fields R_QUEUE_TBL. Figure shows this receive cell process. valid cell received time, queue enter underrun condition.
Wait cell receive UTOPIA FIFO.
cell data cell?
Check CRC-10 place cell queue.
correct? Able correct
Correct SN/SNP specified ITU-T Recommendation I.363.1 (refer Appendix "References" page 203). Unable correct Accept/drop cell specified ITU-T Recommendation I.363.1 "Fast Algorithm" (refer Appendix "References" page 203). Accept
correct?
Drop
Place data signaling appropriate timeslots update write pointers.
Figure Receive Cell Processing
CDVT value allows receiver configured store variable amount data that queue before data emitted. This storage permits cells arrive with variable delays without causing errors line outputs. This CDVT value used when first cell received after underrun. AAL1gator also provides protection from buffer overrun pointer misalignment. RALP reads Acell from RUTOPIA FIFO, verifies header, determines queue which cell belongs. then locates data bytes cell writes them into frame buffers provided that line. Receive queues exist external memory, kBytes
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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external memory allocated receive queues. Since there eight lines, each line allocated kBytes memory. This provides multiframes data multiframes signaling used) multiframes data. queues used wrap-around fashion. Read write pointers used frame multiframe level access receive queue. Figure page shows cell reception. Read write pointers used frame multiframe level access correct data byte location. RALP writes sequential cell data bytes into successive locations assigned that queue. When RALP encounters signaling bytes, places them receive signaling buffer. buffers organized multiframe format. There signaling nibble multiframe allocated each channel. Therefore, bytes signaling storage allocated each multiframe worth data buffer. Figure figures that follow illustrate these points identify different data formats stored data signaling buffers.
R_DATA_BUFFER Channel
RFTC
Frames
RALP reassembles bytes from cell. this case, into DS0s
Figure Cell Reception
RALP determines channels reading from R_CHAN_ALLOC table then storing data corresponding timeslots successive frame buffers R_DATA_BUFFER.
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Figure shows contents receive data buffer ESF-formatted data lines SDF-MF mode. Only first bytes each frame buffer first frame buffers every used. This provides storage frames multiframes data.
Frame Buffer Number
MF15
Figure
SDF-MF Format R_DATA_BUFFER
Figure shows contents receive data buffer SF-formatted data lines SDF-MF mode. Only first bytes each frame buffer first frame buffers every used. This provides storage frames data.
Frame Buffer Number
Figure SDF-MF Format R_DATA_BUFFER
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Figure shows contents receive buffer with data lines SDF-FR mode. Only first bytes each frame buffer first frame buffers every used. This provides storage frames data.
Frame Buffer Number
Frame Frame Frame Frame Frame
Frame Frame
Figure SDF-FR Format R_DATA_BUFFER
Figure shows contents receive buffer with data lines SDF-MF mode.
Frame Buffer Number
Figure
SDF-MF Format R_DATA_BUFFER
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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Figure shows contents receive data buffer SDF-MF data using signaling. this case frame multiframe used.
Frame Buffer Number
MF15
Figure
SDF-MF with Signaling Format R_DATA_BUFFER
Figure shows contents receive data buffers with data lines SDF-FR mode.
Frame Buffer Number
Frame Frame Frame
Frame
Figure SDF-FR Format R_DATA_BUFFER
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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Figure shows contents receive data buffer lines UDF-ML UDF-HS mode, including unstructured mode. unstructured modes, each frame buffer contains bits. case unstructured each frame data consists bits. Therefore, each frame buffer contains 1.33 frames data. This must considered when determining CDVT numbers.
Frame Buffer Number
Data Bits
bits bits bits
bits
Figure
Unstructured Format R_DATA_BUFFER
Figure shows contents receive signaling buffer with ESF-formatted line SDF-MF mode. Even channel bytes stored low-byte data words.
Byte Address
Channel ABCD Channel ABCD Channel ABCD Channel Used
Channel ABCD
Channel Used
Multiframe
Figure SDF-MF Format R_SIG_BUFFER
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Figure shows contents receive signaling buffer with SF-formatted line SDF-MF mode. Even channel bytes stored low-byte data words.
Channel ABAB Channel ABAB
Byte Address
Channel Used
Channel ABAB
Channel Used
Multiframe
Figure SDF-MF Format R_SIG_BUFFER
Figure shows contents receive signaling buffer with line SDF-MF mode. Even channel bytes stored low-byte data words.
Byte Address Multiframe
Channel ABCD Channel ABCD Channel ABCD Channel ABCD
Figure
SDF-MF Format R_SIG_BUFFER
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PM73121 AAL1gator AAL1 Processor
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Figure shows contents receive signaling buffer with line SDF-MF mode with signaling. Even channel bytes stored low-byte data words.
Byte Address Multiframe
Channel ABCD Channel ABCD Channel ABCD Channel ABCD
Figure
SDF-MF Mode with Signaling Format R_SIG_BUFFER
3.6.1
Handling Data Signaling Bytes Structure
data structure consists data bytes that structure, followed signaling bytes that structure, any. order locate data signaling bytes, following memory structures used: R_TOT_SIZE structure provides number data signaling bytes structure. element data byte signaling nibble. This value initialized microprocessor. R_TOT_LEFT structure provides running count number bytes remaining structure. R_DATA_LAST structure identifies last byte data structure. data bytes stored memory, R_TOT_LEFT structure decremented one. When TOT_LEFT equal R_DATA_LAST, indicates data structure. remaining bytes stored R_SIG_QUEUE. signaling nibbles written memory until R_TOT_LEFT equals zero. Once R_TOT_LEFT zero, R_TOT_SIZE copied R_TOT_LEFT storing data signaling structures repeated. TOT_SIZE R_DAT_LAST initialized microprocessor. structure used signaling determined mode line value WITH_T1_SIG (refer "E1_WITH_T1_SIG" page 126). Normally signaling structure will follow mode line. However line mode WITH_T1_SIG set, then signaling structure used. This means that single DS0, signaling updated after data bytes instead after data bytes.
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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line SDF-MF mode R_CHAN_NO_SIG R_MAX_BUF word (refer "R_MAX_BUF Word Format" page 157), then queue handled SDF-FR mode. structure should adjusted from multiframe structure frame structure. example, channel with DS0s would have structure size bytes when R_CHAN_NO_SIG structure size bytes (include signaling nibbles) mode when R_CHAN_NO_SIG off.
Underrun
3.6.2
AAL1gator declares underrun condition when data present receive buffer. When this situation occurs, AAL1gator plays conditioned data signaling from multiframe onto timeslots assigned experiencing underrun. Timeslots generated other unaffected. Each time cell received after queue entered underrun condition, UNDERRUN sticky set. RALP does know about underrun until cell received queue that underflowed. make sure that each underrun counted only once, RALP will increment R_UNDERRUN counter when exiting underrun state entering resume state. initial underrun caused reset counted. Forced underruns other errors counted underrun counter. underrun counter read queue currently underrun, present underrun condition will accounted until queue exits underrun. determine queue underrun, check level R_UNDERRUN R_LINE_STATE register. When UDF-HS mode, choice conditioning data signaling while underrun depends value RX_COND R_CH_QUEUE_TBL. Three choices exist: Play data from R_COND_DATA signaling from multiframe (Default). Play pseudorandom data signaling from multiframe (For applications that sensitive constant data.) pseudorandom data option uses data from COND_DATA then replaces most significant with result 18th order polynomial, specifically Play data signaling from multiframe (Also applications that sensitive constant data.) data option replays contents data receive buffer that channel. Data played from location read pointer. Therefore, oldest data played first. UDF-HS mode underrun, data played conditioned data defined line channel There data pseudorandom data options available UDF-HS mode. data structured, RALP searches pointer, finds start structure. cases RALP queues data CDVT worth time before exiting underrun condition. R_UNDERRUN R_LINE_STATE word R_QUEUE_TBL indicates queue underrun state. UNDERRUN sticky each time cell received during underrun condition. Cells received while pointer start structure being located
Data Sheet PMC-980620
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dropped POINTER_SEARCH sticky set. DROPPED_CELL counter also incremented. underrun condition persists, microprocessor should conditioned bits derive both data signaling from conditioned areas. Refer line items Figure page that show start after underrun occurs.
3.6.3 Pointer Processing
When incoming cell cell pointer, cell pointer checked against local pointer value maintained RALP. single pointer mismatch causes corrective actions. pointer ignored cell used contained valid data. consecutive pointer mismatches occur, then RALP forces underrun condition that causes receiver realign next incoming pointer. proper R_COND_DATA signaling from multiframe played until pointer found CDVT worth time passed. PTR_ MISMATCH sticky when pointer mismatch occurs. FORCED_UNDERRUN sticky each time cell received dropped during forced underrun condition. Then, underrun pointer search bits set, described previously section 3.6.2 "Underrun" page received cell potentially determined processing, should contain pointer, pointer checked against local pointer. However, this situation, when cells inserted, next received pointer mismatches, then PTR_MISMATCH error reported forced underrun occurs. waiting second pointer mismatch these situations where integrity have been lost, quicker detection recovery will result. When PTR_MISMATCH error occurs, R_POINTER_REFRAMES counter incremented. Also, when single pointer mismatch occurs, signaling information will updated until valid pointer received prevent corruption signaling information. Parity checking also performed pointers R_CHK_PARITY R_MP_CONFIG. parity error detected PTR_PARITY_ERR sticky will R_PTR_PAR_ERR counter will increment. consecutive pointer parity errors occur, then RALP forces underrun condition resynchronizes. This resynchronization will cause R_POINTER_ REFRAMES increment.
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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Figure shows state machine that checks valid pointers structures.
pointer found
Underrun
Non-dummy pointer found parity good checking parity)
Underrun force-underrun
Pointer Found
Underrun force-underrun
Pointer does match prediction underrun force-underrun checking parity
Structure found
Pointer matches prediction parity good checking parity)
Structure Found
Pointer does match prediction parity checking parity) out-of-sequence invalid cell received
Mismatch
(Signaling updated) Pointer matches prediction parity good checking parity)
Figure Pointer/Structure State Machine
3.6.4
Overrun
Overrun occurs when data buffer removed slower rate than filled. However, because AAL1gator buffers quite large, kBytes line, time this happens, data buffer quite old. Therefore, buffer size adjustable, which regulates much data stored buffer before overrun occurs. R_MAX_BUF field MAX_BUF register controls maximum size receive buffer. value R_MAX_BUF should equal greater than times CDVT, times number frames required cell, whichever greater. overrun condition declared when data receive buffer exceeds maximum specified buffer size (refer "R_MAX_BUF Word Format" page 157). When cell received that causes maximum buffer depth exceeded, OVERRUN sticky AAL1gator enters forced underrun condition. incoming cells queue dropped until underrun occurs. Each time cell received dropped forced underrun condition,
Data Sheet PMC-980620
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PM73121 AAL1gator AAL1 Processor
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FORCED_UNDERRUN sticky set. Once underrun occurs, overrun flag cleared same algorithm used underrun followed. Figure page describes overrun detection, underrun recovery process. Anytime overflow occurs, R_OVERRUNS counter (refer "R_UNDERRUNS Word Format" page 162) incremented. NOTE: Inserting cells cause overrun. threshold checked each byte written into m
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