DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE PM7345
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
PM7345 S/UNI
S/UNI-PDH
SATURN USER-NETWORK INTERFACE APLESIOCHRONOUS DIGITAL HIERARCHY DATACOM
DATA SHEET
ISSUE JUNE 1998
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
PUBLIC REVISION HISTORY Issue Issue Date June 1998 Details Change Data Sheet Reformatted Change Technical Content. Generated data sheet from PMC-930818,
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
CONTENTS FEATURES APPLICATIONS REFERENCES APPLICATION EXAMPLES BLOCK DIAGRAM. DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION 9.10 9.11 9.12 9.13 FRAMER. FRAMER PMON PERFORMANCE MONITOR ACCUMULATOR. RBOC BIT-ORIENTED CODE DETECTOR RFDL FACILITY DATA LINK RECEIVER SPLR PLCP LAYER RECEIVER ATMF ACELL DELINEATOR RXCP RECEIVE CELL PROCESSOR RXFF RECEIVE FIFO. CPPM CELL PLCP PERFORMANCE MONITOR TRANSMITTER. TRANSMITTER XBOC ORIENTED CODE GENERATOR
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
9.14 9.15 9.16 9.17 9.18 9.19 9.20
XFDL FACILITY DATA LINK TRANSMITTER. SPLT SMDS PLCP LAYER TRANSMITTER TXCP TRANSMIT CELL PROCESSOR TXFF TRANSMIT FIFO. TRAIL TRACE BUFFER MICROPROCESSOR INTERFACE NORMAL MODE REGISTER MEMORY
NORMAL MODE REGISTER DESCRIPTION. 10.1 BASIC OPERATING MODES
TEST FEATURES DESCRIPTION 11.1 TEST MODE
OPERATION 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 PLCP FRAME FORMATS PLCP PATH OVERHEAD OCTET PROCESSING G.832 FRAME FORMAT. G.832 PATH OVERHEAD OCTET PROCESSING S/UNI-PDH CELL DATA STRUCTURE USING PERFORMANCE MONITORING FEATURES USING INTERNAL DATA LINK TRANSMITTER USING INTERNAL DATA LINK RECEIVER SILICON SYSTEMS 78P7200 IMPLEMENTATION
FUNCTIONAL TIMING ABSOLUTE MAXIMUM RATINGS.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS S/UNI-PDH TIMING CHARACTERISTICS ORDERING THERMAL INFORMATION MECHANICAL INFORMATION. 19.1 19.2 PLASTIC LEADED CHIP CARRIER SUFFIX): PLASTIC QUAD FLAT PACK SUFFIX):.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
LIST REGISTERS REGISTER 00H: S/UNI-PDH CONFIGURATION. REGISTER 01H: S/UNI-PDH INTERRUPT ENABLE REGISTER 02H: S/UNI-PDH INTERRUPT STATUS REGISTER 03H: S/UNI-PDH CONTROL REGISTER 04H: S/UNI-PDH IDENTIFICATION MASTER RESET REGISTER 05H: S/UNI-PDH DATA LINK FERF CONTROL. REGISTER 06H: RBOC CONFIGURATION/INTERRUPT ENABLE REGISTER 07H: RBOC INTERRUPT STATUS REGISTER 08H: FRMR CONFIGURATION. REGISTER 09H: FRMR INTERRUPT ENABLE (ACE=0) REGISTER 09H: FRMR ADDITIONAL CONFIGURATION REGISTER (ACE=1). REGISTER 0AH: FRMR INTERRUPT STATUS. REGISTER 0BH: FRMR STATUS. REGISTER 0CH: RFDL CONFIGURATION REGISTER 0DH: RFDL ENABLE/STATUS REGISTER 0EH: RFDL STATUS. REGISTER 0FH: RFDL RECEIVE DATA REGISTER 10H: S/UNI-PDH CHANGE PMON PERFORMANCE METERS REGISTER 11H: PMON INTERRUPT ENABLE/STATUS REGISTER 14H: PMON LINE CODE VIOLATION EVENT COUNT LSB. REGISTER 15H: PMON LINE CODE VIOLATION EVENT COUNT MSB.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
REGISTER 16H: PMON FRAMING ERROR EVENT COUNT LSB. REGISTER 17H: PMON FRAMING ERROR EVENT COUNT MSB. REGISTER 18H: PMON SUMMED EXCESSIVE ZERO DETECT INCOMING ERROR COUNT REGISTER 19H: PMON SUMMED EXCESSIVE ZERO DETECT INCOMING ERROR COUNT REGISTER 1AH: PMON PARITY ERROR EVENT COUNT LSB. REGISTER 1BH: PMON PARITY ERROR EVENT COUNT REGISTER 1CH: PMON PATH PARITY ERROR EVENT COUNT REGISTER 1DH: PMON PATH PARITY ERROR EVENT COUNT REGISTER 1EH: PMON FEBE EVENT COUNT LSB. REGISTER 1FH: PMON FEBE EVENT COUNT REGISTER 20H: TRAN CONFIGURATION. REGISTER 21H: TRAN DIAGNOSTIC REGISTER 24H: XFDL CONFIGURATION REGISTER 25H: XFDL INTERRUPT STATUS REGISTER 26H: XFDL TRANSMIT DATA REGISTER 27H: XBOC CODE REGISTER 28H: SPLR CONFIGURATION. REGISTER 29H: SPLR INTERRUPT ENABLE. REGISTER 2AH: SPLR INTERRUPT STATUS REGISTER 2BH: SPLR STATUS. REGISTER 2CH: SPLT CONFIGURATION REGISTER 2DH: SPLT CONTROL
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
REGISTER 2EH: SPLT DIAGNOSTICS OCTET. REGISTER 2FH: SPLT OCTET. REGISTER 30H: CPPM LOSS CLOCK METERS. REGISTER 31H: CPPM CHANGE CPPM PERFORMANCE METERS REGISTER 32H: CPPM ERROR COUNT LSB. REGISTER 33H: CPPM ERROR COUNT MSB. REGISTER 34H: CPPM FRAMING ERROR EVENT COUNT LSB. REGISTER 35H: CPPM FRAMING ERROR EVENT COUNT MSB. REGISTER 36H: CPPM FEBE COUNT REGISTER 37H: CPPM FEBE COUNT REGISTER 38H: CPPM ERROR COUNT REGISTER 39H: CPPM ERROR COUNT REGISTER 3AH: CPPM IDLE/UNASSIGNED CELL COUNT LSB. REGISTER 3BH: CPPM IDLE/UNASSIGNED CELL COUNT REGISTER 3CH: CPPM RECEIVE CELL COUNT LSB. REGISTER 3DH: CPPM RECEIVE CELL COUNT MSB. REGISTER 3EH: CPPM TRANSMIT CELL COUNT REGISTER 3FH: CPPM TRANSMIT CELL COUNT MSB. REGISTER 40H: RXCP CONTROL REGISTER 41H: RXCP FRAMING CONTROL. REGISTER 42H: RXCP INTERRUPT ENABLE/STATUS REGISTER 43H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTER 44H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
REGISTER 45H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTER 46H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTER 47H: RXCP IDLE/UNASSIGNED CELL MASK: OCTET REGISTER 48H: RXCP IDLE/UNASSIGNED CELL MASK: OCTET REGISTER 49H: RXCP IDLE/UNASSIGNED CELL MASK: OCTET REGISTER 4AH: RXCP IDLE/UNASSIGNED CELL MASK: OCTET REGISTER 4BH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTER 4CH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTER 4DH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTER 4EH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTER 4FH: RXCP USER-PROGRAMMABLE MATCH MASK: OCTET REGISTER 50H: RXCP USER-PROGRAMMABLE MATCH MASK: OCTET REGISTER 51H: RXCP USER-PROGRAMMABLE MATCH MASK OCTET REGISTER 52H: RXCP USER-PROGRAMMABLE MATCH MASK OCTET REGISTER 53H: RXCP CONTROL/STATUS. REGISTER 54H: RXCP COUNT THRESHOLD REGISTER 58H: TXCP CONTROL REGISTER 59H: TXCP INTERRUPT ENABLE/STATUS CONTROL. REGISTER 5AH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
REGISTER 5BH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTER 5CH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTER 5DH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTER 5EH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTER 5FH: TXCP IDLE/UNASSIGNED CELL PAYLOAD. REGISTER 60H: FRMR FRAMING OPTIONS REGISTER 61H: FRMR MAINTENANCE OPTIONS. REGISTER 62H: FRMR FRAMING INTERRUPT ENABLE REGISTER 63H: FRMR FRAMING INTERRUPT INDICATION STATUS REGISTER 64H: FRMR MAINTENANCE EVENT INTERRUPT ENABLE REGISTER 65H: FRMR MAINTENANCE EVENT INTERRUPT INDICATION REGISTER 66H: FRMR MAINTENANCE EVENT STATUS REGISTER 68H: TRAN FRAMING OPTIONS REGISTER 69H: TRAN STATUS DIAGNOSTIC OPTIONS. REGISTER 6AH: TRAN BIP-8 ERROR MASK REGISTER 6BH: TRAN MAINTENANCE ADAPTATION OPTIONS REGISTER 6CH: CONTROL REGISTER 6DH: TRAIL TRACE IDENTIFIER STATUS. REGISTER 6EH: INDIRECT ADDRESS. REGISTER 6FH: INDIRECT DATA. REGISTER 70H: EXPECTED PAYLOAD TYPE LABEL. REGISTER 71H: PAYLOAD TYPE LABEL CONTROL/STATUS:
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viii
PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
REGISTER 74H: SYNC FIFO PARITY CONTROL/STATUS:. ADDRESS MASTER TEST.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
LIST FIGURES FIGURE USER NETWORK INTERFACE FIGURE USER NETWORK INTERFACE FIGURE CELL DELINEATION STATE DIAGRAM. FIGURE VERIFICATION STATE DIAGRAM FIGURE PLCP FRAME FORMAT FIGURE PLCP FRAME FORMAT FIGURE G.751 PLCP FRAME FORMAT. FIGURE PLCP FRAME FORMAT FIGURE G.832 FRAME STRUCTURE. FIGURE CELL DATA STRUCTURE. FIGURE TYPICAL DATA FRAME. FIGURE 78P7200 CONFIGURATION. FIGURE RECEIVE STREAM. FIGURE RECEIVE PLCP STREAM FIGURE RECEIVE ADIRECT-MAPPED STREAM FIGURE RECEIVE BIPOLAR STREAM FIGURE RECEIVE UNIPOLAR STREAM FIGURE RECEIVE BIPOLAR STREAM. FIGURE RECEIVE UNIPOLAR STREAM FIGURE RECEIVE OVERHEAD. FIGURE RECEIVE G.832 OVERHEAD. FIGURE RECEIVE G.751 OVERHEAD.
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DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
FIGURE RECEIVE PLCP OVERHEAD FIGURE TRANSMIT STREAM FIGURE TRANSMIT STREAM FIGURE TRANSMIT BIPOLAR STREAM. FIGURE TRANSMIT UNIPOLAR STREAM FIGURE TRANSMIT BIPOLAR STREAM FIGURE TRANSMIT UNIPOLAR STREAM. FIGURE TRANSMIT OVERHEAD FIGURE TRANSMIT G.832 OVERHEAD FIGURE TRANSMIT G.751 OVERHEAD FIGURE TRANSMIT PLCP OVERHEAD FIGURE GENERIC TRANSMIT STREAM. FIGURE RECEIVE FIFO INTERFACE (84-PIN PLCC 100-PIN PQFP WITH SYFIFOB=1). FIGURE TRANSMIT FIFO INTERFACE (84-PIN PLCC 100-PIN PQFP WITH SYFIFOB=1). FIGURE RECEIVE SYNCHRONOUS FIFO (100-PIN PQFP WITH SYFIFOB=0, TSEN=0) FIGURE RECEIVE SYNCHRONOUS FIFO (100-PIN PQFP WITH SYFIFOB=0, TSEN=1) FIGURE TRANSMIT SYNCHRONOUS FIFO (100-PIN PQFP WITH SYFIFOB=0). FIGURE RECEIVE FIFO BYPASS INTERFACE. FIGURE TRANSMIT FIFO BYPASS INTERFACE FIGURE MICROPROCESSOR READ ACCESS TIMING FIGURE MICROPROCESSOR WRITE ACCESS TIMING
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
FIGURE TRANSMIT FIFO TIMING. FIGURE RECEIVE FIFO TIMING FIGURE TRANSMIT FIFO TIMING. FIGURE RECEIVE FIFO TIMING FIGURE TRANSMIT SYSTEM SIDE FIFO BYPASS FIGURE RECEIVE SYSTEM SIDE FIFO BYPASS FIGURE INPUT TIMING FIGURE INPUT TIMING CONT'D. FIGURE OUTPUT TIMING FIGURE OUTPUT TIMING CONT'D. FIGURE OVERHEAD OUTPUT TIMING
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
FEATURES Implements ADirect Cell Mapping into DS1, DS3, transmission systems according ITU-T Draft Recommendation G.804. Implements Physical Layer Convergence Protocol (PLCP) transmission systems according AForum User Network Interface Specification ANSI TA-TSY-000773, TA-TSY-000772, transmission systems according ETSI Draft Standards T/NA(91)17, T/NA(91)18. Implements Aphysical layer Broadband ISDN according ITU-T Recommendation I.432. Provides on-chip (G.751 G.832) framers. Directly interfaces available E3/DS3 line interface units. Uses PMC-Sierra PM4341 T1XC, PM6341 E1XC, PM4351 COMET framer/line interface chips applications. Provides support arbitrary rate external transmission system interface maximum rate Mbit/s. Support provided SMDS Amappings into various rate transmission systems defined below, well supporting evolving mappings defined G.804:
Rate Format C-bit G.751 G.832 CRC-4 PCM30 SMDS PLCP mapping ADirect mapping SMDS PLCP mapping ADirect mapping
Evolving through G.804
Provides 8-bit microprocessor interface configuration, control status monitoring. power CMOS technology.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
Available high density 100-pin PQFP package, 84-pin PLCC package which pin-compatible with PMC-Sierra PM7321 PLPP standard product. receiver section: Provides frame synchronization C-bit parity applications, alarm detection, accumulates line code violations, framing errors, parity errors, path parity errors FEBE events. addition, alarm channel codes detected, integral HDLC receiver provided terminate path maintenance data link. Provides frame synchronization G.751 G.832 applications, alarm detection, accumulates line code violations, framing errors, parity errors, FEBE events. addition, G.832, Trail Trace detected, integral HDLC receiver provided terminate either Network Requirement General Purpose data link. Provides frame synchronization, path overhead extraction, cell extraction PLCP, PLCP, PLCP, G.751 PLCP formats, G.832 formatted streams. Provides detection yellow alarm loss frame (LOF), accumulates BIP-8 errors, framing errors FEBE events. Provides Aframing using cell delineation. Provides cell descrambling, header check sequence (HCS) error detection, idle/unassigned cell filtering, accumulates number received idle/unassigned cells, number received cells written FIFO, number errors. Provides four cell FIFO rate decoupling between line, higher layer processing entity. This FIFO bypassed minimize delay through device when processing PLCP frames. Provides asynchronous 8-bit wide FIFO interface accessing received cell data bytes (available either 84-pin PLCC 100-pin PQFP packages). Provides synchronous 8-bit wide FIFO with receive byte parity generation compatible timing with current "UTOPIA" specifications single multiPHY interfaces (available only 100-pin PQFP package).
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
transmitter section: Provides frame insertion C-bit parity applications, alarm insertion, diagnostic features. addition, alarm channel codes inserted, integral HDLC transmitter provided insert path maintenance data link. Provides frame insertion G.751 G.832 applications, alarm insertion, diagnostic features. addition, G.832, Trail Trace inserted, integral HDLC transmitter provided insert either Network Requirement General Purpose data link. Provides frame insertion path overhead insertion DS1, DS3, based PLCP formats. addition, alarm insertion, diagnostic features provided. Provides optional reference input locking transmit PLCP frame rate externally applied frame reference. Provides optional Acell scrambling, generation/insertion, programmable idle/unassigned cell insertion, diagnostics features accumulates transmitted cells read from FIFO. Provides four cell FIFO rate decoupling between line, higher layer processing entity. This FIFO bypassed minimize delay through device when processing PCLP frames. Provides asynchronous 8-bit wide FIFO interface accessing transmit cell data bytes (available either 84-pin PLCC 100-pin PQFP packages). Provides synchronous 8-bit wide FIFO with transmit byte parity checking compatible timing with current "UTOPIA" specifications single multiPHY interfaces (available only 100-pin PQFP package). Bypass Loopback features: Allows bypassing framer enable transmission system sublayer processing external device (for example, PM4341 Framer/LIU used DS1-based services, PM6341 Framer/LIU used E1-based services). Provides diagnostic loopback, line loopback, payload loopback, Acell loopback.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
APPLICATIONS SMDS Routers, Bridges, Switches, Adapter Cards DQDB Access Units Aand SMDS test equipment
REFERENCES American National Standard Telecommunications, ANSI T1.107-1995 "Digital Hierarchy Formats Specifications". Bell Communications Research, TA-TSY-000773 "Local Access System Generic Requirements, Objectives, Interface Support Switched Multi-megabit Data Service" Issue March 1990 Supplement December 1990. ITU-T, Recommendation I.432 "B-ISDN User-Network Interface Physical Layer Specification", 1993. ITU-T Recommendation G.704 "General Aspects Digital Transmission Systems; Terminal Equipments Synchronous Frame Structures Used 1544, 6312, 2048, 8488 kbit/s Hierarchical Levels", July, 1995. ITU-T Blue Book, Recommendation G.751, "Digital Multiplex Equipments Operating Third Order Rate 34368 kbit/s Fourth Order Rate 139264 kbit/s using Positive Justification", Vol. III, Fascicle III.4, 1988. ITU-T Recommendation G.804 "ACell Mapping into Plesiochronous Digital Hierarchy (PDH)", 1993. ITU-T Recommendation G.832 "Transport Elements Networks: Frame Multiplexing Structures", 1993. ETSI "Metropolitan Area Network Physical Layer Convergence Procedure 2.048 Mbit/s", April 1994. ETSI "Metropolitan Area Network Physical Layer Convergence Procedure 34.368 Mbit/s", April 1994. IEEE, 802.6-1990 "Distributed Queue Dual Subnetwork Metropolitan Area Network".
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
AForum, V3.1, October, 1995 "AUser-Network Interface Specification". AForum, 94-0406R5, (34,368 kpbs) Physical Layer Interface", Dec. 1994. AForum, 95-1207R1, "DS3 Physical Layer Interface Specification", December, 1995. AForum, Level V2.00 February 1994 APHY Data path Interface".
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
APPLICATION EXAMPLES PM7345 S/UNI-PDH used implement Auser network interfaces (UNI) network node interfaces (NNI). example DS3/E3 User Network Interface (figure DS1/E1 User Network Interface (figure illustrate interconnect between S/UNI-PDH system elements required implement complete Aphysical layer interface. figure DS3/E3 line interface function provided commercially available DS3/E3 Line Interface Unit (LIU) product available from Silicon Systems. DS3/E3 framing function, along with PLCP processing, Atransmission convergence sublayer processing performed S/UNI-PDH. figure framing functions provided PM4341 Transceiver (T1XC) product available from PMC-Sierra. framing functions provided PM6341 Transceiver (E1XC) product, also available from PMC-Sierra. combination these transceiver devices with S/UNI-PDH allows both PLCP-formatted DS1/E1 signals, ITU-T G.804 compliant DS1/E1 signals processed. G.804 specification defines Adirect cell mappings variety transmission formats, including 1.544 Mbit/s DS1, 2.048 Mbit/s formats. optional PLCP DS3/E3 Overhead Processors illustrated expected implemented using programmable logic devices. further S/UNI-PDH application information, please refer document number PMC-930410, "The APhysical Layer".
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
Figure
User Network Interface
RRDENB FRDB/RFCLK RSOC REOH REOC FRDATA[7:0] RFIFOE/RCA TWRENB FWRB/TFCLK TSOC FWDATA[7:0] TFIFOFB/TCA
LINE INTERFACE 78P7200 E3/DS3 LINE INTERFACE
RPOS RNEG RCLK
RPOS/RDAT RNEG/ROHM RCLK
CELL INTERFACE
TPOS TNEG TCLK
44.736 44.736
34.368
TPOS/TDAT TNEG/TOHM TCLK TICLK TIOHM C13/CADD
CELL INTERFACE
ATM/SMDS Adaptation Layer Processor (eg. policing functions)
TPOHCLK TPOHFP TPOHINS PM7345 TPOH TCELL S/UNI-PDH RPOHCLK RCELL SATURN RPOHFP RPOH A[7:0] D[7:0] RSTB
AD[15:0] Intel/ Motorola Single Chip RESB
User-Network Interface TOHCLK
TOHFP TOHINS ROHCLK ROHFP INTB
Optional DS3/E3/PLCP Overhead Processor tester application)
From Master reset circuitry From chip select decode circuitry
Layout information 78P7200 E3/DS3 found OPERATION section this document. Please refer example configuration used PMC-Sierra.1
Please contact Silicon Systems (714) 573-6200 detailed application information concerning 78P7200 E3/DS3 LIU.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
Figure
User Network Interface
BRPCM BRFPO RCLKO RPOS/RDAT RNEG/ROHM RCLK RRDENB FRDB/RFCLK RSOC REOH REOC FRDATA[7:0] RFIFOE/RCA TWRENB FWRB/TFCLK TSOC FWDATA[7:0] TFIFOFB/TCA
PM4341A/PM6341 T1XC/E1XC Transceiver
XCLK D[7:0] A[7:0] 37.056 (DS1) 49.152 (E1) BTPCM BTFP BTCLK TCLKO TCLKI 1.544 2.048 RSTB
CELL INTERFACE
TIOHM C13/CADD
TPOS/TDAT TNEG/TOHM TCLK TICLK
CELL INTERFACE
ATM/SMDS Adaptation Layer Processor (eg. policing functions)
TCELL RCELL
AD[15:0] Intel/ Motorola Single Chip RESB
A[7:0] D[7:0] RSTB
PM7345 S/UNI-PDH SATURN User-Network Interface
TPOHCLK TPOHFP TPOHINS TPOH RPOHCLK RPOHFP RPOH
Optional PLCP Overhead Processor tester application
TOHCLK TOHFP TOHINS ROHCLK ROHFP INTB
From chip select decode circuitry From Master reset circuitry
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
BLOCK DIAGRAM
TPOH TPOHINS TPOHCLK TPOHFP C13/CADD/8KREF TICLK TIOHM
TOHINS TOHCLK TOHFP
XBOC XFDL Trail FEAC HDLC Access Buffer TCLK TPOS/TDAT TNEG/TOHM TRAN Transmit Framer FRMR Receive Framer SPLT Transmit Aand PLCP Framer ATMF/SPLR Receive Aand PCLP Framer TXCP Cell Processor RXCP Cell Processor TXFF Cell FIFO System RXFF Cell FIFO Microprocessor
TCELL
FWDATA[7:0] FWRB TSOC TFIFOFB/FWCLK RSOC REOH/LOF REOC/OOF RFIFOE/FRCLK
Line Encode
RCLK RPOS/RDAT RNEG/ROHM
Line Decode
RBOC RFDL PMON Perf. Trail FEAC HDLC Monitor Access Buffer
CPPM PLCP/cell Perf. Monitor
FRDB FRDATA[7:0]
RPOH RPOHCLK RPOHFP
ROHCLK ROHFP
Normal Operating Mode (84-pin PLCC Async FIFO interface shown)
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RCELL
D[7:0] A[7:0]
RSTB INTB
PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
TPOH TPOHINS TPOHCLK TPOHFP C13/CADD/8KREF TICLK TIOHM
TOHINS TOHCLK TOHFP
TDLSIG TDLCLK
XBOC XFDL Trail FEAC HDLC Access Buffer TRAN Transmit Framer FRMR Receive Framer SPLT Transmit Aand PLCP Framer ATMF/SPLR Receive Aand PCLP Framer TXCP Cell Processor RXCP Cell Processor TXFF Cell FIFO RXFF Cell FIFO Microprocessor System
TCELL
TCLK TPOS/TDAT TNEG/TOHM
Line Encode
RCLK RPOS/RDAT RNEG/ROHM
Line Decode
RBOC RFDL PMON Trail Perf. FEAC HDLC Monitor Access Buffer
CPPM PLCP/cell Perf. Monitor
FWDATA[7:0] TFCLK TWRENB TSOC TXPRTY RSOC REOH REOC RXPRTY RRDENB RFCLK FRDATA[7:0]
TSEN D[7:0] A[7:0] RDLSIG RDLCLK RPOH RPOHCLK RPOHFP ROHCLK ROHFP RCELL RSTB INTB
Normal Operating Mode (100-pin PQFP Sync FIFO interface shown)
TPOH TPOHINS TPOHCLK TPOHFP C13/CADD/8KREF TICLK TIOHM
TOHINS TOHCLK TOHFP
XBOC XFDL Trail FEAC HDLC Access Buffer TRAN Transmit Framer FRMR Receive Framer SPLT Transmit Aand PLCP Framer ATMF/SPLR Receive Aand PCLP Framer TXCP Cell Processor RXCP Cell Processor TXFF Cell FIFO System RXFF Cell FIFO Microprocessor
TCELL
FWDATA[7:0] FWRB TSOC TFIFOFB/FWCLK RSOC REOH/LOF REOC/OOF RFIFOE/FRCLK
TCLK TPOS/TDAT TNEG/TOHM
Line Encode
RCLK RPOS/RDAT RNEG/ROHM
Line Decode
RBOC RFDL PMON Perf. Trail FEAC HDLC Monitor Access Buffer
CPPM PLCP/cell Perf. Monitor
FRDB FRDATA[7:0]
D[7:0] A[7:0]
ROHCLK ROHFP
With FIFO Bypass Enabled
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RPOH RPOHCLK RPOHFP
RCELL
RSTB INTB
PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
TPOH TPOHINS TPOHCLK TPOHFP C13/CADD/8KREF TICLK TIOHM
TOHINS TOHCLK TOHFP
XBOC XFDL Trail FEAC HDLC Access Buffer TCLK TPOS/TDAT TNEG/TOHM TRAN Transmit Framer FRMR Receive Framer SPLT Transmit Aand PLCP Framer ATMF/SPLR Receive Aand PCLP Framer TXCP Cell Processor RXCP Cell Processor TXFF Cell FIFO RXFF Cell FIFO Microprocessor System
TCELL
FWDATA[7:0] FWRB TSOC TFIFOFB/FWCLK RSOC REOH/LOF REOC/OOF RFIFOE/FRCLK
Line Encode
RCLK RPOS/RDAT RNEG/ROHM
Line Decode
RBOC RFDL PMON Perf. Trail FEAC HDLC Monitor Access Buffer
CPPM PLCP/cell Perf. Monitor
FRDB FRDATA[7:0]
D[7:0] A[7:0]
ROHCLK ROHFP
With DS3/E3 Framer Bypassed
TPOH TPOHINS TPOHCLK TPOHFP C13/CADD/8KREF TICLK TIOHM
TOHINS TOHCLK TOHFP
RPOH RPOHCLK RPOHFP
LINE TCLK TPOS/TDAT TNEG/TOHM
XBOC XFDL Trail FEAC HDLC Access Buffer PAYLOAD Line Encode TRAN Transmit Framer FRMR Receive Framer SPLT TIMING Transmit Aand PLCP Framer ATMF/SPLR Receive Aand PCLP Framer TXCP Cell Processor RXCP Cell Processor TXFF Cell FIFO System RXFF Cell FIFO Microprocessor CELL
TCELL
RCELL
RSTB INTB
FWDATA[7:0] FWRB TSOC TFIFOFB/FWCLK RSOC REOH/LOF REOC/OOF RFIFOE/FRCLK
RCLK RPOS/RDAT RNEG/ROHM DIAGNOSTIC
Line Decode
RBOC RFDL PMON Perf. Trail FEAC HDLC Monitor Access Buffer
CPPM PLCP/cell Perf. Monitor
FRDB FRDATA[7:0]
D[7:0] A[7:0]
ROHCLK ROHFP
Loopback Modes
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RPOH RPOHCLK RPOHFP
RCELL
RSTB INTB
PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
DESCRIPTION PM7345 S/UNI-PDH Aphysical layer processor with integrated framing. PLCP sublayer DS1, DS3, processing supported Acell delineation. S/UNI-PDH contains integral framer, which provides framing error accumulation accordance with ANSI specifications, integral framer, which provides framing accordance with ITU-T Recommendations G.832 G.751. When configured transmission system sublayer processing, S/UNI-PDH accepts outputs either B3ZS-encoded bipolar unipolar signal compatible with C-bit parity applications. When configured transmission system sublayer processing, S/UNI-PDH accepts outputs either HDB3-encoded bipolar unipolar signal compatible with G.751 G.832 applications. When configured DS1, transmission system sublayer processing, S/UNI-PDH accepts outputs unipolar signal with appropriate clock frame pulse signals physical sublayer processing. When configured other transmission systems, S/UNI-PDH provides generic interface physical sublayer processing. receive direction, S/UNI-PDH frames signal with maximum average reframe time detects line code violations, loss signal, framing errors, parity errors, path parity errors, AIS, receive failure idle code. overhead bits extracted presented serial output. When C-bit parity mode, Path Maintenance Data Link Alarm Control (FEAC) channel extracted. HDLC receiver provided Path Maintenance Data Link support. addition, valid bit-oriented codes FEAC channel detected available through microprocessor port. receive direction, S/UNI-PDH frames either G.751 G.832 signal with maximum average reframe time detects line code violations, loss signal, framing errors, AIS, remote alarm indication. Further, when processing G.832 formatted data, parity errors, receive failure, block errors also detected; Trail Trace message extracted made available through microprocessor port. HDLC receiver provided either G.832 Network Requirement G.832 General Purpose Data Link support. Error event accumulation also provided S/UNI-PDH. Framing errors, line code violations, parity errors, path parity errors block errors accumulated saturating counters.
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PM7345 S/UNI-PDH
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transmit direction, S/UNI-PDH inserts framing, bits. When enabled C-bit parity operation, bit-oriented code transmitter HDLC transmitter provided insertion FEAC channel Path Maintenance Data Link into appropriate overhead bits. Alarm Indication Signal inserted when enabled external input using internal register bit; other status signals such idle signal inserted when enabled internal register bit. When operation selected, C-bit Parity (the first C-bit first sub-frame) forced toggle that downstream equipment will confuse M23-formatted stream with stuck-at C-bits C-bit Parity application. transmit direction, S/UNI-PDH inserts framing either G.832 G.751 format. When enabled G.832 operation, HDLC transmitter provided insertion either Network Requirement General Purpose Data Link into appropriate overhead bits. Alarm Indication Signal other status signals inserted internal register bits. S/UNI-PDH also supports diagnostic modes which inserts parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, line code violations, all-zeros. S/UNI-PDH provides cell delineation Acells using PLCP framing format, using header check sequence octet Acell header specified ITU-T Recommendation I.432. DS1, DS3, based PLCP frame formats processed. interface consistent with generic physical interface defined ITU-T Recommendation I.432 provided arbitrary rates Mbit/s. This interface used provide physical layer support transmission systems that have associated PLCP sublayer, provide efficient means directly mapping Acells existing transmission system formats (such DS1). PLCP receive direction, framing, path overhead extraction cell extraction provided. BIP-8 error events, frame octet error events block error events accumulated. PLCP transmit direction, S/UNI-PDH provides overhead insertion using inputs internal registers, nibble byte stuffing, automatic BIP-8 octet generation insertion automatic block error insertion. Diagnostic features BIP-8 error, framing error block error insertion also supported. cell receive path, idle/unassigned cells dropped according programmable filter. default, incoming cells with single errors corrected written FIFO buffer. Optionally, cells dropped upon
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detection error. Acell payloads optionally descrambled. Assigned cells containing detectable errors written FIFO buffer. Cells read from FIFO using asynchronous 8-bit wide datapath interface synchronous 9-bit wide datapath, depending upon packaging option selected. Counts error-free assigned cells, cells containing errors accumulated independently performance monitoring purposes. cell transmit path, cells written FIFO buffer using asynchronous 8bit wide datapath interface synchronous 9-bit wide datapath interface, depending upon packaging option selected. Idle/unassigned cells automatically inserted when FIFO contains less than full cell. generation, cell payload scrambling optionally provided. Both receive transmit cell FIFOs provide buffering four cells. FIFOs provide rate matching interface between higher layer Aentity S/UNI-PDH. S/UNI-PDH configured, controlled monitored generic 8-bit microprocessor through which internal registers accessed. sources interrupts identified, acknowledged, masked this interface.
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PM7345 S/UNI-PDH
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DIAGRAM S/UNI-PDH available 84-pin PLCC.
RPOS/RDAT RNEG/ROHM ROHCLK FWDATA[7] FWDATA[6] VSSO RPOH RPOHCLK RPOHFP FWRB ROHFP VDDO FWDATA[5] FWDATA[4]
A[0] A[1] A[2] A[3] D[0] D[1] D[2] D[3] VDDO VSSI VDDI VSSO D[4] D[5] D[6] D[7] A[4] A[5] A[6] A[7]
RSTB INTB RCLK
PM7345
S/UNI-
FWDATA[3] FWDATA[2] FWDATA[1] FWDATA[0] FRDB FRDATA[7] FRDATA[6] FRDATA[5] FRDATA[4] VDDO VSSO VSSI VDDI FRDATA[3] FRDATA[2] FRDATA[1] FRDATA[0] RSOC REOC/OOF REOH/LOF RFIFOE/FRCLK
TOHFP VDDO TICLK C13/CADD/8KREF TCLK TPOS/TDAT TNEG/TOHM TOHCLK VSSO TOHINS TPOHCLK TCELL TFIFOFB/FWCLK TSOC TPOHINS TPOH TIOHM TPOHFP RCELL
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PM7345 S/UNI-PDH
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S/UNI-PDH also available 100-pin PQFP having body size 14x14mm pitch 0.5mm.
RSTB INTB RCLK RPOS/RDAT RNEG/ROHM ROHCLK ROHFP RDLSIG RDLCLK VDDO TXPRTY VSSO RPOH RPOHCLK RPOHFP TWRENB FWRB/TFCLK FWRDATA[7] FWRDATA[6] FWRDATA[5] FWRDATA[4]
A[0] A[1] A[2] A[3] D[0] D[1] D[2] D[3] VDDO VSSI VSSI VDDI VDDI VSSO D[4] D[5] D[6] D[7] A[4] A[5] A[6] A[7]
VSSO FWRDATA[3] FWRDATA[2] FWRDATA[1] FWRDATA[0] RRDENB FRDB/RFCLK FRDATA[7] FRDATA[6] FRDATA[5] FRDATA[4] VDDO VSSO RXPRTY VSSI VDDI FRDATA[3] FRDATA[2] FRDATA[1] FRDATA[0] RSOC REOC/OOF REOH/LOF RFIFOE/RCA/FRCLK TSEN
Index
PM7345 UNI
TIOHM TICLK C13/CADD/8KREF TCLK TPOS/TDAT TNEG/TOHM TOHCLK TOHFP TDLSIG TDLCLK VDDO VSSO TOHINS SYFIFOB TPOHCLK TPOHFP TPOHINS TPOH TCELL TFIFOFB/TCA/FWCLK TSOC RCELL
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PM7345 S/UNI-PDH
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Name
DESCRIPTION Type Input PLCC Function Receive Clock (RCLK). RCLK provides receive direction timing. RCLK externally recovered transmission system baud rate clock that samples RPOS/RDAT RNEG/ROHM inputs rising falling edge. RCLK maximum frequency MHz. Receive Positive Pulse (RPOS). RPOS contains positive pulses received B3ZS-encoded DS3, HDB3-encoded transmission system when dual-rail input format selected. RPOS contains entire stream when single-rail (unipolar) input format enabled. dual-rail/single-rail selection controlled FRMR FRMR Configuration Registers. Receive Data (RDAT). RDAT contains received transmission system stream when non-DS3/E3 based transmission system being processed (for example RDAT contain stream). RPOS/RDAT function selection controlled FRMRBP S/UNI-PDH Configuration Register. Both RPOS RDAT sampled rising edge RCLK default, enabled sampled falling edge RCLK. This sampling controlled RCLKINV S/UNI-PDH Control Register. addition, signal polarity control provided RPNINV S/UNI-PDH Control Register.
RCLK
RPOS/
Input
RDAT
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RNEG/
Input
Receive Negative Pulse (RNEG). RNEG contains negative pulses received B3ZS encoded DS3, HDB3-encoded transmission system when dual-rail input format selected. RNEG contains line code violation indications when single-rail (unipolar) input format enabled. Each line code violation represented RCLK period-wide pulse. dual-rail/single-rail selection controlled FRMR FRMR Configuration Registers. Receive Overhead Mask (ROHM). ROHM indicates position overhead bits nonDS3/E3 based transmission system stream, RDAT. When PLCP formatted signal received, ROHM pulsed once transmission frame, indicates frame alignment. When non-PLCP based signal received, ROHM indicates position each overhead transmission frame. RNEG/ROHM function selection controlled FRMRBP S/UNI-PDH Configuration Register. Both RNEG ROHM sampled rising edge RCLK default, enabled sampled falling edge RCLK. This sampling controlled RCLKINV S/UNI-PDH Control Register. addition, signal polarity control provided RPNINV S/UNI-PDH Control Register.
ROHM
ROHCLK
Output
Receive DS3/E3 Overhead Clock (ROHCLK). ROHCLK active when stream being processed. ROHCLK nominally clock when processing DS3, nominally 1.072 clock when processing G.832 nominally 1.074 clock when processing G.751 ROH, ROHFP updated falling edge ROHCLK.
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PM7345 S/UNI-PDH
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Output
Receive DS3/E3 Overhead Data (ROH). contains overhead bits extracted from received stream; contains overhead bytes (FA1, FA2, extracted from received G.832 stream; contains overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) extracted from received G.751 stream. updated falling edge ROHCLK. Receive DS3/E3 Overhead Frame Position (ROHFP). ROHFP locates individual overhead bits received overhead data stream, ROH. ROHFP high during overhead position stream when processing stream. ROHFP high during first byte when processing G.832 stream. ROHFP high during overhead position when processing G.751 stream. ROHFP updated falling edge ROHCLK. Receive PLCP Overhead Clock (RPOHCLK). RPOHCLK active when PLCP processing enabled. frequency this signal depends selected PLCP format. RPOHCLK nominally 26.7 clock PLCP frame, clock PLCP frame, 33.7 clock based PLCP frame, clock G.751 based PLCP frame. RPOHFP RPOH updated falling edge RPOHCLK. Receive PLCP Overhead Data (RPOH). RPOH contains PLCP path overhead octets (Zn, extracted from received PLCP frame when PLCP layer inframe. When PLCP layer loss frame state, RPOH forced ones. octet data RPOH shifted order from most significant (bit least significant (bit RPOH updated falling edge RPOHCLK.
ROHFP
Output
RPOHCLK
Output
RPOH
Output
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PM7345 S/UNI-PDH
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RPOHFP
Output
Receive PLCP Overhead Frame Position (RPOHFP). RPOHFP locates individual PLCP path overhead bits receive overhead data stream, RPOH. RPOHFP logic while (the most significant bit) path user channel octet (F1)is present RPOH stream. RPOHFP updated falling edge RPOHCLK. Receive Data Link Signal (RDLSIG). mode, RDLSIG contains Path Maintenance Data Link signal from received C-bit Parity stream. RDLSIG affected RNETOP S/UNI-PDH Data Link FERF Control register while mode. G.832 mode, RDLSIG contains data link signal, selected RNETOP bit, from received G.832 stream. G.751 mode, RDLSIG contains National from received G.751 stream RNETOP logic one. RDLSIG updated falling edge RDLCLK. Receive Data Link Clock (RDLCLK). RDLCLK active when G.832 stream being processed. With G.751 stream, RNETOP S/UNI-PDH Data Link FERF Control register must logic RDLCLK active. Receive Cell Indication (RCELL). RCELL pulses once every cell received. RCELL updated using timing derived from receive input clock (RCLK) active minimum RCLK periods. RCELL forced logic when FIFO bypass mode.
RDLSIG
Output
RDLCLK
Output
RCELL
Output
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PM7345 S/UNI-PDH
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Output
Loss Cell Delineation (LCD). signal indicates when cell delineation cannot found. transitions logic when cell delineation (OCD) defect persisted past selected threshold. Once asserted, remains logic until defect been detected past selected threshold. defect state entered when cell delineation state machine SYNC state (please refer Functional Description section explanation cell delineation state machine). indication available register access enabled generate microprocessor interrupt. FIFO Read (FRDB). FRDB reads cell octets from receive FIFO. data enabled FRDATA[7:0] outputs falling edge FRDB. RSOC, REOH, REOC updated rising edge FRDB. Note that when receive FIFO bypassed, FRDB should logic minimize S/UNI-PDH power consumption. Read FIFO Clock (RFCLK). RFCLK used read bytes from synchronous FIFO interface. This interface only available 100-pin PQFP package when synchronous FIFO interface enabled (SYFIFOB tied logic RFCLK must cycle lower instantaneous rate, high enough rate avoid FIFO overflow. RRDENB sampled using rising edge RFCLK. RSOC, RCA, RXPRTY, FRDATA[7:0] updated rising edge RFCLK.
FRDB/
Input
RFCLK
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RRDENB
Input
Receive FIFO Read Enable (RRDENB). This active enable signal used initiate reads from synchronous receive FIFO interface (when SYFIFOB tied logic RRDENB sampled rising edge RFCLK) logic indicates that RSOC FRDATA[7:0] will sampled Alayer current RFCLK cycle next rising edge RFCLK). When RRDENB sampled logic read performed. RRDENB must used conjunction with RFCLK access FIFO high enough instantaneous rate avoid FIFO overflow. RRDENB signal only available 100-pin PQFP package. RRDENB contains integral pull-down resistor.
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RFIFOE/
Output
Receive FIFO Empty (RFIFOE). RFIFOE indicates receive FIFO status. RFIFOE logic when cell-based FIFO empty logic when FIFO contains least cell. RFIFOE timing applicable when using asynchronous FIFO interface S/UNI-PDH (either 84-pin PLCC when SYFIFOB tied logic 100-pin package). Note that with asynchronous FIFO interface RFIFOE transitions from empty full (logic logic write cell boundaries with timing derived from RCLK input. RFIFOE transitions from full empty (logic logic read cell boundaries rising edge FRDB. RFIFOE should treated Alayer purely asynchronous signal. Receive Cell Available (RCA). available 100-pin PQFP package when SYFIFOB tied logic When synchronous FIFO interface used, active high signal logic when cell-based FIFO contains least cell logic when cell-based FIFO empty. enabled transition when FIFO empty (default) when FIFO bytes away from being empty (almost empty), controlled REMPTY4 register bit. transitions rising edges RFCLK. Receive Cell Clock (FRCLK). FRCLK derived from RCLK when receive FIFO bypassed (the FIFOBP S/UNI-PDH Configuration Register logic FRDATA[7:0], LOF, OOF, RSOC updated falling edge FRCLK.
RCA/
FRCLK
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RSOC
Tristate
Receive Start Cell (RSOC). RSOC indicates start octet cell. asserted when first octet read from receive FIFO. RSOC tristateable 100-pin PQFP package when TSEN logic forced tristate while FRDB high receive FIFO bypassed (when SYFIFOB logic while RRDENB sampled high rising edge RFCLK (when SYFIFOB logic RSOC logic value driven while FRDB (asynchronous FIFO interface) while RRDENB sampled logic (synchronous interface). RSOC updated rising edge FRDB RFCLK. When receive FIFO bypassed, RSOC updated falling edge FRCLK. Receive Header (REOH). REOH asserted when fifth octet octet cell read from receive FIFO. REOH tristatable 100-pin PQFP package when TSEN logic forced tristate while FRDB high receive FIFO bypassed (when SYFIFOB logic while RRDENB sampled high rising edge RFCLK (when SYFIFOB logic REOH logic value driven while FRDB (asynchronous FIFO interface) while RRDENB sampled logic (synchronous interface). REOH updated rising edge FRDB RFCLK. PLCP Loss Frame (LOF). asserted while PLCP receiver loss frame state. used indicate valid/invalid status FRDATA[7:0] octets higher layer processing entity while receive FIFO bypassed. updated falling edge FRCLK. REOH/LOF function selection controlled FIFOBP S/UNI-PDH Configuration Register.
REOH/
Tristate
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REOC/
Tristate
Receive Cell (REOC). REOC asserted when 53rd octet octet cell being read from receive FIFO. RSOC tristatable 100-pin PQFP package when TSEN logic forced tristate while FRDB high receive FIFO bypassed (when SYFIFOB logic while RRDENB sampled high rising edge RFCLK (when SYFIFOB logic RSOC logic value driven while FRDB (asynchronous FIFO interface) while RRDENB sampled logic (synchronous interface). REOC updated rising edge FRDB RFCLK. PLCP Frame (OOF). asserted while PLCP receiver frame state. used indicate valid/invalid status FRDATA[7:0] octets higher layer processing entity while receive FIFO bypassed. updated falling edge FRCLK. REOC/OOF function selection controlled FIFOBP S/UNI-PDH Configuration Register.
FRDATA[7] FRDATA[6] FRDATA[5] FRDATA[4] FRDATA[3] FRDATA[2] FRDATA[1] FRDATA[0]
Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate
Receive FIFO Data (FRDATA[7:0]). FRDATA[7:0] contains cell octet that read from receive FIFO. FRDATA[7:0] tristatable 100pin PQFP package when TSEN logic FRDATA[7:0] forced tristate while FRDB high receive FIFO bypassed (when SYFIFOB logic while RRDENB sampled high rising edge RFCLK (when SYFIFOB logic octet read from receive FIFO driven FRDATA[7:0] while FRDB (asynchronous FIFO interface) while RRDENB sampled logic (synchronous interface). FRDATA[7:0] updated falling edge FRCLK when receive FIFO bypassed.
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RXPRTY
Tristate
Receive FIFO Read Data Parity (RXPRTY). RXPRTY only available 100-pin PQFP package. RXPRTY indicates parity byte FRDATA[7:0]. Even parity computed over FRDATA[7:0] bus, depending upon REVEN register setting. REVEN logic even parity calculated; REVEN logic parity calculated. default, RXPRTY indicates parity. RXPRTY tristatable when TSEN logic RXPRTY forced tristate while FRDB high (when SYFIFOB logic while RRDENB sampled high rising edge RFCLK (when SYFIFOB logic parity value driven RXPRTY while FRDB (asynchronous FIFO interface) while RRDENB sampled logic (synchronous interface). Tristate Enable (TSEN). TSEN controls tristatability FRDATA[7:0], RXPRTY, REOH, REOC RSOC pins 100-pin PQFP package. When TSEN logic FRDATA[7:0] bus, RXPRTY, REOH, REOC RSOC tristated either FRDB signal sampled RRDENB signal (depending upon interface selected SYFIFOB). When TSEN logic FRDATA[7:0] bus, RXPRTY, REOH, REOC RSOC always active forced digital logic values. TSEN contains integral pull-up resistor.
TSEN
Input
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FWRB/
Input
FIFO Write (FWRB). FWRB writes cell octets transmit FIFO. data present FWDATA[7:0] written into transmit FIFO rising edge FWRB. TSOC sampled falling edge FWRB. Transmit FIFO Write Clock (TFCLK). TFCLK used write bytes into synchronous transmit FIFO interface. This interface only available 100-pin PQFP package when synchronous FIFO interface enabled (SYFIFOB tied logic TFCLK must cycle lower instantaneous rate. TWRENB, TSOC, TXPRTY, FWDATA[7:0] sampled rising edge TFCLK. updated rising edge TFCLK.
TFCLK
TWRENB
Input
Transmit FIFO Write Enable (TWRENB). This active enable signal used initiate writes into transmit FIFO. TWRENB sampled rising edge TFCLK. When TWRENB sampled logic byte sampled FWDATA[7:0] written transmit FIFO. When TWRENB sampled logic write performed. complete byte cell must written FIFO before inserted into transmission layer. Idle/Unassigned cells inserted when complete cell available. TWRENB signal only available 100-pin PQFP package when SYFIFOB tied logic TWRENB contains integral pull-down resistor. Transmit Cell Indication (TCELL). TCELL pulses once every cell transmitted. TCELL updated using timing derived from transmit input clock (TICLK) active minimum TICLK periods. TCELL forced logic when FIFO bypass mode.
TCELL
Output
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TFIFOFB/
Output
Transmit FIFO Full (TFIFOFB). TFIFOFB indicates transmit FIFO status. depth transmit FIFO controlled using TXCP Control register. When TFIFOFB logic transmit FIFO full cells written into transmit FIFO. TFIFOFB timing applicable when using asynchronous FIFO interface S/UNI-PDH (either 84-pin PLCC when SYFIFOB tied logic 100-pin package). Note that with asynchronous FIFO interface TFIFOFB transitions from empty full/almost full (logic logic rising edge FWRB. TFIFOFB transitions from full empty (logic logic read cell boundaries with timing derived from TICLK input. TFIFOFB should treated Alayer purely asynchronous signal. TFIFOFB also programmed indicate full almost-full through TFULL4 register bit. When TFULL4 logic TFIFOFB transitions from empty almost full, indicating that transmit FIFO accept more than four writes before overflowing. When TFULL4 logic (default), TIFIFOB transitions from empty full, indicating that transmit FIFO accept more writes before overflowing. (cont.)
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TCA/
Output
Transmit Cell Available (TCA). available 100-pin PQFP package when SYFIFOB tied logic When synchronous FIFO interface used, active high signal logic when cell-based transmit FIFO full complete cell written enabled transition when FIFO writes away from being full (almost full) when FIFO full (default), controlled TFULL4 register bit. reduce FIFO latency, FIFO depth which indicates "full" one, two, three four cells FIFODP[1:0] bits TXCP Control register. programmed depth less than four, more than cell written after asserted. transitions rising edges TFCLK. Transmit Cell Clock (FWCLK). FWCLK derived from transmit source clock (TICLK, RCLK determined timing mode selected) when transmit FIFO bypassed (the FIFOBP S/UNI-PDH Configuration Register logic FWDATA[7:0], TSOC sampled rising edge FWCLK.
FWCLK
TSOC
Input
Transmit Start Cell (TSOC). TSOC identifies start cell FWDATA[7:0]. When TSOC logic octet FWDATA[7:0] expected first octet octet cell. necessary TSOC present each cell; internal cell counter flywheels based last occurrence TSOC. TSOC sampled falling edge FWRB asynchronous FIFO interface), TSOC sampled rising edge TFCLK synchronous FIFO interface). TSOC sampled rising edge FWCLK when transmit FIFO bypassed.
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FWDATA[7] FWDATA[6] FWDATA[5] FWDATA[4] FWDATA[3] FWDATA[2] FWDATA[1] FWDATA[0]
Input Input Input Input Input Input Input Input
Transmit FIFO Data (FWDATA[7:0]). FWDATA[7:0] contains cell octet that written transmit FIFO. asynchronous FIFO interface 84-pin PLCC package 100-pin PQFP package when SYFIFOB tied logic FWDATA[7:0] sampled rising edge FWRB. synchronous FIFO interface (i.e. 100pin package with SYFIFOB tied logic FWDATA[7:0] sampled rising edge TFCLK when TWRENB logic FWDATA[7:0] sampled rising edge FWCLK when transmit FIFO bypassed.
TXPRTY
Input
Transmit FIFO Write Data Parity (TXPRTY). TXPRTY only available 100-pin PQFP package. TXPRTY indicates parity byte input FWDATA[7:0] bus. Even parity computed over FWDATA[7:0] bus, depending upon TEVEN register setting, compared value input TXPRTY. TEVEN logic even parity calculated compared; TEVEN logic parity calculated. default, TXPRTY expected indicate parity. When using synchronous FIFO (when SYFIFOB tied logic TXPRTY sampled rising edge TFCLK when TWRENB asserted. When using asynchronous FIFO (when SYFIFOB tied logic TXPRTY sampled rising edge FWRB. computed parity does match value TXPRTY, parity error flagged interrupt generated, enable. TXPRTY contains integral pull-up resistor. Transmit Input Clock (TICLK). TICLK provides transmit direction timing. TICLK externally generated transmission system baud rate clock; internally buffered produce transmit clock output, TCLK, enabled update TPOS/TDAT TNEG/TOHM outputs TICLK rising edge. TICLK maximum frequency MHz.
TICLK
Input
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TIOHM
Input
Transmit Input Overhead Mask (TIOHM). TIOHM indicates position overhead bits transmission system stream, TDAT. TIOHM delayed internally produce TOHM output. When configured operation over DS1, DS3, transmission system sublayer, TIOHM required, should logic When configured other transmission systems, TIOHM logic each overhead position. TIOHM logic transmission system contains overhead bits. TIOHM sampled rising edge TICLK. Transmit Output Clock (TCLK). TCLK provides transmit direction timing. TCLK buffered version TICLK enabled update TPOS/TDAT TNEG/TOHM outputs rising falling edge.
TCLK
Output
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TPOS/
Output
Transmit Positive Pulse (TPOS). TPOS contains positive pulses transmitted B3ZSencoded DS3, HDB3-encoded transmission system when dual-rail output format selected. TPOS contains entire stream when single-rail (unipolar) input format enabled. dual-rail/single-rail selection controlled TUNI S/UNI-PDH Control Register. Transmit Data (TDAT). TDAT contains transmit transmission system stream when non-DS3/E3 based transmission system processed (for example TDAT contain stream). TPOS/TDAT function selection controlled FRMRBP S/UNI-PDH Configuration Register. Both TPOS TDAT updated falling edge TCLK default, enabled updated rising edge TCLK. This sampling controlled TCLKINV S/UNI-PDH Control Register. addition, output signal polarity control provided TPNINV S/UNI-PDH Control Register. Finally, both TPOS TDAT updated rising edge TICLK, enabled TICLK S/UNIPDH Control Register.
TDAT
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TNEG/
Output
Transmit Negative Pulse (TNEG). TNEG contains negative pulses transmitted B3ZSencoded DS3, HDB3-encoded transmission system when dual-rail output format selected. TNEG indicates location Mframe boundary DS3, indicates position frame boundary when single-rail (unipolar) input format enabled. dualrail/single-rail selection controlled TUNI S/UNI-PDH Control Register. Transmit Overhead Mask (TOHM). TOHM indicates position overhead bits (non-payload bits) transmit transmission system stream, TDAT. When internally masked signal transmitted (the SPLT cleared), TOHM indicates frame alignment positions based internal time slot counter synchronized TIOHM pulse. When externally masked signal transmitted (the SPLT set), TOHM delayed version TIOHM input, indicates position each overhead transmission frame. TNEG/TOHM function selection controlled FRMRBP S/UNI-PDH Configuration Register. Both TNEG TOHM updated falling edge TCLK default enabled updated rising edge TCLK. This controlled TCLKINV S/UNIPDH Control Register. addition, output signal polarity control provided TPNINV S/UNI-PDH Control Register. Finally, both TNEG TOHM updated rising edge TICLK, enabled TICLK S/UNI-PDH Control Register.
TOHM
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TOHCLK
Output
Transmit Overhead Clock (TOHCLK). TOHCLK active when stream being processed. TOHCLK nominally clock DS3, nominally 1.072 clock G.832 nominally 1.074 clock G.751 TOHFP updated falling edge TOHCLK. TOH, TOHINS sampled rising edge TOHCLK. Transmit DS3/E3 Overhead Data (TOH). contains overhead bits that inserted transmit stream; contains overhead bytes (FA1, FA2, mask, that inserted transmit G.832 stream; contains overhead bits (RAI, National Use, Stuff Indication, Stuff Opportunity) that inserted transmit G.751 stream. sampled rising edge TOHCLK. Transmit DS3/E3 Overhead Frame Position (TOHFP). TOHFP used align individual overhead bits transmit overhead data stream, TOH, M-frame frame. DS3, TOHFP high during overhead position stream. G.832 TOHFP high during first byte. G.751 TOHFP high during overhead position stream. TOHFP updated falling edge TOHCLK. Transmit DS3/E3 Overhead Insertion (TOHINS). TOHINS controls insertion overhead bits from input. When TOHINS high, associated overhead stream inserted transmitted frame. When TOHINS low, overhead generated inserted internally. TOHINS sampled rising edge TOHCLK.
Input
TOHFP
Output
TOHINS
Input
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TDLSIG
Input
Transmit Data Link Signal (TDLSIG). mode, TDLSIG contains Path Maintenance Data Link signal that inserted C-bit Parity stream TNETOP S/UNI-PDH Data Link Control register logic one. G.832 mode, TDLSIG contains data link signal, selected TNETOP bit, that inserted transmit G.832 stream. G.751 mode, TDLSIG contains National that inserted G.751 stream TNETOP logic one. TDLSIG sampled rising edge TDLCLK. TDLSIG contains integral pull-up resistor. Transmit Data Link Clock (TDLCLK). TDLCLK active when G.751 stream being processed, TNETOP S/UNI-PDH Data Link Control register logic one. TDLCLK active when G.832 stream being processed, independent TNETOP bit. Transmit PLCP Overhead Clock (TPOHCLK). TPOHCLK active when PLCP processing enabled. TPOHCLK nominally 26.7 clock PLCP frame, clock PLCP frame, 33.7 clock based PLCP frame, clock G.751 based PLCP frame. TPOHFP updated falling edge TPOHCLK. TPOH, TPOHINS sampled rising edge TPOHCLK. Transmit PLCP Overhead Data (TPOH). TPOH contains PLCP path overhead octets (Zn, which inserted transmit PLCP frame. octet data TPOH shifted order from most significant (bit least significant (bit 8).TPOH sampled rising edge TPOHCLK.
TDLCLK
Output
TPOHCLK
Output
TPOH
Input
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TPOHFP
Output
Transmit Path Overhead Frame Position (TPOHFP). TPOHFP output locates individual PLCP path overhead bits transmit overhead data stream, TPOH. TPOHFP logic while (the most significant bit) path user channel octet (F1) present TPOH stream. TPOHFP updated falling edge TPOHCLK. Transmit Path Overhead Insertion (TPOHINS). TPOHINS controls insertion PLCP overhead octets TPOH input. When TPOHINS logic associated overhead TPOH stream inserted transmit PLCP frame. When TPOHINS logic PLCP path overhead generated inserted internally. TPOHINS sampled rising edge TPOHCLK. Note, when operating G.751 PLCP mode, bits octet should manipulated.
TPOHINS
Input
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C13/CADD
Input
Transmit Stuff Control (C13/CADD). C13/CADD controls stuffing when configured G.751 PLCP frame formats when 8KREF S/UNI-PDH Control Register logic When PLCP format enabled, C13/CADD determines whether nibble trailer next stuff opportunity. When logic nibble trailer used. When logic nibble trailer used. When G.751 PLCP format enabled, C13/CADD determines whether subtract octet from internally generated octet stuff pattern next stuff opportunity. When logic octet subtracted from next octet trailer. When logic octet added next octet trailer.
8KREF
C13/CADD internally synchronized thus asynchronous. Reference Input (8KREF). PLCP frame rate locked external reference applied this input when 8KREF S/UNI-PDH Control Register logic internal phase-frequency detector compares transmit PLCP frame rate with externally applied reference adjusts PLCP frame rate taking control over internal C13/CADD signal. 8KREF input must transition high once every correct operation. 8KREF input treated asynchronous signal must "glitch-free". minimum high period 8KREF Only rising edge used.
SYFIFOB
Input
Synchronous FIFO Enable (SYFIFOB). This active signal selects between synchronous asynchronous FIFO interfaces system side. This signal available only 100-pin PQFP package must tied enable synchronous FIFO interface. SYFIFOB available 84-pin PLCC package pulled logic internally integral pull-up resistor, thus selecting asynchronous FIFO interface.
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INTB
Output
Interrupt (INTB). active interrupt activated when unmasked interrupt detected internal interrupt sources. INTB signal removed when interrupt acknowledged reading associated interrupt status register. INTB output open drain. Chip Select (CSB). active chip select enable S/UNI-PDH register accesses. required (i.e., register accesses controlled using signals only), must connected inverted version RSTB input. Bidirectional Data (D[7:0]). D[7:0] used during S/UNI-PDH read write accesses.
Input
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Input
Read Enable (RDB). active read enable pulsed enable S/UNI-PDH register read access. S/UNI-PDH drives D[7:0] with contents addressed register while both low. Write Strobe (WRB). active write strobe pulsed enable S/UNI-PDH register write access. D[7:0] contents clocked into addressed normal mode register rising edge while low. Address Latch Enable (ALE). address latch enable latches address bus, A[7:0], when logic When logic address latches transparent. contains integral pullup resistor. Reset (RSTB). active schmitt triggered reset asynchronously resets S/UNI-PDH. RSTB contains integral pullup resistor. minimum assertion interval nsec recommended.
Input
Input
RSTB
Input
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A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] VDDO[0] VDDO[1] VDDO[2] VDDO[3] VDDI[0] VDDI[1] VDDI[2] VSSO[0] VSSO[1] VSSO[2] VSSO[3] VSSO[4] VSSI[0] VSSI[1] VSSI[2]
Input Input Input Input Input Input Input Input Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground
Address (A[7:0]). address (A[7:0) selects specific registers during accesses.
Ring Power (VDDO[3:0]). These pins must connected common, well decoupled supply together with VDDI[2:0] pins. Care must taken avoid coupling noise induced VDDO pins into VDDI pins. Core Power (VDDI[2:0]). These pins must connected common, well decoupled supply together with VDDO[3:0] pins. Ring Ground (VSSO[4:0]). These pins must connected common ground together with VSSI[2:0] pins. Care must taken avoid coupling noise induced VSSO pins into VSSI pins. Core Ground (VSSI[2:0]). These pins must connected common ground together with VSSO[4:0] pins.
Notes Description: Most S/UNI-PDH inputs bidirectionals present minimum capacitive loading operate logic levels. high speed inputs, RCLK, RPOS/RDAT, RNEG/ROHM, TICLK, C13/CADD, TIOHM inputs operate CMOS logic levels. ALE, RSTB, TSEN, TDLSIG, TXPRTY, SYFIFOB inputs have pullups. RRDENB TWRENB inputs have integral pull-down resistors. RSTB uses schmitt trigger input. TCLK, TPOS/TDAT, TNEG/TOHM, RSOC, REOH, REOC, RFIFOE, TFIFOFB outputs, FRDATA[7:0] RXPRTY tristate outputs have slew-rate limited drive capability. D[7:0] bidirectionals INTB have slew-rate limited drive capability. other S/UNI-PDH digital outputs have slew-rate limited drive capability.
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VSSO VSSI ground pins internally connected together. Failure connect these pins externally cause malfunction damage S/UNI-PDH. VDDO VDDI power pins internally connected together. Failure connect these pins externally cause malfunction damage S/UNI-PDH.
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FUNCTIONAL DESCRIPTION Framer Framer (T3-FRMR) Block integrates circuitry required decoding B3ZS-encoded signal framing resulting stream. T3-FRMR directly compatible with C-bit parity applications. T3-FRMR decodes B3ZS-encoded signal provides indications line code violations. B3ZS decoding algorithm definition independently chosen through software. loss signal (LOS) defect also detected B3ZS encoded streams. declared when inputs RPOS RNEG contain zeros consecutive RCLK cycles. removed when ones density RPOS and/or RNEG greater than RCLK cycles. framing algorithm examines five F-bit candidates simultaneously. When least discrepancy occurred each candidate, algorithm examines next five candidates. When single F-bit candidate remains set, first supposed M-subframe examined M-frame alignment signal (i.e., Mbits, following pattern). Framing declared, outof-frame removed, M-bits correct three consecutive M-frames while discrepancies have occurred F-bits. During examination M-bits, X-bits P-bits ignored. algorithm gives maximum average reframe time While T3-FRMR synchronized M-frame, F-bit M-bit positions stream examined. out-of-frame defect detected when F-bit errors consecutive F-bits observed selected M3O8 FRMR Configuration Register), when more M-bit errors detected consecutive M-frames. M-bit error criteria disabled MBDIS Framer Configuration register. consecutive F-bits out-of-frame ratio provides more robust operation, presence high error rate, than consecutive F-bits ratio. Either out-of-frame criteria allows out-of-frame defect detected quickly when M-subframe alignment patterns optionally, when M-frame alignment pattern lost. Also while in-frame, line code violations, M-bit F-bit framing errors, P-bit parity errors indicated. When C-bit parity mode enabled, both C-bit parity errors block errors indicated. These error indications, well line code violation excessive zeros indication, accumulated over second intervals with Performance Monitor (PMON). Note that framer off-line
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framer, indicating both COFA events. Even indicated, framer will continue indicating performance monitoring information based previous frame alignment. Three maintenance signals alarm condition, alarm indication signal, idle signal) detected T3-FRMR. maintenance detection algorithm employs simple integrator with slope that based occurrence "valid" M-frame intervals. alarm, M-frame said "valid" interval contains defect, defined occurrence event during that M-frame. IDLE, M-frame interval "valid" contains IDLE, defined occurrence less than discrepancies expected signal pattern (1010. AIS, 1100. IDLE) while valid frame alignment maintained. This discrepancy threshold ensures detection algorithms operate presence 10-3 error rate. AIS, expected pattern selected framed "1010" signal; framed arbitrary signal C-bits zero; framed "1010" signal C-bits zero; framed all-ones signal (with overhead bits ignored); unframed all-ones signal (with overhead bits equal ones). Each "valid" M-frame causes associated integration counter increment; "invalid" M-frames cause decrement. With "slow" detection option, RED, AIS, IDLE declared when respective counter saturates 127, which results detection time 13.5 With "fast" detection option, RED, AIS, IDLE declared when respective counter saturates which results detection time 2.23 (i.e., times maximum average reframe time). RED, AIS, IDLE removed when respective counter decrements Valid X-bits extracted T3-FRMR provide indication receive failure (FERF). FERF defect detected extracted X-bits equal logic (X1=X2=0); defect removed extracted X-bits equal logic (X1=X2=1). X-bits equal, FERF status remains previous state. extracted FERF status buffered M-frames before being reported within FRMR Status register. This buffer ensures better than 99.99% chance freezing FERF status correct value during occurrence frame. When C-bit parity application enabled, both alarm control (FEAC) channel path maintenance data link extracted. Codes FEAC channel detected Oriented Code Detector (RBOC). HDLC messages Path Maintenance Data Link received Data Link Receiver (RFDL) brought RDLSIG output with associated clock RDLCLK. RDLSIG RDLCLK available only 100-pin PQFP package. T3-FRMR enabled automatically assert indication outgoing transmit stream upon detection combination LOS, RED,
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AIS. When C-Bit parity selected, T3-FRMR automatically inserts C-Bit parity FEBE upon detection receive C-Bit parity error. T3-FRMR extracts entire overhead bits M-frame) using output, along with ROHCLK, ROHFP outputs. T3-FRMR configured generate interrupts error events status changes. sources interrupts masked acknowledged internal registers. Internal registers also used configure T3-FRMR. Access these registers generic microprocessor bus. Framer Framer (E3-FRMR) Block integrates circuitry required decoding HDB3-encoded signal framing resulting stream. E3-FRMR directly compatible with G.751 G.832 applications. E3-FRMR searches frame alignment incoming serial stream based either G.751 G.832 formats. Regardless format selected, E3-FRMR expects selected framing pattern error-free three consecutive frames before declaring INFRAME. Once frame alignment established, incoming data continuously monitored framing errors byte interleaved parity errors G.832 format). While in-frame, E3-FRMR also extracts various overhead bytes processes them according framing format selected: G.832 format, E3-FRMR extracts: Trail Trace bytes outputs them serial stream further processing Trail Trace Buffer (TTB) block; FERF indicates alarm when FERF logic consecutive frames. FERF indication removed when FERF logic consecutive frames; FEBE outputs accumulation PMON; Payload Type bits buffers them that they read microprocessor; Timing Marker asserts Timing Marker indication when value extracted been same state consecutive frames;
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Network Operator byte presents serial stream further processing RFDL block when RNETOP S/UNI-PDH Data Link FERF Control register logic otherwise, byte brought RDLSIG output with associated clock RDLCLK. RDLSIG RDLCLK available only 100-pin PQFP package. When configured Tandem Connection Maintenance, bits Network Operator byte extracted presented overhead output and, optionally, presented RFDL. When configured Tandem Connection, first four bits byte identify incoming error count (IEC) accumulated PMON. last four bits byte output overhead stream and, optionally, presented RFDL. However, envisioned that Tandem Connection Maintenance mode will used S/UNI-PDH applications; General Purpose Communication Channel byte presents RFDL when RNETOP S/UNI-PDH Data Link FERF Control register logic otherwise, byte brought RDLSIG output with associated clock RDLCLK. RDLSIG RDLCLK available only 100-pin PQFP package. G.751 mode, E3-FRMR extracts: Remote Alarm Indication (bit frame) indicates Remote Alarm when logic consecutive frames. Similarly, Remote Alarm removed when logic consecutive frames; National reserved (bit frame) presents serial stream further processing RFDL when RNETOP S/UNIPDH Data Link FERF Control register logic otherwise, brought RDLSIG output with associated clock RDLCLK. RDLSIG RDLCLK available only 100-pin PQFP package. Optionally, interrupt generated when National changes state. Further, while in-frame, E3-FRMR indicates position overhead bits incoming digital stream ATMF/SPLR block. G.751 mode, tributary justification bits optionally identified either overhead payload payload mappings that take advantage full bandwidth. E3-FRMR declares loss frame alignment framing pattern error four consecutive frames. E3-FRMR "off-line" framer, where frame alignment indications, overhead indications, overhead processing continue based previous alignment. Once framer determined frame alignment, out-of-frame indication removed COFA indication declared alignment differs from previous alignment.
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E3-FRMR detects presence incoming data stream when less than zeros frame detected while framer G.832 mode, when less than zeros frame detected while G.751 mode. This algorithm provides probability detecting presence 10-3 92.9% G.832 98.0% G.751. Loss signal declared when marks have been received consecutive periods. Loss signal deasserted after periods during which there sequence four consecutive zeros. E3-FRMR also enabled automatically assert RAI/FERF indication outgoing transmit stream upon detection combination LOS, AIS. E3-FRMR also enabled automatically insert G.832 FEBE upon detection receive BIP-8 errors. PMON Performance Monitor Accumulator Performance Monitor (PMON) Block interfaces directly with either Framer (T3-FRMR) accumulate line code violation (LCV) events, parity error (PERR) events, path parity error (CPERR) events, block error (FEBE) events, framing error (FERR) events using saturating counters; E3-FRMR accumulate LCV, PERR G.832 mode), FEBE, FERR, incoming error counts (IEC) G.832 Tandem Connection mode. off-line nature Framers, PMON continues accumulate performance meters even while T3-FRMR E3-FRMR declared OOF. When accumulation interval signalled write PMON register address space write CPPM register address space, PMON transfers current counter values into microprocessor accessible holding registers resets counters begin accumulating error events next interval. counters reset such manner that error events occurring during reset period missed. When counter data transferred into holding registers, interrupt generated, providing interrupt enabled. holding registers have been read since last interrupt, overrun status set. addition, register provided indicate changes PMON counters since last accumulation interval. RBOC Bit-Oriented Code Detector Bit-Oriented Code Detector only C-bit Parity mode.
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Bit-Oriented Code Detector (RBOC) Block detects presence possible bit-oriented codes (BOCs) contained C-bit parity far-end alarm control (FEAC) channel. 64th code ("111111") similar HDLC flag sequence ignored. Bit-oriented codes (BOCs) received FEAC channel 16-bit sequences each consisting ones, zero, code bits, trailing zero ("111111110xxxxxx0"). BOCs validated when repeated least times. RBOC enabled declare code valid been observed times times, specified RBOC Configuration/Interrupt Enable Register. RBOC declares that code removed code sequences containing code values different from detected code received moving window code periods. Valid BOCs indicated through RBOC Interrupt Status Register. bits ones ("111111") when valid code detected. RBOC programmed generate interrupt when detected code been validated when code removed. RFDL Facility Data Link Receiver Facility Data Link Receiver (RFDL) Block microprocessor peripheral used receive LAPD/HDLC frames C-bit parity Path Maintenance Data Link, G.832 Network Requirement byte General Purpose data link (selectable using RNETOP S/UNI-PDH Data Link FERF Control register), G.751 Network bit. RFDL detects change from flag characters first byte data, removes stuffed zeros incoming data stream, receives frame data, calculates CRC-CCITT frame check sequence (FCS). Received data placed into 4-byte FIFO buffer. RFDL Status Register contains bits which indicate overrun, message, flag detected, buffered data available. message, RFDL Status Register also indicates status number valid bits final data byte. Interrupts generated when one, three (programmable count) bytes stored FIFO buffer. Interrupts also generated when terminating flag sequence, abort sequence, FIFO buffer overrun detected.
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SPLR PLCP Layer Receiver PLCP Layer Receiver (SPLR) Block integrates circuitry support DS1, DS3, G.751 PLCP frame processing. SPLR provides framing PLCP based transmission formats. SPLR frames DS1, DS3, G.751 based PLCP frames with maximum average reframe times respectively. Framing declared (out frame removed) upon finding valid, consecutive sets framing octets valid sequential path overhead identifier (POHID) octets. While framed, POHID octets examined. declared when error detected both octets when consecutive POHID octets found error. declared when state persists more than DS1, DS3, G.751 PLCP formats respectively. When cleared, counter decremented rate 1/12 (DS3 PLCP), 1/10 (E1, PLCP) 1/9(G.751 PLCP) incrementing rate. thus removed when in-frame state persists more than signal, signal, signal, G.751 signal. When declared, PLCP reframe initiated. When frame, SPLR extracts path overhead octets outputs them serially output RPOH, along with RPOHCLK RPOHFP outputs. Framing octet errors path overhead identifier octet errors indicated frame errors. interleaved parity errors block errors indicated. yellow signal extracted accumulated indicate yellow alarms. Yellow alarm declared when consecutive yellow signal bits logical removed when consecutive received yellow signal bits logical octet examined maintain nibble alignment with incoming transmission system sublayer stream.
ATMF ACell Delineator ACell Delineator (ATMF) Block integrates circuitry support HCS-based cell delineation non-PLCP based transmission formats. ATMF block accepts serial cell stream from upstream transmission system sublayer entity (such T3-FRMR E3-FRMR Block) converts stream into byte serial format. Cell delineation used locate cell boundaries. Cell delineation process framing Acell boundaries using header check sequence (HCS) field found Acell header. CRC-8 calculation over first octets Acell header. When performing delineation, correct calculations assumed indicate cell boundaries.
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ATMF performs sequential hunt correct sequence. This state referred HUNT state. When correct found, ATMF locks particular cell boundary assumes PRESYNC state. This state verifies that previously detected pattern false indication. pattern false indication then incorrect should received within next DELTA cells. that point transition back HUNT state executed. incorrect found this PRESYNC period then transition SYNC state made. this state synchronization relinquished until ALPHA consecutive incorrect patterns found. such event transition made back HUNT state. state diagram cell delineation process shown figure Figure Cell delineation State Diagram
correct (bit bit)
HUNT
Incorrect (cell cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell cell)
SYNC
DELTA consecutive correct HCS's (cell cell)
values ALPHA DELTA determine robustness delineation method. ALPHA determines robustness against false misalignments errors. DELTA determines robustness against false delineation synchronization process. ALPHA chosen DELTA chosen recommended ITU-T Recommendation I.432. These values result maximum average time frame stream carrying Acells directly mapped into information payload. Loss cell delineation (LCD) detected counting number incorrect cells while HUNT state. counter value stored RXCP Count Threshold register. threshold default value which results G.832 application detection time G.751 application detection time
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application detection time application detection time application detection time counter value zero, output signal asserted every incorrect cell. RXCP Receive Cell Processor Receive Cell Processor (RXCP) Block integrates circuitry support cell payload descrambling, header check sequence (HCS) verification idle/unassigned cell filtering. RXCP operates upon delineated cell stream. PLCP based transmissions systems, cell delineation performed SPLR. non-PLCP based transmission systems, cell delineation performed ATMF. Framing status indications from these blocks ensure that cells written RXFF while SPLR loss frame state, cells written RXFF while ATMF HUNT PRESYNC states. RXCP descrambles cell payload field using self synchronizing descrambler with polynomial header portion cells descrambled. Note that cell payload scrambling optional S/UNI-PDH, required ITU-T Recommendation I.432. AForum specification requires that cell payloads unscrambled physical layer interface (however, discussions ongoing make scrambling requirement future). CRC-8 calculation over first octets Acell header. RXCP verifies received using accumulation polynomial, coset polynomial added (modulo received octet before comparison with calculated result required AForum specification, ITU-T Recommendation I.432. RXCP programmed drop cells containing error filter cells based and/or octet cell header. Filtering according particular and/or octet header pattern programmable through RXCP configuration/control registers. More precisely, filtering performed when filtering enabled when errors found when checking enabled. Otherwise, cells passed regardless error conditions. Cells blocked pattern invalid filtering 'Match Pattern' 'Match Mask' registers programmed with certain blocking pattern. Idle cells automatically filtered. they required filtered, then that filtering criterion (i.e. Null cell pattern) must programmed through IDLE/Unassigned Cell Pattern Mask registers. direct mapped PLCP mapped Acells, Null cells (Idle cells) identified standardized header pattern 'H00, 'H00, 'H00 'H01 first octets followed valid octet. When operating DQDB system
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PLCP 'Null cell' (Idle cell) slots identified standardized header pattern 'B0xxxxxx, 'H00, 'H00, 'H00 first octets followed valid octet. "don't care" bits first byte header handled leaving these bits cleared appropriate header Idle/Unassigned Cell Mask register. While cell delineation state machine SYNC state, verification circuit implements state machine shown "Figure Verification State Diagram." normal operation, verification state machine remains 'Correction' state. Incoming cells containing errors passed receive FIFO. Incoming single-bit errors corrected, resulting cell passed FIFO. Upon detection single-bit error multi-bit error, state machine transitions 'Detection' state. programmable hysteresis provided when dropping cells based errors. When cell with error detected, RXCP programmed continue discard cells until (where cells received with correct HCS. value selected writing DETHYST[1:0] bits located RXCP Framing control register (0x41H). cell discarded (see figure Note that dropping cells errors only occurs while ATMF SYNC state (for non-PLCP based transmission systems), while SPLR in-frame state (for PLCP based transmission systems).
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Figure
Verification State Diagram
ADELINEATION SYNC STATE
ALPHA consecutive incorrect HCS's HUNT state)
Multi-bit Error Detected (Cell discarded) Cell Accepted Correction
Single-bit Error Detected (Error corrected cell accepted) Detection Cell Discarded
DELTA consecutive correct HCS's (From PRESYNC state)
Errors Detected Consecutive Cells (M'th Cell Accepted)
RXFF Receive FIFO Receive FIFO (RXFF) provides FIFO management S/UNI-PDH receive cell interface. receive FIFO contains four cells. FIFO provides cell rate decoupling function between transmission system physical layer Alayer. general, management functions include filling receive FIFO, indicating when receive FIFO contains cells, maintaining receive FIFO read write pointers, detecting FIFO overrun underrun conditions. When using asynchronous FIFO interface 84-pin PLCC, 100-pin PQFP when SYFIFOB tied high), FIFO automatically reset upon detection overrun underrun condition. four cells lost during FIFO reset operation. FIFO overruns underruns indicated maskable interrupt register bits. This asynchronous interface also indicates FIFO status (RFIFOE), start cell (RSOC), cell header (REOH), cell (REOC) when data read from receive FIFO using FRDB. FIFO status changes from empty full write cell boundaries with timing
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PM7345 S/UNI-PDH
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derived from receive line clock (RCLK). FIFO status changes from full empty almost empty, when REMPTY4 logic read cell boundaries with timing aligned FIFO read clock (FRDB). synchronous FIFO interface provided 100-pin PQFP package when SYFIFOB tied logic This interface "UTOPIA" compliant accepts read clock (RFCLK) read enable signal (RRDENB). receive FIFO output (FRDATA[7:0]) tristated when RRDENB logic enabled TSEN pin. interface indicates start cell (RSOC), cell header (REOH), cell (REOC), receive cell available status (RCA) when data read from receive FIFO (using rising edges RFCLK while RRDENB logic status changes from available unavailable when FIFO byte reads away from being empty when FIFO empty, when REMPTY4 logic This interface also indicates FIFO overruns underruns maskable interrupt register bits, but, unlike asynchronous interface, further read accesses while logic ignored (i.e., FIFO reset FIFO underrun). FIFO still reset FIFO overrun, causing cells lost. 9.10 CPPM Cell PLCP Performance Monitor Cell PLCP Performance Monitor (CPPM) Block interfaces directly with RXCP, SPLR, TXCP accumulate interleaved parity error events, framing octet error events, block error events, header check sequence error events, number received unassigned/idle cells, number received assigned cells, number transmitted assigned cells saturating counters. When PLCP framer (SPLR) declares loss frame when Acell delineator (ATMF) declares delineation, interleaved parity error events, framing octet error events, block error events, header check sequence error events counted. When accumulation interval signalled write PMON register address space write CPPM register address space, CPPM transfers current counter values into holding registers resets counters begin accumulating error events next interval. counters reset such manner that error events occurring during reset period missed. 9.11 Transmitter Transmitter (T3-TRAN) Block integrates circuitry required insert overhead bits into stream produce B3ZS-encoded signal. T3-TRAN directly compatible with C-bit parity formats.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
Status signals such receive failure (FERF), alarm indication signal, idle signal inserted when their transmission enabled internal register bits. FERF also automatically inserted detection combination LOS, RED, T3-FRMR. valid pair P-bits automatically calculated inserted T3-TRAN. When C-bit parity mode selected, path parity bits, block error (FEBE) indications automatically inserted. When enabled C-bit parity operation, FEAC channel sourced XBOC bit-oriented code transmitter. TNETOP S/UNI-PDH Data Link FERF Control register controls source path maintenance data link. TNETOP logic path maintenance data link messages sourced XFDL data link transmitter. TNETOP logic path maintenance data link messages sourced from TDLSIG input with associated clock TDLCLK. TDLSIG TDLCLK only available 100-pin PQFP package. When enabled operation, C-bits forced logic with exception C-bit Parity (first C-bit first M-subframe), which forced toggle every M-frame. T3-TRAN supports diagnostic modes which inserts parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, line code violations, all-zeros. User control each overhead bits frame provided. Overhead bits inserted bit-by-bit basis from user supplied data stream. overhead clock kHz) overhead alignment output provided allow control user provided stream. 9.12 Transmitter Transmitter (E3-TRAN) Block integrates circuitry required insert overhead bits into stream produce HDB3-encoded signal. E3-TRAN directly compatible with G.751 G.832 framing formats. E3-TRAN generates frame alignment signal inserts into incoming serial stream based either G.751 G.832 formats alignment pulse applied SPLT block. overhead status bits each frame format individually controlled register bits transmit overhead stream. While certain framing format modes, E3-TRAN generates various overhead bytes according following: G.832 format, E3-TRAN:
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
inserts BIP-8 byte calculated over preceding frame; inserts Trail Trace bytes through Trail Trace Buffer (TTB) block; inserts FERF register optionally, when E3-FRMR declares OOF, when loss cell delineation (LCD) defect declared; inserts FEBE bit, which logic when more BIP-8 errors detected receive framer. there BIP-8 errors indicated E3-FRMR, E3-TRAN sets FEBE logic inserts Payload Type bits based register value microprocessor; inserts Tributary Unit multiframe indicator bits either overhead stream register values microprocessor; inserts Timing Marker register bit; inserts Network Operator byte from XFDL block when TNETOP S/UNI-PDH Data Link FERF Control register logic otherwise, byte sourced overhead stream TDLSIG with associated clock TDLCLK. TDLSIG TDLCLK only available 100-pin PQFP package. Network Operator byte split into nibbles: upper nibble supporting Tandem Connection operation lower nibble supporting half rate datalink. bits encoded zero. S/UNI-PDH applications expected require Tandem Connection; therefore, bits Network Operator byte available datalink; inserts General Purpose Communication Channel byte from XFDL block when TNETOP S/UNI-PDH Data Link FERF Control register logic otherwise, byte sourced overhead stream TDLSIG with associated clock TDLCLK. TDLSIG TDLCLK only available 100-pin PQFP package. G.751 mode, E3-TRAN inserts Remote Alarm Indication (bit frame) either register optionally, when E3-FRMR declares OOF; inserts National reserved (bit frame) either fixed value through register from XFDL block when TNETOP S/UNI-PDH Data Link FERF Control register logic otherwise, sourced overhead stream TDLSIG with associated clock TDLCLK. TDLSIG TDLCLK only available 100-pin PQFP package. optionally identifies tributary justification bits stuff opportunity bits either overhead payload SPLT payload mappings that take advantage full bandwidth. Further, E3-TRAN provide insertion errors framing pattern parity bits, insertion single line code violations diagnostic purposes.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
9.13 XBOC Oriented Code Generator Oriented Code Generator (XBOC) Block transmits possible oriented codes (BOC) C-bit parity Alarm Control (FEAC) channel. 16-bit sequence consisting ones, zero, code bits, trailing zero (111111110xxxxxx0) which repeated long code 111111. code transmitted programmed writing XBOC Code Register. 64th code (111111) similar HDLC idle sequence used disable transmission oriented codes. When transmission disabled, FEAC channel ones. 9.14 XFDL Facility Data Link Transmitter Facility Data Link Transmitter (XFDL) provides serial data link C-bit parity path maintenance data link DS3, serial Network Operator byte General Purpose datalink G.832 National datalink G.751 XFDL used under microprocessor control transmit HDLC data frames. performs data serialization, generation, zero-bit stuffing, well flag, abort sequence insertion. Upon completion message, CRC-CCITT frame check sequence (FCS) appended, followed flags. XFDL Transmit Data register underflows, abort sequence automatically transmitted. When enabled, XFDL continuously transmits flags (01111110). Data bytes transmitted written into XFDL Transmit Data Register. After parallel-to-serial conversion each data byte, interrupt generated signal microprocessor write next byte. After last data frame byte, insertion been enabled), flag insertion been enabled) transmitted. XFDL then returns transmission flag sequences. there more than five consecutive ones transmit data data, zero stuffed into serial data output. This prevents unintentional transmission flag abort sequences. Abort characters continuously transmitted time setting control bit. During transmission, underrun situation occur data written XFDL Transmit Data register before previous byte been depleted. this case, abort sequence transmitted, controlling processor notified signal. When XFDL disabled, logical inserted path maintenance data link.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
9.15 SPLT SMDS PLCP Layer Transmitter SMDS PLCP Layer Transmitter (SPLT Block integrates circuitry support DS1, DS3, G.751 based PLCP frame insertion. SPLT automatically inserts framing (A1, path overhead identification (POHID) octets provides registers automatic generation octets. Registers provided path user channel octet (F1) path status octet (G1). interleaved parity octet (B1) FEBE subfield automatically inserted. DQDB management information octets, generated. type type patterns described TA-TSY-000772 automatically inserted. type page counter reset using register SPLT Configuration register. Note that this feature required AForum compliant UNI. this application, octets must zeros. cycle/stuff counter octet, controlled using C13/CADD input, fixed stuffing pattern inserted. looped timing operating mode provided where transmit PLCP timing derived from received timing. this mode, stuffing generated based received stuffing pattern determined SPLR block. When PLCP format enabled, pattern inserted. When PLCP format enabled, octet indicates phase nibble stuffing opportunity cycle. During frame three frame cycle, pattern inserted octet, indicating nibble trailer length. During frame two, pattern inserted, indicating nibble trailer length. During frame three, pattern inserted, indicating nibble trailer length respectively. nibble trailer binary value 1100. When configured G.751 PLCP frame format, octet used indicate number octets stuffed trailer. following table shows octet pattern each possible octet stuff lengths: Stuff Length C1(Hex)
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
SPLT block generates stuff length pattern octets determined phase alignment start G.751 frame start PLCP frame. stuff length incremented decremented depending value C13/CADD input. C13/CADD input provisioned loop time PLCP transmit frame externally applied reference. growth octets 00H. octets inserted from external device path overhead stream input, TPOH. 9.16 TXCP Transmit Cell Processor Transmit Cell Processor (TXCP) Block integrates circuitry support Acell payload scrambling, header check sequence (HCS) generation, idle/unassigned cell generation. TXCP scrambles cell payload field using self synchronizing scrambler with polynomial header portion cells scrambled. Note that cell payload scrambling optional S/UNI-PDH, required ITU-T Recommendation I.432. AForum specification requires that cell payloads unscrambled physical layer interface (however discussions ongoing make scrambling requirement future). generated using polynomial, coset polynomial added (modulo calculated octet required AForum specification, ITU-T Recommendation I.432. resultant octet optionally overwrites octet transmit cell. When transmit FIFO empty, TXCP inserts idle/unassigned cells. idle/unassigned cell header fully programmable using five internal registers. Similarly, octet information field programmed with repeating pattern using internal register. 9.17 TXFF Transmit FIFO Transmit FIFO (TXFF) provides FIFO management S/UNI-PDH transmit cell interface. transmit FIFO contains four cells. FIFO depth programmed four, three, two, cells. FIFO provides cell rate decoupling function between transmission system physical layer Alayer.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
general, management functions include emptying cells from transmit FIFO, indicating when transmit FIFO full, maintaining transmit FIFO read write pointers detecting FIFO overrun condition. When using asynchronous FIFO interface 84-pin PLCC, 100-pin PQFP when SYFIFOB tied high), FIFO automatically reset upon detection overrun underrun condition. four cells lost during FIFO reset operation. FIFO overruns indicated maskable interrupt register bit. This asynchronous interface also expects start cell indication (TSOC) when first octet octet cell written into transmit FIFO. transmit FIFO write pointer reset octet octet cell when TSOC sampled high. During normal operation, TSOC should coincide with octet however, TSOC sampled high during other octet, current cell write aborted, FIFO write pointer reset octet current cell. TSOC sync event occurs when TSOC sampled during octet octet cell, when TSOC sampled high during octet except octet TSOC sync events indicated maskable interrupt register bit. asynchronous interface provides external device with indication full/empty transmit FIFO status (TFIFOFB). default, FIFO full indication asserted when FIFO full accept more writes (optionally, full indication selected indicate when FIFO almost full more than four writes accepted). FIFO status changes from full empty read cell boundaries with timing derived from transmit line clock (TICLK). FIFO status changes from empty full write cell boundaries with timing aligned FIFO write clock (FWRB). synchronous FIFO interface provided 100-pin PQFP package when SYFIFOB tied logic This interface "UTOPIA" compliant accepts write clock (TFCLK) write enable signal (TWRENB), start cell (TSOC) indication when data written transmit FIFO (using rising edges TFCLK). interface provides transmit cell available status (TCA) which transition from available unavailable when transmit FIFO near full accept more than more writes (when TFULL4 logic when FIFO full accept more writes (default). reduce FIFO latency, FIFO depth which indicates "full" one, two, three four cells FIFODP[1:0] bits TXCP Control register. programmed depth less than four, more than cell written after asserted. This interface also indicates FIFO overruns underruns maskable interrupt register bits, but, unlike asynchronous interface, further write accesses while logic ignored (i.e., FIFO reset FIFO overrun). Neither FIFO reset FIFO underrun; TXFF automatically transmits idle/unassigned cells until full cell available transmitted.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
9.18 Trail Trace Buffer Trail Trace Buffer (TTB) extracts sources trail trace message carried byte G.832 stream. message used prevent delivery traffic from wrong source bytes length. 16-byte message framed Multiframe Alignment Signal (TMFAS 'b10000000 00000000). TMFAS placed most significant each message byte. receive direction, trail trace message extracted from serial overhead stream output E3-FRMR. extracted message stored internal review external microprocessor. default, will write byte 16-byte message with most significant high first location RAM. extracted trail trace message checked consistency between consecutive multiframes. message received unchanged three five times (programmable) accepted comparison with copy previously written into internal external microprocessor. Alarms raised indicate reception unstable mismatched messages. transmit direction, sources trail trace message from internal insertion into byte E3-TRAN. also extracts Payload Type label carried byte G.832 stream. label used ensure that adaptation function trail termination sink compatible with adaptation function trail termination source. Payload Type label check consistency between consecutive multiframes. Payload Type label received unchanged five frames accepted comparison with copy previously written into external microprocessor. Alarms raised indicate reception unstable mismatched Payload Type label bits. 9.19 Microprocessor Interface Microprocessor Interface (MPIF) Block serves physical interface between microprocessor internal blocks. MPIF Block provides functions such data buffering address decoding. MPIF Block allows device level configuration each block S/UNI-PDH device.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
9.20 Normal Mode Register Memory Address 12H-13H 22H-23H Register S/UNI-PDH Configuration S/UNI-PDH Interrupt Enable S/UNI-PDH Interrupt Status S/UNI-PDH Control S/UNI-PDH Identification Master Reset S/UNI-PDH Data Link Control RBOC Configuration/Interrupt Enable RBOC Interrupt Status FRMR Configuration FRMR Interrupt Enable FRMR Interrupt Status FRMR Status RFDL Configuration RFDL Enable/Status RFDL Status RFDL Data PMON Change PMON Performance Meters PMON Interrupt Enable/Status Reserved PMON Line Code Violation Event Count PMON Line Code Violation Event Count PMON Framing Error Event Count PMON Framing Error Event Count PMON Summed Excessive Zero Detect Count PMON Summed Excessive Zero Detect Count PMON Parity Error Event Count PMON Parity Error Event Count PMON Path Parity Error Event Count PMON Path Parity Error Event Count PMON FEBE Event Count PMON FEBE Event Count TRAN Configuration TRAN Diagnostics Reserved XFDL Configuration XFDL Interrupt Status XFDL Transmit Data
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
XBOC Code SPLR Configuration SPLR Interrupt Enable SPLR Interrupt Status SPLR Status SPLT Configuration SPLT Control SPLT Diagnostics Octet SPLT Octet CPPM Loss Clock Meters CPPM Change CPPM Performance Meter CPPM Error Count CPPM Error Count CPPM Framing Error Event Count CPPM Framing Error Event Count CPPM FEBE Count CPPM FEBE Count CPPM Error Count CPPM Error Count CPPM Idle/Unassigned Cell Count CPPM Idle/Unassigned Cell Count CPPM Receive Cell Count CPPM Receive Cell Count CPPM Transmit Cell Count CPPM Transmit Cell Count RXCP Control RXCP Framing Control RXCP Interrupt Enable/Status RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Mask: octet RXCP Idle/Unassigned Cell Mask: octet RXCP Idle/Unassigned Cell Mask: octet RXCP Idle/Unassigned Cell Mask: octet RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Mask: octet
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
55H-57H 75H-7FH 80H-FFH
RXCP User-Programmable Cell Mask: octet RXCP User-Programmable Cell Mask: octet RXCP User-Programmable Cell Mask: octet RXCP Control/Status RXCP Count Threshold Reserved TXCP Control TXCP Interrupt Enable/Status TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Payload FRMR Framing Options FRMR Maintenance Options FRMR Framing Interrupt Enable FRMR Framing Interrupt Indication Status FRMR Maintenance Event Interrupt Enable FRMR Maintenance Event Interrupt Indication FRMR Maintenance Event Status Reserved TRAN Framing Options TRAN Status Diagnostic Options TRAN BIP-8 Error Mask TRAN Maintenance Adaptation Options Control Register Trail Trace Identifier Status Indirect Address Register Indirect Data Register Expected Payload Type Label Register Payload Type Label Control/Status Reserved Reserved Sync FIFO Parity Control/Status Reserved Reserved Test Mode Registers
register accesses, must low.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
NORMAL MODE REGISTER DESCRIPTION Normal mode registers used configure monitor operation S/UNI-PDH. Normal mode registers opposed test mode registers) selected when (A[7]) low. Notes Normal Mode Register Bits: Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions product, unused register bits must written with logic Reading back unused bits produce either logic logic hence unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling S/UNI-PDH determine programming state block. Writeable normal mode register bits cleared logic upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect S/UNI-PDH operation unless otherwise noted.
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
Register 00H: S/UNI-PDH Configuration Type Function E3ENBL FIFOBP LOOPT FRMRBP Default
CLB: controls cell loopback. When logic written CLB, cell loopback disabled. When logic written CLB, cell loopback enabled. While cell loopback enabled, cells received S/UNI-PDH written into transmit FIFO. These cells also continue written receive FIFO. This must used conjunction with LOOPT bit, otherwise transmit FIFO overflow occur. PLB: controls E3ENBL logic payload loopback. When logic written PLB, enabled) payload loopback disabled. When logic written PLB, enabled) overhead bits regenerated inserted into received stream resulting stream transmitted. Setting disables effect TICLK S/UNI-PDH Control register, thereby forcing flow-through timing. DLB: controls diagnostic loopback. When logic written DLB, diagnostic loopback disabled. When logic written DLB, transmit data stream looped receive direction. Depending S/UNI-PDH configuration, loopback includes framer (FRMR), PLCP framer (SPLR), ACell Delineator (ATMF). should logic when either CLB, logic mode available when S/UNI-PDH used Adirect-mapped applications. FRMRBP: FRMRBP controls bypassing internal framer. When logic written FRMRBP framer activated, selected E3ENBL bit. S/UNI-PDH then receives transmits appropriately
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PM7345 S/UNI-PDH
DATA SHEET PMC-931011 ISSUE SATURN USER-NETWORK INTERFACE
formatted stream. When logic written FRMRBP transceiver held reset, S/UNI-PDH receives transmits nonDS3/E3 formatted stream (for example stream). When using diagnostic loopback framer bypass mode, received cell errors result framer enabled. Ensure that when FRMRBP asserted that E3ENBL this register) asserted. LOOPT: LOOPT selects transmit timing source. When logic written LOOPT, transmitter loop-timed receiver. When loop timing enabled, receive clock (RCLK) used transmit timing source. transmit nibble stuffing derived from nibble stuffing receive PLCP frame (for PLCP frame transmission). FIXSTUFF must logic LOOPT logic When logic written LOOPT, transmit clock (TICLK) used transmit timing source. nibble stuffing derived from C13/CADD input, fixed internally determined FIXSTUFF SPLT Configuration Register (for PLCP frame transmission only). Setting LOOPT disables effect TICLK S/UNI-PDH Control register, thereby forcing flow-through timing. LOOPT mode available when S/UNI-PDH used Adirectmapped applications. When S/UNI-PDH operating DS-3 mode (E3ENBL loop timing enabled (LOOPT then FORMAT[0:1] bits register must both programmed logic Otherwise cell corruption will occur. FIFOBP: FIFOBP controls bypassing receive transmit FIFOs. When logic written FIFOBP receive transmit FIFOs bypassed, thereby minimizing latency through S/UNI-PDH. Note that FIFOs bypassed only when PLCP formatted transmission frames (DS3, DS1, G.751 processed. When logic written FIFOBP receive transmit FIFOs operate normally, both PLCP based non-PLCP based transmission frames processed E3ENBL: E3ENBL controls which transceivers used transmission system sublayer. When logic written E3ENBL, T3-FRMR T3-TRAN held reset E3-FRMR E3-TRAN enabled source sink G.751 G.832 formatted streams. When logic written E3ENBL, E3-FRMR E3-TRAN held reset T3-FRMR T3-TRAN enable source sink f
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