DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER PM6341 E1XC

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DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER PM6341 E1XC

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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
PM6341
E1XC
FRAMER/TRANSCEIVER
DATA SHEET
ISSUE JUNE 1998
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
PUBLIC REVISION HISTORY Issue Issue Date June 1998 Details Change Data Sheet Reformatted Change Technical Content. Generated data sheet from PMC-901204, Creation Document February 1996 June 1995 Update Update
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
CONTENTS FEATURES APPLICATIONS REFERENCES APPLICATION EXAMPLES BLOCK DIAGRAM. DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION DIGITAL RECEIVE INTERFACE (DRIF) ANALOG PULSE SLICER (RSLC) CLOCK DATA RECOVERY (CDRC) FRAMER (FRMR) 1.4.1 FRAME FIND 1.4.2 FRAME FIND. 1.4.3 CHECK DETECTION 1.1.4 SIGNALLING FRAME FIND. 1.1.5 ALARM INTEGRATION. PERFORMANCE MONITOR COUNTERS (PMON) HDLC RECEIVER (RFDL) ELASTIC STORE (ELST) SIGNALLING EXTRACTOR (SIGX).
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18
BACKPLANE RECEIVE INTERFACE (BRIF) TRANSMITTER (TRAN) TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) HDLC TRANSMITTER (XFDL) DIGITAL JITTER ATTENUATOR (DJAT). TIMING OPTIONS (TOPS) DIGITAL DS-1 TRANSMIT INTERFACE (DTIF) ANALOG PULSE GENERATOR (XPLS). BACKPLANE TRANSMIT INTERFACE (BTIF) MICROPROCESSOR INTERFACE (MPIF)
REGISTER DESCRIPTION. NORMAL MODE REGISTER DESCRIPTION. 11.1 INTERNAL REGISTERS 1.1.1 REGISTERS 49-4FH: LATCHING PERFORMANCE DATA
TEST FEATURES DESCRIPTION 12.1 12.2 INTERNAL REGISTERS TEST MODE
TIMING DIAGRAMS OPERATIONS. 14.1 14.2 14.3 CONFIGURING E1XC FROM RESET. USING INTERNAL TRANSMITTER USING INTERNAL RECEIVER. 14.3.1 USED SUBSEQUENT DIAGRAMS:
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
14.4
USING LOOPBACK MODES. 14.4.1 PAYLOAD LOOPBACK 14.4.2 LINE LOOPBACK. 14.4.3 DIAGNOSTIC DIGITAL LOOPBACK 14.4.4 DIAGNOSTIC METALLIC LOOPBACK
14.5
USING PER-CHANNEL SERIAL CONTROLLERS 14.5.1 INITIALIZATION 14.5.2 DIRECT ACCESS MODE 14.5.3 INDIRECT ACCESS MODE
14.6 1.10
INTERFACING ANALOG PULSE SLICER ALTERNATIVE LONGITUDINALLY BALANCED RECEIVE INTERFACE PROGRAMMING XPLS WAVEFORM TEMPLATE CODE REGISTER PROGRAMMING SEQUENCE CUSTOM WAVEFORMS USING DIGITAL JITTER ATTENUATOR. 1.10.1 DEFAULT APPLICATION. 1.10.2 DATA BURST APPLICATION 1.10.3 ELASTIC STORE APPLICATION. 1.10.4 ALTERNATE TCLKO REFERENCE APPLICATION 1.10.5 CHANGING JITTER TRANSFER FUNCTION
1.11
USING PERFORMANCE MONITOR COUNTER VALUES
ABSOLUTE MAXIMUM RATINGS. CAPACITANCE
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS E1XC TIMING CHARACTERISTICS ANALOG CHARACTERISTICS ORDERING THERMAL INFORMATION MECHANICAL INFORMATION
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
LIST REGISTERS REGISTER 00H: E1XC RECEIVE OPTIONS REGISTER 01H: E1XC RECEIVE BACKPLANE OPTIONS REGISTER 02H: E1XC DATALINK OPTIONS. REGISTER 03H: E1XC RECEIVE INTERFACE CONFIGURATION REGISTER 04H: E1XC TRANSMIT INTERFACE CONFIGURATION REGISTER 05H: E1XC TRANSMIT BACKPLANE OPTIONS. REGISTER 06H: E1XC TRANSMIT FRAMING OPTIONS. REGISTER 07H: E1XC TRANSMIT TIMING OPTIONS. REGISTER 08H: E1XC MASTER INTERRUPT SOURCE. REGISTER 09H: RECEIVE DATA LINK ENABLES. REGISTER 0AH: E1XC MASTER DIAGNOSTICS REGISTER 0BH: E1XC MASTER TEST REGISTER 0CH: E1XC REVISION/CHIP REGISTER 0DH: E1XC MASTER RESET. REGISTER 0EH: E1XC PHASE STATUS WORD (LSB) REGISTER 0FH: E1XC PHASE STATUS WORD (MSB). REGISTER 10H: CDRC BLOCK CONFIGURATION. REGISTER 11H: CDRC BLOCK INTERRUPT ENABLE. REGISTER 12H: CDRC INTERRUPT STATUS REGISTER 13H: ALTERNATE LOSS SIGNAL STATUS. REGISTER 14H: XPLS BLOCK LINE LENGTH CONFIGURATION REGISTER 15H: XPLS BLOCK CONTROL/STATUS.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
REGISTER REGISTER 16H: XPLS BLOCK CODE INDIRECT ADDRESS. REGISTER 17H: XPLS BLOCK CODE INDIRECT DATA. REGISTER 18H: DJAT BLOCK INTERRUPT STATUS. REGISTER 19H: DJAT BLOCK REFERENCE CLOCK DIVISOR (N1) CONTROL REGISTER 1AH: DJAT BLOCK OUTPUT CLOCK DIVISOR (N2) CONTROL REGISTER 1BH: DJAT BLOCK CONFIGURATION REGISTER 1CH: ELST CONFIGURATION. REGISTER 1DH: ELST INTERRUPT STATUS. REGISTER 1EH: ELST IDLE CODE REGISTER REGISTER 20H: FRMR FRAME ALIGNMENT OPTIONS. REGISTER 21H: FRMR MAINTENANCE MODE OPTIONS REGISTER 22H: FRMR FRAMING STATUS INTERRUPT ENABLE REGISTER 23H: FRMR MAINTENANCE/ALARM STATUS INTERRUPT ENABLE REGISTER 24H: FRMR FRAMING STATUS INTERRUPT INDICATION REGISTER 25H: FRMR MAINTENANCE/ALARM STATUS INTERRUPT INDICATION REGISTER 26H: FRMR FRAMING STATUS. REGISTER 27H: FRMR MAINTENANCE/ALARM STATUS REGISTER 28H: FRMR INTERNATIONAL/NATIONAL BITS. REGISTER 29H: FRMR EXTRA BITS REGISTER 2AH: FRMR ERROR COUNTER REGISTER 2BH: FRMR ERROR COUNTER
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
REGISTER 2CH: TS16 ALARM STATUS REGISTER 30H: TPSC BLOCK CONFIGURATION. REGISTER 31H: TPSC BLOCK ACCESS STATUS REGISTER TPSC BLOCK TIMESLOT INDIRECT ADDRESS/CONTROL REGISTER 33H: TPSC BLOCK TIMESLOT INDIRECT DATA BUFFER TPSC INTERNAL REGISTERS 20-3FH: DATA CONTROL BYTE. TPSC INTERNAL REGISTERS 40-5FH: IDLE CODE BYTE REGISTER 34H: XFDL BLOCK CONFIGURATION. REGISTER 35H: XFDL BLOCK INTERRUPT STATUS REGISTER 36H: XFDL BLOCK TRANSMIT DATA REGISTER 38H: RFDL BLOCK CONFIGURATION. REGISTER 39H: RFDL BLOCK INTERRUPT CONTROL/STATUS REGISTER 3AH: RFDL BLOCK STATUS. REGISTER 3BH: RFDL BLOCK RECEIVE DATA. REGISTER 40H: SIGX BLOCK CONFIGURATION REGISTER 41H: SIGX BLOCK ACCESS STATUS. REGISTER 42H: SIGX BLOCK TIME SLOT INDIRECT ADDRESS/CONTROL REGISTER 43H: SIGX BLOCK TIME SLOT INDIRECT DATA BUFFER SIGX INDIRECT REGISTERS (21H)- (2FH) SEGMENT TYPICAL TIMESLOT SIGNALLING DATA REGISTER (TSS 1-15) SIGX INDIRECT REGISTERS (31H)- (3FH) SEGMENT TYPICAL TIMESLOT SIGNALLING DATA REGISTER (TSS 17-31) SIGX INDIRECT REGISTERS (40H) (5FH) SEGMENT TYPICAL PER-TIMESLOT TRUNK CONDITIONING DATA REGISTER
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
SIGX INDIRECT REGISTERS (60H) (7FH) SEGMENT 4:TYPICAL PER-TIMESLOT CONFIGURATION SIGNALLING TRUNK CONDITIONING DATA REGISTER REGISTER TRAN BLOCK CONFIGURATION REGISTER TRAN BLOCK TRANSMIT ALARM/DIAGNOSTIC CONTROL172 REGISTER TRAN BLOCK INTERNATIONAL/NATIONAL CONTROL. REGISTER TRAN BLOCK EXTRA BITS CONTROL REGISTER 48H: PMON BLOCK CONTROL/STATUS REGISTER FRAMING ERROR COUNT. REGISTER BLOCK ERROR COUNT REGISTER BLOCK ERROR COUNT REGISTER ERROR COUNT LSB. REGISTER ERROR COUNT MSB. REGISTER LINE CODE VIOLATION COUNT LSB. REGISTER LINE CODE VIOLATION COUNT REGISTER 5CH: RSLC BLOCK CONFIGURATION. REGISTER 5DH: RSLC BLOCK INTERRUPT ENABLE/STATUS. REGISTER 0BH: E1XC MASTER TEST
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
LIST FIGURES FIGURE USER NETWORK INTERFACE FIGURE CROSS-CONNECT. FIGURE PLCC (Q-SUFFIX):. FIGURE PQFP (R-SUFFIX):. FIGURE EXTERNAL ANALOG RECEIVE INTERFACE CIRCUIT FIGURE CDRC JITTER TOLERANCE FIGURE BASIC FRAMING ALGORITHM FLOWCHART FIGURE DJAT JITTER TOLERANCE FIGURE DJAT MINIMUM JITTER TOLERANCE XCLK ACCURACY FIGURE DJAT JITTER TRANSFER. FIGURE EXTERNAL ANALOG TRANSMIT INTERFACE CIRCUIT FIGURE TRANSMIT TIMING OPTIONS FIGURE TS16 TRANSMIT DATALINK INTERFACE. FIGURE TRANSMIT DATALINK INTERFACE. FIGURE TS16 RECEIVE DATALINK INTERFACE FIGURE RECEIVE DATALINK INTERFACE FIGURE RECEIVE BACKPLANE INTERFACE FIGURE RECEIVE COMPOSITE MULTIFRAME OUTPUT (BRXSMFP=1 BRXCMFP=1): FIGURE RECEIVE OVERHEAD OUTPUT (ROHM=1):. FIGURE RECEIVE LINE DATA INTERFACE FIGURE TRANSMIT BACKPLANE INTERFACE
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
FIGURE TYPICAL DATA FRAME. FIGURE RFDL NORMAL DATA ABORT SEQUENCE. FIGURE RFDL FIFO OVERRUN FIGURE XFDL NORMAL DATA SEQUENCE FIGURE XFDL UNDERRUN SEQUENCE FIGURE PAYLOAD LOOPBACK. FIGURE LINE LOOPBACK. FIGURE DIAGNOSTIC DIGITAL LOOPBACK FIGURE DIAGNOSTIC METALLIC LOOPBACK. FIGURE LONGITUDINALLY BALANCED RECEIVE LINE INTERFACE FIGURE CODE REGISTER SEQUENCE DURING G.803 (120) PULSE GENERATION FIGURE COUNT FIGURE COUNT BER. FIGURE CRCE COUNT FIGURE MICROPROCESSOR READ ACCESS TIMING FIGURE MICROPROCESSOR WRITE ACCESS TIMING FIGURE BACKPLANE TRANSMIT INPUT TIMING DIAGRAM FIGURE XCLK=49.152MHZ INPUT TIMING FIGURE TCLKI INPUT TIMING FIGURE DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM. FIGURE TRANSMIT DATA LINK INPUT TIMING DIAGRAM FIGURE BACKPLANE RECEIVE INPUT TIMING DIAGRAM. FIGURE RECEIVE DATA LINK OUTPUT TIMING DIAGRAM.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
FIGURE BACKPLANE RECEIVE OUTPUT TIMING DIAGRAM. FIGURE RECOVERED DATA OUTPUT TIMING DIAGRAM FIGURE TRANSMIT INTERFACE OUTPUT TIMING DIAGRAM FIGURE TRANSMIT DATA LINK INTERFACE OUTPUT TIMING DIAGRAM FIGURE RECEIVE DATA LINK INTERFACE OUTPUT TIMING DIAGRAM FIGURE ANALOG RECEIVE DATA INPUT TIMING DIAGRAM. FIGURE PLASTIC LEADED CHIP CARRIER SUFFIX). FIGURE COPPER LEADFRAME PLASTIC QUAD FLAT PACK SUFFIX):.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE RECOMMENDED NETWORK VALUES. NORMAL MODE REGISTER MEMORY TRANSMIT TIMING OPTIONS XPLS CODE REGISTER MEMORY TPSC INDIRECT MEMORY MAP. A-LAW DIGITAL MILLIWATT PATTERN. µ-LAW DIGITAL MILLIWATT PATTERN SIGX INDIRECT MEMORY TEST MODE REGISTER MEMORY MAP.
TABLE E1XC DEFAULT SETTINGS. TABLE RSLC PERFORMANCE LIMITS TABLE RECOMMENDED NETWORK VALUES. TABLE ALTERNATIVE NETWORK RSLC PERFORMANCE LIMITS. TABLE RECOMMENDED ALTERNATIVE NETWORK VALUES TABLE XPLS TYPICAL OUTPUT PULSE AMPLITUDES TABLE REQUIRED PMON COUNTER SATURATION TABLE E1XC D.C. CHARACTERISTICS. TABLE MICROPROCESSOR READ ACCESS (FIGURE TABLE MICROPROCESSOR WRITE ACCESS (FIGURE TABLE BACKPLANE TRANSMIT INPUT TIMING (FIGURE TABLE XCLK=49.152MHZ INPUT (FIGURE 39). TABLE TCLKI INPUT (FIGURE 40).
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
TABLE DIGITAL RECEIVE INTERFACE INPUT TIMING (FIGURE TABLE TRANSMIT DATA LINK INPUT TIMING (FIGURE TABLE BACKPLANE RECEIVE INPUT TIMING (FIGURE TABLE RECEIVE DATA LINK OUTPUT TIMING (FIGURE TABLE BACKPLANE RECEIVE OUTPUT TIMING (FIGURE TABLE RECOVERED DATA OUTPUT TIMING (FIGURE 46). TABLE TRANSMIT INTERFACE OUTPUT TIMING (FIGURE 47). TABLE TRANSMIT DATA LINK INTERFACE OUTPUT TIMING (FIGURE 48). TABLE RECEIVE DATA LINK INTERFACE OUTPUT TIMING (FIGURE 49). TABLE RECEIVE ANALOG INPUT THRESHOLD TABLE ANALOG RECEIVE DATA INPUT TIMING (FIGURE TABLE TRANSMIT PULSE SYMMETRY TABLE E1XC ORDERING INFORMATION TABLE E1XC THERMAL INFORMATION.
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xiii
PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
FEATURES Integrates full-featured transceiver single device with analog circuitry receiving transmitting G.703 2048 kbit/s compatible signals digital circuitry terminating duplex digital signal. compatible with PM4341A Framer/Transceiver device. Provides 8-bit microprocessor interface configuration, control, status monitoring. power CMOS technology. Available either PLCC PQFP package.
receiver section: Provides analog circuitry receiving G.703 2048 kbit/s signal with cable attenuation. Direct digital inputs also provided allow bypassing analog front-end. Recovers clock data using digital phase locked loop high jitter tolerance. direct clock input provided allow clock recovery bypassed. Accepts dual rail single rail digital inputs. Supports HDB3 line code. Accepts gapped data streams support higher rate demultiplexing. Frames G.704 2048 kbit/s signal within Frames signalling multiframe alignment when enabled. Frames multiframe alignment when enabled. Provides loss signal detection, indicates loss frame alignment (OOF), loss signalling multiframe alignment loss multiframe alignment. Supports line path performance monitoring according ITU-T recommendations. Accumulators provided counting: CRC-4 errors 1000 second; block errors 1000 second; Frame sync errors second; Line code violations 8191 second.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Indicates reception remote alarm remote multiframe alarm. Indicates reception alarm indication signal (AIS) time slot AIS. Declares alarms using Q.516 recommended integration periods. Provides HDLC/LAPD interface terminating data link. Supports polled, interrupt-driven, servicing HDLC interface. Optionally extracts data link from timeslot kbit/s), which used receive common channel signalling, from combination national bits timeslot non-frame alignment signal frames kbit/s kbit/s). Provides two-frame elastic store buffer jitter wander attenuation that performs controlled slips indicates slip occurrence direction. Provides channel associated signalling extraction, with optional data inversion, programmable idle code substitution, multiframes signalling debounce per-timeslot basis. Provides trunk conditioning which forces programmable trouble code substitution signalling conditioning timeslots selected timeslots. Optionally provides dual rail digital output signals allow transparency. Also supports unframed mode. Supports transfer received signalling data 2048 kbit/s backplane buses.
transmitter section: Supports transfer transmitted signalling data from 2048 kbit/s backplane buses. Formats data create G.704 2048 kbit/s signal. Optionally inserts signalling multiframe alignment signal. Optionally inserts multiframe structure including optional transmission block errors. Optionally accepts dual rail digital inputs allow transparency. Also supports unframed mode. Provides channel associated signalling insertion, programmable idle code substitution, digital milliwatt code substitution, data inversion timeslot basis.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Provides trunk conditioning which forces programmable trouble code substitution signalling conditioning timeslots selected timeslots. Supports transmission alarm indication signal (AIS), timeslot AIS, remote alarm signal remote multiframe alarm signal. Provides HDLC/LAPD interface generating data link. Supports polled, interrupt-driven, servicing HDLC interface. Optionally inserts data link into timeslot kbit/s), which used transmit common channel signalling, into combination national bits timeslot non-frame alignment signal frames kbit/s kbit/s). Provides digital phase locked loop generation jitter transmit clock. Provides FIFO buffer jitter attenuation rate conversion transmitter. FIFO full empty indication allows bit-stuffing higher rate multiplexing applications. Supports HDB3 line code. Provides analog circuitry transmitting G.703 compatible 2048 kbit/s signal coaxial line symmetrical line. Digitally programmable line build provided. Provides dual rail single rail digital output signals.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
APPLICATIONS AInterfaces Frame Relay Interfaces Multiplexers (MUX) Digital Private Branch Exchanges (DPBX) Digital Access Cross-Connect Systems (DACS) Electronic Cross-Connect Systems (EDSX) Test Equipment (TEST) ISDN Primary Rate Interfaces (PRI) Channel Service Units (CSU) Data Service Units (DSU) SONET/SDH Add/Drop Multiplexers (ADM)
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
REFERENCES ITU-T Recommendation G.703, "Physical/Electrical Characteristics Hierarchical Digital Networks", Sept. 1991. ITU-T Recommendation G.704, "Synchronous Frame Structures Used Primary Secondary Hierarchical Levels", Oct. 1991. ITU-T Recommendation G.706, "Frame Alignment Cyclic Redundancy Check (CRC) Procedures Relating Basic Frame Structures Defined Recommendation G.704", Aug. 1991 ITU-T Recommendation G.711, "Pulse Code Modulation (PCM) Voice Frequencies", June 1990. ITU-T Recommendation G.732, "Characteristics Primary Multiplex Equipment Operating 2048 kbit/s", June 1990. ITU-T Recommendation G.735, "Characteristics Primary Multiplex Equipment Operating 2048 kbit/s Offering Synchronous Digital Access kbit/s and/or kbit/s", July 1990. ITU-T Recommendation G.821, "Error Performance International Digital Connection Forming Part Integrated Services Digital Network", July 1990. ITU-T Recommendation G.823, "The Control Jitter Wander Within Digital Networks Which Based 2048 kbit/s Hierarchy", Jan. 1994. ITU-T Recommendation O.151, "Error Performance Measuring Equipment Digital Systems Primary Rate Above", July 1993. ITU-T Blue Book, Recommendation O.162, "Equipment Perform Service Monitoring 2048 kbit/s Signals", Vol. Fascicle IV.4, 1988. ITU-T Recommendation Q.506, "Operations maintenance functions", Vol. Fascicle VI.5, 1984. ITU-T Recommendation Q.516, "Operations maintenance functions", Vol. Fascicle VI.5, 1984. Transmission Multiplexing (TM); Generic Functional Requirements Transmission Equipment, Part Generic Processes Performance", ETSI DE/TM-1015, November, 1993, Version 1.0.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
American National Standard Telecommunications, ANSI T1.102-1992 "Digital Hierarchy Electrical Interfaces".
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
APPLICATION EXAMPLES Figure
User Network Interface
RCLK /CAD FIFO B/TFC
6341 E1XC
BTPC
49.152
A[8:0 [7:0]
2.048
[7:0]
otoro
A[7:0 [7:0]
7345
From sele decode circuitry
From ster reset ircuitry
Figure shows PM6341 E1XC used with PM7345 Saturn User Network Interface (S/UNI-PDHTM) implement Awide area User Network Interface (UNI) Network Node Interface (NNI). this example, framing functions provided PM6341 E1XC. combination E1XC with S/UNI-PDH allows both PLCP formatted signals ITU-T G.804 compliant signals processed. G.804 specification defines Acell mappings variety transmission formats, including 2.048 Mbit/s format.
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PMC-910419
DATA SHEET
BTFP BRFPI BRFPO BRFPI BRPCM BRFPO
Figure
6341
ISSUE
8980
Cross-connect
yste ulse
6341
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from BRPC BRPCM from eive eive
FRAMER/TRANSCEIVER
PM6341 E1XC
PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Figure application utilizing PM6341 E1XC chips Mitel MT8980 Digital Time/Space Switch implement simple cross-connect. alternate architecture could MT8980, voice switch other signalling switch, E1XCs cross-connect E1's. Note: true implementation would require redundancy switch core.) "system frame pulse" signal stretched through D-FF into pulse 488ns duration, which used frame align data each E1XC through elastic store provide frame alignment indication transmitters. system frame pulse signal used indicate frame alignment synchronization MT8980. Another D-FF configured toggle generate 2.048MHz clock from system 4.096MHz clock source, synchronized system frame pulse.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
BLOCK DIAGRAM
BTSIG BTFP
Backplane Inte rface Tran itter: Fram ration, Alarm Insertio Trunk nditioning Line oding TOPS ptions
igita Jitter Attenuator
Analog Pulse enerator
Inte rnal
Per-channel ontroller: Signa llin Idle ontrol
A[7:0
icroProcessor Inte rface
igital Inte rfac
XFDL Tran itter
[7:0] LK/VC
Fram Fram Alignm ent, Alarm etection Perform ance onitor ounters ELST Elastic Store Signalling Extractor, onditioner
Analog Pulse Slicer
Backplane eceive Inte rfac
LCV/
igital eceive Inte rface
lock ecovery
RFDL eceiver
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
DESCRIPTION PM6341 Framer/Transceiver (E1XC) feature-rich device suitable many systems (such CSU, DSU, BANK, MUX, DPBX, DACS, ESDX) with minimum external circuitry. E1XC software configurable, allowing feature selection without changes external wiring. receive side, E1XC recovers clock data configured frame basic G.704 2048 kbit/s signal also frame signalling multiframe alignment signal multiframe alignment signal. Analog circuitry provided allow direct reception G.703 2048 kbit/s signal with loss using only external transformer passive components. E1XC also supports detection various alarm conditions such loss signal, loss frame, loss signalling multiframe, loss multiframe, reception remote alarm signal, remote multiframe alarm signal, alarm indication signal, timeslot alarm indication signal. E1XC detects indicates presence remote alarm patterns also integrates alarms industry specifications. Performance monitoring with accumulation CRC-4 errors, block errors, framing errors, line code violation provided. E1XC also detects terminates HDLC messages data link. data link extracted from timeslot used common channel signalling extracted from national bits. elastic store slip buffering adaptation backplane timing provided, channel associated signalling extractor that supports signalling debounce, signalling freezing, idle code substitution, data inversion per-timeslot basis. Receive side data signalling trunk conditioning also provided. transmit side, E1XC generates framing basic G.704 2048 kbit/s signal, framing optionally disabled. signalling multiframe alignment signal optionally inserted multiframe structure optionally inserted. Internal analog circuitry allows direct transmission G.703 2048 kbit/s signal into either line using only external transformer.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Channel associated signalling insertion, idle code substitution, digital milliwatt tone substitution, data inversion per-timeslot basis also supported. Transmit side data signalling trunk conditioning provided. HDLC messages data link transmitted. data link inserted into timeslot used common channel signalling inserted into national bits. E1XC generate jitter transmit clock provides FIFO transmit jitter attenuation. When used jitter attenuation, full empty status this FIFO made available facilitate higher order multiplexing applications controlling bit-stuffing logic. Interfaces include both parallel microprocessor port controlling operation device serial interface that allows 2048 kbit/s backplanes directly supported. Tolerance gapped clocks allows other backplane rates supported with minimum external logic.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
DIAGRAM Figure PLCC (Q-Suffix):
TDN/TFLG TDLCLK/TDLUDR TDLSIG/TDLINT
BTPCM/BTDP BTSIG/BTDN BTFP
XCLK/VCLK
TDP/TDD VSSO[0] VDDO[0]
RSTB INTB D[0] D[1] D[2] D[3] VSSO[1] VSSI[0] VDDI[0] VDDO[1] D[4] D[5] D[6] D[7]
VDDO[3]
TCLKO
BTCLK TCLKI
TAVD
TAVS
VSSO[3] RAVD RAVS VSSI[1] VDDI[1] RCLKI BRFPO BRPCM/BRDP BRSIG/BRDN RDP/RDD/SDP RDN/RLCV/SDN VDDO[2]
PM6341
(TOP VIEW)
RDLCLK/RDLEOM RDLSIG/RDLINT RCLKO RDPCM/RPCM VSSO[2] BRFPI BRCLK A[1] A[2] A[3] A[5] A[6] A[7] A[0] A[4]
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Figure
PQFP (R-suffix):
TDN/TFLG TDLCLK/TDLUDR TDLSIG/TDLINT TAVS TAVD VDDO[3] XCLK/VCLK BTPCM/BTDP BTSIG/BTDN BTFP BTCLK TCLKI TCLKO
RSTB INTB D[0] D[1] D[2] D[3] VSSO[1] VSSI[0] VDDI[0] VDDO[1] D[4] D[5] D[6] D[7]
TDP/TDD VSSO[0] VDDO[0]
PM6341
(TOP VIEW)
VSSO[3] RAVD RAVS VSSI[1] VDDI[1] RCLKI BRFPO BRPCM/BRDP BRSIG/BRDN RDP/RDD/SDP RDN/RLCV/SDN VDDO[2]
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BRCLK RDLCLK/RDLEOM RDLSIG/RDLINT RCLKO RDPCM/RPCM VSSO[2] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] BRFPI
PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
DESCRIPTION Name Type PQFP RDP/ PLCC Receive Digital Positive Line Pulse (RDP). This input available when E1XC configured receive dual-rail formatted data. input enabled either waveforms. When enabled NRZ, this input enabled sampled rising falling edge RCLKI. When enabled clock recovered from inputs. Receive Digital Data (RDD). When E1XC configured receive single-rail data, this input enabled sampled rising falling edge RCLKI. Sliced Positive Line Pulse (SDP). This becomes output when receive analog line interface powered positive pulse output corresponds sampled positive pulse excursion input. Receive Digital Negative Line Pulse (RDN). This input available when E1XC configured receive dual-rail formatted data. input enabled either waveforms. When enabled NRZ, this input enabled sampled rising falling edge RCLKI. When enabled clock recovered from inputs. Function
RDD/
RDN/
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
RLCV/
Receive Line Code Violation Indication (RLCV). When E1XC configured receive single-rail data, this input enabled sampled rising falling edge RCLKI. Sliced Negative Line Pulse (SDN). This becomes output when receive analog line interface powered positive pulse output corresponds sampled negative pulse excursion input.
RCLKI
Input
Receive Line Clock Input (RCLKI). This input externally recovered 2.048 line clock that enabled sample inputs rising falling edge when input format enabled dual-rail NRZ; sample RLCV inputs rising falling edge when input format enabled single-rail. Receive Analog Signal (RAS). This analog input samples signal external isolation transformer. connected positive lead transformer secondary through passive attenuation network. Receive Reference (REF). This analog bidirectional provides bias external isolation transformer. connected negative lead transformer secondary decoupling capacitor RAVS.
Input
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
Receive Peak Hold Network (RRC). This analog bidirectional connected external parallel resistor/capacitor network RAVS. This network necessary operation internal peak detector that tracks incoming signal level. Receive Analog Power (RAVD). This provides supply receive analog line interface. receive analog line interface used, power consumption E1XC reduced connecting RAVD analog ground pin, RAVS. RAVD must connected common, well decoupled supply together with VDDO[3:0] VDDI[1:0] pins. Care must taken avoid coupling noise induced VDDO VDDI pins into RAVD pin. Receive Analog Ground (RAVS). This provides ground supply receive analog line interface. RAVS must connected common ground together with VSSO[3:0] VSSI[1:0] pins. Care must taken avoid coupling noise induced VSSO VSSI pins into RAVS pin.
RAVD
Power
RAVS
Ground
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
RCLKO
Output
Recovered Clock Output (RCLKO). This output signal recovered 2.048 clock, synchronized XCLK signal. RCLKO signal recovered from received analog inputs interface powered up), from inputs input format dualrail RZ), from RCLKI input input format NRZ). Recovered Decoded (RDPCM). This output available when E1XC configured decoded data output. This output signal recovered data stream with HDB3 decoding applied, HDB3 decoding enabled. updated falling edge RCLKO. RDPCM signal meant used when digital receive interface configured unipolar operation (RUNI RDIEN since data should available input. Recovered (RPCM). This output available when E1XC configured data output. This output signal recovered data stream without optional HDB3 decoding applied. updated falling edge RCLKO.
RDPCM/
Output
RPCM
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
Output
Receive Frame Pulse (RFP). When E1XC configured receive frame pulse output, pulses high RCLKO cycle during each 256-bit frame, indicating frame alignment RDPCM data stream. When configured receive signalling multiframe output, pulses high RCLKO cycle during frame frame signalling multiframe, indicating signalling multiframe alignment RDPCM data stream. (Even when signalling multiframing disabled, output continues indicate position every 16th frame.) When configured receive multiframe output, pulses high RCLKO cycle during frame every frame multiframe, indicating multiframe alignment RDPCM data stream. (Even when multiframing disabled, output continues indicate position frame every 16th frame.)
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
Output
When configured composite multiframe output, goes high falling RCLKO edge marking beginning frame every frame signalling multiframe, indicating signalling multiframe alignment RDPCM data stream, returns falling RCLKO edge marking ending frame every frame multiframe, indicating multiframe alignment RDPCM data stream. This mode allows both multiframe alignments decoded externally from single signal. Note that signalling multiframe alignments coincident, will pulse high RCLKO cycle every frames. does indicate frame multiframe alignment RDPCM when digital receive interface configured unipolar operation (RUNI RDIEN register 03H.) updated falling edge RCLKO.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
RDLSIG/
Output
Receive Data Link Signal (RDLSIG). RDLSIG signal available this output when internal HDLC receiver (RFDL) disabled from use. RDLSIG contains data link stream extracted from selected data link bits. E1XC configured utilize timeslot data link utilize combination national bits data link. RDLSIG updated falling edge RDLCLK. Receive Data Link Interrupt (RDLINT). RDLINT signal available this output when RFDL enabled. RDLINT goes high when event occurs which changes status HDLC receiver.
RDLINT
RDLCLK/
Output
Receive Data Link Clock (RDLCLK). RDLCLK signal available this output when internal HDLC receiver (RFDL) disabled from use. RDLCLK used process data stream contained RDLSIG output. When E1XC configured extract data link, RDLCLK output held low. other formats rising edge RDLCLK used sample data RDLSIG. Receive Data Link Message (RDLEOM). RDLEOM signal available this output when RFDL enabled. RDLEOM goes high when last byte received sequence read from RFDL FIFO buffer, when FIFO buffer overrun.
RDLEOM
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
BRPCM/
Output
Backplane Receive (BRPCM). BRPCM signal available this output when backplane configured single-rail output. BRPCM contains recovered data stream passed through ELST SIGX. When ELST bypassed, BRPCM stream aligned backplane timing updated falling edge BRCLK. When ELST bypassed, BRPCM aligned receive line timing updated falling edge RCLKO. Backplane Receive Positive Line Pulse (BRDP). BRDP signal available this output when backplane configured dual-rail output. BRDP output represents receive digital positive pulse signal extracted from input bipolar signal. BRDP updated falling edge RCLKO.
BRDP
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
BRSIG/
Output
Backplane Receive Signalling (BRSIG). BRSIG signal available this output when backplane configured single-rail output. BRSIG contains extracted signalling bits each timeslot frame, repeated entire signalling multiframe. Each timeslot's signalling bits valid locations 5,6,7,8 timeslot timeslot-aligned with BRPCM data stream. When ELST bypassed, BRSIG stream aligned backplane timing updated falling edge BRCLK. When ELST bypassed, BRSIG aligned receive line timing updated falling edge RCLKO. Backplane Receive Negative Line Pulse (BRDN). BRDN signal available this output when backplane configured dual-rail output. BRDN output represents receive digital negative pulse signal extracted from input bipolar signal. BRDN updated falling edge RCLKO.
BRDN
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
BRFPO
Output
Backplane Frame Pulse Output (BRFPO). When E1XC configured backplane receive frame pulse output, BRFPO pulses high BRCLK cycle RCLKO cycle ELST by-passed) during each 256-bit frame, indicating frame alignment BRPCM data stream. When configured backplane receive signalling multiframe output, BRFPO pulses high BRCLK cycle RCLKO cycle ELST bypassed) during frame frame signalling multiframe, indicating signalling multiframe alignment BRPCM data stream. (Even when signalling multiframing disabled, BRFPO output continues indicate every 16th frame.) When configured backplane receive multiframe output, BRFPO pulses high BRCLK cycle RCLKO cycle ELST bypassed) during frame every frame multiframe, indicating multiframe alignment BRPCM data stream. (Even when multiframing disabled, BRFPO output continues indicate position frame every 16th frame.)
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
BRFPO
Output
When configured backplane receive composite multiframe output, BRFPO goes high falling BRCLK edge RCLKO edge ELST by-passed) marking beginning frame every frame signalling multiframe, indicating signalling multiframe alignment BRPCM data stream, returns falling BRCLK edge RCLKO edge ELST bypassed) marking frame every frame multiframe, indicating multiframe alignment BRPCM data stream. This mode allows both multiframe alignments decoded externally from single BRFPO signal. signalling multiframe alignments coincident, BRFPO will pulse high clock cycle. When configured backplane receive overhead output, BRFPO high timeslot timeslot each 256-bit frame, indicating overhead positions BRPCM data stream. BRFPO updated falling edge BRCLK RCLKO.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
BRCLK
Input
Backplane Receive Clock (BRCLK). This clock should 2.048MHz with optional gapping adaptation non-uniform backplane data streams. E1XC configured ignore BRCLK input RCLKO signal place when ELST bypassed. Backplane Frame Pulse Input (BRFPI). This input used frame align received data system backplane. pulse least BRCLK cycle wide must provided BRFPI multiples periods. BRFPI sampled rising edge BRCLK. Backplane Transmit (BTPCM). When backplane configured single-rail input, BTPCM inputs data stream transmitted, sampled rising edge BTCLK. Backplane Transmit Positive Line Pulse (BTDP). When backplane configured dual-rail input, BTDP input by-passes transmitter directly into DJAT. BTDP sampled rising edge BTCLK.
BRFPI
Input
BTPCM/
Input
BTDP
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
BTSIG/
Input
Backplane Transmit Signalling (BTSIG). When backplane configured single-rail input, BTSIG input signal contains signalling bits each timeslot transmit data frame, repeated entire signalling multiframe. Each timeslot's signalling bits locations 5,6,7,8 timeslot timeslot-aligned with BTPCM data stream. BTSIG sampled rising edge BTCLK. Backplane Transmit Negative Line Pulse (BTDN). When backplane configured dual-rail input, BTDN input by-passes transmitter directly into DJAT. BTDN sampled rising edge BTCLK.
BTDN
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
BTFP
Input
Backplane Transmit Frame Pulse (BTFP). This input used frame align transmitter system backplane. basic frame alignment only required, pulse least BTCLK cycle wide must provided BTFP multiples periods. multiframe alignment required, transmit multiframe alignment must enabled, BTFP must brought high mark frame every frame signalling multiframe brought following frame every frame multiframe. This mode allows both multiframe alignments independently controlled using single BTFP signal. Note that signalling multiframe alignments coincident, BTFP must pulse high BTCLK cycle every frames. Backplane Transmit Clock (BTCLK). This clock should 2.048MHz with optional gapping adaptation from non-uniform backplane data streams. E1XC configured ignore BTCLK input RCLKO signal place.
BTCLK
Input
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
TDLSIG/
Transmit Data Link Signal (TDLSIG). TDLSIG signal input this when internal HDLC transmitter (XFDL) disabled from use. TDLSIG source data stream inserted into selected data link bits. E1XC configured utilize timeslot data link utilize combination national bits data link. TDLSIG sampled rising edge TDLCLK. Transmit Data Link Interrupt (TDLINT). TDLINT signal output this when XFDL enabled. TDLINT goes high when last data byte written XFDL been transmission processor intervention required either write control information message, provide more data.
TDLINT
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
TDLCLK/
Output
Transmit Data Link Clock (TDLCLK). TDLCLK signal available this output when internal HDLC transmitter (XFDL) disabled from use. rising edge TDLCLK used sample data stream contained TDLSIG input. When E1XC configured insert data link, TDLCLK output held low. Transmit Data Link Underrun (TDLUDR). TDLUDR signal available this output when XFDL enabled. TDLUDR goes high when processor failed service TDLINT interrupt before transmit buffer emptied.
TDLUDR
TCLKO
Output
Transmit Clock Output (TCLKO). TDN, outputs enabled updated rising falling edge TCLKO. outputs also driven with timing derived from TCLKO. TCLKO 2.048 clock that adequately jitter wander free absolute terms permit acceptable G.703 2048 kbit/s signal generated. Depending configuration E1XC, TCLKO derived from TCLKI, RCLKO, BTCLK, with without jitter attenuation.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
TDP/
Output
Transmit Digital Positive Line Pulse (TDP). This signal available output when E1XC configured transmit dual-rail data. signal formatted either waveforms, enabled updated rising falling edge TCLKO. Transmit Digital Data (TDD). This signal available output when configured transmit single-rail data. signal enabled updated rising falling edge TCLKO.
TDN/
Output
Transmit Digital Negative Line Pulse (TDN). This signal available output when E1XC configured transmit dual-rail data. signal formatted either waveforms, enabled updated rising falling edge TCLKO. Transmit FIFO Flag (TFLG). This signal available when configured transmit single-rail data. TFLG output indicates when transmit rate conversion FIFO DJAT nearing empty full condition. Either indication selected. This output enabled updated rising falling edge TCLKO.
TFLG
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
Output
Transmit Analog Positive Pulse (TAP). This analog output drives signal through external matching transformer. connected positive lead transformer primary. analog Transmit Monitor Positive point internally bonded this output used monitor positive pulses transmit line.
Output
Transmit Analog Negative Pulse (TAN). This analog output drives signal through external matching transformer. connected negative lead transformer primary. analog Transmit Monitor Negative point internally bonded this output used monitor negative pulses transmit line.
Transmit Reference Decoupling Capacitor (TC). This analog bidirectional provides decoupling internal reference generator. connected decoupling capacitor TAVD.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
TAVD
Power
Transmit Analog Power (TAVD). This provides supply transmit analog line interface. Even transmit analog line interface used, supply must provided. transmit analog line interface remains power consumption state after reset until enabled. TAVD must connected common, well decoupled supply together with VDDO[3:0] VDDI[1:0] pins. Care must taken avoid coupling noise induced VDDO VDDI pins into TAVD pin. Transmit Analog Ground (TAVS). This provides ground supply transmit analog line interface. TAVS must connected common ground together with VSSO[3:0] VSSI[1:0] pins. Care must taken avoid coupling noise induced VSSO VSSI pins into TAVS pin.
TAVS
Ground
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
TCLKI
Input
Transmit Clock Input (TCLKI). This input signal used generate TCLKO clock signal. Depending upon configuration E1XC, TCLKO derived directly from TCLKI dividing TCLKI TCLKO derived from TCLKI after jitter attenuation frequency multiplication (default frequency ratio one). TCLKI jitter-free when divided down kHz, then possible derive TCLKO from TCLKI when TCLKI multiple (i.e. kHz, equals 256). E1XC configured ignore TCLKI input utilize BTCLK RCLKO instead. RCLKO also substituted TCLKI line loopback enabled. Crystal Clock Input (XCLK). This signal provides timing many portions E1XC. Depending configuration E1XC, XCLK nominally 49.152 16.384 MHz, duty cycle clock. When transmit clock generation jitter attenuation required, XCLK driven with 16.384 clock. When transmit clock generation jitter attenuation required, XCLK must driven with 49.152 clock. Vector Clock (VCLK). VCLK signal used during E1XC production test verify internal functionality.
XCLK/
Input
VCLK
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
INTB
Output
Active open-drain Interrupt signal (INTB). This signal goes when unmasked interrupt event detected internal interrupt sources, including internal HDLC transceiver. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source. Active chip select (CSB). This signal must enable E1XC register accesses. Note that when being used, must tied high. required (i.e. register accesses controlled using signals only), must connected inverted version RSTB input. case, must high least once after powerup order clear internal test modes. Bidirectional data (D[7:0]). This used during E1XC read write accesses.
Input
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Name
Type
PQFP PLCC
Function
Input
Active read enable (RDB). This signal pulsed enable E1XC register read access. E1XC drives D[7:0] with contents addressed register while both low. Active write strobe (WRB). This signal pulsed enable E1XC register write access. D[7:0] contents clocked into addressed normal mode register rising edge while low. Address latch enable (ALE). This signal latches address bus, A[7:0], when low. This allows E1XC interfaced multiplexed address/data bus. When high, address latches transparent. Active reset (RSTB). This signal asynchronously resets E1XC. Address (A[7:0]). This selects specific registers during E1XC register accesses.
Input
Input
RSTB A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]
Input Input
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PM6341 E1XC
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Name
Type
PQFP PLCC
Function
VDDO[0] VDDO[1] VDDO[2] VDDO[3]
Power
ring power pins (VDDO[3:0]). These pins must connected common, well decoupled supply together with VDDI[1:0] pins. Care must taken avoid coupling noise induced VDDO pins into VDDI pins. Core power pins (VDDI[1:0]). These pins must connected common, well decoupled supply together with VDDO[3:0] pins. ring ground pins (VSSO[3:0]). These pins must connected common ground together with VSSI[1:0] pins. Care must taken avoid coupling noise induced VSSO pins into VSSI pins. Core ground pins (VSSI[1:0]). These pins must connected common ground together with VSSO[3:0] pins.
VDDI[0] VDDI[1]
Power
VSSO[0] VSSO[1] VSSO[2] VSSO[3] VSSI[0] VSSI[1]
Ground
Ground
Notes Description: VDDI VSSI ground connections, respectively, core circuitry device. VDDO VSSI ground connections, respectively, ring circuitry device. TAVD TAVS ground connections, respectively, transmit analog circuitry device. These power supply connections must utilized must connect common ground rail, appropriate. There impedance connection within PM6341 between core, ring, transmit analog supply rails. Failure properly make these connections result improper operation damage device. Care must taken avoid coupling noise into transmit analog supply rails. RAVD RAVS ground connections, respectively, receive analog circuitry device. These power supply connections need
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
only used receive analog function desired should then connect common ground rail, appropriate, with core, ring, transmit analog supply rails. There impedance connection within PM6341 between receive analog supply rail other supply rails. When receive analog function desired, RAVD should connected RAVS. Care must taken avoid coupling noise into receive analog supply rails. Inputs RSTB have integral pull-up resistors. TDLSIG/TDLINT integral pull-up resistor defaults being input after reset.
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PM6341 E1XC
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FUNCTIONAL DESCRIPTION Digital Receive Interface (DRIF) Digital Receive Interface provides control over various input options available multifunctional digital receive pins RDP/RDD/SDP RDN/RLCV/SDN. When configured dual-rail input, multifunctional pins become inputs. These inputs enabled receive either return-to-zero (RZ) non-return-to-zero (NRZ) signals; input signals sampled either rising falling edge RCLKI. When interface configured single-rail input, multifunctional pins become RLCV inputs, which sampled either rising falling RCLKI edge. Finally, when analog interface used, multifunction pins become outputs, indicating sliced pulses corresponding received positive negative analog line pulses.
Analog Pulse Slicer (RSLC) Analog Pulse Slicer function provided RSLC block. Receive Data Slicer (RSLC) block provides first stage signal conditioning G.703 2048 kbit/s serial data stream converting bipolar line signals dual rail pulses. Before output pulse generated RSLC block, bipolar input signals must rise (for G.703 2048 kbit/s) their peak amplitude. This level referred Slicing Level. threshold criteria insures accurate pulse mark recognition presence noise. RSLC block provides squelch alarm, which occurs when input pulses below squelching level threshold. this state, data sliced, which prevents detection noise idle transmission line. status register goes high whenever RSLC block squelching input signal. RSLC configured register 5DH) generate interrupt whenever status goes high. RSLC block relies external network compliance G.703 twisted pair G.703 coax. RSLC block configured off-chip attenuator (see Figure following network values recommended intended applications:
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PM6341 E1XC
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Table Signal Type
Recommended Network Values Turns Ratio Squelch Level Primary
G.703 95.3
Tight tolerances required resistors turns ratio meet return loss specification. details these values were determined, refer section entitled "Interfacing Analog Pulse Slicer" "Operation" section this databook.
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PM6341 E1XC
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Figure
External Analog Receive Interface Circuit RAVD (Zin 10%) RAVS ±10%
Notes:
capacitors ceramic Recommended Transformers: Electronics 500-1775 (1:1:1); Pulse Engineering 64931 (1:1:1); Pulse Engineering 65341 (1:1:1) (for extended temp range) Alternatively, dual part containing both 1:2CT 1:1.36 transformers used, i.e.: Electronics 500-1777; Pulse Engineering PE64952; Pulse Engineering PE65774 (for extended temp range)
RSLC block disabled strapping receive analog power pin, RAVD ground. When RLSC disabled, E1XC accepts input pulses RDP/RDD RDN/RLCV pins. Clock Data Recovery (CDRC) Clock Data Recovery function provided Data Clock Recovery (CDRC) block that provides clock data recovery, HDB3 decoding, bipolar violation detection, loss signal detection. CDRC block recovers clock from incoming data pulses using digital phase-
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PM6341 E1XC
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locked-loop recovers data. Loss signal indicated after exceeding programmed threshold consecutive periods absence pulses both positive negative line pulse inputs cleared after occurrence single line pulse. alternate loss signal indication provided which cleared only after periods during which sequence four consecutive zeros been received. enabled, microprocessor interrupt generated when loss signal detected when signal returns. HDB3 decoding summarized follows: bipolar violation (BPV) preceded zeros received, violation preceding three periods decoded four zeros. line code selected, substitution made. HDB3 line code selected, line code violation declared bipolar violation same polarity previous preceded spaces (the second criteria maskable). line code selected, bipolar violations counted line code violations. input jitter tolerance CDRC complies with ITU-T Recommendation G.823.
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PM6341 E1XC
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Figure
CDRC Jitter Tolerance
lerance eiling BRCLK slip
SINEWAVE JITTER AMPLITUDE (UI) SCALE REC. G823 JITTER TOLERANCE SPECIFICATION
DPLL TOLERANCE WITH ZEROS RESTRICTION (ALGSEL=0) SPEC REGION DPLL TOLERANCE WITH ONES DENSITY (ALGSEL=0) ONES DENSITY (ALGSEL=1)
SINEWAVE JITTER FREQUENCY, SCALE
Framer (FRMR) Framer (FRMR) block searches frame alignment, multiframe alignment, channel associated signalling (CAS) multiframe alignment incoming recovered stream. Once FRMR found basic FAS) frame alignment, incoming data continuously monitored FAS/NFAS framing errors. Framing errors accumulated framing error counter contained PMON block. Once FRMR found multiframe alignment, data continuously monitored multiframe alignment pattern errors. Once FRMR found multiframe alignment, data continuously monitored multiframe alignment pattern errors, CRC-4 errors. FRMR also detects indicates loss frame, loss multiframe, loss
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PM6341 E1XC
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multiframe, based user-selectable criteria. reframe operation initiated software (via FRMR Frame Alignment Options Register), excessive errors, when multiframe alignment found within FRMR also identifies position frame, multiframe, multiframe. FRMR extracts timeslot optional data link also extracts contents International bits (from both frames NFAS frames), National bits, Extra bits (from timeslot frame multiframe), stores them FRMR International/National Bits Register, FRMR Extra Bits Register respectively. FRMR identifies values remote distant frame) alarm (bit timeslot NFAS frames) remote signalling multiframe distant multiframe) alarm (bit timeslot frame multiframe) FRMR International/National Bits Register, FRMR Extra Bits Register respectively. Access also provided "debounced" remote alarm remote signalling multiframe alarm bits which when corresponding signals have been logic consecutive occurrences, Recommendation O.162. Detection timeslot provided; also integrated Alarm indicated condition persisted least frame (OOF=1) condition also integrated, indicating Alarm condition persisted least interrupt generated signal change state status bits (OOF, OOSMF, OOCMF, AIS, RED), signal when event (RRA, RRMA, AISD, T16AISD, COFA, FER, SMFER, CMFER, CRCE, FEBE) occurred. 9.4.1 Frame Find Frame Find Block searches frame alignment using userselectable algorithms, defined Recommendation G.706. Optionally, frame check sequence added either algorithm provide protection against false frame alignment presence random mimic patterns. first algorithm finds frame alignment using following sequence: Search presence correct 7-bit FAS; Check that absent following frame verifying that assumed timeslot byte logic
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Check that correct 7-bit present assumed timeslot byte next frame. either conditions steps met, search frame alignment initiated immediately following errored timeslot byte location. second algorithm similar first, adds frame "hold-off" step begin search immediately following second 7-bit that checked. This "hold-off" performed only condition step fails, providing more robust algorithm which allows framer operate correctly presence fixed timeslot data imitating pattern. check sequence added either algorithm verify correct frame alignment presence random imitative FASs. Note that this check sequence should enabled when monitoring unframed pseudo random sequence avoid framing single mimic framing pattern contained sequence. check consists verifying correct frame alignment additional frames, follows: once frame alignment frame "n") determined, check that absent following frame (frame "n+1") verifying that timeslot logic then, check that correct 7-bit present timeslot next frame (frame "n+2").
either conditions check sequence met, search frame alignment initiated immediately following errored byte location when using first algorithm, initiated immediately following byte location frame "n+2" when using second algorithm. These algorithms illustrated Figure
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Figure
Basic Framing Algorithm Flowchart
Frame Synchronization
found
search 7-bit pattern
Algorithm found
Check current byte loc. next frame
found
Algorithm
check occurrence 7-bit next frame
Wait byte location next frame
Found Check Sequence selected Algorithm Check
Algorithm
Frame alignment following established frame
Found Check Sequence selected
found
check occurrence 7-bit next frame
Found
Frame alignment established
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These algorithms provide robust framing operation even presence random errors: framing with algorithm provides 99.98% probability finding frame alignment within presence 10-3 error rate mimic patterns. Once frame alignment found, block sets indication low, indicates change frame alignment occurred), monitors frame alignment signal, indicating errors occurring 7-bit pattern NFAS frames, indicating debounced value Remote Alarm (bit NFAS frames). Using debounce, Remote Alarm <0.00001% probability being falsely indicated presence 10-3 error rate. block declares loss frame alignment consecutive FASs have been received error additionally, NFAS frames been error consecutive occasions. presence random 10-3 error rate frame loss criteria provides mean time falsely lose frame alignment minutes. Frame Find Block forced initiate frame search time when following conditions met: software re-frame Frame Alignment Options Register goes logic Frame Find Block unable find multiframe alignment; Frame Find Block accumulates excessive evaluation errors errors second) enabled force re-frame.
9.4.2 Frame Find Once basic frame alignment been found, Frame Find Block searches multiframe alignment observing whether International bits (bit timeslot NFAS frames follow multiframe alignment pattern. Multiframe alignment declared least valid multiframe alignment signals observed within with time separating alignment signals being multiple Once multiframe alignment found, block sets OOCMF indication low, monitors multiframe alignment signal, indicating errors occurring 6-bit pattern, indicating value FEBE bits (bit frames multiframe).The block declares loss multiframe alignment four consecutive multiframe alignment signals have been received error, frame alignment been lost. Frame Find Block will force Frame Find Block initiate basic frame search when multiframe alignment been found
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9.4.3 Check Detection Check Detect Block computes 4-bit checksum each incoming sub-multiframe compares this 4-bit result received remainder bits subsequent sub-multiframe. block also accumulates errors over second intervals, monitoring excessive errors optionally, forcing Frame Find Block initiate frame search when errors occur second. number errors accumulated during previous second available reading FRMR Error Counter Registers. block also detects occurrence unframed all-ones receive data stream, indicating setting AISD indication when less than zero bits received frames (512 consecutive bits); AISD indication reset when more zeros stream observed, when frame alignment found. 9.4.4 Signalling Frame Find Once basic frame alignment been found, Signalling Frame Find Block searches multiframe alignment using user-selectable algorithms, which compatible with Recommendation G.732. Once frame alignment been found, first algorithm monitors timeslot each frame; declares multiframe alignment when consecutive frames with bits timeslot containing alignment pattern observed precede frame with timeslot containing correct alignment pattern. second algorithm, compatible with G.732, also monitors timeslot each frame, declares multiframe alignment when non-zero bits timeslot observed precede timeslot containing correct alignment pattern. Once multiframe alignment been found, block sets OOSMF indication logic monitors multiframe alignment signal, indicating errors occurring 4-bit pattern, indicating debounced value remote signalling multiframe alarm (bit timeslot frame multiframe). Using debounce, remote signalling multiframe alarm 0.00001% probability being falsely indicated presence 10-3 error rate. This block also indicates reception timeslot when timeslot been all-ones consecutive frames while multiframe. block declares loss multiframe alignment consecutive multiframe alignment signals have been received error,
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additionally, bits timeslot logic (selectable) multiframes. Loss multiframe alignment also declared frame alignment been lost. 9.4.5 Alarm Integration Alarm Integrator Block monitors indications, verifying that each condition persisted before indicating alarm condition. alarm removed when condition been absent ms). alarm algorithm accumulates occurrences AISD (AIS detection). AISD defined unframed pattern with less than zeros consecutive frame times (512 bits). Alarm Integrator Block counts occurrences AISD over interval indicates valid presence when more AISD indications possible have been received. Each interval with valid presence indication increments interval counter which declares Alarm when valid intervals have been accumulated. interval with valid presence indication decrements interval counter; Alarm declaration removed when counter reaches This algorithm provides 99.8% probability declaring Alarm within presence 10-3 mean error rate. TS16 alarm algorithm accumulates occurrences T16AISD (TS16 detection). T16AISD defined consecutive ones time slot bytes while signalling multiframe. Each interval with valid TS16 presence indication increments interval counter which declares TS16 Alarm when valid intervals have been accumulated. interval with valid TS16 presence indication decrements interval counter; TS16 Alarm declaration removed when counter reaches This algorithm provides 99.1% probability declaring TS16 Alarm within after loss signalling multiframe detection presence 10-3 mean error rate. alarm algorithm monitors occurrences over interval, indicating valid interval when more indications occurred during interval, indicating valid frame (INF) interval when indication occurred entire interval. Each interval with valid indication increments interval counter which declares Alarm when valid intervals have been accumulated. interval with valid indication decrements interval counter; Alarm declaration removed when counter reaches This algorithm biases occurrences, leading declaration alarm when intermittent loss frame alignment occurs.
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Performance Monitor Counters (PMON) Performance Monitor Counters function provided Performance Monitor (PMON) block that accumulates error events, frame synchronization error events, line code violation events, block error events with saturating counters over consecutive intervals defined period supplied transfer clock signal (typically second). When transfer clock signal applied, PMON block transfers counter values into holding registers resets counters begin accumulating events interval. counters reset such manner that error events occurring during reset missed. enabled, interrupt generated whenever counter data transferred into holding registers. holding registers read between successive transfer clocks, OVERRUN register asserted. Generation transfer clock within E1XC chip performed writing counter register location. holding register addresses contiguous facilitate polling operations.
HDLC Receiver (RFDL) HDLC Receiver function provided RFDL block. RFDL microprocessor peripheral used receive LAPD/HDLC frames either Time Slot National bits Time Slot RFDL detects change from flag characters first byte data, removes stuffed zeros incoming data stream, receives frame data, calculates Q.921 frame check sequence (FCS). Received data placed into 4-level FIFO buffer. Status Register contains bits which indicate overrun, message, flag detected, buffered data available. message, Status Register also indicates status number valid bits final data byte. Interrupts generated when one, three bytes (programmable RFDL configuration register) stored FIFO buffer. Interrupts also generated when terminating flag sequence, abort sequence, FIFO buffer overrun detected. When internal HDLC receiver disabled, serial data extracted FRMR output RDLSIG updated falling clock edge RDLCLK pin.
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Elastic Store (ELST) Elastic Store function provided ELST block. Elastic Store (ELST) block synchronizes incoming frames local backplane clock, BRCLK. frame data buffered frame circular data buffer. Input data written buffer using write pointer output data read from buffer using read pointer. When backplane timing derived from receive line data (i.e. RCLKO output used), elastic store bypassed eliminate frame delay. this configuration elastic store used measure frequency differences between recovered line clock another 2.048 clock applied BRCLK input. typical example might measure difference frequency between received streams (i.e. East-West frequency difference) monitoring number SLIP occurrences direction with respect other. When elastic store being used, average frequency incoming data greater than average frequency backplane clock, write pointer will catch read pointer buffer will filled. Under this condition controlled slip will occur when read pointer crosses next frame boundary. following frame data will deleted. average frequency incoming data less than average frequency backplane clock, read pointer will catch write pointer buffer will empty. Under this condition controlled slip will occur when read pointer crosses next frame boundary. last frame which read will repeated. slip operation always performed frame boundary. allow extraction signalling information data timeslots, multiframe identification also passed through ELST.
Signalling Extractor (SIGX) Signalling Extraction function provided Signalling Extractor (SIGX) block. provides channel associated signalling (CAS) extraction from signalling multiframe. Signalling data extracted from timeslot (TS) each frame within signalling multiframe buffered. SIGX selectively debounces bits, serializes results onto 2048 kbit/s serial stream BRSIG output. Buffered signalling data aligned with associated voice
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timeslot frame output format. Both output data stream output signalling stream compatible with TRAN Transmitter block. SIGX provides user control over signalling freezing with confidence level freezing with valid signalling data ones density out-of-frame condition. SIGX also provides control over timeslot data inversion, trunk conditioning, signalling debounce per-timeslot basis directly, Common Interface (CBI). Backplane Receive Interface (BRIF) Backplane Receive Interface allows data presented backplane 2048 kbit/s serial stream, allows transparency outputting dual-rail data 2048 kbit/s, allows access recovered stream (either HDB3 decoded stream, undecoded stream) 2048 kbit/s. block generates output data stream BRPCM containing timeslot bytes data. BRSIG output contains bytes signalling nibble data located least significant nibble each byte. framing alignment indication BRFPO configured indicate first each 256-bit frame, first first frame multiframe, first first frame signalling multiframe overhead bits. 9.10 Transmitter (TRAN) Transmitter function provided TRAN block. TRAN generates 2048 kbit/s data stream according ITU-T recommendations, providing individual enables frame generation, multiframe generation, channel associated signalling (CAS) multiframe generation. concert with Transmit Per-Channel Serial Controller (TPSC), TRAN block provides per-timeslot control idle code substitution, data inversion, digital milliwatt substitution, selection signalling source data. timeslots forced into trunk conditioning state (idle code substitution signalling substitution) master trunk conditioning Configuration Register. Common Channel Signalling (CCS) supported time slot either through internal HDLC Transmitter (XFDL) through serial data input clock
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output. Support provided transmission TS16 AIS, transmission remote alarm remote multiframe alarm signals. output signals selected conform HDB3 line coding. 9.11 Transmit Per-channel Serial Controller (TPSC) Transmit Per-channel Serial Controller allows data signalling trunk conditioning idle code applied transmit stream pertimeslot basis. also allows per-timeslot control data inversion application digital milliwatt. Transmit Per-channel Serial Controller function provided Per-Channel Serial Controller (PCSC) block. TPSC interfaces directly TRAN block provides serial streams signalling control, idle code data data control. registers accessible from interface indirect address mode. BUSY indication signal polled from internal status register check completion current operation. 9.12 HDLC Transmitter (XFDL) HDLC Transmitter function provided XFDL block. XFDL designed provide serial data link TRAN Transmitter block. XFDL used under microprocessor control transmit HDLC data frames Time Slot Time Slot National bits when E1XC enabled internal HDLC transmitter. XFDL performs data serialization, generation, zero-bit stuffing, well flag, idle, abort sequence insertion. Data transmitted provided interrupt-driven basis writing double-buffered transmit data register. Upon completion frames, Q.921 frame check sequence transmitted, followed idle flag sequences. transmit data register underflows, abort sequence automatically transmitted. When enabled (via XFDL Configuration register), XFDL continuously transmits flag character (01111110). Data bytes transmitted written into Transmit Data Register. After parallel-to-serial conversion each data byte, interrupt generated signal controller write next byte into Transmit Data Register. After last data frame byte transmitted, word insertion been enabled), flag insertion been enabled) transmitted. XFDL then returns transmission flag characters.
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there more than five consecutive ones transmit data data, zero stuffed into serial data output. This prevents unintentional transmission flag abort characters. Abort characters continuously transmitted time setting control bit. During transmission, underrun situation occur data written Transmit Data Register before previous byte been depleted. this case, abort sequence transmitted, controlling processor notified TDLUDR signal. Optionally, interrupt underrun signals independently enabled also generate interrupt INTB output, providing means notify controlling processor changes XFDL operating status. When internal HDLC transmitter disabled, serial data transmitted data link input TDLSIG timed clock rate output TDLCLK pin. 9.13 Digital Jitter Attenuator (DJAT) Digital Jitter Attenuation function provided Digital Jitter Attenuator (DJAT) block. DJAT block receives jittered, dual-rail data format from TRAN separate inputs, which allows bipolar violations pass through block uncorrected. incoming data streams stored FIFO timed transmit clock (either BTCLK RCLKO). respective input data emerges from FIFO timed jitter attenuated clock (TCLKO) referenced either TCLKI, BTCLK, RCLKO. jitter attenuator generates jitter-free 2.048 TCLKO output transmit clock adaptively dividing 49.152 XCLK signal according phase difference between generated TCLKO input data clock DJAT (either BTCLK RCLKO). Jittered fluctuations phase input data clock attenuated phase-locked loop within DJAT that frequency TCLKO equal average frequency input data clock. Phase fluctuations with jitter frequency above attenuated octave jitter frequency. Wandering phase fluctuations with frequencies below tracked generated TCLKO. provide smooth flow data DJAT, TCLKO used read data FIFO. FIFO read pointer (timed TCLKO) comes within write pointer (timed input data clock, BTCLK RCLKO), DJAT will track jitter input clock. This permits phase jitter pass through unattenuated, inhibiting loss data.
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Jitter Characteristics DJAT Block provides excellent jitter tolerance jitter attenuation while generating minimal residual jitter. accommodate UIpp input jitter jitter frequencies above jitter frequencies below more correctly called wander, tolerance increases decade. most applications DJAT Block will limit jitter tolerance lower jitter frequencies only. high frequency jitter, above example, other factors such clock data recovery circuitry limit jitter tolerance must considered. frequency wander, below example, other factors such slip buffer hysteresis limit wander tolerance must considered. DJAT Block meets frequency jitter tolerance requirements ITU-T Recommendation G.823. DJAT exhibits negligible jitter gain jitter frequencies below attenuates jitter frequencies above decade. most applications DJAT Block will determine jitter attenuation higher jitter frequencies only. Wander, below example, will essentially passed unattenuated through DJAT. Jitter, above example, will attenuated specified, however, outgoing jitter dominated generated residual jitter cases where incoming jitter insignificant. This generated residual jitter directly related (49.152 MHz) digital phase locked loop transmit clock generation. DJAT meets jitter attenuation requirements ITU-T Recommendations G.737, G.738, G.739 G.742. Jitter Tolerance Jitter tolerance maximum input phase jitter given jitter frequency that device accept without exceeding linear operating range, corrupting data. DJAT, input jitter tolerance Unit Intervals peak-to-peak (UIpp) with worst case frequency offset UIpp with frequency offset. frequency offset difference between frequency XCLK divided that input data clock.
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Figure Jitter Amplitude,
DJAT Jitter Tolerance
DJAT minimum tolerance
CCITT G.823 unacceptable Region
acceptable
0.01
Jitter Frequency,
100k
accuracy XCLK frequency that DJAT reference input clock used generate jitter-free TCLKO have effect minimum jitter tolerance. Given that DJAT reference clock accuracy ±103 from 2.048 MHz, that XCLK input accuracy ±100 from 49.152 MHz, minimum jitter tolerance various differences between frequency reference clock XCLK/24 shown Figure
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Figure
DJAT Minimum Jitter Tolerance XCLK Accuracy 42.4
DJAT Minimum Jitter Tolerance
34.9
frequency offset (PLL XCLK) XCLK Accuracy
Jitter Transfer output jitter jitter frequencies from more than greater than input jitter, excluding residual jitter. Jitter frequencies above attenuated level octave, shown Figure
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Figure Jitter Gain (dB)
DJAT Jitter Transfer
G.737, G738, G.739, G.742 DJAT response
Unacceptable Region
Jitter Frequency,
Jitter Generation When jitter applied input port, jitter attenuator generates 0.042 UIpp (1/24 UIpp) output jitter. Frequency Range non-attenuating mode, that when FIFO within overrunning under running, tracking range 1.963 2.133 MHz. guaranteed linear operating range jittered input clock 2.048 1278 with worst case jitter UIpp) maximum XCLK frequency offset ppm). nominal range 2.048 with jitter XCLK frequency offset. 9.14 Timing Options (TOPS) Timing Options block provides means selecting source internal input clock DJAT block, reference signal digital PLL, clock source used derive output TCLKO signal.
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9.15
Digital DS-1 Transmit Interface (DTIF) Digital DS-1 Transmit Interface provides control over various output options available multifunctional digital transmit pins TDP/TDD TDN/TFLG. When configured dual-rail output, multifunctional pins become outputs. These outputs formatted either return-to-zero (RZ) non-return-to-zero (NRZ) signals updated either rising falling edge TCLKO. When interface configured single-rail output, multifunctional pins become TFLG outputs, which enabled updated either rising falling TCLKO edge. Further, TFLG output enabled indicate FIFO empty FIFO full status. DTIF block also provides Alarm Indication Signalling (AIS) generation capability generating alternating mark signals TDP/TDN outputs, allones output, when TAISEN Transmit Interface Configuration register. This useful when internal loopback modes used.
9.16
Analog Pulse Generator (XPLS) Analog Pulse Generator function provided Transmit Pulse Generator block (XPLS) block that converts Return Zero (NRZ) pulses into Alternate Mark Inversion (AMI) line signals suitable G.703 2048 kbit/s intra-office environment. dual-rail pulses supplied DJAT block. logical output from DJAT causes positive pulse transmitted; similar signal output from DJAT causes negative pulse transmitted. both logical "1," output pulse transmitted. output pulse shape synthesized digitally with internal Digital Analog (D/A) converter. converter updated eight times 2048 kbit/s period with words stored ROM. These words define output pulse shape. words ITU-T G.703 2048 kbit/s compatible. external circuit different from that recommended Figure used, pulse generator permits creation custom pulse shapes. Refer Operations section details. signalling created exciting either internal RING DRIVERS that drive line-coupling transformer differentially outputs. This differential driving scheme insures small positive negative pulse imbalance. drivers, with step-up transformer, amplify output pulses their final levels. RING drivers also supply high current capability required drive impedance output load.
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default line build duty cycle square pulse compatible with ITU-T G.703 specification symmetrical line. separate build available coaxial line. small, high-frequency negative-going spike observed falling edge transmit pulse. This spike filtered using optional "snubbing" network shown Figure XPLS includes driver performance monitor detect nonfunctional links. monitor inputs, PM_TIP PM_RING, internally bonded XPLS's outputs. pulses detected alternately across PM_TIP PM_RING monitor points consecutive TCLKO periods, monitored link declared failed. XPLS programmed produce interrupt whenever link monitor state changes. XPLS block provides Alarm Indication Signalling (AIS) generation capability generating alternating mark signals link when TAIS programmed high. This useful when internal loopback modes used.
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Figure
External Analog Transmit Interface Circuit
optional "snubbing netw ork"
470nF TAVD 0.68µ
TAVS
1:1.3
.703 +/-5% 1/8W .703 +/-5% 1/8W
lectronics 500-1776 (1:1.36); Puls Engineering (1:1.3 Puls Engineering (1:1.3 extended rang Alternativ ely, dual part containing 1:2C trans form necessa receiver transm itter circuits used, i.e.: lectronic 500-1777; ulse ngineering 4952; ulse inee ring 6577 (for extended rang
9.17
Backplane Transmit Interface (BTIF) Backplane Transmit Interface allows data taken from backplane 2048kbit/s serial stream allows transparency accepting dual-rail data.
9.18
Microprocessor Interface (MPIF) Microprocessor Interface allows E1XC configured, controlled monitored internal registers.
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REGISTER DESCRIPTION Table Address Normal Mode Register Memory Register E1XC Receive Options E1XC Receive Backplane Options E1XC Datalink Options E1XC Receive Interface Configuration E1XC Transmit Interface Configuration E1XC Transmit Backplane Options E1XC Transmit Framing Options E1XC Transmit Timing Options E1XC Master Interrupt Source E1XC Receive Data Link Enables E1XC Master Diagnostics E1XC Master Test E1XC Revision/Chip E1XC Master Reset E1XC Phase Status Word (LSB) E1XC Phase Status Word (MSB) CDRC block Configuration CDRC block Interrupt Enable CDRC block Interrupt Status Alternate Loss Signal XPLS block Line Length Configuration XPLS block Control/Status XPLS block CODE Indirect Address XPLS block CODE Indirect Data DJAT block Interrupt Status
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Address
Register DJAT block Reference Clock Divisor (N1) Control DJAT block Output Clock Divisor (N2) Control DJAT block Configuration ELST block Configuration ELST block Interrupt Enable/Status ELST block Idle Code ELST Reserved FRMR block Framing Alignment Options FRMR block FRMR Maintenance Mode Options FRMR block Framing Status Interrupt Enable FRMR block Maintenance/Alarm Status Interrupt Enable FRMR block Framing Status Interrupt Indication FRMR block Maintenance/Alarm Status Interrupt Indication FRMR block Framing Status FRMR block Maintenance/Alarm Status FRMR block International/National Bits FRMR block Extra Bits FRMR block Error Count FRMR block Error Count TS16 Alarm Status Reserved TPSC block Configuration TPSC block Access Status TPSC block Timeslot Indirect Address/Control TPSC block Timeslot Indirect Data Buffer XFDL block Configuration XFDL block Interrupt Status
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Address 50H-5BH
Register XFDL block Transmit Data XFDL Reserved RFDL block Configuration RFDL block Interrupt Control/Status RFDL block Status RFDL block Receive Data Reserved SIGX block Configuration SIGX block Access Status SIGX block Timeslot Indirect Address/Control SIGX block Timeslot Indirect Data Buffer TRAN block Configuration TRAN block Transmit Alarm/Diagnostic Control TRAN block International/National Control TRAN block Extra Bits Control PMON block Control/Status PMON block Count PMON block FEBE Count (LSB) PMON block FEBE Count (MSB) PMON block Count (LSB) PMON block Count (MSB) PMON block Count (LSB) PMON block Count (MSB) Reserved RSLC block Configuration RSLC block Interrupt Enable/Status
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NORMAL MODE REGISTER DESCRIPTION Normal mode registers used configure monitor operation E1XC. Normal mode registers opposed test mode registers) selected when A[7] low. Notes Normal Mode Register Bits: Writing values into unused register bits effect. Reading back unused bits produce either logic logic hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling E1XC determine programming state chip. Writeable normal mode register bits cleared zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect E1XC operation unless otherwise noted.
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11.1
Internal Registers Register 00H: E1XC Receive Options Type Function WORDERR CNTNFAS ELSTBYP TRSLIP SRPCM SRSMFP SRCMFP TRKEN Default
This register allows software configure receive functions E1XC. WORDERR: WORDERR determines frame alignment signal (FAS) errors reported. When WORDERR logic more errors seven word results single framing error count. When WORDERR logic each error word results single framing error count. CNTNFAS: When CNTNFAS logic zero time slot non-frame alignment signal (NFAS) frames results increment framing error count. WORDERR also logic word defined eight bits comprising pattern time slot next NFAS frame. When CNTNFAS logic only errors affect framing error count. ELSTBYP: ELSTBYP allows Elastic Store (ELST) block bypassed, eliminating frame delay incurred through ELST. When logic received data clock inputs ELST internally routed directly ELST outputs. TRSLIP: TRSLIP allows ELST block used measure, through SLIP indications, frequency difference between recovered receive line clock
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transmit clock driving TRAN block when ELST bypassed. When TRSLIP logic transmit clock input TRAN internally substituted BRCLK input system side ELST. When TRSLIP logic BRCLK input routed system side ELST. TRSLIP should only ELSTBYP logic SRPCM: SRPCM selects output signal seen multifunction output RPCM/ RDPCM. When logic multifunction output becomes RPCM, undecoded output from Clock Data Recovery (CDRC) block. When SRPCM logic multifunction output becomes RDPCM, HDB3-decoded output from CDRC block. SRSMFP SRCMFP: SRSMFP SRCMFP bits select output signal seen output following table summarizes four configurations: SRSMFP SRCMFP Result Receive frame pulse output: pulses high RCLKO cycle during each 256-bit frame, indicating frame alignment RDPCM/RPCM data stream. Receive multiframe output: pulses high RCLKO cycle during frame every frame multiframe, indicating multiframe alignment RDPCM/RPCM data stream. (Even when multiframing disabled, output continues indicate position frame every 16th frame.) Receive signalling multiframe output: pulses high RCLKO cycle during frame frame signalling multiframe, indicating signalling multiframe alignment RDPCM/RPCM data stream. (Even when signalling multiframing disabled, output continues indicate position every 16th frame.)
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SRSMFP
SRCMFP
Result Receive composite multiframe output: goes high falling RCLKO edge marking beginning frame every frame signalling multiframe, indicating signalling multiframe alignment RPCM/RDPCM data stream, returns falling RCLKO edge marking frame every frame multiframe, indicating multiframe alignment RPCM/RDPCM data stream. This mode allows both multiframe alignments decoded externally from single signal. Note that signalling multiframe alignments coincident, will pulse high RCLKO cycle every frames.
TRKEN: TRKEN enables receive trunk conditioning upon out-of-framecondition. TRKEN logic contents ELST Idle Code register inserted into time slots (including TS16) BRPCM framer out-of-basic frame (i.e. status logic TRKEN only effect BRX2RAIL ELSTBYP bits both logic TRKEN logic receive trunk conditioning still performed per-timeslot basis SIGX Per-Timeslot Trunk Conditioning Data Registers Upon reset E1XC, these bits cleared zero.
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Register 01H: E1XC Receive Backplane Options Type Function Unused Unused RXDMAGAT ROHM BRX2RAIL BRXSMFP BRXCMFP Unused Default
This register allows software configure Receive backplane interface format E1XC. RXDMAGAT: RXDMAGAT selects gating RDLINT output with RDLEOM output when internal HDLC receiver used with DMA. When RXDMAGAT logic RDLINT output gated with RDLEOM output that RDLINT forced logic when RDLEOM logic When RXDMAGAT logic RDLINT RDLEOM outputs operate independently. BRX2RAIL: BRX2RAIL selects whether backplane receive data signal multifunction outputs BRPCM/BRDP BRSIG/BRDN either dual rail single rail format. When BRX2RAIL logic multifunction pins become BRDP BRDN dual rail outputs, which contain received positive negative line pulses timed 2.048MHz receive line rate, RCLKO. When BRX2RAIL logic multifunction pins become BRPCM BRSIG digital outputs. ROHM, BRXSMFP BRXCMFP: ROHM, BRXSMFP BRXCMFP bits select output signal seen backplane output BRFPO. following table summarizes configurations:
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ROHM
BRXSMFP
BRXCMFP Result Backplane receive frame pulse output: BRFPO pulses high BRCLK cycle RCLKO cycle ELST by-passed) during each 256-bit frame, indicating frame alignment BRPCM data stream.
Backplane receive multiframe output: BRFPO pulses high BRCLK cycle RCLKO cycle ELST by-passed) during frame every frame multiframe, indicating multiframe alignment BRPCM data stream. (Even when multiframing disabled, BRFPO output continues indicate position frame every 16th frame).
Backplane receive signalling multiframe output: BRFPO pulses high BRCLK cycle RCLKO cycle ELST by-passed) during frame frame signalling multiframe, indicating signalling multiframe alignment BRPCM data stream. (Even when signalling multiframing disabled, BRFPO output continues indicate position every 16th frame.)
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ROHM
BRXSMFP
BRXCMFP Result Backplane receive composite multiframe output: BRFPO goes high falling BRCLK edge RCLKO edge ELST by-passed) marking beginning frame every frame signalling multiframe, indicating signalling multiframe alignment BRPCM data stream, returns falling BRCLK edge RCLKO edge ELST bypassed) marking frame every frame multiframe, indicating multiframe alignment BRPCM data stream. This mode allows both multiframe alignments decoded externally from single BRFPO signal. Note that signalling multiframe alignments coincident, BRFPO will pulse high BRCLK cycle RCLKO cycle ELST bypassed) every frames.
Backplane receive overhead output: BRFPO high timeslot timeslot each 256-bit frame, indicating overhead BRPCM data stream.
Upon reset E1XC, these bits cleared zero.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Register 02H: E1XC Datalink Options Type Function RXDMASIG Unused TXDMASIG Unused RDLINTE RDLEOME TDLINTE TDLUDRE Default
This register allows software configure datalink options E1XC. RXDMASIG: RXDMASIG selects internal HDLC receiver (RFDL) data-received interrupt (INT) end-of-message (EOM) signals output RDLINT RDLEOM pins. When RXDMASIG logic RDLINT RDLEOM output pins used controller process datalink. When RXDMASIG logic RFDL signals longer available controller; signals RDLINT RDLEOM become extracted datalink data clock, RDLSIG RDLCLK. this mode, data stream available RDLSIG output corresponds extracted datalink from Time Slot Time Slot National bits depending state RXSAxEN bits Receive Data Link Enables register. TXDMASIG: TXDMASIG selects internal HDLC transmitter (XFDL) request service interrupt (INT) data underrun (UDR) signals output TDLINT TDLUDR pins. When TXDMASIG logic TDLINT TDLUDR output pins used controller service datalink. When TXDMASIG logic XFDL signals longer available controller; signals TDLINT TDLUDR become serial datalink data input clock, TDLSIG TDLCLK. this mode external controller responsible formatting data stream presented TDLSIG input correspond datalink Time Slot Time Slot National bits. TRAN block Configuration DLEN logic TRAN block Configuration SIGEN
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
logic TDLSIG data stream inserted into Time Slot TDLCLK duty cycle clock; otherwise, TDLSIG data stream inserted into Time Slot National positions enabled TXSAxEN bits. default case TDLCLK bursted clock TDLSIG inserted into bit. RDLINTE: RDLINTE enables RFDL received-data interrupt also generate interrupt microprocessor interrupt, INTB. This allows single microprocessor service RFDL without needing interface control signals. When RDLINTE logic event causing interrupt RFDL (which visible RDLINT output when RXDMASIG logic also causes interrupt generated INTB output. When RDLINTE logic interrupt event RFDL does cause interrupt INTB. RDLEOME: RDLEOME enables RFDL end-of-message interrupt also generate interrupt microprocessor interrupt, INTB. This allows single microprocessor service RFDL without needing interface control signals. When RDLEOME logic end-of-message event causing interrupt RFDL (which visible RDLEOM output when RXDMASIG logic also causes interrupt generated INTB output. When RDLEOME logic interrupt event RFDL does cause interrupt INTB. NOTE: within RFDL, end-of-message event causes interrupt both RFDL interrupt outputs. Operation section further details using RFDL. TDLINTE: TDLINTE enables XFDL request service interrupt also generate interrupt microprocessor interrupt, INTB. This allows single microprocessor service XFDL without needing interface control signals. When TDLINTE logic request service interrupt event XFDL (which visible TDLINT output when TXDMASIG logic also causes interrupt generated INTB output. When TDLINTE logic interrupt event XFDL does cause interrupt INTB. TDLUDRE: TDLUDRE enables XFDL transmit data underrun interrupt also generate interrupt microprocessor interrupt, INTB. This allows
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
single microprocessor service XFDL without needing interface control signals. When TDLUDRE logic underrun event causing interrupt XFDL (which visible TDLUDR output when TXDMASIG logic also causes interrupt generated INTB output. When TDLUDRE logic underrun event XFDL does cause interrupt INTB. Upon reset E1XC, these bits cleared zero.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Register 03H: E1XC Receive Interface Configuration Type Function Unused SDOEN RDIEN RDNINV RDPINV RUNI RFALL Unused Default
This register enables Receive Interface handle various input waveform formats. SDOEN: SDOEN enables sliced positive negative pulses from analog receive slicer visible pins when Analog G.703 Receive Slicer active. When SDOEN logic multifunction pins SDP/RDP/RDD SDN/RDN/RLCV become sliced positive negative pulse outputs, SDN. Pulses will seen outputs RSLC powered When SDOEN logic multifunction pins SDP/RDP/RDD SDN/RDN/RLCV become digital inputs, RDP/RDD RDN/RLCV. function digital inputs determined RUNI bit. RDIEN: RDIEN enables data received digital inputs, RDP/RDD RDN/RLCV, used internally instead outputs from Analog G.703 Receive Slicer. When RDIEN logic SDOEN logic digital data input multifunction pins RDP/RDD RDN/RLCV handled accordance with remaining setting this register resulting signals used internally drive clock data recovery block. When RDIEN logic output signals from analog RSLC used internally drive CDRC block. RDPINV,RDNINV: RDPINV RDNINV bits enable Receive Interface logically invert signals received multifunction pins SDP/RDP/RDD
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
SDN/RDN/RLCV, respectively. When RDPINV logic interface inverts signal RDP/RDD input. When RDPINV logic interface passes RDP/RDD signal unaltered. When RDNINV logic interface inverts signal RDN/RLCV input. When RDNINV logic interface passes RDN/RLCV signal unaltered. RUNI: RUNI enables interface receive unipolar digital data line code violation indications multifunction pins SDP/RDP/RDD SDN/RDN/RLCV. When RUNI logic SDP/RDP/RDD SDN/RDN/RLCV multifunction pins become data line code violation inputs, RLCV, sampled selected RCLKI edge. When RUNI logic SDP/RDP/RDD SDN/RDN/RLCV multifunction pins become positive negative pulse inputs, RDN, sampled selected RCLKI edge. RFALL: RFALL enables Receive Interface sample multifunction pins falling RCLKI edge. When RFALL logic interface enabled sample either RLCV inputs, inputs, falling RCLKI edge. When RFALL logic interface enabled sample inputs rising RCLKI edge.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Register 04H: E1XC Transmit Interface Configuration Type Function FIFOBYP TAISEN TDNINV TDPINV TUNI FIFOFULL TRISE Default
This register enables Transmit Interface generate required digital output waveform format. FIFOBYP: FIFOBYP enables transmit bipolar input signals DJAT bypassed around FIFO bipolar outputs. When jitter attenuation being used, XPLS pulse driver being driven with "jitter-free" 16.384MHz clock TCLKI, DJAT FIFO bypassed reduce delay through transmitter section typically bits. NOTE: under this condition, BTCLK signal must synchronous TCLKI SMCLKO Transmit Timing Options register must set. When FIFOBYP logic bipolar inputs DJAT routed around FIFO directly into XPLS. When FIFOBYP logic bipolar transmit data passes through DJAT FIFO. TAISEN: TAISEN enables interface generate unframed all-ones alarm TDP/TDD TDN/TFLG multifunction pins. When TAISEN logic TUNI logic bipolar outputs forced pulse alternately, creating all-ones signal; when TAISEN TUNI both logic unipolar output forced all-ones. When TAISEN logic TDP/TDD TDN/TFLG multifunction outputs operate normally. transition transmitting outputs done such introduce bipolar violations.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
TDPINV,TDNINV: TDPINV TDNINV bits enable E1/DS1A Transmit Interface logically invert signals output TDP/TDD TDN/TFLG multifunction pins, respectively. When TDPINV logic TDP/TDD output inverted. When TDPINV logic TDP/TDD output inverted. When TDNINV logic TDN/TFLG output inverted. When TDNINV logic TDN/TFLG output inverted. TUNI: TUNI enables transmit interface generate unipolar digital outputs TDP/TDD TDN/TFLG multifunction pins. When TUNI logic TDP/TDD TDN/TFLG multifunction pins become unipolar outputs TFLG, updated selected TCLKO edge. When TUNI logic TDP/TDD TDN/TFLG multifunction pins become bipolar outputs TDN, also updated selected TCLKO edge. When TUNI logic (unipolar mode) analog transmit data outputs, TAN, from XPLS cannot used. FIFOFULL: FIFOFULL determines indication given TFLG output pin. When FIFOFULL logic TFLG output indicates when Digital Jitter Attenuator's FIFO within positions becoming full. When FIFOFULL logic TFLG output indicates when Digital Jitter Attenuator's FIFO within positions becoming empty. TRISE: TRISE configures interface update multifunction outputs rising edge TCLKO. When TRISE logic interface enabled update TDP/TDD TDN/TFLG output pins rising TCLKO edge. When TRISE logic interface enabled update outputs falling TCLKO edge. TRZ: configures interface transmit bipolar return-to-zero formatted waveforms. When logic interface enabled generate output signals waveforms with duration equal half TCLKO period. When logic interface enabled generate output signals waveforms with duration equal TCLKO period, updated selected edge TCLKO. only used when TUNI TRISE logic
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
When system reset, contents register logic enabling Transmit Interface output formatted positive negative pulse data outputs, updated falling TCLKO edge.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Register 05H: E1XC Transmit Backplane Options Type Function Unused Unused Unused Unused BTXCLK Unused BTX2RAIL BTXMFP Default
This register allows software configure Transmit backplane interface format. BTXCLK: BTXCLK selects source TRAN transmit clock input signal. When BTXCLK logic TRAN transmit clock driven with 2.048MHz recovered output clock (RCLKO) from receiver section. When BTXCLK logic TRAN transmit clock driven with 2.048MHz backplane transmit clock (BTCLK). Note that this must logic when Line Loopback enabled. BTX2RAIL: BTX2RAIL selects whether backplane transmit data signal presented transmitter multifunction inputs BTPCM/BTDP BTSIG/BTDN either dual-rail single-rail format. When BTX2RAIL logic multifunction pins become BTDP BTDN dual-rail inputs, which bypass TRAN input directly into jitter attenuator. expected that framing bits already inserted into dual-rail streams before they input BTDP BTDN. When BTX2RAIL logic multifunction pins become BTPCM BTSIG digital inputs. BTXMFP: BTXMFP selects type backplane frame alignment signal presented transmitter BTFP input. When BTXMFP logic BTFP must brought high mark frame every frame signalling multiframe brought following frame every frame multiframe. This mode allows both multiframe alignments
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
independently controlled using single BTFP signal. Note that signalling multiframe alignments coincident, BTFP must pulse high BTCLK cycle multiple frames. When BTXMFP logic rising edge BTFP indicates first each frame. Upon reset E1XC, these bits cleared zero.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Register 06H: E1XC Transmit Framing Options PATHCRC: PATHCRC allows upstream block errors preserved transmit bits. PATHCRC logic CRC-4 bits modified reflect values BTPCM which have changed prior transmission. When PATHCRC logic TRAN block allowed generate CRC-4 value which overwrites incoming CRC-4 word. PATHCRC effective, BTXMFP Transmit Backplane Options register must logic otherwise, identification incoming CRC-4 bits would impossible. PATHCRC only takes effect GENCRC TRAN Configuration register (44H) logic either INDIS FDIS same register logic1. TXSA4EN, TXSA5EN, TXSA6EN, TXSA7EN TXSA8EN: TXSAxEN bits control insertion data link into Time Slot National bits (Sa4 through Sa8). These bits only have effect TRAN block Configuration DLEN logic TRAN block Configuration SIGEN logic TXSAxEN bits take priority over INDIS FDIS bits TRAN block Configuration register. data link bits still inserted either INDIS FDIS logic TXDMASIG logic data link bits sourced internal HDLC transmitter; otherwise, bits sourced from TDLSIG pin. TXSA4EN logic TDLSIG value written into Time Slot non-frame alignment signal frames. TXSA8EN logic TDLSIG value written into Time Slot non-frame alignment signal frames. other enable bits operate analogous fashion. clock pulse Type Function PATHCRC Unused Unused TXSA4EN TXSA5EN TXSA6EN TXSA7EN TXSA8EN Default
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
generated TDLCLK each enable that logic combination enable bits allowed, resulting data rate between kbit/s kbit/s. Clearing enables disables insertion. National bits which included data link sourced from either BTPCM TRAN block International/National Control register. Upon reset E1XC, bits logic except TXSA4EN. default, kbit/s data link inserted into from TDLSIG input.
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Register 07H: E1XC Transmit Timing Options Type Function HSBPSEL XCLKSEL OCLKSEL1 OCLKSEL0 PLLREF1 PLLREF0 TCLKISEL SMCLKO Default
This register allows software configure options transmit timing section. HSBPSEL: HSBPSEL selects source high-speed clock used ELST, SIGX TPSC blocks. This allows E1XC interface higher rate backplanes (>2.048MHz) that externally gapped; however, instantaneous backplane clock frequency must exceed 3.0MHz. When HSBPSEL logic XCLK input signal divided used high-speed clock these blocks. XCLK must driven with 49.152MHz. When HSBPSEL logic block high-speed clock driven with internal 16.384MHz clock source selected XCLKSEL bit. XCLKSEL: XCLKSEL selects source high-speed clock used CDRC, FRMR, PMON blocks. When XCLKSEL logic XCLK input signal used high-speed clock these blocks. XCLK must driven with 16.384MHz. When XCLKSEL logic block high-speed clock driven with internal DJAT generated smooth 16.384MHz clock source. XCLK must driven with 49.152MHz. OCLKSEL1, OCLKSEL0: OCLKSEL[1:0] bits select source Digital Jitter Attenuator FIFO output clock signal. When OCLKSEL1 logic DJAT FIFO output clock driven with input data clock driving DJAT ICLK input. this mode jitter attenuation disabled input clock must jitter-free. When OCLKSEL1 logic DJAT FIFO output clock driven with
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
either TCLKI input clock internal smooth 2.048MHz clock, selected OCLKSEL0 bit. When OCLKSEL0 logic DJAT FIFO output clock driven with TCLKI input clock. When OCLKSEL0 logic DJAT FIFO output clock driven with internal smooth 2.048 clock selected TCLKISEL SMCLKO bits. PLLREF1, PLLREF0: PLLREF[1:0] bits select source Digital Jitter Attenuator phase locked loop reference signal follows: PLLREF1 PLLREF0 Source Reference Transmit clock used TRAN either 2.048MHz BTCLK 2.048MHz RCLKO, selected BTXCLK) BTCLK input RCLKO output TCLKI input
TCLKISEL,SMCLKO:
TCLKISEL SMCLKO bits select source internal smooth 2.048MHz 16.384MHz output clock signals. When TCLKISEL SMCLKO logic internal 2.048MHz 16.384MHz clock signals driven smooth 2.048MHz 16.384MHz clock sources generated DJAT. When TCLKISEL logic SMCLKO logic internal 2.048MHz clock signal driven TCLKI input signal divided internal 16.384MHz clock signal driven TCLKI input signal. When TCLKISEL SMCLKO logic internal 2.048MHz clock signal driven XCLK input signal divided internal 16.384MHz clock signal driven XCLK input signal. combination TCLKISEL logic SMCLKO logic should used. following table illustrates required settings these various clock sources affect transmitted data:
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PM6341 E1XC
DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER
Table
Transmit Timing Options Settings HSBPSEL XCLKSEL XCLK Freq 49.152MHz Effect Output Transmit Data Jitter attenuated. TCLKO smooth 2.048 MHz

DATA SHEET PMC-910419 ISSUE FRAMER/TRANSCEIVER PM6341 E1XC

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