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DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER PM4341A T1XC


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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
PM4341A
T1XC
SINGLE DSX-1 TRANSCEIVER DEVICE
DATA SHEET
ISSUE JUNE 1998
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
PUBLIC REVISION HISTORY Issue Issue Date June 1998 Details Change Data Sheet Reformatted Change Technical Content. Generated datasheet from PMC891007, February 1996 Release Issue T1XC July 1996 Release Issue T1XC
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
CONTENTS FEATURES APPLICATIONS
REFERENCES APPLICATION EXAMPLES BLOCK DIAGRAM. DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION 8.10 8.11 8.12 8.13 DIGITAL DS-1 RECEIVE INTERFACE (DRIF) ANALOG DSX-1 PULSE SLICER (RSLC). CLOCK DATA RECOVERY (CDRC) FRAMER (FRMR) FRAMER/SLIP BUFFER (FRAM) INBAND LOOPBACK CODE DETECTOR (IBCD) PULSE DENSITY VIOLATION DETECTOR (PDVD). PERFORMANCE MONITOR COUNTERS (PMON) ORIENTED CODE DETECTOR (RBOC) HDLC RECEIVER (RFDL) ALARM INTEGRATOR (ALMI) ELASTIC STORE (ELST) SIGNALLING EXTRACTOR (SIGX).
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23
RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) SIGNALLING ALIGNER (SIGA). BACKPLANE RECEIVE INTERFACE (BRIF) BASIC TRANSMITTER (XBAS) TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) INBAND LOOPBACK CODE GENERATOR (XIBC). ORIENTED CODE GENERATOR (XBOC) HDLC TRANSMITTER (XFDL) PULSE DENSITY ENFORCER (XPDE) DIGITAL JITTER ATTENUATOR (DJAT). 8.23.1 JITTER CHARACTERISTICS 8.23.2 JITTER TOLERANCE. 8.23.3 JITTER TRANSFER 8.23.4 FREQUENCY RANGE
8.24 8.25 8.26 8.27 8.28
TIMING OPTIONS (TOPS) DIGITAL DS-1 TRANSMIT INTERFACE (DTIF) ANALOG DSX-1 PULSE GENERATOR (XPLS) BACKPLANE TRANSMIT INTERFACE (BTIF) MICROPROCESSOR INTERFACE (MPIF)
REGISTER DESCRIPTION. NORMAL MODE REGISTER MEMORY
NORMAL MODE REGISTER DESCRIPTION. 10.1 INTERNAL REGISTERS
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
10.1.1 REGISTERS 4A-4FH: LATCHING PERFORMANCE DATA TEST FEATURES DESCRIPTION 11.1 11.2 11.3 TEST MODE REGISTER MEMORY INTERNAL REGISTERS TEST MODE
TIMING DIAGRAMS OPERATION 13.1 13.2 CONFIGURING T1XC FROM RESET USING INTERNAL TRANSMITTER 13.2.1 POLLED MODE 13.2.2 INTERRUPT MODE 13.2.3 DMA-CONTROLLED MODE 13.3 USING INTERNAL RECEIVER. 13.3.1 POLLED MODE 13.3.2 INTERRUPT MODE 13.3.3 DMA- CONTROLLED MODE 13.3.4 USED SUBSEQUENT DIAGRAMS: 13.4 USING LOOPBACK MODES. 13.4.1 PAYLOAD LOOPBACK. 13.4.2 LINE LOOPBACK. 13.4.3 DIAGNOSTIC DIGITAL LOOPBACK 13.4.4 DIAGNOSTIC METALLIC LOOPBACK 13.5 USING PER-CHANNEL SERIAL CONTROLLERS
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
13.5.1 INITIALIZATION 13.5.2 DIRECT ACCESS MODE 13.5.3 INDIRECT ACCESS MODE 13.6 13.7 PROGRAMMING XPLS WAVEFORM TEMPLATE USING DIGITAL JITTER ATTENUATOR. 13.7.1 DEFAULT APPLICATION. 13.7.2 DATA BURST APPLICATION 13.7.3 ELASTIC STORE APPLICATION. 13.7.4 ALTERNATE TCLKO REFERENCE APPLICATION 13.8 USING PERFORMANCE MONITOR COUNTER VALUES
ADDITIONAL APPLICATIONS ABSOLUTE MAXIMUM RATINGS. CAPACITANCE D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS T1XC CHARACTERISTICS ANALOG CHARACTERISTICS ORDERING THERMAL INFORMATION MECHANICAL INFORMATION.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
LIST REGISTERS REGISTER 00H: T1XC RECEIVE OPTIONS. REGISTER 01H: T1XC RECEIVE BACKPLANE OPTIONS REGISTER 02H: T1XC DATALINK OPTIONS REGISTER 03H: T1XC RECEIVE INTERFACE CONFIGURATION. REGISTER 04H: T1XC TRANSMIT INTERFACE CONFIGURATION REGISTER 05H: T1XC TRANSMIT BACKPLANE OPTIONS REGISTER 06H: T1XC TRANSMIT FRAMING BYPASS OPTIONS. REGISTER 07H: T1XC TRANSMIT TIMING OPTIONS REGISTER 08H: T1XC MASTER INTERRUPT SOURCE REGISTER 09H: T1XC MASTER INTERRUPT SOURCE REGISTER 0AH: T1XC MASTER DIAGNOSTICS. REGISTER 0BH: T1XC MASTER TEST REGISTER 0CH: T1XC REVISION/CHIP REGISTER 0DH: T1XC MASTER RESET REGISTER 0EH: T1XC PHASE STATUS WORD (LSB). REGISTER 0FH: T1XC PHASE STATUS WORD (MSB) REGISTER 10H: CDRC CONFIGURATION. REGISTER 11H: CDRC INTERRUPT ENABLE REGISTER 12H: CDRC INTERRUPT STATUS REGISTER 14H: XPLS LINE LENGTH CONFIGURATION REGISTER 15H: XPLS CONTROL/STATUS REGISTER 16H: XPLS CODE INDIRECT ADDRESS
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
REGISTER 17H: XPLS CODE INDIRECT DATA REGISTER 18H: DJAT INTERRUPT STATUS REGISTER 19H: DJAT REFERENCE CLOCK DIVISOR (N1) CONTROL. REGISTER 1AH: DJAT OUTPUT CLOCK DIVISOR (N2) CONTROL. REGISTER 1BH: DJAT CONFIGURATION REGISTER 1CH: ELST CONFIGURATION. REGISTER 1DH: ELST INTERRUPT ENABLE/STATUS. REGISTER 1EH: ELST TROUBLE CODE REGISTER 20H: FRMR CONFIGURATION. REGISTER 21H: FRMR INTERRUPT ENABLE REGISTER 22H: FRMR INTERRUPT STATUS REGISTER 2AH: RBOC ENABLE. REGISTER 2BH: RBOC CODE STATUS REGISTER 2CH: ALMI CONFIGURATION REGISTER 2DH: ALMI INTERRUPT ENABLE REGISTER 2EH: ALMI INTERRUPT STATUS REGISTER 2FH: ALMI ALARM DETECTION STATUS REGISTER 30H: TPSC CONFIGURATION. REGISTER 31H: TPSC ACCESS STATUS REGISTER 32H: TPSC CHANNEL INDIRECT ADDRESS/CONTROL. REGISTER 33H: TPSC CHANNEL INDIRECT DATA BUFFER. TPSC INTERNAL REGISTERS 01-18H: DATA CONTROL BYTE. TPSC INTERNAL REGISTERS 19-30H: IDLE CODE BYTE
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
REGISTER 34H: XFDL CONFIGURATION REGISTER 35H: XFDL INTERRUPT STATUS REGISTER 36H: XFDL TRANSMIT DATA REGISTER 38H: RFDL CONFIGURATION. REGISTER 39H: RFDL INTERRUPT CONTROL/STATUS. REGISTER 3AH: RFDL STATUS. REGISTER 3BH: RFDL RECEIVE DATA. REGISTER 3CH: IBCD CONFIGURATION REGISTER 3DH: IBCD INTERRUPT ENABLE/STATUS REGISTER 3EH: IBCD ACTIVATE CODE. REGISTER 3FH: IBCD DEACTIVATE CODE REGISTER 40H: SIGX CONFIGURATION. REGISTER 41H: SIGX ACCESS STATUS REGISTER 42H: SIGX CHANNEL INDIRECT ADDRESS/CONTROL REGISTER 43H: SIGX CHANNEL INDIRECT DATA BUFFER SIGX INTERNAL REGISTERS 01-18H: SIGNALLING DATA SIGX INTERNAL REGISTERS 21-38H: PER-CHANNEL CONFIGURATION DATA REGISTER 44H: XBAS CONFIGURATION. REGISTER 45H: XBAS ALARM TRANSMIT. REGISTER 46H: XIBC CONTROL. REGISTER 47H: XIBC LOOPBACK CODE REGISTER 49H: PMON INTERRUPT STATUS. REGISTER 4AH: PMON COUNT (LSB).
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
REGISTER 4BH: PMON COUNT (MSB). REGISTER 4CH: PMON COUNT (LSB) REGISTER 4DH: PMON COUNT (MSB) REGISTER 4EH: PMON COUNT. REGISTER 4FH: PMON OOF/COFA COUNT. REGISTER 50H: RPSC CONFIGURATION REGISTER 51H: RPSC ACCESS STATUS. REGISTER 52H: RPSC CHANNEL INDIRECT ADDRESS/CONTROL REGISTER 53H: RPSC CHANNEL INDIRECT DATA BUFFER RPSC INTERNAL REGISTERS 01-18H: DATA CONTROL BYTE RPSC INTERNAL REGISTERS 19-30H: DATA TRUNK CONDITIONING CODE BYTE RPSC INTERNAL REGISTERS 31-48H: SIGNALLING TRUNK CONDITIONING BYTE REGISTER 55H: PDVD INTERRUPT ENABLE/STATUS REGISTER 57H: XBOC CODE REGISTER 59H: XPDE INTERRUPT ENABLE/STATUS REGISTER 5DH: RSLC INTERRUPT ENABLE/STATUS REGISTER 0BH: T1XC MASTER TEST
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
viii
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
LIST FIGURES FIGURE EXAMPLE AINTERFACE USING PM7345 FIGURE EXAMPLE DSX-1/0 CROSS-CONNECT. FIGURE EXAMPLE MULTI-FEATURED, JITTER ATTENUATING FIGURE PLCC. FIGURE PQFP. FIGURE EXTERNAL ANALOG RECEIVE INTERFACE CIRCUIT FIGURE CDRC JITTER TOLERANCE FIGURE DJAT JITTER TOLERANCE FIGURE DJAT MINIMUM JITTER TOLERANCE XCLK ACCURACY. FIGURE DJAT JITTER TRANSFER. FIGURE EXTERNAL ANALOG TRANSMIT INTERFACE CIRCUIT FIGURE TRANSMIT TIMING OPTIONS FIGURE SLC®96 TRANSMIT DATALINK INTERFACE. FIGURE T1DM TRANSMIT DATALINK INTERFACE. FIGURE 4KBIT/S TRANSMIT DATALINK INTERFACE. FIGURE 2KBIT/S TRANSMIT DATALINK INTERFACE. FIGURE SLC®96 RECEIVE DATALINK INTERFACE. FIGURE T1DM RECEIVE DATALINK INTERFACE FIGURE 4KBIT/S RECEIVE DATALINK INTERFACE FIGURE 2KBIT/S RECEIVE DATALINK INTERFACE FIGURE D-CHANNEL RECEIVE DATALINK INTERFACE. FIGURE D-CHANNEL TRANSMIT DATALINK INTERFACE
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
FIGURE 1.544MHZ RECEIVE BACKPLANE INTERFACE. FIGURE 1.544MHZ RECEIVE LINE DATA INTERFACE. FIGURE 1.544MHZ TRANSMIT BACKPLANE INTERFACE FIGURE 2.048MHZ RECEIVE BACKPLANE INTERFACE. FIGURE 2.048MHZ TRANSMIT BACKPLANE INTERFACE FIGURE 1.544MHZ RECEIVE BACKPLANE INTERFACE WITHOUT SIGNALLING ALIGNMENT. FIGURE 1.544MHZ RECEIVE BACKPLANE INTERFACE WITH SIGNALLING ALIGNMENT. FIGURE 1.544MHZ TRANSMIT BACKPLANE INTERFACE WITHOUT SIGNALLING ALIGNMENT. FIGURE 1.544MHZ TRANSMIT BACKPLANE INTERFACE WITH SIGNALLING ALIGNMENT. FIGURE 1.544MHZ RECEIVE BACKPLANE INTERFACE WITH ALTFDL. FIGURE 1.544MHZ TRANSMIT BACKPLANE INTERFACE WITH ALTFDL FIGURE TYPICAL DATA FRAME. FIGURE RFDL NORMAL DATA ABORT SEQUENCE. FIGURE RFDL FIFO OVERRUN FIGURE XFDL NORMAL DATA SEQUENCE FIGURE XFDL UNDERRUN SEQUENCE FIGURE PAYLOAD LOOPBACK. FIGURE LINE LOOPBACK. FIGURE DIAGNOSTIC DIGITAL LOOPBACK FIGURE DIAGNOSTIC METALLIC LOOPBACK.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
FIGURE CODE REGISTER SEQUENCE DURING PULSE GENERATION. FIGURE CODE REGISTER SEQUENCE 0-110 FEET BUILD-OUT FIGURE COUNT FIGURE COUNT T1DM FRAMING FORMATS FIGURE COUNT SLC®96 FRAMING FORMAT. FIGURE COUNT FRAMING FORMAT FIGURE COUNT FRAMING FORMAT FIGURE COUNT FRAMING FORMAT. FIGURE COUNT SLC®96 FRAMING FORMAT. FIGURE COUNT T1DM FRAMING FORMAT. FIGURE EXAMPLE TERMINATING ISDN PRIMARY RATE D-CHANNEL WITH QFDL. FIGURE EXAMPLE TERMINATING ISDN PRIMARY RATE D-CHANNEL WITH VL1935 FIGURE MICROPROCESSOR READ ACCESS TIMING FIGURE MICROPROCESSOR WRITE ACCESS TIMING FIGURE BACKPLANE TRANSMIT INPUT TIMING DIAGRAM FIGURE XCLK=37.056MHZ INPUT TIMING FIGURE TCLKI INPUT TIMING FIGURE DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM. FIGURE TRANSMIT DATA LINK INPUT TIMING DIAGRAM FIGURE BACKPLANE RECEIVE INPUT TIMING DIAGRAM. FIGURE RECEIVE DATA LINK OUTPUT TIMING DIAGRAM.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
FIGURE BACKPLANE RECEIVE OUTPUT TIMING DIAGRAM. FIGURE RECOVERED DATA OUTPUT TIMING DIAGRAM FIGURE TRANSMIT INTERFACE OUTPUT TIMING DIAGRAM FIGURE TRANSMIT DATA LINK INTERFACE OUTPUT TIMING DIAGRAM FIGURE RECEIVE DATA LINK INTERFACE OUTPUT TIMING DIAGRAM FIGURE ANALOG RECEIVE DATA INPUT TIMING DIAGRAM. FIGURE PLASTIC LEADED CHIP CARRIER SUFFIX). FIGURE COPPER LEADFRAME PLASTIC QUAD FLAT PACK SUFFIX)
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE RECOMMENDED RECEIVE NETWORK VALUES TYPICAL CHARACTERISTICS RECEIVE TRANSFORMER TYPICAL CHARACTERISTICS TRANSMIT TRANSFORMER56 PLLREF[1:0] OPTIONS. TRANSMIT CLOCK OPTIONS. PHASE STATUS WORD OPERATION TRANSMIT LINE LENGTH OPTIONS. XPLS INTERNAL CODE REGISTER FRMR FRAME FORMAT OPTIONS.
TABLE ALMI FRAME FORMAT OPTIONS. TABLE TPSC INDIRECT REGISTER TABLE TPSC INVERT SIGNINV FUNCTIONS TABLE TPSC ZERO CODE SUPPRESSION OPTIONS. TABLE RFDL FILL LEVEL INTERRUPT OPTIONS TABLE IBCD CODE LENGTH OPTIONS. TABLE SIGX FRAME FORMAT OPTIONS. TABLE SIGX INDIRECT REGISTER MAP. TABLE XBAS ZERO CODE SUPPRESSION OPTIONS. TABLE XBAS FRAME FORMAT OPTIONS. TABLE XIBC CODE LENGTH OPTIONS TABLE RPSC INDIRECT REGISTER TABLE RPSC INVERSION OPTIONS.
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xiii
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
TABLE TEST MODE PRIMARY INPUT READING MAP. TABLE TEST MODE PRIMARY OUTPUT WRITING TABLE DEFAULT SETTINGS TABLE FRAME FORMAT TABLE SLC®96 FRAME FORMAT. TABLE FRAME FORMAT. TABLE T1DM FRAME FORMAT. TABLE PMON POLLING SEQUENCE TABLE PROCESSING. TABLE TYPICAL OUTPUT VOLTAGES XPLS CODES. TABLE PREPROGRAMMED XPLS CODE SEQUENCES. TABLE PMON COUNTER SATURATION CHARACTERISTICS TABLE SETTING T1XC PROCESS D-CHANNEL TABLE D.C. CHARACTERISTICS TABLE MICROPROCESSOR READ ACCESS TABLE MICROPROCESSOR WRITE ACCESS. TABLE BACKPLANE TRANSMIT INPUT TIMING (FIGURE TABLE XCLK=37.056MHZ INPUT (FIGURE 58). TABLE TCLKI INPUT (FIGURE 59). TABLE DIGITAL RECEIVE INTERFACE INPUT TIMING (FIGURE TABLE TRANSMIT DATA LINK INPUT TIMING (FIGURE TABLE BACKPLANE RECEIVE INPUT TIMING (FIGURE TABLE RECEIVE DATA LINK OUTPUT TIMING (FIGURE
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
TABLE BACKPLANE RECEIVE OUTPUT TIMING (FIGURE TABLE RECOVERED DATA OUTPUT TIMING (FIGURE 65). TABLE TRANSMIT INTERFACE OUTPUT TIMING (FIGURE 66). TABLE TRANSMIT DATA LINK INTERFACE OUTPUT TIMING (FIGURE TABLE RECEIVE DATA LINK INTERFACE OUTPUT TIMING (FIGURE TABLE SLICING THRESHOLD VOLTAGE. TABLE ANALOG RECEIVE DATA INPUT TIMING (FIGURE TABLE TAP/TAN OUTPUT RESISTANCE TABLE PACKAGING OPTIONS. TABLE THERMAL PROPERTIES.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
FEATURES Integrates full-featured framer line interface single device with analog circuitry receiving transmitting DSX-1 compatible signals digital circuitry terminating duplex DS-1 signal. Provides 8-bit microprocessor interface configuration, control, status monitoring. power CMOS technology Available either PLCC package, high density 14mm) PQFP package.
receiver section: Provides analog circuitry receiving DSX-1 signal feet from cross-connect. Direct digital inputs also provided allow by-passing analog front-end. Recovers clock data using digital phase locked loop high jitter tolerance. direct clock input provided allow clock recovery bypassed. Accepts dual rail single rail digital inputs. Supports B8ZS line code. Accepts gapped data streams support higher rate demultiplexing. Frames ESF, T1DM (DDS), SLC®96 format signals. Provides loss signal detection, red, yellow, alarm detection. Red, yellow, alarms integrated industry specifications. Detects violations ANSI T1.403 12.5% pulse density rule over moving window. Provides programmable in-band loopback code detection. Supports line path performance monitoring according AT&T ANSI specifications. Accumulators provided counting: CRC-6 errors second; Framing errors second; Line code violations 4095 second; Loss frame change frame alignment events second.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Provides bit-oriented code detection, HDLC/LAPD interface terminating data link. Supports polled, interrupt-driven, servicing HDLC interface. Extracts data link ESF, T1DM (DDS) SLC®96 modes. Extracts Dchannel Primary Rate interfaces. Provides two-frame elastic store buffer jitter wander attenuation that performs controlled slips indicates slip occurrence direction. Provides robbed signalling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, fixing, superframes signalling debounce per-channel basis. Provides trunk conditioning which forces programmable trouble code substitution signalling conditioning channels selected channels. Optionally provides dual rail digital output signals allow transparency. Also supports unframed mode. Supports transfer received signalling data 1.544 Mbit/s backplane buses 2.048 Mbit/s backplane buses.
transmitter section: Supports transfer transmitted signalling data from 1.544 Mbit/s 2.048 Mbit/s backplane buses. Formats data ESF, T1DM (DDS), SLC®96 format signals. Optionally accepts dual rail digital inputs allow transparency. Also supports unframed mode framing bit, CRC, data link by-pass. Provides signalling insertion, programmable idle code substitution, digital milliwatt code substitution, data inversion channel basis. Provides trunk conditioning which forces programmable trouble code substitution signalling conditioning channels selected channels. Provides minimum ones density through Bell (bit zero code suppression channel basis. Detects violations ANSI T1.403 12.5% pulse density rule over moving window optionally stuffs ones maintain minimum ones density. Allows insertion framed unframed in-band loopback code sequences.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Allows insertion data link ESF, T1DM (DDS) SLC®96 modes. Allows insertion channel Primary Rate interfaces. Supports transmission alarm indication signal (AIS) yellow alarm signal formats. Provides bit-oriented code generation HDLC/LAPD interface generating data link. Supports polled, interrupt-driven, servicing HDLC interface. Provides digital phase locked loop generation jitter transmit clock. Provides FIFO buffer jitter attenuation rate conversion transmitter. FIFO full empty indication allows bit-stuffing higher rate multiplexing applications. Supports B8ZS line code. Provides analog circuitry transmitting DSX-1 signal. Digitally programmable line build provided. Direct digital outputs also provided. Provides dual rail single rail digital output signals.
APPLICATIONS Channel Service Units (CSU) Data Service Units (DSU) Channel Banks BANK) Multiplexers (CPE MUX) Digital Private Branch Exchanges (DPBX) Digital Access Cross-Connect Systems (DACS) Electronic Cross-Connect Systems (EDSX) Frame Relay Interfaces AInterfaces ISDN Primary Rate Interfaces (PRI) SONET Add/Drop Multiplexers (ADM) Test Equipment
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
REFERENCES American National Standard Telecommunications, ANSI T1.102-1992 "Digital Hierarchy Electrical Interfaces." American National Standard Telecommunications Digital Hierarchy Formats Specification, ANSI T1.107-1991 American National Standard Telecommunications Carrier Customer Installation Metallic Interface Specification, ANSI T1.403-1989 American National Standard Telecommunications Integrated Services Digital Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer Specification, ANSI T1.408-1990 Bell Communications Research Digital Interface Between SLC96 Digital Loop Carrier System Local Digital Switch, TR-TSY-000008, Issue August 1987. Bell Communications Research Rate Digital Service Monitoring Unit Functional Specification, TA-TSY-000147, Issue October, 1987. Bell Communications Research Digital Cross-Connect System Requirements Objectives, TR-TSY-000170, Issue November 1985. Bell Communications Research Alarm Indication Signal Requirements Objectives, TR-TSY-000191 Issue 1986. Bell Communications Research Extended Superframe Format Interface Specification, TR-TSY-000194 Issue December 1987. (Replaced TRTSY-000499) Bell Communications Research Digital Data System (DDS) Data Multiplexor (T1DM), TA-TSY-000278, Issue November 1985. Bell Communications Research Integrated Digital Loop Carrier Generic Requirements, Objectives, Interface, TR-TSY-000303, Issue September, 1986. Bell Communications Research Functional Criteria Interface Connector, TR-TSY-000312, Issue March, 1988. Bell Communications Research Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue December, 1989.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
AT&T Digital Channel Bank Requirements Objectives, PUB43801, November 1982. AT&T Digital Channel Bank Requirements Objectives Addendum PUB43801A, January 1985. AT&T Requirements Interfacing Digital Terminal Equipment Services Employing Extended Superframe Format, PUB54016, October 1984. AT&T, 62411 Accunet T1.5 "Service Description Interface Specification" December, 1990.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
APPLICATION EXAMPLES Figure Example AInterface Using PM7345
BRPCM 13/CA [7:0] [7:0]
T1XC
BTFP
tatio
37.056
[8:0 [7:0
[7:0 RESB
[7:0 [7:0
terfa
From sele decode circuitry
From ster reset ircuitry
Example shows PM4341 T1XC PM6341 E1XC used with PM7345 Saturn User Network Interface (S/UNI-PDHTM) implement Awide area user network interfaces (UNI) network node interfaces (NNI). this example, framing functions provided PM4341A T1XC. combination T1XC E1XC devices with S/UNI-PDHallows both PLCP formatted DS1/E1 signals CCITT G.804 compliant DS1/E1 signals processed. G.804 specification defines Acell mappings variety transmission formats, including 1.544 Mbit/s 2.048 Mbit/s formats.
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PMC-900602
BTPCM BTFP BTCLK BRFP STo3 STo4 STo5 STo6 STo7 CSTo BRPCM BRFPO ack. BTPCM BTFP BTCLK BRFP BRPCM BRFPO STo2 STo0 STo1
DATA SHEET
Figure
ISSUE
T8980
Example DSX-1/0 Cross-connect
4.096 Fram Puls
DSX-1 Receive
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
tran eiver BRPCM BRPCM tran eiver tran eivers tran eive
FRAMER/TRANSCEIVER
PM4341A T1XC
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Example shows Cross-Connect utilizing four T1XC chips Mitel MT8980 Digital Time/Space Switch implement simple cross-connect. alternate architecture could MT8980s, voice switch other signalling switch, T1XCs cross-connect eight T1s. (Note: true implementation would require redundancy switch core.) this example, T1XC chips programmed receive generate same framing format, using 2.048 backplane data rate. "system frame pulse" signal stretched through D-FF into pulse 488ns duration, which used frame align data each transceiver through elastic store provide frame alignment indication transmitters. system frame pulse signal used indicate frame alignment synchronization MT8980. Another D-FF configured toggle generate 2.048MHz clock from system 4.096MHz clock source, synchronized system frame pulse. Figure Example Multi-featured, jitter attenuating
341A
etwork inte rface unit
BRFP BRCLK BRPCM BRFPO RCLKO
BRFP BRCLK BRPCM BRFPO RCLKO
eive
XCLK
XCLK
Example application utilizing T1XC chips implement multi-featured Channel Service Unit with jitter attenuation. T1XCs programmed receive generate same framing format, using 1.544 backplane data rate with Elastic Stores bypassed. T1XC #1's Timing Options Register programmed enable jitter attenuation outgoing transmit data network, using backplane transmit clock (BTCLK= recovered clock from customer interface) jitter reference. Similarly, T1XC programmed attenuate outgoing transmit data jitter customer equipment using backplane transmit clock (BTCLK= recovered
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
clock from network interface) jitter reference. Also, since T1XC #2's elastic store bypassed, TRSLIP Receive Options register provide measure frequency difference between network clock customer clock monitoring time interval between resulting slip indications. This application readily modified provide additional features simply changing T1XC configurations software. external wiring changes necessary support framing format conversion loop time network transmit data network receive recovered clock. example, provide format conversion customer's SF-based equipment network, T1XC would programmed receive transmit formatted data, while providing superframe alignment indication backplane frame pulse output (BRFPO). T1XC would programmed receive transmit formatted data, while providing every second superframe alignment indication BRFPO. provide loop timing network transmit network receive clock, T1XC would programmed elastic store, thereby providing slip buffering handle frequency difference between network customer equipment clocks. T1XC would programmed RCLKO transmitter clock instead input BTCLK.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
BLOCK DIAGRAM
TCLKI BTIF BACKPLANE TRANSMIT INTERFACE XBAS TOPS BASICTRANSMITTER: TIMING FRAME GENERATION, OPTIONS ALARM INSERTION, TRUNK CONDITIONING LINE CODING TPSC XIBC PER-CHAN IN-BAND CONT: LOOPBACK SIG,IDLE, CODE ZERO CONT GENERATOR A(7-0) INTB RSTB MPIF MICROPROCESSOR INTERFACE XPDE PULSE DENSITY ENFORCER XBOC BITORIENTED CODE GEN. XFDL HDLC TRANSMITTER TOPS TIMING OPTIONS DJAT DIGITAL JITTER ATTENUATOR
TRANSMITTER
XPLS ANALOG DSX-1 PULSE GENERATOR
BTPCM/BTDP BTSIG/BTDN BTFP BTCLK
DTIF DIGITAL DS-1 TRANSMIT INTERFACE
TCLKO TDP/TDD TDN/TFLG
TDLCLK/ TDLUDR TDLSIG/ TDLINT
D(7-0) BRCLK BRFPI XCLK/VCLK RSLC ANALOG DSX-1 PULSE SLICER PMON PERFORMANCE MONITOR COUNTERS FRMR FRAMER: FRAME ALIGNMENT, ALARM EXTRACT ALMI ALARM INTEGRATOR RBOC BITORIENTED CODE DETECTOR ELST ELASTIC STORE SIGX SIGNALLING EXTRACTOR BRPCM/BRDP BRSIG/BRDN BRFPO
RECEIVER
RCLKI RDP/RDD/ RDN/RLCV/ SDN/
DRIF DIGITAL DS-1 INTERFACE
BRIF BACKPLANE RECEIVE INTERFACE
CDRC CLOCK DATA RECOVERY IBCD IN-BAND LOOPBACK CODE DETECTOR PDVD PULSE DENSITY VIOLATION DETECTOR
RDPCM/RPCM RCLKO
RPSC FRAM PER-CHANNEL FRAMER/ CONTROL: SLIP BUFFER TRUNK CONDITION
RFDL HDLC RECEIVER
RDLSIG/ RDLINT RDLCLK/ RDLEOM
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
DESCRIPTION PM4341A Single Framer/Transceiver (T1XC) feature-rich device suitable many systems with minimum external circuitry. T1XC software configurable, allowing feature selection without changes external wiring. receive side, T1XC recovers clock data configured frame common DS-1 signal formats: ESF, T1DM (DDS), SLC®96. Analog circuitry provided allow direct reception DSX-1 compatible signal feet from cross-connect using only external transformer passive components. T1XC also supports detection various alarm conditions such loss signal, pulse density violation, alarm, yellow alarm, alarm. T1XC detects indicates presence yellow patterns also integrates yellow, red, alarms industry specifications. Performance monitoring with accumulation CRC-6 errors, framing errors, line code violations, loss frame events provided. T1XC also detects presence in-band loopback codes, oriented codes, detects terminates HDLC messages data link. elastic store slip buffering adaptation backplane timing provided, signalling extractor that supports signalling debounce, signalling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, signalling fixing per-channel basis. Receive side data signalling trunk conditioning also provided. transmit side, T1XC generates framing ESF, T1DM (DDS), SLC®96 formats, framing optionally disabled. Internal analog circuitry allows direct transmission DSX-1 compatible signal using only external transformer. Digitally programmable line build allows transmission DSX-1 compatible signals feet from cross-connect. T1XC also supports signalling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, zero code suppression per-channel basis. zero code suppression selectable Bell (bit GTE, standards, also disabled. Transmit side data signalling trunk conditioning provided. T1XC also generate in-band loopback codes, oriented codes, transmit HDLC messages data link. T1XC generate jitter transmit clock provides FIFO transmit jitter attenuation. When used jitter attenuation, full empty status this FIFO made
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
available facilitate higher order multiplexing applications controlling bitstuffing logic. T1XC provides both parallel microprocessor interface controlling operation T1XC device, serial interfaces that allow 1.544 Mbit/s 2.048 Mbit/s backplanes directly supported. Tolerance gapped clocks allows other backplane rates supported with minimum external logic.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
DIAGRAM Figure PLCC
TDN/TFLG TDLCLK/TDLUDR TDLSIG/TDLINT
BTPCM/BTDP BTSIG/BTDN BTFP
XCLK/VCLK
TDP/TDD VSSO[0] VDDO[0]
RSTB INTB D[0] D[1] D[2] D[3] VSSO[1] VSSI[0] VDDI[0] VDDO[1] D[4] D[5] D[6] D[7]
VDDO[3]
TCLKO
BTCLK TCLKI
TAVD
TAVS
VSSO[3] RAVD RAVS VSSI[1] VDDI[1] RCLKI BRFPO BRPCM/BRDP BRSIG/BRDN RDP/RDD/SDP RDN/RLCV/SDN VDDO[2]
PM4341A
(TOP VIEW)
RDLCLK/RDLEOM RDLSIG/RDLINT RCLKO RDPCM/RPCM VSSO[2] BRFPI BRCLK A[1] A[2] A[3] A[5] A[6] A[7] A[0] A[4]
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Figure
PQFP
TDN/TFLG TDLCLK/TDLUDR TDLSIG/TDLINT TAVS TAVD VDDO[3] XCLK/VCLK BTPCM/BTDP BTSIG/BTDN BTFP BTCLK TCLKI TCLKO
RSTB INTB D[0] D[1] D[2] D[3] VSSO[1] VSSI[0] VDDI[0] VDDO[1] D[4] D[5] D[6] D[7]
TDP/TDD VSSO[0] VDDO[0]
PM4341A
(TOP VIEW)
VSSO[3] RAVD RAVS VSSI[1] VDDI[1] RCLKI BRFPO BRPCM/BRDP BRSIG/BRDN RDP/RDD/SDP RDN/RLCV/SDN VDDO[2]
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
BRCLK RDLCLK/RDLEOM RDLSIG/RDLINT RCLKO RDPCM/RPCM VSSO[2] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] BRFPI
PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
DESCRIPTION Name RDP/ Type PQFP PLCC Function Receive Digital Positive Line Pulse (RDP). This input available when T1XC configured receive dual-rail formatted data. input enabled either waveforms. When enabled NRZ, this input enabled sampled rising falling edge RCLKI. When enabled clock recovered from inputs. Receive Digital DS-1 Signal (RDD). When T1XC configured receive single-rail data, this input enabled sampled rising falling edge RCLKI. Sliced Positive Line Pulse (SDP). This becomes output when receive analog line interface powered positive pulse output corresponds sampled positive pulse excursion input. Receive Digital Negative Line Pulse (RDN). This input available when T1XC configured receive dual-rail formatted data. input enabled either waveforms. When enabled NRZ, this input enabled sampled rising falling edge RCLKI. When enabled clock recovered from inputs.
RDD/
RDN/
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name RLCV/ Type
PQFP PLCC Function Receive Line Code Violation Indication (RLCV). When T1XC configured receive single-rail data, this input enabled sampled rising falling edge RCLKI. Sliced Negative Line Pulse (SDN). This becomes output when receive analog line interface powered positive pulse output corresponds sampled negative pulse excursion input. Input Receive Line Clock Input (RCLKI). This input externally recovered 1.544 line clock that enabled sample inputs rising falling edge when input format enabled dual-rail NRZ; sample RLCV inputs rising falling edge when input format enabled single-rail. Receive Analog Signal (RAS). This analog input samples signal external isolation transformer. connected positive lead transformer secondary through passive attenuation network. Receive Reference (REF). This analog bidirectional provides bias external isolation transformer. connected negative lead transformer secondary decoupling capacitor RAVS.
RCLKI
Input
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name Type
PQFP PLCC Function Receive Peak Hold Network (RRC). This analog bidirectional connected external parallel resistor/capacitor network RAVS. This network necessary operation internal peak detector that tracks incoming signal level. Receive Analog Power (RAVD). This provides supply receive analog line interface. receive analog line interface used, power consumption T1XC reduced connecting RAVD analog ground pin, RAVS. RAVD must connected common, well decoupled supply together with VDDO[2:0] VDDI[1:0] pins. Care must taken avoid coupling noise induced VDDO VDDI pins into RAVD pin. Receive Analog Ground (RAVS). This provides ground supply receive analog line interface. RAVS must connected common ground together with VSSO[2:0] VSSI[1:0] pins. Care must taken avoid coupling noise induced VSSO VSSI pins into RAVS pin. Recovered Clock Output (RCLKO). This output signal recovered 1.544 clock, synchronized XCLK signal. RCLKO signal recovered from received analog inputs interface powered up), from inputs input format dual-rail RZ), from RCLKI input input format NRZ).
RAVD
Power
RAVS
Ground
RCLKO
Output
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name RDPCM/ Type Output
PQFP PLCC Function Recovered Decoded (RDPCM). This output available when T1XC configured decoded data output. This output signal recovered data stream with B8ZS decoding applied, B8ZS decoding enabled. updated falling edge RCLKO. RDPCM signal meant used when digital receive interface configured uni-polar operation since this data should available input. Recovered (RPCM). This output available when T1XC configured data output. This output signal recovered data stream without optional B8ZS decoding applied. updated falling edge RCLKO.
RPCM
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name Type Output
PQFP PLCC Function Receive Frame Pulse (RFP). When T1XC configured receive frame pulse output, pulses high RCLKO cycle during each 193-bit frame, indicating frame alignment RPCM/RDPCM data stream. does indicate frame alignment RDPCM when digital receive interface configured unipolar operation (i.e. RUNI=1and RDIEN=1 Register 03h). When configured receive superframe output, pulses high RCLKO cycle during frame frame superframe, indicating superframe alignment RPCM/RDPCM data stream. When configured receive alternate superframe output, pulses high RCLKO cycle during frame every second frame superframe, indicating superframe alignment RPCM/RDPCM data stream. This alternate superframe indication useful performing format conversion from while maintaining same superframe alignment. updated falling edge RCLKO.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name RDLSIG/ Type Output
PQFP PLCC Function Receive Data Link Signal (RDLSIG). RDLSIG signal available this output when internal HDLC receiver (RFDL) disabled from use, optionally, when D-channel Primary Rate interface extracted. When T1XC configured receive formatted data, RDLSIG contains data stream extracted from facility data link; when T1XC configured receive formatted data, RDLSIG output held low; when T1XC configured receive T1DM, RDLSIG reflects value R-bit T1DM sync word; when T1XC configured SLC®96, RDLSIG contains value framing bits. When Dchannel enabled extraction, RDLSIG contains contents channel each DS-1 frame. RDLSIG updated falling edge RDLCLK. Receive Data Link Interrupt (RDLINT). RDLINT signal available this output when RFDL enabled. RDLINT goes high when event occurs which changes status HDLC receiver.
RDLINT
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name RDLCLK/ Type Output
PQFP PLCC Function Receive Data Link Clock (RDLCLK). RDLCLK signal available this output when internal HDLC receiver (RFDL) disabled from use, optionally, when D-channel Primary Rate interface extracted. RDLCLK used process data stream contained RDLSIG output. When T1XC configured receive formatted data, RDLCLK output held low. other formats rising edge RDLCLK used sample data RDLSIG. Receive Data Link Message (RDLEOM). RDLEOM signal available this output when RFDL enabled. RDLEOM goes high when last byte received sequence read from RFDL FIFO buffer, when FIFO buffer overrun. Output Backplane Receive (BRPCM). BRPCM signal available this output when backplane configured single-rail output. BRPCM contains recovered data stream passed through ELST, SIGX, RPSC. When ELST by-passed, BRPCM stream aligned backplane timing updated falling edge BRCLK. When ELST by-passed, BRPCM aligned receive line timing updated falling edge RCLKO.
RDLEOM
BRPCM/
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name BRDP Type Output
PQFP PLCC Function Backplane Receive Positive Line Pulse (BRDP). BRDP signal available this output when backplane configured dual-rail output. BRDP output represents receive digital positive pulse signal extracted from input bipolar signal. BRDP updated falling edge RCLKO. Backplane Receive Signalling (BRSIG). BRSIG signal available this output when backplane configured single-rail output. BRSIG contains extracted signalling bits each channel frame, repeated entire superframe. Each channel's signalling bits valid locations 5,6,7,8 channel channel-aligned with BRPCM data stream. When ELST by-passed, BRSIG stream aligned backplane timing updated falling edge BRCLK. When ELST by-passed, BRSIG aligned receive line timing updated falling edge RCLKO. Backplane Receive Negative Line Pulse (BRDN). BRDN signal available this output when backplane configured dual-rail output. BRDN output represents receive digital negative pulse signal extracted from input bipolar signal. BRDN updated falling edge RCLKO.
BRSIG/
Output
BRDN
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name BRFPO Type Output
PQFP PLCC Function Backplane Frame Pulse Output (BRFPO). When T1XC configured backplane receive frame pulse output, BRFPO pulses high BRCLK cycle RCLKO cycle ELST by-passed) during each 193-bit frame, indicating frame alignment BRPCM data stream. When configured backplane receive superframe output, BRFPO pulses high BRCLK cycle RCLKO cycle ELST by-passed) during frame frame superframe, indicating superframe alignment BRPCM data stream. When configured backplane alternate receive superframe output, BRFPO pulses high BRCLK cycle RCLKO cycle ELST by-passed) during frame every second frame superframe, indicating superframe alignment BRPCM data stream. This alternate superframe indication useful performing format conversion from while maintaining same superframe alignment. BRFPO updated falling edge BRCLK RCLKO.
BRCLK
Input
Backplane Receive Clock (BRCLK). This clock should either 1.544MHz 2.048MHz with optional gapping adaptation non-uniform backplane data streams. T1XC configured ignore BRCLK input RCLKO signal place when ELST bypassed.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name BRFPI Type Input
PQFP PLCC Function Backplane Frame Pulse Input (BRFPI). This input used frame align received data system backplane. frame alignment only required, pulse least BRCLK cycle wide must provided BRFPI every times. receive signalling alignment required, receive signalling alignment must enabled, pulse least BRCLK cycle wide must provided BRFPI every frame times. BRFPI sampled rising edge BRCLK. Backplane Transmit (BTPCM). non-return zero, digital data stream transmitted input this when backplane configured single-rail input. BTPCM signal sampled rising edge BTCLK. Backplane Transmit Positive Line Pulse (BTDP). positive pulse dualrail signal transmitted input this when backplane configured dual-rail input. dual-rail input mode, BTDP input by-passes transmitter directly into DJAT. BTDP sampled rising edge BTCLK.
BTPCM/
Input
BTDP
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name BTSIG/ Type Input
PQFP PLCC Function Backplane Transmit Signalling (BTSIG). BTSIG input signal contains signalling bits each channel transmit data frame, repeated entire superframe. This signal input BTSIG when backplane configured single-rail input. Each channel's signalling bits locations 5,6,7,8 channel channel-aligned with BTPCM data stream. BTSIG sampled rising edge BTCLK. Backplane Transmit Negative Line Pulse (BTDN). negative pulse dual-rail signal transmitted input this when backplane configured dual-rail input. dual-rail input mode, BTDN input by-passes transmitter directly into DJAT. BTDN sampled rising edge BTCLK. Input Backplane Transmit Frame Pulse (BTFP). This input used frame align transmitter system backplane. frame alignment only required, pulse least BTCLK cycle wide must provided BTFP every times. superframe alignment required, transmit superframe alignment must enabled, pulse least BTCLK cycle wide must provided BTFP every frame times.
BTDN
BTFP
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name BTCLK Type Input
PQFP PLCC Function Backplane Transmit Clock (BTCLK). This clock should either 1.544MHz 2.048MHz with optional gapping adaptation from non-uniform backplane data streams. T1XC configured ignore BTCLK input RCLKO signal place. Transmit Data Link Signal (TDLSIG). TDLSIG signal input this when internal HDLC transmitter (XFDL) disabled from use. TDLSIG source data stream inserted into data link. When T1XC configured transmit SLC®96 formatted data, TDLSIG input source framing bits; when T1XC configured transmit T1DM with R-bit replacement, TDLSIG source R-bit T1DM sync word. TDLSIG sampled rising edge TDLCLK. Transmit Data Link Interrupt (TDLINT). TDLINT signal output this when XFDL enabled. TDLINT goes high when last data byte written XFDL been transmission processor intervention required either write control information message, provide more data.
TDLSIG/
TDLINT
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name TDLCLK/ Type Output
PQFP PLCC Function Transmit Data Link Clock (TDLCLK). TDLCLK signal available this output when internal HDLC transmitter (XFDL) disabled from use. rising edge TDLCLK used sample data stream contained TDLSIG input. When T1XC configured transmit formatted data, TDLCLK output held low. Transmit Data Link Underrun (TDLUDR). TDLUDR signal available this output when XFDL enabled. TDLUDR goes high when processor failed service TDLINT interrupt before transmit buffer emptied. Output Transmit Clock Output (TCLKO). TDN, outputs enabled updated rising falling edge TCLKO. outputs also driven with timing derived from TCLKO. TCLKO 1.544 clock that adequately jitter wander free absolute terms permit acceptable DSX-1 DS-1 signal generated. Depending configuration T1XC, TCLKO derived from TCLKI, RCLKO, BTCLK, with without jitter attenuation. Transmit Digital Positive Line Pulse (TDP). This signal available output when T1XC configured transmit dual-rail data. signal formatted either waveforms, enabled updated rising falling edge TCLKO.
TDLUDR
TCLKO
TDP/
Output
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name Type Output
PQFP PLCC Function Transmit Digital DS-1 Signal (TDD). This signal available output when configured transmit single-rail data. signal enabled updated rising falling edge TCLKO. Transmit Digital Negative Line Pulse (TDN). This signal available output when T1XC configured transmit dual-rail data. signal formatted either waveforms, enabled updated rising falling edge TCLKO. Transmit FIFO Flag (TFLG). This signal available when configured transmit single-rail data. TFLG output indicates when transmit rate conversion FIFO DJAT nearing empty full condition. Either indication selected. This output enabled updated rising falling edge TCLKO. Output Transmit Analog Positive Pulse (TAP). This analog output drives signal through external matching transformer. connected positive lead transformer primary. analog Transmit Monitor Positive point internally bonded this output used monitor positive pulses transmit line.
TDN/
Output
TFLG
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name Type Output
PQFP PLCC Function Transmit Analog Negative Pulse (TAN). This analog output drives signal through external matching transformer. connected negative lead transformer primary. analog Transmit Monitor Negative point internally bonded this output used monitor negative pulses transmit line.
Transmit Reference Decoupling Capacitor (TC). This analog bidirectional provides decoupling internal reference generator. connected decoupling capacitor TAVD. Transmit Analog Power (TAVD). This provides supply transmit analog line interface. Even transmit analog line interface used, supply must provided. TAVD must connected common, well decoupled supply together with VDDO[2:0] VDDI[1:0] pins. Care must taken avoid coupling noise induced VDDO VDDI pins into TAVD pin. Transmit Analog Ground (TAVS). This provides ground supply transmit analog line interface. TAVS must connected common ground together with VSSO[2:0] VSSI[1:0] pins. Care must taken avoid coupling noise induced VSSO VSSI pins into TAVS pin.
TAVD
Power
TAVS
Ground
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name TCLKI Type Input
PQFP PLCC Function Transmit Clock Input (TCLKI). This input signal used generate TCLKO clock signal. Depending upon configuration T1XC, TCLKO derived directly from TCLKI dividing TCLKI TCLKO derived from TCLKI after jitter attenuation. TCLKI jitter-free when divided down kHz, then possible derive TCLKO from TCLKI when TCLKI multiple (i.e. kHz, equals 256). T1XC configured ignore TCLKI input utilize BTCLK RCLKO instead. RCLKO also substituted TCLKI line loopback enabled. Crystal Clock Input (XCLK). This signal provides timing many portions T1XC. Depending configuration T1XC, XCLK nominally 37.056 32ppm 12.352 50ppm, duty cycle clock. When transmit clock generation jitter attenuation required, XCLK driven with 12.352 clock. When transmit clock generation jitter attenuation required, XCLK must driven with 37.056 clock. Implementation Line Loopback also simplified when 37.056 clock used. Vector Clock (VCLK). VCLK signal used during T1XC production test verify internal functionality.
XCLK/
Input
VCLK
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name INTB Type Output
PQFP PLCC Function Active open-drain Interrupt signal (INTB). This signal goes when unmasked interrupt event detected internal interrupt sources, including internal HDLC transceiver. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source. Active chip select (CSB). This signal must enable T1XC register accesses. must high least once after powerup clear internal test modes. used, then should tied inverted version RSTB, which case determine register access. Bidirectional data (D[7:0]). This used during T1XC read write accesses.
Input
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]
Input
Active read enable (RDB). This signal pulsed enable T1XC register read access. T1XC drives D[7:0] with contents addressed register while both low.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name Type Input
PQFP PLCC Function Active write strobe (WRB). This signal pulsed enable T1XC register write access. D[7:0] contents clocked into addressed normal mode register rising edge CSB, where indicates logical Address latch enable (ALE). This signal latches address contents, A[7:0], when low, allowing T1XC interfaced multiplexed address/data bus. When high, address latches transparent. Active reset (RSTB). This signal asynchronously reset T1XC. RSTB Schmitt-trigger input with integral pull-up. Address (A[7:0]). This selects specific registers during T1XC register accesses.
Input
RSTB
Input
A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] VDDO[0] VDDO[1] VDDO[2] VDDO[3]
Input
Power
ring power pins (VDDO[3:0]). These pins must connected common, well decoupled supply together with VDDI[1:0] pins. Care must taken avoid coupling noise induced VDDO pins into VDDI pins.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Name VDDI[0] VDDI[1] Type Power
PQFP PLCC Function Core power pins (VDDI[1:0]). These pins must connected common, well decoupled supply together with VDDO[2:0] pins. ring ground pins (VSSO[3:0]). These pins must connected common ground together with VSSI[1:0] pins. Care must taken avoid coupling noise induced VSSO pins into VSSI pins. Core ground pins (VSSI[1:0]). These pins must connected common ground together with VSSO[2:0] pins.
VSSO[0] VSSO[1] VSSO[2] VSSO[3] VSSI[0] VSSI[1]
Ground Ground
Notes Description: VDDI VSSI ground connections, respectively, core circuitry device. VDDO VSSO ground connections, respectively, ring circuitry device. TAVD TAVS ground connections, respectively, transmit analog circuitry device. These power supply connections must utilized must connect common ground rail, appropriate. There impedance connection within PM4341A between core, ring, transmit analog supply rails. Failure properly make these connections result improper operation damage device. Care must taken avoid coupling noise into transmit analog supply rails. RAVD RAVS ground connections, respectively, receive analog circuitry device. These power supply connections need only used receive analog function desired should then connect common ground rail, appropriate, with core, ring, transmit analog supply rails. There impedance connection within PM4341A between receive analog supply rail other supply rails. When receive analog function desired, RAVD should connected RAVS. Care must taken avoid coupling noise into receive analog supply rails.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Inputs RSTB have integral pull-up resistors. Pins 80-pin PQFP connected. These pins should left unconnected application. TDLSIG/TDLINT integral pull-up resistor defaults being input after reset. When internal RFDL enabled, RDLINT output goes high: when number bytes specified RFDL Interrupt Status/Control Register have been received data link, immediately detection RFDL FIFO buffer overrun, immediately detection message, immediately detection abort condition, immediately detection transition from receiving ones flags.
interrupt cleared start next RFDL Data Register read that results empty FIFO buffer. This independent FIFO buffer fill level which interrupt programmed. there still data remaining buffer, RDLINT will remain high. interrupt RFDL FIFO buffer overrun condition cleared RFDL Data Register read RFDL Status Register read. RDLINT output always forced disabling RFDL (setting RFDL Configuration Register logic disabling internal HDLC receiver T1XC Receive Data Link Configuration Register), forcing RFDL terminate reception (setting RFDL Configuration Register logic RDLINT output forced disabling interrupts with RFDL Interrupt Status/Control Register. However, internal interrupt latch cleared, state this latch still read through RFDL Interrupt Status/Control Register. RDLEOM output goes high: immediately detection RFDL FIFO buffer overrun, when data byte written into RFDL FIFO buffer message condition read, when data byte written into RFDL FIFO buffer abort condition read,
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
when data byte written into RFDL FIFO buffer transition from receiving ones flags read.
RDLEOM reading RFDL Status Register disabling RFDL. TDLUDR output goes high when processor unable service TDLINT request more data within specific time-out period. This period dependent upon frequency TDLCLK: TDLCLK frequency (ESF full rate), time-out TDLCLK frequency (half FDL), time-out 2.0ms; TDLCLK frequency (T1DM R-bit insertion), timeout 500µs.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
FUNCTIONAL DESCRIPTION Digital DS-1 Receive Interface (DRIF) Digital DS-1 Receive Interface provides control over various input options available multifunctional digital receive pins RDP/RDD/SDP RDN/RLCV/SDN. When configured dual-rail input, multifunctional pins become inputs. These inputs enabled receive either return-to-zero (RZ) non-return-to-zero (NRZ) signals; input signals sampled either rising falling edge RCLKI. When interface configured single-rail input, multifunctional pins become RLCV inputs, which sampled either rising falling RCLKI edge. Finally, when analog interface used, multifunction pins become outputs, indicating sliced pulses corresponding received positive negative analog line pulses.
Analog DSX-1 Pulse Slicer (RSLC) Analog DSX-1 Pulse Slicer function provided RSLC block. Receive Data Slicer (RSLC) block provides first stage signal conditioning G.703 1544kbit/s serial data stream converting bipolar line signals dual rail pulses. Before output pulse generated RSLC block, bipolar input signals must rise their peak amplitude. This level referred slicing level. threshold criteria insures accurate pulse mark recognition presence noise. RSLC block disabled strapping receive analog power pin, RAVD ground. When RLSC disabled, T1XC accepts input pulses RDP/RDD RDN/RLCV pins. RSLC block relies external network compliance DSX-1 input port specifications. RSLC block configured off-chip attenuator operate modes: terminating mode bridging mode. According G.703, amplitude DSX-1 terminating mode received pulse line-coupling transformer's primary should range from 3.6V 1.2V (depending length cable from signal source). this mode, T1XC receive signal levels down squelching level 227mV±20%. Assuming worst-case squelching level 272mV, there 12.9dB margin between minimum expected signal level minimum receivable signal level.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
bridging mode, T1XC connected monitor jack which bridges across line attenuates signal levels expected pulse amplitude line-coupling transformer's primary should range from 360mV 120mV (depending length cable from signal source). this mode, T1XC receive signal levels down squelching level 50mV±20% which means that there 6.0dB margin between minimum expected signal level minimum receivable signal level, worst case. RSLC block provides squelching circuit, which indicates alarm when input pulses below squelching level threshold. this state, data sliced, which prevents detection noise idle transmission line. status RSLC Interrupt Enable/Status register (5DH) goes high whenever RSLC block squelching input signal. RSLC configured generate interrupt whenever status changes state. off-chip attenuator network shown Figure network values below recommended specified applications: Table Mode Recommended Receive Network Values Turns Ratio Squelch Level Primary 20%)
Terminating Bridging
Tight tolerances required resistors turns ratio meet return loss specification.
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PM4341A T1XC
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Figure
External Analog Receive Interface Circuit
RAVD
±10%
RAVS
Notes:
capacitors ceramic Some transformer manufacturers produce dual part containing both 1:1.36 transformers required receive transmit interfaces, respectively.
transformer used should designed applications. Many manufacturers have standard products these applications. Typical characteristics suitable transformer given following table. Table Turns Ratio (PRI:SEC) Typical Characteristics Receive Transformer min.) 1.20 Cw/w max.) max.) 0.80 pri. max.) 0.80 sec. max.)
where open-circuit inductance, Cw/w inter-winding capacitance,
leakage inductance, resistance.
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PM4341A T1XC
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PMC-Sierra verified operation RSLC functional block with following transformers: Pulse Engineering PE64931 (1:1:1) PE64952 (1:2CT) Electronics 500-1775 (1:1:1) 500-1777 (1:2CT)
Many manufacturers produce dual transformers containing 1:1.36 transformers necessary receiver transmitter circuits. PMC-Sierra verified operation XPLS RSLC with following dual parts: Pulse Engineering PE64952 Pulse Engineering PE65774 (for extended temperature range)
Electronics 500-1777 Clock Data Recovery (CDRC) Clock Data Recovery function provided Data Clock Recovery (CDRC) block. CDRC provides clock data recovery, B8ZS decoding, line code violation detection, loss signal detection. recovers clock from incoming data pulses using digital phaselocked-loop recovers data. Loss signal indicated after consecutive periods absence pulses both positive negative line pulse inputs cleared after occurrence single line pulse. enabled, microprocessor interrupt generated when loss signal detected when signal returns. line code violation defined bipolar violation (BPV) AMI-coded signals defined that part zero substitution code B8ZS-coded signals. input jitter tolerance CDRC complies with Bell Core Document TA-TSY-000170 with AT&T specification TR62411. tolerance measured with QRSS sequence (220-1 with zero restriction). CDRC block provides algorithms clock recovery that result differing jitter tolerance characteristics. first algorithm (when ALGSEL register logic provides good frequency jitter tolerance, high frequency tolerance close TR62411 limit. second algorithm (when ALGSEL logic provides much better high frequency jitter tolerance (approaching 0.5UIpp) expense frequency tolerance; frequency tolerance second algorithm approximately that first algorithm.
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PM4341A T1XC
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Figure
CDRC Jitter Tolerance
SPEC. REGION
SINEWAVE JITTER AMPLITUDE (UI) SCALE
CDRC MAX. TOLERANCE
(ALGSEL=0)
CDRC MAX. TOLERANCE
(ALGSEL=1)
AT&T SPEC. BELLCORE SPEC.
0.31
0.70
SINEWAVE JITTER FREQUENCY, SCALE
Framer (FRMR) framing function provided FRMR block. This block searches framing position incoming recovered stream. works conjunction with FRAM block DATA RECOVERY (DREC) block search framing pattern ESF, T1DM, SLC®96 framing formats. When searching frame, FRMR examines each (SF, T1DM, SLC®96), each 4*193 (ESF) framing candidates. FRAM block addressed controlled FRMR while frame synchronization acquired. time required find frame alignment error-free stream containing randomly distributed channel data (i.e. each channel data probability being dependent upon framing format.
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PM4341A T1XC
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standard superframe format (SF; also known format), FRMR block will determine frame alignment within 4.4ms times 100. SLC®96 format, FRMR will determine frame alignment within 9.9ms times 100. extended superframe format (ESF), FRMR will determine frame alignment within 15ms times 100. T1DM format, FRMR will determine frame alignment within 1.125ms times 100. Once FRMR found frame, internal INFRAME indication high incoming data continuously monitored framing errors, error events framing error SLC®96, framing error sync error T1DM, CRC-6 error ESF), severe errored framing events. FRMR also detects loss frame, based selectable ratio framing errors. FRMR extracts yellow alarm signal bits from incoming data stream SLC®96 framing formats, extracts Y-bit from T1DM sync word T1DM framing format. FRMR also extracts SLC®96 data link SLC®96 framing format, extracts facility data link bits framing format, extracts R-bit from T1DM sync word T1DM framing format. FRMR also disabled allow reception unframed data. While FRMR disabled, control FRAM block relinquished elastic store. Framer/Slip Buffer (FRAM) Framer/Slip Buffer function provided FRAMER (FRAM) block. FRAM used store frames data while FRMR finding frame frames data during normal operation (i.e. when accessed Elastic Store). FRAM shared between Elastic Store (ELST) FRMR: when frame synchronization lost, FRMR takes control FRAM uses find frame; when frame synchronization determined, FRMR relinquishes control FRAM ELST which buffers incoming data. Inband Loopback Code Detector (IBCD) Inband Loopback Code Detection function provided IBCD block. This block detects presence either programmable INBAND LOOPBACK ACTIVATE DEACTIVATE code sequences either framed unframed data streams. inband code sequences expected overwritten framing framed data streams. Each INBAND LOOPBACK code sequence defined repetition programmed code
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PM4341A T1XC
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stream least seconds. code sequence detection timing compatible with specifications defined T1.403-1989, TA-TSY000312, TR-TSY-000303. LOOPBACK ACTIVATE DEACTIVATE code indication provided through internal register bits. interrupt generated indicate when either code status changed. Pulse Density Violation Detector (PDVD) Pulse Density Violation Detection function provided PDVD block. detects pulse density violations requirement that there ones each every time window 8(N+1) data bits (where equal through 23). PDVD also detects periods consecutive zeros incoming data. Pulse density violation detection provided through internal register bit. interrupt generated signal consecutive zero event, and/or change state pulse density violation indication. Performance Monitor Counters (PMON) Performance Monitor Counters function provided PMON block. accumulates error events, Frame Synchronization error events, Line Code Violation events, Loss Frame events, optionally, Change Frame Alignment (COFA) events with saturating counters over consecutive intervals defined period supplied transfer clock signal (typically second). When transfer clock signal applied, PMON transfers counter values into holding registers resets counters begin accumulating events interval. counters reset such manner that error events occurring during reset missed. holding registers read between successive transfer clocks, OVERRUN register asserted. Generation transfer clock within T1XC chip performed writing counter register location. holding register addresses contiguous facilitate polling operations. Oriented Code Detector (RBOC) Oriented Code detection function provided RBOC block. This block detects presence possible oriented codes transmitted Facility Data Link channel framing format, defined ANSI T1.403-1989 TR-TSY-000194. 64th code (111111) similar FLAG sequence used RBOC indicate valid code received.
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PM4341A T1XC
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oriented codes received Facility Data Link channel 16-bit sequence consisting ones, zero, code bits, trailing zero (111111110xxxxxx0) which repeated least times. RBOC enabled declare received code valid been observed times times, specified control register. Valid indicated through internal status register. bits ones (111111) valid code been detected. interrupt generated signal when detected code been validated, optionally, when valid code goes away (i.e. bits ones). 8.10 HDLC Receiver (RFDL) HDLC Receiver function provided RFDL block. RFDL microprocessor peripheral used receive LAPD/HDLC frames facility data link (FDL). RFDL detects change from flag characters first byte data, removes stuffed zeros incoming data stream, receives frame data, calculates CRC-CCITT frame check sequence (FCS). Received data placed into 4-level FIFO buffer. Status Register contains bits which indicate overrun, message, flag detected, buffered data available. message, Status Register also indicates status number valid bits final data byte. Interrupts generated when one, three bytes (programmable RFDL configuration register) stored FIFO buffer. Interrupts also generated when terminating flag sequence, abort sequence, FIFO buffer overrun detected. When internal HDLC receiver disabled, serial data extracted FRMR block output RDLSIG updated falling clock edge output RDLCLK pin. Optionally, when internal HDLC receiver used, D-channel Primary Rate interface output RDLSIG updated falling clock edge RDLCLK. 8.11 Alarm Integrator (ALMI) Alarm Integration function provided ALMI block. This block detects presence YELLOW, RED, Carrier Fail Alarms (CFA) T1DM, SLC®96, formats. alarm detection integration compatible with specifications defined Bell 43801, TA-TSY-000278, TR-TSY-000008,
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PM4341A T1XC
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ANSI T1.403-1989, TR-TSY-000191. Alarm detection validation SLC®96 handled same framing format. ALMI block declares presence YELLOW alarm when YELLOW pattern been received ms); YELLOW alarm removed when YELLOW pattern been absent ms). presence alarm declared when out-of-frame condition been present 2.55 ms); alarm removed when out-of-frame condition been absent 16.6 ms). T1DM framing format alarm declaration criteria selected either 2.55 (±40 ms); removal alarm T1DM selected either (±50 16.6 ms). presence alarm declared when out-of-frame condition all-ones data stream have been present (±100 ms); alarm removed when condition been absent 16.8 (±500 ms). alarm detection algorithms operate presence random 10-3 error rate. ALMI also indicates presence absence YELLOW, RED, alarm signal conditions over 40ms, intervals, respectively, allowing external microprocessor integrate alarm conditions software with user-specific algorithms. Alarm indication provided through internal register bits. 8.12 Elastic Store (ELST) Elastic Store function provided ELST block. ELST synchronizes incoming frames local backplane clock, BRCLK. frame data buffered frame circular data buffer. Input data written buffer using write pointer output data read from buffer using read pointer. When backplane timing derived from receive line data (i.e. RCLKO output used), elastic store bypassed eliminate frame delay. this configuration elastic store used measure frequency differences between recovered line clock another 1.544 clock applied BRCLK input. typical example might measure difference frequency between received streams (i.e. East-West frequency difference) monitoring number SLIP occurrences direction with respect other.
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PM4341A T1XC
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When elastic store being used, average frequency incoming data greater than average frequency backplane clock, write pointer will catch read pointer buffer will filled. Under this condition controlled slip will occur when read pointer crosses next frame boundary. following frame data will deleted. average frequency incoming data less than average frequency backplane clock, read pointer will catch write pointer buffer will empty. Under this condition controlled slip will occur when read pointer crosses next frame boundary. last frame which read will repeated. slip operation always performed frame boundary. allow extraction signalling information data channels, superframe identification also passed through ELST. payload conditioning, ELST inserts programmable idle code into channels when FRMR frame synchronization. This code when ELST reset. 8.13 Signalling Extractor (SIGX) Signalling Extraction function provided SIGX block. This block provides signalling extraction from stream ESF, SLC®96 framing formats, serializes bits into 1.544 Mbit/s serial stream channelaligned outgoing data stream. signalling data stream contains A,B,C,D bits lower channel locations (bits 5,6,7,8) framing format; SLC®96 formats bits repeated locations (i.e. signalling stream contains bits ABAB each channel). This signalling data stream compatible with Basic Transmitter XBAS block. SIGX also provides user control over signalling freezing provides control over channel data inversion, signalling fixing signalling debounce per-channel basis. block contains three superframes worth signal buffering ensure that there greater than probability that signalling bits frozen correct state ones density out-of-frame condition, specified TR-TSY-000170 BELL 43801. With signalling debounce enabled, per-channel signalling state must same state superframes before appearing serial output stream. SIGX provides superframe signal freezing occurrence slips. When slip event occurs, SIGX freezes output signalling entire superframe which slip occurred; signaling unfrozen when next slip-free superframe occurs.
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PM4341A T1XC
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8.14 Receive Per-channel Serial Controller (RPSC) Receive Per-channel Serial Controller (RPSC) function provided second PCSC block. RPSC allows data signalling trunk conditioning applied receive DS-1 stream per-channel basis. also allows per-channel control data inversion, idle code substitution, digital milliwatt code substitution. definition serial streams RPSC analogous those TPSC. 8.15 Signalling Aligner (SIGA) Signalling Aligner positioned either after signalling extractor before basic transmitter provide superframe alignment between backplane either received DS-1 stream transmit DS-1 stream. purpose signalling alignment block maintain signalling integrity across superframe boundaries. 8.16 Backplane Receive Interface (BRIF) Backplane Receive Interface allows data presented backplane either 1.544Mbit/s 2.048Mbit/s serial stream, allows transparency outputting dual-rail data 1.544Mbit/s, allows access recovered stream (either B8ZS decoded stream, undecoded stream) 1.544Mbit/s. When configured provide 1.544Mbit/s data rate, block generates output data stream BRPCM containing channel bytes data followed single containing framing bit. BRSIG output contains bytes signalling nibble data located least significant nibble each byte followed single position representing "place holder" framing bit. framing alignment indication BRFPO indicates first 193-bit frame (or, optionally, first first frame superframe, every second superframe). When configured provide 2.048Mbit/s data rate, block internally gaps 2.048MHz rate backplane clock provide serial data BRPCM containing three channel bytes data followed byte "filler" (can logic logic "1"). data stream BRSIG similar, containing three bytes valid signalling nibbles (i.e. three channels' signalling contained least significant nibble each three byte locations) followed byte "filler". frame alignment indication provided BRFPO pin, going logic BRCLK cycle during first "filler" byte,
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PM4341A T1XC
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indicating next data byte first channel frame, first channel first frame superframe. 8.17 Basic Transmitter (XBAS) Basic Transmitter function provided XBAS. BASIC TRANSMITTER (XBAS) block generates 1.544 Mbit/s data stream according ESF, T1DM, SLC®96 formats. serial control stream provides channel control idle code substitution, data inversion (either bits, sign only, magnitude only), digital milliwatt substitution, zero code suppression. Three types zero code suppression (GTE, Bell DDS) supported selected channel basis provide minimum ones density control. serial signalling control stream provides channel control robbed signalling selection signalling source. channels forced into trunk conditioning state (idle code substitution signalling conditioning) Master Trunk Conditioning Configuration Register. data link provided ESF, T1DM SLC®96 modes. Serial data input clock output allow variety data link sources including oriented codes LAPD messages. Support provided transmission framed unframed Inband Code sequences transmission Yellow alarm signals formats. output signals selected conform B8ZS line coding. transmitter disabled framing disable Transmit Functions Enable register. When transmitting formatted data, framing bit, datalink bit, CRC-6 from input stream by-passed output stream. Finally, transmitter by-passed completely provide transparency. 8.18 Transmit Per-Channel Serial Controller (TPSC) Transmit Per-channel Serial Controller allows data signalling trunk conditioning idle code applied transmit DS-1 stream perchannel basis. also allows per-channel control zero code suppression, data inversion, application digital milliwatt. Transmit Per-channel Serial Controller function provided PERCHANNEL SERIAL CONTROLLER (PCSC) block. PCSC general
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PM4341A T1XC
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purpose triple serializer. Data sourced from banks 8-bit registers, each bank supporting single serial output. TPSC interfaces directly XBAS provides serial streams signalling control, idle code data data control. registers accessible from interface indirect address mode. BUSY indication signal polled from internal status register check completion current operation. 8.19 Inband Loopback Code Generator (XIBC) Inband Loopback Code Generator function provided XIBC block. This block generates stream inband loopback codes (IBC) inserted into data stream. stream consists continuous repetitions specific code either framed unframed. When XIBC enabled generate framed IBC, framing overwrites inband code pattern. contents code length programmable from bits. XIBC interfaces directly XBAS Basic Transmitter block. 8.20 Oriented Code Generator (XBOC) Oriented Code Generator function provided XBOC block. This block transmits possible oriented codes Facility Data Link channel framing format, defined ANSI T1.403-1989. 64th code (111111) similar HDLC Flag sequence used XBOC disable transmission oriented codes. oriented codes transmitted Facility Data Link channel 16-bit sequence consisting ones, zero, code bits, trailing zero (111111110xxxxxx0) which repeated long code 111111. transmitted oriented codes have priority over data transmitted except YELLOW Alarm. code transmitted programmed writing code register. 8.21 HDLC Transmitter (XFDL) HDLC Transmitter function provided XFDL block. This block designed provide serial data link XBAS Basic Transmitter block. XFDL used under microprocessor control transmit HDLC data frames Facility Data Link when T1XC enabled internal HDLC transmitter. XFDL performs data serialization, generation, zero-bit stuffing, well flag, idle, abort sequence insertion.
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Data transmitted provided interrupt-driven basis writing double-buffered transmit data register. Upon completion frames, CRCCCITT frame check sequence transmitted, followed idle flag sequences. transmit data register underflows, abort sequence automatically transmitted. When enabled (via XFDL Configuration register), XFDL continuously transmits flag character (01111110). Data bytes transmitted written into Transmit Data Register. After parallel-to-serial conversion each data byte, interrupt generated signal controller write next byte into Transmit Data Register. After last data frame byte transmitted, word insertion been enabled), flag insertion been enabled) transmitted. XFDL then returns transmission flag characters. there more than five consecutive ones transmit data data, zero stuffed into serial data output. This prevents unintentional transmission flag abort characters. Abort characters continuously transmitted time setting control bit. During transmission, underrun situation occur data written Transmit Data Register before previous byte been depleted. this case, abort sequence transmitted, controlling processor notified TDLUDR signal. Optionally, interrupt underrun signals independently enabled also generate interrupt INTB output, providing means notify controlling processor changes XFDL operating status. When internal HDLC transmitter disabled, serial data transmitted Facility Data Link input TDLSIG timed clock rate output TDLCLK pin. 8.22 Pulse Density Enforcer (XPDE) Pulse Density Enforcer function provided XPDE block. Pulse density enforcement enabled register within XPDE. This block monitors digital output transmitter, detecting when stream about violate ANSI T1.403 12.5% pulse density rule over moving 192-bit window. density violation detected, enabled insert logic into digital stream ensure resultant output longer violates pulse density requirement. When XPDE disabled from inserting logic digital stream from transmitter passed through unaltered.
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PM4341A T1XC
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8.23 Digital Jitter Attenuator (DJAT) Digital Jitter Attenuation function provided DJAT block. This block receives jittery, dual-rail data format from XBAS separate inputs, which allows bipolar violations pass through block uncorrected. incoming data streams stored FIFO timed transmit clock (either BTCLK RCLKO). respective input data emerges from FIFO timed jitter attenuated clock (TCLKO) referenced either TCLKI, BTCLK, RCLKO. jitter attenuator generates jitter-free 1.544 TCLKO output transmit clock adaptively dividing 37.056 XCLK signal according phase difference between generated TCLKO input data clock DJAT (either BTCLK RCLKO). Jitter fluctuations phase input data clock attenuated phase-locked loop within DJAT that frequency TCLKO equal average frequency input data clock. best jitter attenuation transfer function recommended 62411, phase fluctuations with jitter frequency above attenuated octave jitter frequency. Wandering phase fluctuations with frequencies below tracked generated TCLKO. provide smooth flow data DJAT, TCLKO used read data FIFO. FIFO read pointer (timed TCLKO) comes within write pointer (timed input data clock, BTCLK RCLKO), DJAT will track jitter input clock. This permits phase jitter pass through unattenuated, inhibiting loss data. 8.23.1 Jitter Characteristics DJAT Block provides excellent jitter tolerance jitter attenuation while generating minimal residual jitter. accommodate UIpp input jitter jitter frequencies above jitter frequencies below more correctly called wander, tolerance increases decade. most applications DJAT Block will limit jitter tolerance lower jitter frequencies only. high frequency jitter, above example, other factors such clock data recovery circuitry limit jitter tolerance must considered. frequency wander, below example, other factors such slip buffer hysteresis limit wander tolerance must considered. DJAT block meets stringent frequency jitter tolerance requirements AT&T 62411 thus allows compliance with this standard other less stringent jitter tolerance standards cited references.
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PM4341A T1XC
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DJAT exhibits negligible jitter gain jitter frequencies below attenuates jitter frequencies above decade. most applications DJAT Block will determine jitter attenuation higher jitter frequencies only. Wander, below example, will essentially passed unattenuated through DJAT. Jitter, above example, will attenuated specified, however, outgoing jitter dominated generated residual jitter cases where incoming jitter insignificant. This generated residual jitter directly related (37.056 MHz) digital phase locked loop transmit clock generation. block allows implied jitter attenuation requirements given ANSI Standard T1.408, implied jitter attenuation requirements type customer interface given ANSI T1.403 met. 8.23.2 Jitter Tolerance Jitter tolerance maximum input phase jitter given jitter frequency that device accept without exceeding linear operating range, corrupting data. DJAT, input jitter tolerance Unit Intervals peak-to-peak (UIpp) with worst case frequency offset UIpp with frequency offset. frequency offset difference between frequency XCLK divided that input data clock.
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PM4341A T1XC
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Figure Jitter Amplitude, UIpp
DJAT Jitter Tolerance
DJAT minimum tolerance
acceptable
unacceptable
0.01
0.3k
100k
Jitter Frequency,
accuracy XCLK frequency that DJAT reference input clock used generate jitter-free TCLKO have effect minimum jitter tolerance. Given that DJAT reference clock accuracy ±200 from 1.544 MHz, that XCLK input accuracy ±100 from 37.056 MHz, minimum jitter tolerance various differences between frequency reference clock XCLK/24 shown Figure
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PM4341A T1XC
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Figure
DJAT Minimum Jitter Tolerance XCLK Accuracy
DJAT Minimum Jitter Tolerance
frequency offset (PLL XCLK)
XCLK Accuracy
8.23.3 Jitter Transfer output jitter jitter frequencies from more than greater than input jitter, excluding residual jitter. Jitter frequencies above attenuated level octave, shown Figure below: Figure Jitter Gain (dB)
62411 DJAT response 62411 43802
DJAT Jitter Transfer
Jitter Frequency,
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PM4341A T1XC
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8.23.4 Frequency Range non-attenuating mode, that when FIFO within overrunning under running, tracking range 1.48 1.608 MHz. guaranteed linear operating range jittered input clock 1.544 with worst case jitter UIpp) maximum XCLK frequency offset ppm). nominal range 1.544 with jitter XCLK frequency offset. 8.24 Timing Options (TOPS) Timing Options block provides means selecting source internal input clock DJAT TSB, reference signal digital PLL, clock source used derive output TCLKO signal. 8.25 Digital DS-1 Transmit Interface (DTIF) Digital DS-1 Transmit Interface provides control over various output options available multifunctional digital transmit pins TDP/TDD TDN/TFLG. When configured dual-rail output, multifunctional pins become outputs. These outputs formatted either return-to-zero (RZ) non-return-to-zero (NRZ) signals updated either rising falling edge TCLKO. When interface configured single-rail output, multifunctional pins become TFLG outputs, which enabled updated either rising falling TCLKO edge. Further, TFLG output enabled indicate FIFO empty FIFO full status. DTIF block also provides Alarm Indication Signalling (AIS) generation capability generating alternating mark signals TDP/TDN outputs, allones output, when TAISEN Transmit Interface Configuration register. This useful when internal loopback modes used. 8.26 Analog DSX-1 Pulse Generator (XPLS) Analog DSX-1 Pulse Generator function provided XPLS block. This block converts Return Zero (NRZ) pulses into Alternate Mark Inversion (AMI) line signals suitable DSX-1 intra-office environment. dual-rail pulses supplied DJAT block. logical output from DJAT causes positive pulse transmitted; similar signal output from DJAT causes negative pulse transmitted. both logical "1," output pulse transmitted.
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PM4341A T1XC
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output pulse shape synthesized digitally with internal Digital Analog (D/A) converter. converter updated eight times rate with words stored ROM. These words define output pulse shape. signalling created exciting either internal RING DRIVERS that drive line-coupling transformer differentially outputs. This differential driving scheme insures small positive negative pulse imbalance. drivers, with step-up transformer, amplify output pulses their final levels. RING drivers also supply high current capability required drive impedance output load. cable length used link between XPLS DSX-1 crossconnect greatly affects resulting pulse shapes. This compensated selecting from eight different pulse output shapes built into XPLS. short line length settings, small, negative-going spike observed falling edge DSX-1 pulse. This spike filtered using optional "snubbing" network shown Figure This snubber network should required when driving longer lines. XPLS includes driver performance monitor detect nonfunctional links. monitor inputs, PM_TIP PM_RING, internally bonded XPLS's outputs. pulses detected alternately across PM_TIP PM_RING monitor points consecutive TCLKO periods, monitored link declared failed. exact threshold pulses) depends line build-out pattern bipolar violations. XPLS programmed produce interrupt whenever link monitor state changes. XPLS block provides Alarm Indication Signalling (AIS) generation capability generating alternating mark signals link when TAIS programmed high. This useful when internal loopback modes used.
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Figure
External Analog Transmit Interface Circuit
470nF TAVD
±10% ±10%
0.68µF 10%,
foot cable
1:1.36
DSX-1 Interface
TAVS
optional "snubbing network
transformer used should designed T1/CEPT/ISDN-PRI applications. Many manufacturers have standard products these applications. Typical characteristics suitable transformer given following table. Table Turns Ratio (PRI:SEC) 1:1.36 1.20 0.80 0.80 Typical Characteristics Transmit Transformer min.) Cw/w max.) max.) pri. max.) sec. max.)
Where open-circuit inductance, Cw/w inter-winding capacitance, leakage inductance, resistance.
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PMC-Sierra verified operation XPLS functional block with following 1:1.36 transformers: Pulse Engineering PE64937 (1:1.36) Pulse Engineering PE65340 (1:1.36) (for extended temperature range) Electronics 500-1776 (1:1.36)
Many manufacturers produce dual transformers containing the1:2 1:1.36 transformers necessary receiver transmitter circuits. PMC-Sierra verified operation XPLS RSLC with following dual parts: Pulse Engineering PE64952 Pulse Engineering PE65774 (for extended temperature range) Electronics 500-1777
8.27 Backplane Transmit Interface (BTIF) Backplane Transmit Interface allows data taken from backplane either 1.544Mbit/s 2.048Mbit/s serial stream allows transparency accepting dual-rail data input 1.544Mbit/s. When configured receive 1.544Mbit/s data rate stream, block expects input data stream BTPCM contain channel bytes data followed single location framing bit. BTSIG input must contain bytes signalling nibble data located least significant nibble each byte followed single position framing bit. framing alignment indication BTFP indicates framing position 193-bit frame (or, optionally, framing position first frame superframe, every second superframe). When configured receive 2.048Mbit/s data rate stream, block internally gaps 2.048MHz rate backplane clock convert serial data BTPCM containing three channel bytes data followed byte "filler" (which logic logic "1") into internal 1.544Mbit/s serial stream transmission. data stream BTSIG pin, containing three bytes valid signalling nibbles (i.e. three channels' signalling contained least significant nibble each three byte locations) followed byte "filler", similarly converted internal 1.544Mbit/s rate. frame alignment indication provided BTFP must logic BTCLK cycle during first "filler" byte, indicating next data byte first channel frame, first channel first frame superframe.
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8.28 Microprocessor Interface (MPIF) Microprocessor Interface allows T1XC configured, controlled monitored internal registers.
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PM4341A T1XC
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REGISTER DESCRIPTION Normal Mode Register Memory Address Register T1XC Receive Options T1XC Receive Backplane Options T1XC Datalink Options T1XC Receive Interface Configuration T1XC Transmit Interface Configuration T1XC Transmit Backplane Options T1XC Transmit Framing Bypass Options T1XC Transmit Timing Options T1XC Master Interrupt Source T1XC Master Interrupt Source T1XC Master Diagnostics T1XC Master Test T1XC Revision/Chip T1XC Master Reset T1XC Phase Status Word (LSB) T1XC Phase Status Word (MSB) CDRC Configuration CDRC Interrupt Enable CDRC Interrupt Status CDRC Reserved XPLS Line Length Configuration XPLS Control/Status XPLS CODE Indirect Address XPLS CODE Indirect Data DJAT Interrupt Status
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DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Address
Register DJAT Reference Clock Divisor (N1) Control DJAT Output Clock Divisor (N2) Control DJAT Configuration ELST Configuration ELST Interrupt Enable/Status ELST Trouble Code ELST Reserved FRMR Configuration FRMR Interrupt Enable FRMR Interrupt Status FRMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved RBOC Enable RBOC Code Status ALMI Configuration ALMI Interrupt Enable ALMI Interrupt Status ALMI Alarm Detection Status TPSC Configuration TPSC Access Status TPSC Channel Indirect Address/Control TPSC Channel Indirect Data Buffer XFDL Configuration
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Address
Register XFDL Interrupt Status XFDL Transmit Data XFDL Reserved RFDL Configuration RFDL Interrupt Control/Status RFDL Status RFDL Receive Data IBCD Configuration IBCD Interrupt Enable/Status IBCD Activate Code IBCD Deactivate Code SIGX Configuration SIGX Access Status SIGX Channel Indirect Address/Control SIGX Channel Indirect Data Buffer XBAS Configuration XBAS Alarm Transmit XIBC Control XIBC Loopback Code PMON Reserved PMON Status PMON Count (LSB) PMON Count (MSB) PMON Count (LSB) PMON Count (MSB) PMON Count PMON OOF/COFA Count RPSC Configuration
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Address 5AH-5BH 5EH-7FH 80H-FFH
Register RPSC Access Status RPSC Channel Indirect Address/Control RPSC Channel Indirect Data Buffer PDVD Reserved PDVD Interrupt Enable/Status XBOC Reserved XBOC Code XPDE Reserved XPDE Interrupt Enable/Status Reserved RSLC Reserved RSLC Interrupt Enable/Status Reserved Reserved Test
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
NORMAL MODE REGISTER DESCRIPTION Normal mode registers used configure monitor operation T1XC. Normal mode registers opposed test mode registers) selected when A[7] low. Notes Normal Mode Register Bits: Writing values into unused register bits effect. Reading back unused bits produce either logic logic hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling T1XC determine programming state chip. Writeable normal mode register bits cleared zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect T1XC operation unless otherwise noted.
10.1 Internal Registers
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Register 00H: T1XC Receive Options Type Function Unused ELSTBYP TRSLIP SRPCM SRSFP ALTRFP CCOFA Default
This register allows software configure receive functions T1XC. UNF: allows T1XC operate with unframed DS-1 data. When logic FRMR disabled recovered data passes through receiver section T1XC without frame channel alignment. While held logic Alarm Integrator continues operate detects integrates alarm. When logic T1XC operates normally, searching frame alignment incoming data. ELSTBYP: ELSTBYP allows Elastic Store (ELST) bypassed, eliminating frame delay incurred through ELST. When logic received data clock inputs ELST internally routed directly ELST outputs. TRSLIP: TRSLIP allows ELST used measure, through SLIP indications, frequency difference between recovered receive line clock transmit clock driving XBAS when ELST bypassed. When TRSLIP logic transmit clock input XBAS internally substituted BRCLK input system side ELST. When TRSLIP logic BRCLK input routed system side ELST. TRSLIP valid only when ELSTBYP logic
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
SRPCM: SRPCM selects output signal seen multifunction output RPCM/ RDPCM. When logic multifunction output becomes RPCM, undecoded output from Clock Data Recovery (CDRC) When SRPCM logic multifunction output becomes RDPCM, B8ZS-decoded output from CDRC SRSFP: SRSFP selects output signal seen multifunction output When logic multifunction output becomes RSFP receive superframe pulse indication, which pulses high during first framing frame frame (depending framing format selected FRMR When SRSFP logic multifunction output becomes which pulses high during each framing (i.e. every bits). ALTRFP: ALTRFP suppresses every second output pulse multifunction output When ALTRFP logic output signal pulses every bits, indicating every second framing SRSFP logic output signal pulses every frames SRSFP logic When ALTRFP logic output signal pulses accordance SRSFP setting. CCOFA: CCOFA determines whether PMON counts Change-Of-Frame Alignment (COFA) events out-of-frame (OOF events. When CCOFA logic COFA events counted PMON. When CCOFA logic events counted PMON. Upon reset T1XC, these bits cleared zero.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Register 01H: T1XC Receive Backplane Options Type Function Unused ALTFDL RXDMAGAT BRX2M BRX2RAIL BRXSFP ALTBRFP RXMTKC Default
This register allows software configure Receive backplane interface format T1XC. ALTFDL: ALTFDL enables framing position backplane output contain copy bit. When ALTFDL logic each M-bit value ESF-formatted stream duplicated replaces subsequent F-bit output signal stream BRPCM. When ALTFDL logic output BRPCM stream contains received CRC, bits framing position. Note that this function only valid ESF-formatted streams, ALTFDL should logic when other framing formats being received. RXDMAGAT: RXDMAGAT selects gating RDLINT output with RDLEOM output when internal HDLC receiver used with DMA. When RXDMAGAT logic RDLINT output gated with RDLEOM output that RDLINT forced logic when RDLEOM logic When RXDMAGAT logic RDLINT RDLEOM outputs operate independently. BRX2M: BRX2M selects 2.048 data rate format backplane data frame alignment signals. When BRX2M logic clock rate BRCLK input expected 2.048MHz, data stream BRPCM output byte "filler" followed bytes channel data, repeated times. When BRX2M logic backplane data rate
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
format identical (i.e. 1.544MHz rate with contiguous channel bytes followed framing bit). BRX2RAIL: BRX2RAIL selects whether backplane receive data signal multifunction outputs BRPCM/BRDP BRSIG/BRDN either dual rail single rail format. When BRX2RAIL logic multifunction pins become BRDP BRDN dual rail outputs, which contain received positive negative line pulses timed 1.544MHz receive line rate, RCLKO. When BRX2RAIL logic multifunction pins become BRPCM BRSIG digital outputs. BRXSFP: BRXSFP selects output signal seen backplane output BRFPO. When logic BRFPO output pulses high during first framing frame frame (depending framing format selected FRMR When BRXSFP logic BRFPO output pulses high during each framing (i.e. every bits). ALTBRFP: ALTBRFP suppresses every second output pulse backplane output BRFPO. When ALTBRFP logic output signal BRFPO pulses every bits, indicating every second framing BRXSFP logic output signal BRFPO pulses every frames BRXSFP logic This latter setting (i.e. both ALTBRFP BRXSFP logic useful converting formatted data formatted data between T1XC devices. When ALTBRFP logic output signal BRFPO pulses accordance BRXSFP setting. RXMTKC: RXMTKC allows global trunk conditioning applied received data signalling streams, BRPCM BRSIG. When RXMKTC logic data BRPCM each channel replaced with data contained data trunk conditioning registers within RPSC; similarly, signalling data BRSIG each channel replaced with data contained signalling trunk conditioning registers. When RXMKTC logic data signalling signals modified per-channel basis accordance with control bits contained per-channel control registers within RPSC. Upon reset T1XC, these bits cleared zero.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Register 02H: T1XC Datalink Options Type Function RXDMASIG RXDCHAN TXDMASIG TXDCHAN RDLINTE RDLEOME TDLINTE TDLUDRE Default
This register allows software configure datalink options T1XC. RXDMASIG: RXDMASIG selects internal HDLC receiver (RFDL) data-received interrupt (INT) end-of-message (EOM) signals output RDLINT RDLEOM pins when RXDCHAN logic When RXDMASIG logic RDLINT RDLEOM output pins used controller process datalink. When RXDMASIG logic RFDL signals longer available controller; signals RDLINT RDLEOM become extracted datalink data clock, RDLSIG RDLCLK. this mode, data stream available RDLSIG output corresponds extracted facility datalink ESF, extracted R-bit value sync word T1DM, extracted framing bits SLC®96. When RXDCHAN logic RXDMASIG effect. RXDCHAN: RXDCHAN selects whether Primary Rate D-Channel extracted made available RDLSIG output, whether RDLINT/RDLSIG RDLEOM/RDLCLK pins operate defined RXDMASIG bit. When RXDCHAN logic D-Channel data (channel every frame) output RDLSIG burst clock output RDLCLK. When RXDCHAN logic RDLINT/RDLSIG RDLEOM/RDLCLK pins contain signals selected RXDMASIG bit.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
TXDMASIG: TXDMASIG selects internal HDLC transmitter (XFDL) request service interrupt (INT) data underrun (UDR) signals output TDLINT TDLUDR pins when TXDCHAN logic When TXDMASIG logic TDLINT TDLUDR output pins used controller service datalink. When TXDMASIG logic XFDL signals longer available controller; signals TDLINT TDLUDR become serial datalink data input clock, TDLSIG TDLCLK. this mode external controller responsible formatting data stream presented TDLSIG input correspond facility datalink ESF, R-bit value sync word T1DM, framing bits SLC®96. When TXDCHAN logic TXDMASIG effect. TXDCHAN: TXDCHAN selects whether Primary Rate D-Channel inserted into channel each frame TDLSIG input, whether TDLINT/TDLSIG TDLUDR/TDLCLK pins operate defined TXDMASIG bit. When TXDCHAN logic D-Channel data expected TDLSIG, sampled rising edge burst clock provided TDLCLK. When TXDCHAN logic TDLINT/TDLSIG TDLUDR/TDLCLK pins contain signals selected TXDMASIG bit. RDLINTE: RDLINTE enables RFDL received-data interrupt also generate interrupt microprocessor interrupt, INTB. This allows single microprocessor service RFDL without needing interface control signals. When RDLINTE logic event causing interrupt RFDL (which visible RDLINT output when RXDMASIG logic RXDCHAN logic also causes interrupt generated INTB output. When RDLINTE logic interrupt event RFDL does cause interrupt INTB. RDLEOME: RDLEOME enables RFDL end-of-message interrupt also generate interrupt microprocessor interrupt, INTB. This allows single microprocessor service RFDL without needing interface control signals. When RDLEOME logic end-of-message event causing interrupt RFDL (which visible RDLEOM output when RXDMASIG logic RXDCHAN logic also causes interrupt generated INTB output. When RDLEOME logic interrupt event RFDL does cause interrupt INTB. NOTE: within RFDL, end-of-message
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
event causes interrupt both RFDL interrupt outputs. Operation section further details using RFDL. TDLINTE: TDLINTE enables XFDL request service interrupt also generate interrupt microprocessor interrupt, INTB. This allows single microprocessor service XFDL without needing interface control signals. When TDLINTE logic request service interrupt event XFDL (which visible TDLINT output when TXDMASIG logic TXDCHAN logic also causes interrupt generated INTB output. When TDLINTE logic interrupt event XFDL does cause interrupt INTB. TDLUDRE: TDLUDRE enables XFDL transmit data underrun interrupt also generate interrupt microprocessor interrupt, INTB. This allows single microprocessor service XFDL without needing interface control signals. When TDLUDRE logic underrun event causing interrupt XFDL (which visible TDLUDR output when TXDMASIG logic TXDCHAN logic also causes interrupt generated INTB output. When TDLUDRE logic underrun event XFDL does cause interrupt INTB. Upon reset T1XC, these bits cleared zero.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Register 03H: T1XC Receive Interface Configuration Type Function Unused SDOEN RDIEN RDNINV RDPINV RUNI RFALL Default
This register enables Receive Interface handle various input waveform formats. SDOEN: SDOEN enables sliced positive negative pulses from analog receive slicer visible pins when Analog DSX-1 Receive Slicer active. When SDOEN logic multifunction pins SDP/RDP/RDD SDN/RDN/RLCV become sliced positive negative pulse outputs, SDN. Pulses will seen outputs RSLC powered When SDOEN logic multifunction pins SDP/RDP/RDD SDN/RDN/RLCV become digital inputs, RDP/RDD RDN/RLCV. function digital inputs determined RUNI bit. RDIEN: RDIEN enables data received digital inputs, RDP/RDD RDN/RLCV, used internally instead outputs from Analog DSX1 Receive Slicer. When RDIEN logic SDOEN logic digital data input multifunction pins RDP/RDD RDN/RLCV handled accordance with remaining setting this register resulting signals used internally drive clock data recovery block. When RDIEN logic output signals from analog RSLC used internally drive CDRC block. RDPINV,RDNINV: RDPINV RDNINV bits enable DS-1 Receive Interface logically invert signals received multifunction pins SDP/RDP/RDD
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
SDN/RDN/RLCV, respectively. When RDPINV logic interface inverts signal RDP/RDD input. When RDPINV logic interface passes RDP/RDD signal unaltered. When RDNINV logic interface inverts signal RDN/RLCV input. When RDNINV logic interface passes RDN/RLCV signal unaltered. RUNI: RUNI enables interface receive uni-polar digital data line code violation indications multifunction pins SDP/RDP/RDD SDN/RDN/RLCV. When RUNI logic SDP/RDP/RDD SDN/RDN/RLCV multifunction pins become data line code violation inputs, RLCV, sampled selected RCLKI edge. When RUNI logic SDP/RDP/RDD SDN/RDN/RLCV multifunction pins become positive negative pulse inputs, RDN, sampled selected RCLKI edge. RFALL: RFALL enables DS-1 Receive Interface sample multifunction pins falling RCLKI edge. When RFALL logic interface enabled sample either RLCV inputs, inputs, falling RCLKI edge. When RFALL logic interface enabled sample inputs rising RCLKI edge. RRZ: configures interface receive return-to-zero formatted waveforms. When logic interface configured pass signals inputs unaltered directly into CDRC RCLKI input ignored. When logic interface configured sample either input inputs RCLKI edge specified RFALL generate internal representation these inputs with duration equal half RCLKI period. internally-generated signals then passed CDRC. only valid when RUNI logic When system reset, contents register logic enabling analog Receive Slicer Interface handle incoming DSX-1 signal.
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
Register 04H: T1XC Transmit Interface Configuration Type Function FIFOBYP TAISEN TDNINV TDPINV TUNI FIFOFULL TRISE Default
This register enables Transmit Interface generate required digital output waveform format. FIFOBYP: FIFOBYP enables transmit bi-polar input signals DJAT bypassed around FIFO bi-polar outputs. When jitter attenuation being used, XPLS pulse driver being driven with "jitter-free" 12.352MHz clock TCLKI, DJAT FIFO bypassed reduce delay through transmitter section typically bits. NOTE: under this condition, BTCLK signal must synchronous TCLKI. When FIFOBYP logic bi-polar inputs DJAT routed around FIFO directly into XPLS. When FIFOBYP logic bi-polar transmit data passes through DJAT FIFO. TAISEN: TAISEN enables interface generate unframed all-ones alarm TDP/TDD TDN/TFLG multifunction pins. When TAISEN logic TUNI logic bi-polar outputs forced pulse alternately, creating all-ones signal; when TAISEN TUNI both logic uni-polar output forced all-ones. When TAISEN logic TDP/TDD TDN/TFLG multifunction outputs operate normally. transition transmitting outputs done such introduce bi-polar violations. TDPINV,TDNINV: TDPINV TDNINV bits enable DS-1 Transmit Interface logically invert signals output TDP/TDD TDN/TFLG multifunction pins,
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PM4341A T1XC
DATA SHEET PMC-900602 ISSUE FRAMER/TRANSCEIVER
respectively. When TDPINV logic TDP/TDD output inverted. When TDPINV logic TDP/TDD output inverted. When TDNINV logic TDN/TFLG output inverted. When TDNINV logic TDN/TFLG output inverted. TUNI: TUNI enables transmit interface generate uni-polar digital outputs TDP/TDD TDN/TFLG multifunction pins. When TUNI logic TDP/TDD TDN/TFLG multifunction pins become unipolar outputs TFLG, updated selected TCLKO edge. When TUNI logic TDP/TDD TDN/TFLG multifunction pins become bipolar outputs TDN, also updated selected TCLKO edge. When TUNI logic (unipolar mode), analog transmit data outputs, TAN, from XPLS block cannot used. FIFOFULL: FIFOFULL determines indication given TFLG output pin. When FIFOFULL logic TFLG output indicates when Digital Jitter Attenuator's FIFO within positions becoming full. When FIFOFULL logic TFLG output indicates when Digital Jitter Attenuator's FIFO within positions becoming empty. TRISE: TRISE configures interface update multifunction outputs rising edge TCLKO. When TRISE logic interface enabled update TDP/TDD TDN/TFLG output pins rising TCLKO edge. When TRISE logic interface enabled update outputs falling TCLKO edge. TRZ: configures interface transmit bipolar return-to-zero formatted waveforms. When logic interface ena

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