Mapping Controller Controller Product Line Selection Table H

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Mapping Controller Controller Product Line Selection Table H

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HT16270
Mapping Controller
Controller Product Line Selection Table
HT162X Built-in Osc. Crystal Osc. HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
Features
Operating voltage: 2.7V~5.2V External Crystal 32768Hz oscillator Stand-by current bias, 1/16 duty, frame frequency 64Hz Max. patterns, commons, segments Built-in internal resistor type bias generator wires serial interface kinds time base /WDT selection Time base overflow output
Built-in display address auto increment Built-in buzzer driver (2K/4K) Power down command reduces power consumption Software configuration feature Data mode Command mode instructions Three data accessing modes Provide VLCD adjust operating voltage
General Description
HT16270 peripheral device specially designed type used expand display capability. max. display segment device 1024 patterns also supports serial interface, buzzer sound, watchdog timer time base timer functions. HT16270 memory mapping multifunction controller. software configuration feature HT16270 make suitable multiple applications including modules display subsystems. Only lines required interface between host controller HT16270. HT162X series have many kinds products that match various applications.
HT16270
Assignment (PQFP100)
Block Diagram
HT16270
Assignment (Layout Plot)
Chip size: (mil)2 substrate should connected layout artwork.
HT16270
Coordinates
-116.57 -116.68 -116.72 -116.72 -116.72 -115.93 -116.72 -116.72 -116.72 -115.94 -115.94 -115.94 -115.90 -115.97 -115.93 -115.93 -115.93 -115.93 -115.97 -115.93 -115.93 -115.94 -115.94 -108.08 -96.03 -89.43 -77.43 -70.82 -58.83 -52.17 -40.22 -33.58 -21.58 -14.98 -2.97 3.67 15.63 22.27 34.28 40.88 52.88 59.47 71.47 78.13 90.07 96.72 108.72 116.19 99.90 90.80 84.15 77.50 70.90 64.25 54.75 41.45 21.85 11.39 -0.60 -7.18 -19.21 -25.85 -37.85 -44.45 -56.45 -63.05 -75.05 -81.70 -93.65 -100.30 -112.37 -112.07 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.00 -112.05 -112.00 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.00 -112.00 -112.05 -112.05 -112.00 -111.82 116.15 116.15 116.19 116.19 116.15 116.19 116.19 116.19 116.19 116.19 116.19 116.24 116.24 116.19 116.24 116.19 116.19 116.15 116.15 116.19 116.15 116.19 116.11 112.20 100.04 93.42 81.43 74.80 62.77 56.23 44.20 37.57 25.63 18.95 6.97 0.38 -11.65 -18.23 -30.22 -36.89 -48.92 -55.51 -67.45 -74.12 -86.15 -92.72 -104.72 -114.22
Unit:
-99.79 -93.16 -81.18 -74.54 -62.58 -55.93 -43.94 -37.40 -25.37 -18.70 -6.72 -0.09 11.90 18.49 30.51 37.10 49.09 55.76 67.75 74.38 86.36 93.03 104.85 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.20 112.24 112.24 112.24 112.24 112.29 112.24 112.24 112.25 112.25 112.25
HT16270
Description
Name Description
Chip selection input with pull high resistor. When logic high, data command read from written HT16270 disabled. serial interface circuit also reset logic level input pad, data command transmission between host controller HT16270 READ clock input with pull high resistor.Data HT16270 clocked rising edge signal. clocked data will appear data line. host controller next falling edge latch clocked data. WRITE clock input with pull high resistor. Data DATA line latched into HT16270 rising edge signal.
10~13 14~29 30~93
DATA OSCI OSCO VLCD T1~T4 COM0~COM15 SEG0~SEG63
Serial data input/output with pull high resistor Negative power supply, Ground Crystal oscillator input output pins Crystal oscillator input output pins Positive power supply operating voltage input pad. Time base Watch Timer overflow flag, NMOS open drain output frequency output pair (Tristate output buffer) connected common outputs segment outputs
Absolute Maximum Ratings*
Supply Voltage .-0.3V 5.5V Input Voltage. VSS-0.3V VDD+0.3V Storage Temperature. -50°C 125°C Operating Temperature. -25°C 75°C
*Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damageto device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied exposure absolute maximum rating conditions extended periods affect device reliability.
HT16270
D.C. Characteristics
Symbol
IDD1 (Ta=25°C)
Parameter
Operating voltage Operating current Operating current Stand-by current Input voltage Input high voltage DATA DATA common sink current common source current segment sink current segment source current Pull-high resistor
Test Conditions Conditions
load/LCD Crystal load/LCD Crystal load Power down mode DATA,
Min. Typ. Max. Unit
IDD2
ISTB
DATA, VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA,
IOL1
IOH1
IOL2
IOH2
IOL3
IOH3
IOL4
IOH4
HT16270
A.C. Characteristics
Symbol
fSYS fLCD tCOM fCLK1 fCLK2 (Ta=25°C)
Parameter
System clock
Test Conditions
Conditions
Crystal oscillator
Min.
Typ.
n/fLCD
Max. Unit
frame frequency common period Serial data clock pin)
Crystal oscillator Number Duty cycle
Serial data clock pin) Serial Interface Reset Pulse Width
Duty cycle Write mode Read mode Write mode Read mode 3.34 6.67 1.67 3.34
Pulse Width Serial Data Clock (Figure Rise/Fall Time Serial Data Clock (Figure Setup Time DATA Serial Data Clock (Figure Hold Time DATA Serial Data Clock (Figure High Serial Data Clock (Figure High Serial Data Clock High (Figure Serial Interface Reset High (Figure Serial Pulse Width Serial Data Clock High (Figure
trtf trec
HT16270
Figure
Figure
Figure
Application Diagram
connection selected depending requirement host controller. Note: voltage must greater than VLCD PIN. (VDD VLCD)
HT16270
System Architecture
Display memory structure Time base watchdog timer (WDT)
static display organized into bits stores display data. contents directly mapped contents driver. Data accessed READ, WRITE READ-MODIFY-WRITE commands. following mapping from patterns.
time base generator share same divided (/256) counter. TIMER DIS/EN/CLR, DIS/EN/CLR EN/DIS independent from each other. Once timeout occurs, will stay logic level until command issued.
Time base configurations
HT16270
external clock selected source system frequency, command turns invalid power down mode fails carried until external clock source removed.
Buzzer tone output
following data mode command mode
Operation
READ WRITE READ-MODIFY-WRITE COMMAND
Mode
Data Data Data
simple tone generator implemented HT16270. tone generator output pair differential driving signals which used generate single tone.
Command format
Command
HT16270 configured software setting. There mode commands configure HT16270 resource transfer display data.
successive commands have been issued, command mode omitted. While system operating non-successive command non-successive address data mode, should previous operation mode will reset also. returns "0", operation mode should issued first.
Name
TONE TONE TONE
Command Code
0000-1000-X 010X-XXXX-X 0110-XXXX-X Turn-off tone output
Function
Turn-on tone output, tone frequency 4kHz Turn-on tone output, tone frequency 2kHz
HT16270
Timing Diagrams
HT16270
HT16270
HT16270
HT16270
Command Summary
Name
READ WRITE
Command Code
Function
Read data from Write data Read Write data Turn system oscillator Turn system oscillator Turn display Turn display Disable time base output Disable time-out flag output Enable time base output Enable time-out flag output Turn tone outputs Clear contents time base generator Clear contents stage Tone frequency output: 4kHz Tone frequency output: 2kHz Disable output Enable output Time base clock output: time-out flag after: Time base clock output: time-out flag after: Time base clock output: time-out flag after: Time base clock output: time-out flag after: 1/2s Time base clock output: 16Hz time-out flag after: 1/4s Time base clock output: 32Hz time-out flag after: 1/8s Time base clock output: 64Hz time-out flag after: 1/16s
Def.
a7a6a5a4a3a2a1a0 d0d1d2d3 a7a6a5a4a3a2a1a0 d0d1d2d3
Read-modify-write a7a6a5a4a3a2a1a0 d0d1d2d3 TIMER TIMER TONE TIMER TONE TONE 0000-0000-X 0000-0001-X 0000-0010-X 0000-0011-X 0000-0100-X 0000-0101-X 0000-0110-X 0000-0111-X 0000-1000-X 0000-1101-X 0000-1111-X 010X-XXXX-X 0110-XXXX-X 100X-0XXX-X 100X-1XXX-X 101X-0000-X 101X-0001-X 101X-0010-X 101X-0011-X 101X-0100-X 101X-0101-X
101X-0110-X
HT16270
Name
F128 TOPT NORMAL Note: Don't care a7~a0: address d3~d0: data D/C: Data/Command mode Def.: Default
Command Code
Function
Def.
101X-0111-X 1110-0000-X 1110-0011-X
Time base clock output: 128Hz time-out flag after: 1/32s Test mode Normal mode

Mapping Controller Controller Product Line Selection Table H

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