DRIVER CONTROLLER July. 1999. Ver. Tae-Kwang, Park parktk@sa

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KS0040
DRIVER CONTROLLER
July. 1999. Ver.
Tae-Kwang, Park parktk@samsung.co.kr
Contents this document subject change without notice. part this document reproduced transmitted form means, electronic mechanical, purpose, without express written permission Driver Team.
KS0040
DRIVER CONTROLLER
KS0040 Specification Revision History Version Original
Changed function interface method changed. DDRAM extended style changed from horizontal vertical. Reference voltage selected between internal VREF pin. Removed function Horizontal display shift function removed. Added function Double height character display function Center mode display function CGRAM full graphic function Line cursor function Vertical shift character first line vertical shift function 4-bit interface mode Changed name DUMMY (Not connected) (Reference voltage selection) DIRC (6800- 8080-series selection) DIRS interface length selection) RESET (H/W reset) RW_WR (Read Write selection 6800-series, Write enable 8080-series) E_RD (Read Write enable 6800-series, Read enable 8080-series) COMS1, COMI1, (Common icon) SEGS1 SEGS4 SEGI1 SEGI4 (Segment icons) Changed name VC5ON TEST3 (Connect VSS) TMPS0 TEST4 (Connect VSS) TMPS1 TEST5 (Connect VSS) Spec changed (3V): 150µA Max. 180µA Max. (5V): 250µA Max. 280µA Max. Power sequence added. Page CGROM character size changed from 8,192 8,160. Page VREF Item, Page X-coordinates changed (Pad No.206 246)
Content
Date Mar.1998
Jun.1998
Apr.1999
Jun.1999 Jul.1999
DRIVER CONTROLLER
KS0040
CONTENTS
INTRODUCTION FEATURES BLOCK DIAGRAM CONFIGURATION CENTER COORDINATES. DESCRIPTION POWER SUPPLY. DRIVER SUPPLY. SYSTEM CONTROL INTERFACE DRIVER OUTPUT TEST FUNCTION DESCRIPTION SYSTEM INTERFACE.11 CHARACTER GENERATOR FULL-SIZE FONT (FCGROM).23 CHARACTER GENERATOR HALF-SIZE FONT (HCGROM) POWER CONSUMPTION MODE DRIVING CIRCUIT DISPLAY SHIFT CONTROL INSTRUCTION DESCRIPTION.28 INITIALIZING POWER SAVE MODE SETUP.40 HARDWARE RESET.40 INITIALIZING INSTRUCTION SLEEP MODE RELEASE INSTRUCTION.43 RECOMMENDATION POWER SEQUENCE DRIVING POWER SUPPLY CIRCUIT VOLTAGE CONVERTER VOLTAGE REGULATOR.48 BIAS RESISTOR FOLLOWER EXTERNAL POWER SUPPLY APPLICATION INFORMATION INTERFACE METHOD PANEL CONNECTION METHOD (1/65 DUTY CONFIGURATION) FRAME FREQUENCY.60 MAXIMUM ABSOLUTE RATE.63 ELECTRICAL CHARACTERISTICS.64 CHARACTERISTICS.64 CHARACTERISTICS
DRIVER CONTROLLER
KS0040
INTRODUCTION
KS0040 driver controller liquid crystal matrix character display systems. display lines characters with dots format. suitable display Asian characters such Korean, Chinese Japanese. Also half size alphanumeric characters displayed. display dots graphic using internal CGRAM. Voltage converter times), voltage regulator voltage follower bias circuits built
FEATURES
Driver Output Circuits Common outputs: common common icon Segment outputs: segment segment icon
Applicable Duty Ratios Display size 1-line characters 2-line characters 3-line characters 4-line characters On-chip Display Data Full-size Character Generator (FCGROM): 2,088,960 bits (8,160 characters dot) Half-size Character Generator (HCGROM): 16,384 bits (128 characters dot) Character Generator (CGRAM): 8,192 bits characters dot) Display Data (DDRAM): 1,024 bits characters byte) Icon (ICONRAM): bits (128 horizontal icons vertical icons) parallel interface mode: 6800-series, 8080-series Serial interface mode: pins clock synchronous serial interface Various instruction sets: vertical dot-by-dot display shift, double height character, power control, etc. bi-directional reset Automatically adjusted oscillator circuit duty Electrical volume contrast control steps) Voltage converter times) voltage regulator (temperature coefficient -0.05%/ voltage follower bias circuit Supply voltage (VDD): 5.5V driving voltage (VLCD VSS) 13.0V Duty 1/17 1/33 1/49 1/65 Contents outputs characters vertical icons horizontal icons characters vertical icons horizontal icons characters vertical icons horizontal icons characters vertical icons horizontal icons
Microprocessor Interface
Function
On-chip Analog Circuit
Operating Voltage Range
KS0040
DRIVER CONTROLLER
Power Consumption Sleep mode operation (VDD Max.) Normal mode operation (VDD 150uA Typ.) Gold bumped chip
Package Type
DRIVER CONTROLLER
KS0040
BLOCK DIAGRAM
RESET Oscillator RW_WR E_RD (SI) (SCL) System Interface Timing Generator
Instruction Register (IR)
Instruction Decoder Display data (DDRAM) 128X8 bits 128-bits Shift Register
bit/8
Address Counter Data register (DR)
bits Shift Register (Bi-dir)
Common Driver
COM1 COM64 COMI1 COMI2
Serial Interface
Buffer
128-bits Latch Circuit (Bi-dir)
Segment Driver
SEG1 SEG128
Address Generator
Character generator full size char. font (FCGROM) 2,088,960bit
SEGI1
Icon
Cursor blink control
bits Latch Circuit
SEGI2 SEGI3 SEGI4
Character generator (ICONRAM) bytes (CGRAM) 1,024 bytes
Character generator half size char. font (HCGROM) 16,384 bits
Driver Voltage Selector
Display attribute control circuit
Parallel serial converter Scroll Control circuit
Driving Power Circuit
Voltage Converter
Voltage Regulator Voltage Follower Bias Resistor
CAP1+
CAP1-
CAP2+
CAP2-
CAP3+
CAP3-
VOUT
Figure Block Diagram
KS0040
DRIVER CONTROLLER
CONFIGURATION
Align Coordinate
30µm 30µm 30µm 30µm 30µm 30µm 30µm 30µm 30µm 30µm
(-5886.5, -1558)
(0,0)
KS0040
DUMMY
Figure Configuration Table KS0040 Dimensions Item Chip size pitch Bumped size Bumped height (Typ.) Align Coordinate
42µm 108µm 108µm 42µm
Size 12160 3860
Unit
(-5738, +1800)
(+5738, +1800)
42µm
42µm
(+5886.5, -1543)
60µm 108µm 108µm
DRIVER CONTROLLER
KS0040
CENTER COORDINATES
Table Center Coordinates
[Unit: Name DUMMY DUMMY TEST1 DUMMY RESET RW_WR E_RD DUMMY DUMMY DUMMY Coordinate -5220 -5130 -5040 -4950 -4860 -4770 -4680 -4590 -4500 -4410 -4320 -4230 -4140 -4050 -3960 -3870 -3780 -3690 -3600 -3510 -3420 -3330 -3240 -3150 -3060 -2970 -2880 -2790 -2700 -2610 -2520 -2430 -2340 -2250 -2160 -2070 -1980 -1890 -1800 -1710 -1620Y -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 Name DUMMY DUMMY VOUT VOUT VOUT VOUT DUMMY CAP3+ CAP3+ CAP3+ CAP3+ CAP3CAP3CAP3CAP3CAP1+ CAP1+ CAP1+ CAP1+ CAP1CAP1CAP1CAP1CAP2+ CAP2+ CAP2+ CAP2+ CAP2CAP2CAP2Coordinate -1530 -1440 -1350 -1260 -1170 -1080 -990 -900 -810 -720 -630 -540 -450 -360 -270 -180 1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 Name CAP2DUMMY DUMMY DUMMY DUMMY DUMMY TEST3 TEST5 TEST4 TEST2 DUMMY DUMMY DUMMY COMI1 COM1 COM2 COM3 COM4 Coordinate 2160 2250 2340 2430 2520 2610 2700 2790 2880 2970 3060 3150 3240 3330 3420 3510 3600 3690 3780 3870 3960 4050 4140 4230 4320 4410 4500 4590 4680 4770 4860 4950 5040 5130 5220 5920 5920 5920 5920 5920 5920 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1326 -1256 -1186 -1116 -1046 -976
KS0040
DRIVER CONTROLLER
Table Center Coordinates (Continued)
[Unit: Name COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 SEGI1 SEGI2 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG1 SEG2 Coordinate 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5005 4935 4865 4795 4725 4655 4585 4515 4445 4375 -906 -836 -766 -696 -626 -556 -486 -416 -346 -276 -206 -136 1054 1124 1194 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 Name SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 Coordinate 4305 4235 4165 4095 4025 3955 3885 3815 3745 3675 3605 3535 3465 3395 3325 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 Name SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 Coordinate 1435 1365 1295 1225 1155 1085 1015 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770
DRIVER CONTROLLER
KS0040
Table Location (Continued)
[Unit: Name SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 Coordinate -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115 -3185 -3255 -3325 -3395 -3465 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 Name SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEGI3 SEGI4 COMI2 COM64 COM63 COM62 COM61 Coordinate -3535 -3605 -3675 -3745 -3815 -3885 -3955 -4025 -4095 -4165 -4235 -4305 -4375 -4445 -4515 -4585 -4655 -4725 -4795 -4865 -4935 -5005 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1194 1124 1054 Name COM60 COM59 COM58 COM57 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 DUMMY Coordinate -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -136 -206 -276 -346 -416 -486 -556 -626 -696 -766 -836 -906 -976 -1046 -1116 -1186 -1256 -1326
KS0040
DRIVER CONTROLLER
DESCRIPTION
POWER SUPPLY
Table Description Name bias bias bias bias bias (8/9) (7/8) (6/7) (4/5) (7/9) (6/8) (5/7) (3/5) (2/9) (2/8) (2/7) (2/5) (1/9) (1/8) (1/7) (1/5) Power Power supply Connect power supply (GND) Bias voltage level driving Voltages have following relationship: When on-chip power circuit active, these voltages generated according state bias, following table. Description
DRIVER SUPPLY
Table Description (Continued) Name CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT Description Capacitor1+ connect internal voltage converter Capacitor1- connect internal voltage converter Capacitor2+ connect internal voltage converter Capacitor2- connect internal voltage converter Capacitor3+ connect internal voltage converter Capacitor3- connect internal voltage converter Voltage converter output voltage adjustment which valid only when using external resistors Select reference voltage internal voltage regulator "High": reference voltage internal voltage regulator voltage VDD. "Low": reference voltage internal voltage regulator internal VREF (2.0V).
DRIVER CONTROLLER
KS0040
SYSTEM CONTROL
Table Description (Continued) Name Description External clock input must fixed "High" "Low" when internal oscillation circuit used. case external clock mode, used clock input should OFF. Select kinds interface When "High": 6800-series interface mode When "Low": 8080-series interface Select interface length when parallel interfacing "High") When "High": 8-bit interface mode When "Low": 4-bit interface mode Select Interface mode with When "High": parallel interface mode When "Low": serial interface mode
INTERFACE
Table Description (Continued) Name RESET Description Hardware reset input Initialization performed edge sensing (rising falling) RESET signal. Used chip selection input When "High", selected When "Low", selected Used register selection input When "High", data register When "Low", instruction register When "High"(6800-series interfacing), used read (RW_WR "High") write (RW_WR "Low") selection input (R/W). When "Low "(8080-series interfacing), used write enable input (WR). When "High"(6800-series interfacing), used read/write enable input (E). When "Low "(8080-series interfacing), used read enable input (RD). When 8-bit interface mode, used bi-directional data pin. When 4-bit interface mode, only used data input used. When serial mode, (SCL) used serial clock input pin, (SI) used serial data input others used.
RW_WR E_RD
KS0040
DRIVER CONTROLLER
DRIVER OUTPUT
Table Description (Continued) Name COM1 COM64 COMI1, COMI2 SEG1 SEG128 SEGI1 SEGI4 Description Common signal output character display Common signal output horizontal icon display These same signal name different. Segment signal output character display
Segment signal output vertical icon display
TEST
Table Description (Continued) Name TEST1 TEST5 Test Connect these "Low". Description
NOTE: DUMMY These pins should opened (floated).
DRIVER CONTROLLER
KS0040
FUNCTION DESCRIPTION
SYSTEM INTERFACE
KS0040 kinds interface type with MPU: mode 4-bit length), serial mode. Serial mode selected pin. Table Various Kinds Interface 6800series 8080series (H)/(L) (H)/(L) RW_WR (H)/(L) E_RD (H)/(L) (H)/(L) DB0-3 DB0-3 DB0-3 DB4-5 DB4-5 DB4-5 DB4-5 DB4-5
mode
Serial mode
NOTE: Don't care ("High", "Low" "Open"). (H)/(L): fixed "High" (VDD) "Low" (VSS) NOTE: Read operation permitted 4-bit serial interface mode.
"High" parallel interface mode, "High" 6800-series interface, "High" 8-bit interface mode, CSB: "High" chip selected, "High" data Register select, RW_WR: 6800-series read write select, E_RD: 6800-series "Low" enable, (DB6): serial clock input (DB7): serial data input
"Low" serial interface mode "Low" 8080-series interface mode "Low" 4-bit interface mode "Low" chip selected "Low" instruction register select 8080-series active "High write enable 8080-series active "Low read enable
KS0040
DRIVER CONTROLLER
Interface with Parallel Mode "High") parallel interface mode, 6800-series 8080-series selected pin, interface length 4bit) selected pin. During write operation, 16-bit data register (DR) 8-bit instruction register (IR) used. data register (DR) used temporary data storage place from being written into DDRAM CGRAM ICONRAM. target selected selection instruction. instruction register (IR) used only store instruction code transferred from MPU. select either input parallel mode serial mode.
RW_WR E_RD
8-Bit Mode "High")
4-Bit Mode "Low")
Instruction Write
Data Write
Dummy Read
Data Write
Data Read
Instruction Write
Figure Timing Diagram 6800-series Mode Data Transfer "High")
RW_WR E_RD
8-Bit Mode "High")
4-Bit Mode "Low")
Instruction Write
Data Write
Dummy Read
D7D0
Data Write
Data Read
Instruction Write
Figure Timing Diagram 8080-Series Mode Data Transfer "Low")
DRIVER CONTROLLER
KS0040
Interface with Serial Mode "Low") When input "Low", clock synchronized serial interface mode selected. this time, following four ports, (DB6, synchronizing transfer clock input), (DB7, serial data input), (register selection input), (chip selection input) used. setting "Low", KS0040 receive input. "High", KS0040 initialize interface circuit (8-bit shift register 3-bit counter). Serial data input order "D7, from serial data input DB7) rising edge serial clock (SCL DB6). rising edge serial clock, serial data (D7-D0) converted into 8-bit data. input selection latched rising edge serial clock (SCL).
SI(DB7) SCL(DB6) Figure Timing Diagram Serial Data Transfer
KS0040
DRIVER CONTROLLER
Internal total 1,200 bytes, consist DDRAM (128 bytes), ICONRAM bytes) CGRAM (1,024 bytes). Table Address
data usage (D7~D0) DDRAM line) DDRAM (2nd line) DDRAM (3rd line) DDRAM (4th line) DDRAM (5th line) DDRAM (6th line) DDRAM (7th line) DDRAM (8th line) ICONRAM upper icons C128) ICONRAM lower icons (C129 C256) ICONRAM COMS data S128) CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM 10th pattern CGRAM 11th pattern CGRAM 12th pattern CGRAM 13th pattern CGRAM 14th pattern CGRAM 15th pattern CGRAM 16th pattern CGRAM 17th pattern CGRAM pattern CGRAM pattern CGRAM 20th pattern CGRAM 21st pattern CGRAM 22nd pattern CGRAM 23rd pattern CGRAM 24th pattern CGRAM 25th pattern CGRAM 26th pattern CGRAM 27th pattern CGRAM 28th pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern
size
128byte
48byte
128byte (page
128byte (page
128byte (page
128byte (page
128byte (page
128byte (page
128byte (page
128byte (page
NOTE: system select register
DRIVER CONTROLLER
KS0040
Display Data (DDRAM) DDRAM stores 16-bits character code FCGROM CGRAM 8-bits character code HCGROM, maximum number 128-byte (64-word: Characters full-size fonts characters half-size fonts). displayable area 64-byte other extended data area. display extended DDRAM data, "High" system register instruction. DDRAM address address counter (AC) hexadecimal number.
Relations DDRAM Address Display Position When DDRAM normal mode (EXT "Low")
COM1 COM16 COM17 COM32 COM33 COM48 COM49 COM64
Display Shift performed
COM1 COM16 COM17 COM32 COM33 COM48 COM49 COM64
Display Shift performed
COM1 COM16 COM17 COM32 COM33 COM48 COM49 COM64
Display Shift Down performed Figure Normal Mode DDRAM Address (EXT "Low")
KS0040
DRIVER CONTROLLER
When DDRAM Extended Mode (EXT "High")
COM1 COM16 COM17 COM32 COM33 COM48 COM49 COM64
Display Shift performed
COM1 COM16 COM17 COM32 COM33 COM48 COM49 COM64
Display Shift-up performed
COM1 COM16 COM17 COM32 COM33 COM48 COM49 COM64
Display Shift-down performed
Figure Extended Mode DDRAM Address (EXT "High")
DRIVER CONTROLLER
KS0040
Character Generator (CGRAM) CGRAM used user defined character pattern. generate 32,16 dots full-size fonts include cursor position. capacity CGRAM support bitmap graphics dot. character pattern CGRAM write character code into DDRAM like table Table Relationship between Character Code (DDRAM) Character Pattern (CGRAM) Character code (DDRAM data) CGRAM address RRRR 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 AAAAAA 654321 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 CGRAM data CGRAM data Pattern number
0000h
Pattern
001Fh
Pattern
KS0040
DRIVER CONTROLLER
Table Example Bitmap Graphic CGRAM Character code (DDRAM data) CGRAM address RRRR AAAAAA 654321 CGRAM data CGRAM data Pattern number
0000h
Pattern
0001h
Pattern
CGRAM0 CGRAM1 CGRAM2 CGRAM3
Character Display
Figure Example Bitmap Display with Character
DRIVER CONTROLLER
KS0040
(*15)
(*16)
Figure Relationship between CGRAM Full Graphic Mode Data Writing Display Pattern "High") During CGROM full graphic mode, CGRAM data written from (*1) (*1024) 8-bit length Table Order CGRAM Data Writing (*1) (*17) (*2) (*18) (*3) (*19) (*4) (*20) (*5) *(21) (*6) (*22) -(*15) (*31) (*16) (*32)
(*1) (*1009)
(*2) (*1010)
(*3) (*1011)
(*4) (*1012)
(*5) (*1013)
(*6) (*1014)
(*1023)
(*1024)
(*1009)
(*1010)
(*1011)
(*1012)
(*1013)
(*1014)
(*1022)
(*1023)
(*1024)
KS0040
DRIVER CONTROLLER
Segment Common Icon (ICONRAM) ICONRAM Segment Common Icon pattern data. COMI1 COMI2 SEGI1~4 makes data ICONRAM enable display icons. Table Relationship between ICONRAM Address Display Pattern ICONRAM address H113 H121 H114 H122 H115 H123 H116 H124 VL121 VL125 VL122 VL126 VR121 VR122 VR125 VR126 H117 H125 H118 H126 H119 H127 H120 H128 VL57 VL61 VL65 VL69 VL58 VL62 VL66 VL70 VR57 VR61 VR65 VR69 VR58 VR62 VR66 VR70 VL123 VL127 VL124 VL128 VR123 VR124 VR127 VR128 COMI icons data (*3) ICONRAM bits VL59 VL63 VL67 VL71 VL60 VL64 VL68 VL72 VR59 VR63 VR67 VR71 VR60 VR64 VR68 VR72 Lower SEGI icons data (*2) Upper SEGI icons data (*1) Icons
NOTE: VLn: vertical left n-th icon, VRn: vertical right n-th icon horizontal n-th icon (where 128)
DRIVER CONTROLLER
KS0040
(*3)
COMI1 COM1 COM2 COM3 COM31 COM32 COM33 COM34 COM62 COM63 COM64 VL63 VL65 VL64 VL66 H127 H128 VR64 VR66
(*1)
Character Display Area
VR63 VR65
(*2)
VL125 VL126 VL127 VL128
VR125 VR126 VR127 VR128 SEGI3SEGI4VR2 -SEGI1
Figure Relationship between Icon Pattern Data Line (When DIRC DIRS
-SEG128
-SEG127
-SEG126
-SEG125
-SEGI4
-SEGI3
COM64 COM63 COM62 COM34 COM33 COM32 COM31 COM3 COM2 COM1 COMI1
VL63 VL65
VL64 VL66
-SEGI2
-SEG2
-SEG1
(*1)
VR64 VR66
Character Display Area
VR63 VR65
(*2)
VL125 VL126 VL127 VL128 H127 H128
VR125 VR126 VR127 VR128
(*3) Figure Relationship between Icon Pattern Data Line (When DIRC DIRS
KS0040
DRIVER CONTROLLER
(*3)
COMI1 COM1 COM2 COM3 COM31 COM32 COM33 COM34 COM62 COM63 COM64 VL63 VL65 VL64 VL66 H127 H128 VR63 VR65
(*1)
VR64 VR66
Character Display Area
(*2)
VL125 VL126 VL127 VL128
VR125 VR126 VR127 VR128 SEGI2SEGI1VR2 -SEGI4
Figure Relationship between Icon Pattern Data Line (When DIRC DIRS
-SEG127
-SEG128
-SEGI1
-SEGI2
COM64 COM63 COM62 COM34 COM33 COM32 COM31 COM3 COM2 COM1 COMI1
VL63 VL65
VL64 VL66
-SEGI3
-SEG1
-SEG2
-SEG3
-SEG4
(*1)
VR64 VR66 VR63 VR65
Character Display Area
(*2)
VL125 VL126 VL127 VL128 H127 H128
VR125 VR126 VR127 VR128
(*3) Figure Relationship between Icon Pattern Data Line (When DIRC DIRS
DRIVER CONTROLLER
KS0040
CHARACTER GENERATOR FULL-SIZE FONT (FCGROM)
FCGROM generates characters pattern from Character Generate code DDRAM. FCGROM 16-dot 8,160 character pattern include cursor position Asian language character font (like Chinese, Japanese Kanji, Korean). data cursor position high, data included character pattern. selected positions always without regard cursor position.
CHARACTER GENERATOR HALF-SIZE FONT (HCGROM)
HCGROM generates characters pattern from Character Generate code DDRAM. HCGROM 16dot character pattern include cursor position half-size font (like alphanumeric characters symbols). data cursor position high, data included character pattern. selected positions always without regard cursor position. Table Relationship between CGROM Address Font Pattern (KS0040-00 Font) FCGROM address Font data (D15 FEFCBA9876543210 HCGROM address Font data 76543210
0380(h)
41(h)
KS0040
DRIVER CONTROLLER
Table KS0040-00 Font (KSC5601 Code) KSC5601 code A1A1 ACFE B0A1 B0FE B1A1 B1FE B2A1 B2FE B3A1 B3FE B4A1 B4FE B5A1 B5FE B6A1 B6FE B7A1 B7FE B8A1 B8FE B9A1 B9FE BAA1 BAFE BBA1 BBFE BCA1 BCFE BDA1 BDFE BEA1 BEFE BFA1 BFFE C0A1 C0FE C1A1 C1FE C2A1 C2FE C3A1 C3FE C4A1 C4FE C5A1 C5FE C6A1 C6FE C7A1 C7FE C8A1 C8FE CAA1 CBA1 CBFE CCA1 CCFE CDA1 CDFE CEA1 CEFE CFA1 CFFE D0A1 D0FE D1A1 D1FE D2A1 D2FE D3A1 D3FE D4A1 D4FE D5A1 D5FE D6A1 D6FE D7A1 D7FE D8A1 D8FE D9A1 D9FE DAA1 DAFE DBA1 DBFE DCA1 DCFE DDA1 DDFE KS0040 FCGROM code 0000 001F 0020 037F 0380 03DD 03DE 043B 043C 0499 049A 04F7 04F8 0555 0556 05B3 05B4 0611 0612 066F 0670 06CD 06CE 072B 072C 0789 078A 07E7 07E8 0845 0846 08A3 08A4 0901 0902 095F 0960 09BD 09BC 0A1B 0A1C 0A7C 0A7D 0AD7 0AD8 0B35 0B36 0B93 0B94 0BF1 0BF2 0C4F 0C50 0CAD 0CB0 0D0D 0D0E 0D6B 0D6C 0DC9 0DCA 0E27 0E28 0E85 0E86 0EE3 0EE4 0F41 0F42 0F9F 0FA0 0FFD 0FFE 105B 105C 10B9 10BA 1117 1118 1175 1176 11D3 11D4 1231 1232 128F 1290 12FD 12EE 134B 134C 13A9 13AA 1407 Font data CGRAM font area Symbol character area
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KS0040
Table KS0040F00 Font (KSC5601 Code) (Continued) KSC5601 code DEA1 DEFE DFA1 DFFE E0A1 E0FE E1A1 E1FE E2A1 E2FE E3A1 E3FE E4A1 E4FE E5A1 E5FE E6A1 E6FE E7A1 E7FE E8A1 E8FE E9A1 E9FE EAA1 EAFE EBA1 EBFE ECA1 ECFE EDA1 EDFE EEA1 EEFE EEA1 EFFE F0A1 F0FE F1A1 F1FE F2A1 F2FE F3A1 F3FE F4A1 F4FE F5A1 F5FE F6A1 F6FE F7A1 F7FE F8A1 F8FE F9A1 F9FE FAA1 FAFE FBA1 FBFE FCA1 FCFE FDA1 FDFE KS0040 FCGROM code 1408 1465 1466 14C3 14C4 1521 1522 157F 1580 15DD 15DE 163B 163C 1699 169A 16F7 16F8 1755 1756 17B3 17B4 1811 1812 186F 1870 18CD 18CE 192B 192C 1989 198A 19E7 19E8 1A45 1A46 1AA3 1AA4 1B01 1B02 1B5F 1B60 1BBD 1BBE 1C1B 1C1C 1C79 1C7A 1CD7 1CD8 1D35 1D36 1D93 1D94 1DF1 1DF2 1E4F 1E50 1EAD 1EAE 1F0B 1F0C 1F69 1F6A 1FC7 Font data
KS0040
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POWER CONSUMPTION MODE
KS0040 sleep mode saving power consumption during standby period. (refer "INITIALIZING POWER SAVE MODE SETUP") Sleep Mode Sleep Mode, power circuit oscillation circuit turned OFF. This mode helps save power consumption reducing current almost resting current level. Liquid Crystal Display Output COM1 COM64, COMI1, level SEG1 SEG128, SEGI1, level DDRAM, CGRAM, ICONRAM register written information saved. Operation mode retained same prior execution sleep mode. internal circuits stopped. Power Circuit Oscillation Circuit built-in supply circuit oscillation circuit turned automatically using sleep command.
DRIVING CIRCUIT
Driver circuit common segment signals driving. data from CGROM CGRAM ICONRAM transferred 128-bit segment latch serially 8-bits unit, then stored 128-bit shift latch. data from ICONRAM stored 4-bit latch. When each common line selected 65-bit common register, segment data segment icon data also output through segment driver from 128-bit segment latch 4-bit segment icon latch. KS0040 common segment bi-directional function help various panel applications. (refer table table Table Data Shift Direction DIRS High SEGI1, SEGI2, SEG1 data shift direction SEG128, SEGI3, SEGI4 SEGI4, SEGI3, SEG128 SEG1, SEGI2, SEGI1 Table Data Shift Direction Duty 1/17 (1-line mode) 1/33 (2-line mode) 1/49 (3-line mode) 1/65 (4-line mode) DIRC High High High High data shift direction COM1 COM16, COMI1 (COMI2) COM16 COM1, COMI1 (COMI2) COM1 COM32, COMI1 (COMI2) COM32 COM1, COMI1 (COMI2) COM1 COM48, COMI1 (COMI2) COM48 COM1, COMI1 (COMI2) COM1 COM64, COMI1 (COMI2) COM64 COM1, COMI1 (COMI2)
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KS0040
DISPLAY SHIFT CONTROL
KS0040 vertical dot-by-dot character-by-character shift function, which usable when display panel size less than 4-line display want display hidden-line data, when extended DDRAM want display extended DDRAM data
Display Home State
After Dot-By-Dot Shift-up
After Dot-By-Dot Shift-up
After Dot-By-Dot Shift-up
After 16th Dot-By-Dot Shift-up
Figure Vertical Dot-by-Dot Shift-up (down) Example
KS0040
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INSTRUCTION DESCRIPTION
Outline overcome speed difference between internal clock KS0040 clock, KS0040 performs internal operation storing control information internal operation determined according signal from MPU, composed read write data bus. Instruction divided four kinds, System register instructions (power control, contrast value set, etc.) Internal access instructions (RAM select, address set, data read write, etc.) Display control instructions (vertical shift, double height character, etc.) Others address internal automatically increased decreased
NOTE: Every instruction takes cycle execution time, execute next instruction, minimum cycle time (tc) must kept.
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KS0040
Table Instruction table Instruction Return home
Instruction code
(Hex) (Hex)
Description operation DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed Display (D), character cursor (CC), line
Display control Power save mode Contrast increment decrement Vertical shift Double height character
(Hex) (Hex) (Hex) (Hex) (Hex)
cursor (LC), reverse display (REV)
control
Sleep mode (SLP) control
Contrast increment (CID decrement (CID Vertical character shift down Double height character enable (EN) selected line (DH1, DH0).
Selected register DDRAM ICONRAM CGRAM page CGRAM page Power control register Contrast control register Environment control register Function control register
select system register
(Hex)
ICON address setting, address
selected select
instruction. Write data Read data
NOTE: Don't care
ICON system register data write ICON system register data read
KS0040
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Table System Register Values Register select Selected system register Power control register Contrast control register Environment control register Function control register Register value INTR
DIRC DIRS
NOTE: Don't care
OSC: internal oscillator (OSC (OSC control voltage converter control voltage regulator control voltage follower control INTR: internal voltage regulating resisters (INTR (INTR control RR0: internal voltage adjusting resisters control register bits (refer table electronic contrast control register bits. (refer figure DT1, DT0: duty select bits (refer table DIRC, DIRS: common data direction (DIRC), segment data direction (DIRS) select (refer table table EXT: DDRAM extended mode (EXT (EXT control DDRAM CGRAM ICONRAM address increment decrement control CGRAM full graphic mode control center display mode control FL1: first line mode (FL1 (FL1 control, during vertical shift cursor attribute control
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KS0040
Return Home
DDRAM address "00h" into address counter. display position shifted, return original positions. When cursor blinking displayed bring cursor left edge first line display. data DDRAM does change. Display Control
Display control instruction
Display Control When "High", entire display turned When "Low", entire display turned OFF, display data remained DDRAM (default) Character Cursor Control When "High", character cursor turned When "Low", character cursor disappeared current display (default). Line Cursor Control When "High", line cursor turned according most significant 2-bits (ADDR[6], ADDR[5]) current DDRAM address (ADDR [6:0]). When "Low", line cursor disappeared current display (default) REV: Black White Reverse Display Control When REV= "High", display area except icon area black white reversed. When REV= "Low", normal display status (default) Power Save Mode
Power Save mode used making KS0040 sleep mode.
SLP: Sleep Mode Control When "High", sleep mode (default). When "Low", sleep mode reset. (refer "LOW POWER CONSUMPTION MODE" "INITIALIZING POWER SAVE MODE SETUP")
KS0040
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Contrast Increment Decrement
Contrast control register value increment decrement instruction CID: Contrast Increment Decrement Enable When "High": contrast register value increased until When "Low": contrast register value decreased until Vertical Shift-up down
Vertical dot-by-dot display shift-up down instruction (refer figure
Character Shift Select When "High": display shift-up down character selected (It's same 16-time shift). When "Low": display shift-up down selected. Vertical Display Shift Direction Select When "High": display shift-up performed. When "Low": display shift-down performed. Double Height Character
Double height character instruction (refer figure
Double Height Character Mode Enable When "High": double height character mode enabled. When "Low": double height character mode disabled (default). DH1, DH0: Double Height Character Line Select When [DH1, DH0] [Low, Low]: 2-line becomes double height character [Low, High]: 3-line becomes double height character [High, Low]: 4-line becomes double height character [High, High]: 4-line becomes double height character
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KS0040
Select System Register
selection (DDRAM CGRAM ICONRAM) system register instruction. system register selection bits Select bits Data length value Selected registers DDRAM ICONRAM CGRAM page0 CGRAM page1 CGRAM page2 CGRAM page3 CGRAM page4 CGRAM page5 CGRAM page6 CGRAM page7 Power control register Contrast control register Environment control register Function control register 1-byte (half-size font) 2-byte (full-size font) 1-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte INTR DIRC DIRS
NOTE: Don't care writing 2-byte data into RAM, data write instruction must performed twice.
OSC: oscillator circuit (OSC "High"), (OSC "Low": default) control voltage converter regulator follower circuit "High"), "Low": default) control INTR: internal voltage regulating resistors (INTR "High"), (INTR "Low": default) control RR2~RR0: internal voltage adjusting resistors control register bits ([0,0,0]: default). (refer table electronic contrast control register ([0, default) (refer figure DT1, DT0: duty select register ([1, default) (refer table DIRC, DIRS: common data shift direction (DIRC), segment data shift direction (DIRS) flag register ([0, default) (refer table table EXT: DDRAM extended mode (EXT "High"), (EXT "Low": default) control address increment "High": default), decrement "Low") mode CGRAM full graphic mode control register "Low": default). (refer figure center display mode control register "Low": default). (refer figure FL1: first line mode, during vertical scroll instruction, control register (FL1 "Low": default). (refer figure character line cursor attribute select register ([0, default) (refer table
KS0040
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Address
DDRAM CGRAM ICONRAM address instruction. Each selected select instruction. Write Data
DDRAM CGRAM ICONRAM data system register value write instruction. Each system register selected select system register instruction. After write operation, address increased/decreased automatically, according function control register set. When writing full-size character address FCGROM DDRAM, data write instruction must written twice, because FCGROM address 13-bits long. (refer figure Read Data (8-bit Mode Interface only)
DDRAM CGRAM ICONRAM data system register value read instruction. Each system register selected select system register instruction. read data after address instruction, correct data from second. first data would incorrect, because there timing margin transfer data output register. After write read operation, address increased/decreased automatically, according function control register set. When reading full size character address FCGROM from DDRAM, data read instruction must executed twice, because FCGROM address 13-bits long. (refer figure
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KS0040
Full-size Character Code (FCGROM CGRAM Address Attribute)
[A1] [A0]
Full-size Display Character Attribute Code
Upper Character Code
Lower Character Code Half-size Character Code (HCGROM Address) Half-size Character
Character Code
Figure DDRAM Data (FCGROM HCGROM CGRAM Address) Format
Table Display Attributes [A1] [A0] Display state (when cursor blink OFF)
Normal display
reversed display
Character blink mode
Character blink mode
KS0040
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Table Cursor Attributes [B1] [B0] Display state cursor position)
Underline cursor
reverse cursor
Blink cursor
Blink cursor
Table Relationship between Duty Environment Duty 1/17 1/33 1/49 1/65 Bias fosc (kHz) 24.5 47.6 68.3 93.7 Display line number 1-line display 2-line display 3-line display 4-line display
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KS0040
Normal Display Line Cursor (LC) First Line Mode (FL1) Vertical Shift
Normal Display Line Cursor Line Cursor (LC) (B1, First Line Mode (FL1) Vertical Shift
Vertical Shifted Display First Line Mode) Line Cursor (LC) (B1, First Line Mode (FL1) Vertical Shift-up times
Vertical Shifted Display First Line Mode Line Cursor (LC) (B1,B0 First Line Mode (FL1) Vertical Shift times Vertical Shift-up Character once
Figure Examples Vertical Shift First Line Mode
KS0040
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DH1,
DH1,
DH1,
DH1,
DH1, Center Mode When 3-line Display Figure Examples Double Height Character Display
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KS0040
Figure Examples Full Graphic Mode Display
KS0040
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INITIALIZING POWER SAVE MODE SETUP
HARDWARE RESET
When RESET "Active (rising falling)", KS0040 initialized following state. Return Home Address counter Control Display Instruction display character line cursor reverse display (normal display) Power Save Mode Instruction sleep mode Select Instruction DDRAM selected. System Register Instruction
oscillator voltage converter regulator follower INTR internal voltage regulating resister Internal voltage adjusting resistors control register value 000. Electronic contrast control register values 00H. DT1, 4-line display mode DIRC normal direction common outputs (COM1 COM64, COMI1 (COMI2)) DIRS normal direction segment outputs (SEGI1, SEGI2, SEG1 SEG128, SEGI3, SEGI4) Normal DDRAM mode selected. address increment condition CGRAM full graphic mode center display mode first line mode under line cursor attribute selected.
NOTE: initialization done RESET pin, unstable condition might result. initializing RESET input must active first.
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KS0040
VDD=2.4V
tRESETB RESET Internal Reset Time Reset Start Time Reset Pulse Width Reset Time tRESETB
50ns 1.0µs 1.0µs
Figure Reset Timing
NOTE: indicates minimum RESET duration activating internal reset signal. indicates reset completion time internal circuit from edge internal reset signal.
KS0040
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INITIALIZING INSTRUCTION
VDD-VSS Power Power Regulation Input Reset Signal Command Status Initializing Hardware Reset Input Status Waiting more Command Input Power Save Command (Sleep Mode OFF) System Register Command Environment Register Value (DT1, DT0, DIRC, DIRS, EXT, Function Control Register Value (FG, FL1, Internal Voltage Adjusting Resistors Control Register (RR2~RR0) Contrast Control Register Value Power Control Register Value (OSCVCVR (INTR)VF: Address Command Data Writing (RAM Clear) (DDRAM A0H, ICONRAM 00H) Waiting 20msec more Command Input Display Control Commands Initialization Input Address Setup Command Input (Data) Write Command Display Written Data NOTE: Commands initialize RAM. non-display area must satisfy following conditions (for clear). DDRAM: Write data. (Half character flag space character code "20H": "0100000") CGRAM: Write data (blank data) ICONRAM: Write data (off data) data unstable during reset signal input (after power ON), blank data must written. not, unexpected display result.
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KS0040
SLEEP MODE RELEASE INSTRUCTION
Sleep Mode Setting Initialization Command Status Initializing Instruction Setup Input Status Normal Operation Status Command Input Display Control Command (Display OFF) Power Save Command (Power Save *OSC, automatically OFF. Enter Sleep Mode Internal voltage regulating resistor control (INTR) voltage adjusting resistors control register bits (RR2 RR0) changed sleep mode.
Sleep Mode Releasing Initialization Command Input Power Save Command (Sleep Mode OFF) System Register Command (Power Control Register Set) OSCVCVRVF: Waiting more Display Control Command (Display Return Normal Operation
KS0040
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RECOMMENDATION POWER SEQUENCE
Power Sequence (Power Control Register Set) Power
Oscillator [OSC, Waiting Voltage Converter [OSC, Waiting Voltage Regulator [OSC, Waiting Voltage Follower [OSC,
Power Sequence
Display Waiting 50ms Voltage Regulator [OSC, Waiting Voltage Follower [OSC, Waiting Voltage Converter [OSC, Waiting VDD-VSS Power
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KS0040
DRIVING POWER SUPPLY CIRCUIT
This Power Supply circuit generating voltages drive consists voltage converter, voltage regulator, voltage follower. Voltage converter boosts logic voltage (VDD) times this boosted voltage (VOUT) delivered voltage regulator. Voltage regulator adjusts between VOUT this adjusted voltage sent voltage follower. VLCD voltage (V0) resistively divided into four voltage levels (V1, those output impedance converted voltage follower increasing drive capability. Power Supply circuit controlled Power Control instruction. There eight combination states according instruction sets (VC, VF). Table shows useful combinations which recommended, remaining combination states impractical, recommended used. Table Recommended Power Supply Combination Voltage converter Enable Disable Voltage regulator Enable Enable Voltage follower Enable Enable VOUT Internal voltage output External voltage input Open VO,VR Used voltage adjustment Used voltage adjustment External voltage input open External voltage input open Internal voltage output Internal voltage output Internal voltage output External voltage input
Disable
Disable
Enable
Disable
Disable
Disable
Open
NOTE: recommendation only case listed above table.
KS0040
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VOLTAGE CONVERTER
This circuit boosts electric potential between times toward positive side boosted voltage come through VOUT terminal.
VOUT CAP3+ CAP3CAP2+ CAP2C1 CAP1+ CAP1VSS Recommended Capacitance value Figure Times Boosting VOUT
VOUT CAP3+ CAP3C1 CAP2+ CAP2CAP1+ CAP1VSS Recommended Capacitance value Figure Three Times Boosting VOUT
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KS0040
VOUT CAP3+ CAP3CAP2+ CAP2C1 CAP1+ CAP1VSS Recommended Capacitance value Figure Four Times Boosting VOUT
KS0040
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VOLTAGE REGULATOR
boosting voltage occurring VOUT sent voltage regulator. Voltage Regulator determines driver voltage adjusting resistor within range |V0| |VOUT|. This determined equation (1), where internal external resistors VREF determined equation voltage source electric potential VREF levels setting 6-bit reference voltage register.
where value 6-bit reference voltage register when "High", "Low", VREF (internal reference voltage)
VREF Inside Chip Figure Voltage Regulator Circuit VOUT
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KS0040
When Using Internal Resistors, (INTR "High") When INTR "High", resistor connected internally between VSS, connected between determine instructions, "Regulator Resistor Select" "Set Reference Voltage". Table Internal Ratio Depending 3-bit Data (RR2 RR0) 3-bit data settings (RR2 RR0) 1+(Rb
following figure shows voltage measured adjusting internal regulator resistor ratio 6-bit electronic volume registers (temperature coefficient -0.05%/°C).
14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00
Electronic Volume Level
Figure Electronic Volume Level (Temperature Coefficient -0.05%
KS0040
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Table Relationship between Electronic Volume Constant, 6-bit Voltage Reference Register (C5,
Table Change Ratio VREF Following Table
(REF [RR2, RR1, RR0] 25°C)
7.90 7.93 8.90 8.93 8.97 9.97 10.00
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KS0040
When Using External Resistors, (INTR "Low") When INTR "Low", necessary connect external regulator resistor between VSS, between Example: following requirements driver voltage, 6-bit reference voltage register Maximum current flowing From equation VREF
From equation VREF where From requirement [µA] From equations (2), When (REF "Low") When (REF "High")
KS0040
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BIAS RESISTOR FOLLOWER
CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT When internal bias circuit (VC, INTR When external bias circuit (VC, INTR CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT
Recommended Capacitance value Figure Bias Circuit
Table Duty Select Input Internal Bias Circuit High High High High Duty 1/17 1/33 1/49 1/65 Internal bias
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KS0040
EXTERNAL POWER SUPPLY
CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT (VC, INTR CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT External Power Supply (VC, INTR Recommended Capacitance value
CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT
External Power Supply
External Power Supply
(VC, INTR CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT External Power Supply (VC, INTR
Figure When External Power Supply used
KS0040
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APPLICATION INFORMATION
INTERFACE METHOD
Parallel Interfacing with 8080-series Microprocessors
A1~A7 IORQ DECODER
(8080-series) D0-D7 RESET RESETB
KS0040
E_RD RW_WR DB0-DB7 RESET
Figure 8080-series Interface Parallel Interfacing with 6800-series Microprocessors
A1~A7 DECODER
(6800 -series) D0-D7
KS0040
E_RD RW_WR DB0-DB7 RESET RESETB
RESET
Figure 6800-series Interface
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KS0040
Clock Synchronized Serial Interfacing with Microprocessors
PORT4 PORT3
PORT1 PORT0 RESET RESETB
KS0040
SCL(DB6) SI(DB7) RESET
Figure 4-Pin Serial Interface
KS0040
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PANEL CONNECTION METHOD (1/65 DUTY CONFIGURATION)
Chip Bottom Lower View (DIRS DIRC
SEGI2 SEGI1 COM56 COM49 COM40 COM33 COM24 COM17 COM8 COM1 COMI1
BOTTOM VIEW
SEGI3 SEGI4 COMI2 COM64 COM57 COM48 COM41 COM32 COM25 COM16 COM9
Figure Chip Bottom Lower View (DIRS DIRC
SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115
DRIVER CONTROLLER
KS0040
Chip Bottom Upper View (DIRS DIRC
COM9 COM16 COM25 COM32 COM41 COM48 COM57 COM64 COMI2 SEGI4 SEGI3
BOTTOM VIEW
SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14
COMI1 COM1 COM8 COM17 COM24 COM33 COM40 COM49 COM56 SEGI1 SEGI2
Figure Chip Bottom Lower View (DIRS DIRC
KS0040
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Chip Lower View (DIRS DIRC
SEGI3 SEGI4 COMI2 COM64 COM57 COM48 COM41 COM32 COM25 COM16 COM9
VIEW
SEGI2 SEGI1 COM56 COM49 COM40 COM33 COM24 COM17 COM8 COM1 COMI1
Figure Chip Lower View (DIRS DIRC
SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128
SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14
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KS0040
Chip Upper View (DIRS DIRC
COMI1 COM1 COM8 COM17 COM24 COM33 COM40 COM49 COM56 SEGI1 SEGI2
VIEW
SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM9 COM16 COM25 COM32 COM41 COM48 COM57 COM64 COMI2 SEGI4 SEGI3
Figure Chip Lower View (DIRS DIRC
KS0040
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FRAME FREQUENCY
1/17 Duty (DT1,
1-line Selection Period
COM1
FRAME
FRAME
1-line Selection Period Clock Pulses Frame 40.8µs 11.8ms Clock=40.8µs fosc=24.5kHz) Frame Frequency 11.8ms 85Hz
Figure Frame Frequency (1/17 Duty) 1/33 Duty (DT1,
1-line Selection Period
COM1
303132
303132
FRAME
FRAME
1-line Selection Period Clock Pulses Frame 21.0µs 11.8ms Clock=21.0µs fosc=47.6kHz) Frame Frequency 11.8ms 85Hz
Figure Frame Frequency (1/33 Duty)
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KS0040
1/49 Duty (DT1,
1-line Selection Period
COM1
FRAME
FRAME
1-line Selection Period Clock Pulses Frame 14.2µs 11.8ms Clock=14.2µs fosc=68.3kHz) Frame Frequency 11.8ms 85Hz
Figure Frame Frequency (1/49 Duty) 1/65 Duty (DT1,
1-line Selection Period
COM1
62636465
62636465
FRAME
FRAME
1-line Selection Period Clock Pulses Frame 10.7µs 11.8ms Clock=10.7µs fosc=93.7kHz) Frame Frequency 11.8ms 85Hz
Figure Frame Frequency (1/65 Duty)
KS0040
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Table Duty Select Input Display Window Size High High High High Duty 1/17 1/33 1/49 1/65 Display window size 1-line 8-character 2-line 8-character 3-line 8-character 4-line 8-character
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KS0040
MAXIMUM ABSOLUTE RATE
Table Absolute Maximum Ratings Characteristics Power supply voltage Power supply voltage Input voltage Operating temperature Storage temperature Symbol VOUT TOPR TSTG Value -0.3 +7.0 -0.3 -0.3 +0.3 +125 Unit
NOTE1: voltage levels based NOTE2: Voltage greater than above damage circuit Voltage level: VOUT VSS. (VLCD VSS) Voltage level:
KS0040
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ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
Table Characteristics (VDD 2.4V 3.6V, Item Operating voltage Symbol Condition Display operation (checker pattern) without load access from Sleep operation without load Oscillator Access operation from fcyc 200kHz 50µA 50µA 25°C Display 1-line mode External clock frequency Display 2-line mode Display 3-line mode Display 4-line mode Voltage converter times Voltage regulator reference voltage driving voltage VOUT 25°C, without load 25°C, value without load VLCD Min. Typ. Max. Unit
IDD1 Supply current (VDD 25°C)
IDD2 IDD3
0.8VDD
24.5 47.6 68.3 93.7
0.2VDD
Input voltage Input leakage current resistance RSEG Frame frequency ILEAK RCOM
VREF VLCD
1.94
2.06 13.0
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KS0040
Table Characteristics (Continued) (VDD 3.6V 5.5V, Item Operating voltage Symbol Condition Display operation (checker pattern) without load access from Sleep operation without load oscillator Access operation from fcyc 200kHz 50µA 50µA 25°C Display 1-line mode External clock frequency Display 2-line mode Display 3-line mode Display 4-line mode *Voltage converter times Voltage regulator reference voltage driving voltage VOUT 25°C, without load 25°C, value without load VLCD 68.3 93.7 Unit
IDD1 Supply current (VDD 25°C)
IDD2 IDD3
0.8VDD
24.5 47.6
1000
Input voltage Input leakage current resistance RSEG Frame frequency ILEAK RCOM 0.2VDD
VREF VLCD
1.94
2.06 13.0
NOTE: When power supply (VDD) range 3.6V 5.5V, times boosting allowed.
KS0040
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CHARACTERISTICS
6800-series Interface Write Instruction Table Characteristics (6800-series Write Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time setup time hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time setup time hold time Symbol tSU1 tSU2 tSU1 tSU2 Min. Typ. Max. Unit
tSU1 RW_WR E_RD Figure Write Mode Timing (6800-series Interface) tSU2
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KS0040
8080-series Interface Write Instruction Table Characteristics (8080-series Write Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time setup time hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time setup time hold time Symbol tSU1 tSU2 tSU1 tSU2 Min. Typ. Max. Unit
tSU1 RW_WR Figure Write Mode Timing (8080-series Interface) tSU2
KS0040
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6800-series Interface Read Instruction Table Characteristics (6800-series Read Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time output delay time output hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time output delay time output hold time Symbol Min. Typ. Max. Unit
RW_WR E_RD toDB7 Figure Read Mode Timing (6800-series Interface)
DRIVER CONTROLLER
KS0040
8080-series Interface Read Instruction Table Characteristics (8080-series Read Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time output delay time output hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time output delay time output hold time Symbol Min. Typ. Max. Unit
E_RD
Figure Read Mode Timing (8080-series Interface)
KS0040
DRIVER CONTROLLER
Clock Synchronized Serial Mode Table Characteristics (Serial Mode) Condition Characteristic clock cycle time Pulse rise fall time clock width 2.4V 3.6V, setup time hold time data setup time data hold time data setup time data hold time clock cycle time Pulse rise fall time clock width setup time 3.6V 5.5V, hold time data setup time data hold time data setup time data hold time Symbol tSU1 tSU2 tSU3 tSU1 tSU2 tSU3 Min. 1000 Typ. Max. Unit
tSU1
tSU2
SCL(DB6) tSU3 SI(DB7)
Figure Clock Synchronized Serial Interface Mode Timing Diagram

DRIVER CONTROLLER July. 1999. Ver. Tae-Kwang, Park parktk@sa

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