Close Captioning Support Teletext Support (Passthrough Mode) On-Board
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Integrated Digital CCIR-601 YCrCb PAL/NTSC Video Encoder ADV7175/ADV7176
Close Captioning Support Teletext Support (Passthrough Mode) On-Board Color Generation On-Board Voltage Reference 2-Wire Serial Interface (I2C Compatible) CMOS Monolithic Construction 44-Pin PQFP Thermally Enhanced Package APPLICATIONS MPEG-1 MPEG-2 Video Digital Satellite/Cable Systems (Set Boxes/IRDs) Video Games Video/Karaoke Professional Studio Quality Video/Multimedia GENERAL DESCRIPTION
FEATURES CCIR-601 YCrCb PAL/NTSC Video Encoder Single Clock Required Oversampling) Pixel Port Supports: CCIR-656 4:2:2 8-Bit Parallel Input Format 4:2:2 16-Bit Parallel Input Format SMPTE 170M NTSC Compatible Composite Video Output CCIR624/CCIR601 Compatible Composite Video Output SCART/PeriTV Support Output Mode Simultaneous Composite S-VHS Video Outputs Programmable Luma Filters (Low-Pass/Notch) Square Pixel Support (Slave Mode) Allows Subcarrier Phase Locking with External Video Source 10-Bit Resolution Encoded Video Channels 8-Bit Resolution Output Interpolation Accurate Subcarrier Construction Programmable Subcarrier Frequency Phase Programmable LUMA Delay Color Signal Control/Burst Signal Control Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Master/Slave Operation Supported Master Mode Timing Programmability Macrovision Antitaping Facility 6.1/7.x (ADV7175 Only)*
ADV7175/ADV7176 integrated digital video encoder that converts Digital CCIR-601 4:2:2 component video data into standard analog baseband television signal compatible with world wide standards NTSC, B/D/G/H/I, addition composite output signal, there facility output S-VHS video, video. Y/C, format simultaneously available analog outputs with composite video signal. Each analog output generates standard video-level signal into doubly terminated load.
(Continued page
FUNCTIONAL BLOCK DIAGRAM
MATRIX
10-BIT 10-BIT 10-BIT
RESET
GREEN/ LUMA/ RED/ CHROMA/ BLUE/ COMPOSITE/
COLOR DATA P7-P0 P15-P8 4:2:2 4:4:4 INTERPOLATOR YCrCb MATRIX
SYNC
INTERPOLATOR
LOW-PASS FILTER LOW-PASS FILTER
BURST
INTERPOLATOR
10-BIT COMPOSITE
BURST
INTERPOLATOR
LOW-PASS FILTER
ADV7175/ADV7176
VOLTAGE REFERENCE CIRCUIT VREF RSET COMP
HSYNC FIELD/VSYNC BLANK
VIDEO TIMING GENERATOR
PORT
REAL-TIME CONTROL CIRCUIT
SIN/COS BLOCK
CLOCK
SCLOCK SDATA ALSB
SCRESET/RTC
*This device protected U.S. Patent Numbers 4631603, 4577216, 4819098 other intellectual property rights. Macrovision anticopy process licensed noncommercial home only, which sole intended devic Please contact sales office latest Macrovision version available.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1996 Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
ADV7175/ADV7176-SPECIFICATIONS
Model Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, DIGITAL OUTPUTS Output High Voltage, Output Voltage, Floating-State Leakage Current Floating-State Output Capacitance ANALOG OUTPUTS Output Current3 Output Current4 Full-Scale Output Size DAC-to-DAC Matching Output Compliance, Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Voltage Reference Range, VREF POWER REQUIREMENTS IDAC6 ICCT7 Power Supply Rejection Ratio DYNAMIC PERFORMANCE Luma Bandwidth9 (Low-Pass Filter) Stopband Cutoff Pass Band Cutoff Chroma Bandwidth Stopband Cutoff Pass Band Cutoff Luma Bandwidth9 (Low-Pass Filter) Stopband Cutoff Pass Band Cutoff Chroma Bandwidth Stopband Cutoff Pass Band Cutoff Differential Gain Differential Phase Differential Gain Differential Phase Accuracy Color Saturation Accuracy
(VAA VREF 1.235 RSET TMIN TMAX2 unless otherwise noted)
specifications
Conditions1
ADV7175/ADV7176
Units Bits
Guaranteed Monotonic ISOURCE ISINK
34.7 182.5 33.9
IOUT IVREFOUT 1.112 1.235 0.02
+1.4 1.359
COMP NTSC Mode Attenuation <0.06 Attenuation NTSC Mode Attenuation >0.1 Attenuation MODE Attenuation <0.06 Attenuation MODE Attenuation >0.1 Attenuation Lower Power Mode Lower Power Mode Peak Periodic
Degree Degree Degree
NOTES versions. Temperature range TMIN TMAX: 70°C. Full drive into 37.5 load. Minimum drive with buffered/scaled output load. Power measurements taken with Clock Frequency MHz. 100°C. IDAC total current drive four DACs. Turning reduces IDAC correspondingly. ICCT (Circuit Currrent) continuous currrent required drive device. Guaranteed characterization. These specifications low-pass filter only. other internal filters please Figure Specifications subject change without notice.
REV.
ADV7175/ADV7176
CHARACTERISTICS1
Parameter Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma Noise Chroma Noise
Units
Condition Referenced NTSC Referenced (NTSC) Referenced (PAL)
TIMING-SPECIFICATIONS2
Parameter PORT1 SCLOCK Frequency SCLOCK High Pulse Width, SCLOCK Pulse Width, Hold Time (Start Condition), Setup Time (Start Condition), Data Setup Time, SDATA, SCLOCK Rise Time, SDATA, SCLOCK Fall Time, Setup Time (Stop Condition), ANALOG OUTPUTS1, Analog Output Delay Analog Output Skew CLOCK CONTROL PIXEL PORT6 FCLOCK Clock High Time Clock Time Data Setup Time Data Hold Time Control Setup Time Control Hold Time Digital Output Access Time Digital Output Hold Time Pipeline Delay
(VAA VREF 1.235 RSET
specifications TMIN TMAX4 unless otherwise noted)
Units Condition
After this period first clock pulse generated Relevant repeated start condition.
24.52
29.5
Clock Cycles
NOTES Guaranteed characterization. input values volts, with input rise/fall times measured between points. Timing reference points inputs outputs. Analog Output Load versions. Temperature range TMAX); +70°C. Output delay measured from point rising edge CLOCK point full-scale transition. Pixel Port consists following inputs: Pixel Inputs: P15-P0 Pixel Controls: HSYNC, FIELD/VSYNC, BLANK Clock Input: CLOCK Specifications subject change without notice.
REV.
ADV7175/ADV7176
SDATA
SCLOCK
Figure Port Timing Diagram
CLOCK
CONTROL I/PS HSYNC, FIELD/VSYNC, BLANK
PIXEL INPUT DATA
CONTROL O/PS HSYNC, FIELD/VSYNC, BLANK
Figure Pixel Control Data Timing Diagram
ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE
Voltage Digital Input Storage Temperature (TS) -65°C +150°C Junction Temperature (TJ) +150°C Lead Temperature (Soldering, secs) +260°C Analog Outputs GND2 -0.5
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Analog Output Short Circuit Power Supply Common indefinite duration.
Model ADV7175KS ADV7176KS
Temperature Range +70°C +70°C
Package Option S-44 S-44
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADV7175/ADV7176 feature proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
ADV7175/ADV7176
DESCRIPTION
Mnemonic P15-P0 CLOCK
Input/Output
Function 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7-P0) 16-Bit YCrCb Pixel Port (P15-P0). represents LSB. Clock Input. Requires stable reference Clock proper operation. Alternatively 24.52 (NTSC) 29.5 (PAL) used square pixel operation. HSYNC (Modes Control Signal. This configured output (Master Mode) accept (Slave Mode) Sync signals. Dual Function FIELD (Mode VSYNC (Mode Control Signal. This configured output (Master Mode) accept (Slave Mode) these control signals. Video Blanking Control Signal. pixel inputs ignored when this logic level "0." This signal optional. This configured input setting MR22 MR21 Mode Register configured subcarrier reset pin, which case high transition this will reset subcarrier field Alternatively configured Real Time Control (RTC) input. Voltage Reference Input DACs Voltage Reference Output (1.2 resistor connected from this used control full-scale amplitudes video signals. Compensation Pin. Connect capacitor from COMP VAA. PAL/NTSC Composite Video Output. Full-Scale Output 180IRE (1286 NTSC 1300 PAL. RED/S-VHS Analog Output. GREEN/S-VHS Analog Output. BLUE/Composite/U Analog Output. Port Serial Interface Clock Input. Port Serial Data Input/Output. Address Input. This signal address. input resets chip timing generator sets ADV7175/ADV7176 into default mode. This NTSC operation, Timing Slave Mode 8-bit operation, composite out. Supply. Ground Pin.
CONFIGURATION
SCRESET CLOCK
HSYNC FIELD/VSYNC BLANK SCRESET/RTC
VREF RSET COMP COMPOSITE RED/CHROMA/V GREEN/LUMA/Y BLUE/COMPOSITE/U SCLOCK SDATA ALSB RESET
RSET
VREF COMPOSITE BLUE/COMPOSITE/U GREEN/LUMA/Y RED/CHROMA/V COMP SDATA SCLOCK
IDENTIFIER
ADV7175/ADV7176 PQFP
VIEW (Not Scale)
ALSB
HSYNC FIELD/ VSYNC
REV.
BLANK
RESET
ADV7175/ADV7176
(Continued from page
ADV7175/ADV7176 also supports both NTSC square pixel mode slave mode. video encoder accepts 8-bit parallel pixel data stream CCIR-656 format 16-bit parallel data stream. This 4:2:2 data stream interpolated into 4:4:4 component video (YUV). video interpolated times pixel rate. color-difference components (UV) quadrature modulated using subcarrier frequency generated on-chip synthesizer (also running times pixel rate). times pixel rate sampling allows more accurate generation subcarrier because frequency phase errors reduced higher sampling rate. ADV7175/ADV7176 also offers option output information directly. luminance chrominance components digitally combined resulting composite signal output 10-bit DAC. Three additional 10-/8-bit DACs provided output S-VHS Video bits), Video bits). output video frames synchronized with incoming data timing reference codes. Optionally encoder accepts (and generate) HSYNC, VSYNC FIELD timing signals. These timing signals adjusted change pulse width position while part master mode. encoder requires single times pixel rate MHz) clock standard operation. Alternatively encoder requires 24.54 clock NTSC 29.5 clock square pixel mode operation. internal clocks generated on-chip. ADV7175/ADV7176 modes over wire serial bidirectional port (I2C Compatible) with slave addresses. Additionally, ADV7175/ADV7176 allows subcarrier phase lock with external video source color generator on-board. Functionally ADV7175 ADV7176 same with exception that ADV7175 output Macrovision (Revision 6.1/7.x) anticopy algorithm. ADV7175/ADV7176 fabricated CMOS process. monolithic CMOS construction ensures greater functionality with power dissipation. ADV7175/ADV7176 packaged 44-pin thermally enhanced PQFP package (patent pending).
PASSBAND (MHz)
ADV7175/ADV7176 protected U.S. Patent Numbers 5,343,196 5,442,355 other intellectual property rights.
DATA PATH DESCRIPTION
NTSC modes, YCrCb 4:2:2 data input CCIR-656 compatible pixel port 13.5 data rate. pixel data de-multiplexed form three data paths. range 235, have range 112. ADV7175/ADV7176 supports NTSC (with without Pedestal) standards. appropriate SYNC, BLANK burst levels added YCrCb data. Macrovision antitaping (ADV7175 only) close-captioning levels also added resultant data interpolated rate MHz. interpolated data filtered scaled three digital filters. signals modulated appropriate subcarrier sine/cosine phases added together make chrominance signal. luma signal delayed luma cycles (each cycle with respect chroma signal. luma chroma signals then added together make composite video signal. edges slew rate limited. YCrCb data also used generate data with appropriate SYNC BLANK levels. data sychronization with composite video output. Alternatively analog data generated instead RGB. four 10-bit DACs used output: 10-bit composite video 8-bit video. 10-bit composite video 8-bit video. 10-bit composite video signals 10-bit LUMA CHROMA (Y/C) signals. Alternatively, each individually powered required. possible video outputs illustrated Appendix
INTERNAL FILTER RESPONSE
filter supports several different frequency responses including 4.5/5.0 low-pass PAL/NTSC subcarrier notch responses. filters have 0.6/1 low-pass response. These filter characteristics illustrated Figures
STOPBAND (MHz) 3.57 4.43 STOPBAND ATTENUATION (dB)
FILTER SELECTION NTSC NTSC NTSC/PAL NTSC MR04 MR03
PASSBAND RIPPLE (dB) 0.026 0.098 0.085 0.107 0.150 0.054 0.106
F3dB 5.65
>51.3 >27.6 >29.3 >50.3
Figure Filter Specifications
PASSBAND (MHz) PASSBAND RIPPLE (dB) 0.085 0.04 STOPBAND (MHz) STOPBAND ATTENUATION (dB) ATTENUATION 1.3MHz (dB) 0.02 F3dB 2.05 2.45
FILTER SELECTION NTSC
Figure Filter Specifications
REV.
ADV7175/ADV7176
TYPE TYPE
AMPLITUDE
TYPE
AMPLITUDE
TYPE
-100
-100
-120 FREQUENCY
-120 FREQUENCY
Figure NTSC Low-Pass Filter
Figure Low-Pass Filter
AMPLITUDE
AMPLITUDE
-100
-100
-120 FREQUENCY
-120 FREQUENCY
Figure NTSC Notch Filter
Figure Notch Filter
AMPLITUDE
-100
-120 FREQUENCY
Figure NTSC/PAL Extended Mode Filter
REV.
ADV7175/ADV7176
AMPLITUDE
AMPLITUDE
-100 FREQUENCY
-100 FREQUENCY
Figure NTSC Filter
COLOR GENERATION
Figure Filter
ADV7175/ADV7176 configured generate amplitude, saturation (75/7.5/75/7.5) NTSC amplitude, 100% saturation (100/0/75/0) color bars. These enabled setting MR17 Mode Register Logic "1."
SQUARE PIXEL MODE
CLOCK COMPOSITE VIDEO e.g. CABLE VIDEO DECODER (e.g.SAA7110) MPEG DECODER SCRESET/RTC GREEN/LUMA/Y P7-P0 RED/CHROMA/V BLUE/COMPOSITE/U HSYNC FIELD/VSYNC COMPOSITE
ADV7175/ADV7176 used operate square pixel mode. NTSC operation input clock 24.54 required. Alternatively, operation, input clock 29.5 required. internal filters scale accordingly square pixel mode operation.
COLOR SIGNAL CONTROL
ADV7175/ADV7176
Figure Connections
PIXEL TIMING DESCRIPTION
color information switched video output using MR24 Mode Register
BURST SIGNAL CONTROL
ADV7175/ADV7176 operate either 8-bit 16-bit YCrCb Mode.
8-Bit YCrCb Mode
burst information switched video output using MR25 Mode Register
NTSC PEDESTAL CONTROL
pedestal information both even fields controlled line line basis using NTSC Pedestal Control Registers. This allows pedestals controlled during vertical blanking interval (Lines 25).
SUBCARRIER RESET
This default mode accepts multiplexed YCrCb inputs through P7-P0 pixel inputs. inputs follow sequence Cb0, Cr0, Cb1, etc. data input rising clock edge.
16-Bit YCrCb Mode
Together with SCRESET/RTC Bits MR22 MR21 Mode Register ADV7175/ADV7176 used subcarrier reset mode. subcarrier will reset field start following field when high transition occurs this input pin.
REAL TIME CONTROL
This mode accepts inputs through P7-P0 pixel inputs multiplexed CrCb inputs through P15-P8 pixel inputs. data loaded every second rising clock edge CLOCK. inputs follow sequence Cb0, Cr0, Cb1, etc.
VIDEO TIMING DESCRIPTION
Together with SCRESET/RTC Bits MR22 MR21 Mode Register ADV7175/ADV7176 used lock external video source. real time control mode allows ADV7175/ADV7176 automatically alter subcarrier frequency compensate line length variation. When part connected device that outputs digital datastream format (such Phillips SAA7110 video decoder), part will automatically change compensated subcarrier frequency line line basis. This digital datastream bits wide subcarrier contained bits Each clock cycles long.
ADV7175/ADV7176 intended interface shelf MPEG1 MPEG2 Decoders. consequence ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data CCIR-656 pixel port several video timing modes operation that allow configured either system master video timing generator slave system video timing generator. ADV7175/ADV7176 generates required horizontal vertical timing periods levels analog video outputs. ADV7175/ADV7176 calculates width placement analog sync pulses, blanking levels color burst envelopes. Color bursts disabled appropriate lines serration equalization pulses inserted where required.
(Continued page
REV.
ADV7175/ADV7176
Mode (CCIR-656): Slave Option. (Timing Register
ADV7175/ADV7176 controlled (Start Active Video) (End Active Video) time codes pixel data. timing information transmitted using 4-byte synchronization pattern. synchronization pattern sent immediately before after each line during active picture retrace. Mode illustrated Figure HSYNC, FIELD/VSYNC BLANK used) pins should tied high this mode.
ANALOG VIDEO
CODE INPUT PIXELS ANCILLARY DATA (HANC) PIXELS PIXELS SYSTEM ACTIVE VIDEO LINE PIXELS
CODE
PIXELS NTSC SYSTEM
PIXELS 1440 PIXELS PIXELS 1440 PIXELS START ACTIVE VIDEO LINE
Figure Timing Mode (Slave Mode)
Mode (CCIR-656): Master Option. (Timing Register ADV7175/ADV7176 generates signals required (start active video) (end active video) time codes CCIR656 standard. output HSYNC pin, output BLANK output FIELD/VSYNC pin. Mode illustrated Figure (NTSC) Figure (PAL). transitions relative video waveform illustrated Figure
DISPLAY VERTICAL BLANK
DISPLAY
EVEN FIELD
FIELD
DISPLAY VERTICAL BLANK
DISPLAY
FIELD
EVEN FIELD
Figure Timing Mode (NTSC Master Mode)
REV.
ADV7175/ADV7176
DISPLAY VERTICAL BLANK DISPLAY
EVEN FIELD
FIELD
DISPLAY VERTICAL BLANK
DISPLAY
FIELD EVEN FIELD
Figure Timing Mode (PAL Master Mode)
ANALOG VIDEO
Figure Timing Mode Data Transitions (Master Mode)
-10-
REV.
ADV7175/ADV7176
Mode Slave Option. HSYNC, BLANK, FIELD. (Timing Register this mode ADV7175/ADV7176 accepts horizontal SYNC Odd/Even FIELD signals. transition FIELD input when HSYNC indicates frame, i.e., vertical retrace. BLANK signal optional. When BLANK input disabled ADV7175/ADV7176 automatically blanks normally blank lines CCIR-624. Mode illustrated Figure (NTSC) Figure (PAL).
DISPLAY
VERTICAL BLANK
DISPLAY
HSYNC BLANK FIELD
EVEN FIELD
FIELD
DISPLAY VERTICAL BLANK
DISPLAY
HSYNC
BLANK
FIELD
FIELD
EVEN FIELD
Figure Timing Mode (NTSC)
DISPLAY
VERTICAL BLANK
DISPLAY
HSYNC BLANK FIELD
EVEN FIELD
FIELD
DISPLAY
DISPLAY VERTICAL BLANK
HSYNC BLANK FIELD
FIELD
EVEN FIELD
Figure Timing Mode (PAL)
REV.
-11-
ADV7175/ADV7176
Mode Master Option. HSYNC, BLANK, FIELD. (Timing Register this mode ADV7175/ADV7176 generate horizontal SYNC Odd/Even FIELD signals. transition FIELD input when HSYNC indicates frame i.e., vertical retrace. BLANK signal optional. When BLANK input disabled ADV7175/ADV7176 automatically blanks normally blank lines CCIR-624. Pixel data latched rising clock edge following timing signal transitions. Mode illustrated Figure (NTSC) Figure (PAL). Figure illustrates HSYNC, BLANK FIELD even field transition relative pixel data.
HSYNC
FIELD
CLOCK/2 NTSC CLOCK/2 BLANK
PIXEL DATA
CLOCK/2 NTSC CLOCK/2
Figure Timing Mode Odd/Even Field Transitions
Mode Slave Option. HSYNC, VSYNC, BLANK. (Timing Register this mode ADV7175/ADV7176 accepts horizontal vertical SYNC signals. coincident transition both HSYNC VSYNC inputs indicates start field. VSYNC transition when HSYNC high indicates start even field. BLANK signal optional. When BLANK input disabled, ADV7175/ADV7176 automatically blanks normally blank lines CCIR-624. Mode illustrated Figure (NTSC) Figure (PAL).
DISPLAY
VERTICAL BLANK
DISPLAY
HSYNC BLANK VSYNC
EVEN FIELD
FIELD
DISPLAY
DISPLAY VERTICAL BLANK
HSYNC
BLANK VSYNC
FIELD
EVEN FIELD
Figure Timing Mode (NTSC)
-12-
REV.
ADV7175/ADV7176
DISPLAY VERTICAL BLANK DISPLAY
HSYNC BLANK VSYNC
EVEN FIELD
FIELD
DISPLAY
DISPLAY VERTICAL BLANK
HSYNC BLANK VSYNC
FIELD
EVEN FIELD
Figure Timing Mode (PAL)
Mode Master Option. HSYNC, VSYNC, BLANK. (Timing Register this mode ADV7175/ADV7176 generate horizontal vertical SYNC signals. coincident transition both HSYNC VSYNC inputs indicates start field. VSYNC transition when HSYNC high indicates start even field. BLANK signal optional. When BLANK input disabled ADV7175/ADV7176 automatically blanks normally blank lines CCIR-624. Mode illustrated Figure (NTSC) Figure (PAL). Figure illustrates HSYNC, BLANK VSYNC even field transition relative pixel data. Figure illustrates HSYNC, BLANK VSYNC even field transition relative pixel data.
HSYNC
VSYNC
BLANK
CLOCK/2 NTSC CLOCK/2
PIXEL DATA 132* CLOCK/2 NTSC CLOCK/2 LINE LINE
Figure Timing Mode Even-to-Odd Field Transition
REV.
-13-
ADV7175/ADV7176
HSYNC
VSYNC CLOCK/2 NTSC CLOCK/2 BLANK CLOCK/2 NTSC CLOCK/2
PIXEL DATA CLOCK/2 NTSC CLOCK/2 LINE LINE
Figure Timing Mode Odd-to-Even Field Transition
Mode Master/Slave Option. HSYNC, BLANK, FIELD. (Timing Register this mode ADV7175/ADV7176 accepts generates Horizontal SYNC odd/even FIELD signals. transition FIELD input when HSYNC high indicates frame i.e., vertical retrace. BLANK signal optional. When BLANK input disabled ADV7175/ADV7176 automatically blanks normally blank lines CCIR-624. Mode illustrated Figure (NTSC) Figure (PAL).
DISPLAY VERTICAL BLANK DISPLAY
HSYNC BLANK FIELD
EVEN FIELD
FIELD
DISPLAY VERTICAL BLANK
DISPLAY
HSYNC
BLANK
FIELD
FIELD
EVEN FIELD
Figure Timing Mode (NTSC)
-14-
REV.
ADV7175/ADV7176
DISPLAY VERTICAL BLANK DISPLAY
HSYNC BLANK FIELD
EVEN FIELD
FIELD
DISPLAY
DISPLAY VERTICAL BLANK
HSYNC BLANK FIELD
EVEN FIELD
FIELD
Figure Timing Mode (PAL)
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addition ADV7175/ADV7176 supports NTSC square pixel operation slave mode. part requires input pixel clock 24.54 NTSC input pixel clock 29.5 PAL. internal horizontal line counters place various video waveform sections correct location clock frequencies. ADV7175/ADV7176 distinct master slave timing configurations. These divided into timing modes which operate discrete clock frequency MHz). Timing control established with bidirectional SYNC, BLANK FIELD/VSYNC pins. Timing Mode Register also used vary timing pulse widths where they occur relation each other.
OUTPUT VIDEO TIMING
PAL-Interlaced: Scan lines 1-6, 311-318 624-625 always blanked vertical sync pulses included Fields Scan lines 1-5, 311-319 624-625 always blanked vertical sync pulses included Fields remaining scan lines vertical interval also blanked used close captioning data. Burst disabled lines 1-6, 311-318 623-625 Fields Burst disabled lines 1-5, 311-319 623-625 Fields PAL-Noninterlaced: Scan lines 311-312 always blanked vertical sync pulses included. remaining scan lines vertical interval also blanked used close captioning data. Burst disabled lines 1-5, 310-312.
POWER-ON RESET
video timing generator generates appropriate SYNC, BLANK BURST sequence that controls output analog waveforms. These sequences summarized below. slave modes following sequences synchronized with input timing control signals. master modes timing generator free runs generates following sequences addition output timing control signals. NTSC-Interlaced: Scan lines 264-272 always blanked vertical sync pulses included. Scan lines 525, 10-21 262, 263, 273-284 also blanked used close captioning data. Burst disabled lines 1-6, 261- 523-525. NTSC-Noninterlaced: Scan lines always blanked vertical sync pulses included. Scan lines 10-21 also blanked used close captioning data. Burst disabled lines 1-6, 261-262.
After power-up, necessary execute reset operation. reset occurs falling edge high transition RESET pin. This initializes pixel port such that pixel inputs P7-P0 selected. After reset, ADV7175/ADV7176 automatically operate NTSC mode. Subcarrier frequency code 21F07C16 loaded into subcarrier frequency registers. other registers, with exception Mode Register 00H. bits Mode Register Logic Level except MR02. MR02 Mode Register Logic "1." This enables pedestal.
REV.
-15-
ADV7175/ADV7176
PORT DESCRIPTION
ADV7175 ADV7176 support wire serial (I2C compatible) microprocessor driving multiple peripherals. inputs serial data (SDATA) serial clock (SCLOCK) carry information between device connected bus. Each slave device recognized unique address. ADV7175 ADV7176 each have four possible slave addresses both read write operations. These unique addresses each device illustrated Figure Figure sets either read write operation. Logic Level corresponds read operation while Logic Level corresponds write operation. setting ALSB ADV7175/ADV7176 Logic Level Logic Level "1."
ADDRESS CONTROL ALSB READ/WRITE CONTROL WRITE READ
will write information peripheral. Logic first byte means that master will read information from peripheral. ADV7175/ADV7176 acts standard slave device bus. data SDATA bits long supporting 7-bit addresses plus bit. ADV7175 subaddresses ADV7176 subaddresses enable access internal registers. therefore, interprets first byte device address second byte starting subaddress. subaddresses auto increment allowing data written from starting subaddress. data transfer always terminated stop condition. user also access unique subaddress register basis without having update registers. There exception. Subcarrier Frequency Registers should updated sequence, starting with Subcarrier Frequency Register auto increment function should then used increment access subcarrier frequency registers subcarrier frequency registers should accessed independently. Stop start conditions detected stage during data transfer. these conditions asserted sequence with normal read write operations, then these cause immediate jump idle condition. During given SCLOCK high period user should only issue start condition, stop condition single stop condition followed single start condition. invalid subaddress issued user, ADV7175/ADV7176 will issue acknowledge will return idle condition. auto-increment mode, user exceeds highest subaddress then following action will taken: Read Mode highest subaddress register contents will continue output until master device issues no-acknowledge. This indicates read. no-acknowledge condition where SDATA line pulled ninth pulse. Write Mode, data invalid byte will loaded into subaddress register, no-acknowledge will issued ADV7175/ADV7176 part will return idle condition. Figure illustrates example data transfer read sequence start stop conditions.
SDATA
ADV7175 Slave Address
ADDRESS CONTROL ALSB READ/WRITE CONTROL WRITE READ
ADV7176 Slave Address
control various devices following protocol must followed. First master initiates data transfer establishing start condition, defined high transition SDATA while SCLOCK remains high. This indicates that address/data stream will follow. peripherals respond start condition shift next eight bits (7-bit address bit). bits transferred from down LSB. peripheral that recognizes transmitted address responds pulling data line during ninth clock pulse. This known acknowledge bit. other devices withdraw from this point maintain idle condition. idle condition where device monitors SDATA SCLOCK lines waiting Start condition correct transmitted address. determines direction data. Logic first byte means that master
WRITE SEQUENCE SLAVE ADDR A(S) READ SEQUENCE SLAVE ADDR START STOP A(S) ADDR A(S) ADDR DATA
SCLOCK
DATA
STOP
START ADDR SUBADDRESS
Figure Data Transfer
Figure shows write read sequences.
A(S) DATA A(S)
A(S)
SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M)
A(S) ACKNOWLEDGE SLAVE A(M) ACKNOWLEDGE MASTER
A(S) NO-ACKNOWLEDGE SLAVE A(M) NO-ACKNOWLEDGE MASTER
Figure Write Read Sequences
-16-
REV.
ADV7175/ADV7176
SR7-SR5 (000) ZERO SHOULD WRITTEN THESE BITS SUBADDRESS REGISTER MODE REGISTER MODE REGISTER CARRIER FREQ REGISTER CARRIER FREQ REGISTER CARRIER FREQ REGISTER CARRIER FREQ REGISTER CARRIER PHASE REGISTER TIMING MODE REGISTER CLOSED CAPTIONING EXTENDED DATA BYTE CLOSED CAPTIONING EXTENDED DATA BYTE CLOSED CAPTIONING DATA BYTE CLOSED CAPTIONING DATA BYTE TIMING MODE REGISTER MODE REGISTER NTSC PEDESTAL CONTROL (FIELD 1/3) NTSC PEDESTAL CONTROL (FIELD 1/3) NTSC PEDESTAL CONTROL (FIELD 2/4) NTSC PEDESTAL CONTROL (FIELD 2/4) MODE REGISTER MACROVISION REGISTERS (ADV7175 ONLY) MACROVISION REGISTERS (ADV7175 ONLY)
Figure Subaddress Register
REGISTER ACCESSES
Subaddress Register (SR7-SR0)
write read from registers ADV7175/ADV7176 except subaddress register which write only register. subaddress register determines which register next read write operation accesses. communications with part through start with access subaddress register. Then read/write operation performed from/to target address which then increments next address until stop command performed.
REGISTER PROGRAMMING
communications register eight write-only register. After part been accessed over read/write operation selected, subaddress subaddress register determines to/from which register operation takes place. Figure shows various operations under control subaddress register. Zero should always written SR7- SR5.
Register Select (SR4-SR0):
following section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers NTSC pedestal control registers terms configuration.
These bits setup point required starting address.
MODE REGISTER (MR07-MR00) (Address (SR4-SR0) 00H)
Mode Register 8-bit wide register. Figure shows various operations under control Mode Register This register read from well written
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
OUTPUT SELECT MR06 OUTPUT RGB/YUV OUTPUT
FILTER SELECT MR04 MR03 PASS FILTER NOTCH FILTER EXTENDED MODE PASS FILTER
OUTPUT VIDEO STANDARD SELECTION MR01 MR00 NTSC RESERVED
MR07 ZERO SHOULD WRITTEN THIS
SYNC MR05 DISABLE ENABLE
PEDESTAL CONTROL MR02 PEDESTAL PEDESTAL
Figure Mode Register
REV.
-17-
ADV7175/ADV7176
MODE REGISTER (MR07-MR00) DESCRIPTION Encode Mode Control (MR01-MR00): MODE REGISTER (MR17-MR10) (Address (SR4-SR0) 01H)
These bits used encode mode. ADV7175/ ADV7176 output NTSC, standard video.
Pedestal Control (MR02)
Mode Register 8-bit wide register. Figure shows various operations under control Mode Register This register read from well written
MODE REGISTER (MR17-MR10) DESCRIPTION Interlaced Mode Control (MR10):
This specifies whether pedestal generated NTSC composite video signal. This invalid ADV7175/ADV7176 configured mode.
Luminance Filter Control (MR04-MR03)
This used setup output interlaced non-interlaced mode. This mode only relevant when part composite video mode.
Closed Captioning Field Control (MR12-MR11)
These bits used selecting between filter luminance signal. These filters automatically cutoff frequency low-pass filters subcarrier frequency notch filter. extended mode filter low-pass filter. filters illustrated Figures
Sync (MR05)
These bits control field that close captioning data displayed close captioning information displayed field, even field both fields.
Control (MR16-MR13)
This used outputs with sync information encoded.
Output Control (MR06)
These bits used power down DACs. This used reduce power consumption ADV7175/ADV7176 DACs required application.
Color Control (MR17)
This specifies part composite video RGB/YUV mode. Please note that RGB/YUV mode main composite signal still available.
This used generate output internal color bar. color configuration 75/75/75/7.5 NTSC 100/0/75/0 PAL.
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
COMPOSITE CONTROL MR16 NORMAL POWER DOWN
GREEN/LUMA CONTROL MR14 NORMAL POWER DOWN
CLOSED CAPTIONING FIELD SELECTION MR12 MR11 DATA FIELD ONLY EVEN FIELD ONLY DATA (BOTH FIELDS) INTERLACE CONTROL MR10 NORMAL POWER DOWN INTERLACED NON-INTERLACED
COLOR CONTROL MR17 DISABLE ENABLE
BLUE/COMPOSITE CONTROL MR15 NORMAL POWER DOWN
RED/CHROMA CONTROL MR13
Figure Mode Register
-18-
REV.
ADV7175/ADV7176
SUBCARRIER FREQUENCY REGISTERS (FSC3-FSC0) (Address (SR4-SR0) 05H-02H) TIMING REGISTER (TR07-TR00) (Address (SR4-SR0) 07H)
These 8-bit wide registers used subcarrier frequency. value these registers calculated using following equation: Subcarrier Frequency Register
FCLK
Timing Register 8-bit wide register. Figure shows various operations under control Timing Register This register read from well written
TIMING REGISTER (TR07-TR00) DESCRIPTION Master/Slave Control (TR00)
i.e.: NTSC Mode, FCLK MHz, FSCF 3.5796 Subcarrier Frequency Register
3.579545
This controls whether ADV7175/ADV7176 master slave mode.
Timing Mode Control (TR02-TR01)
Subcarrier Frequency Register 21F07C16 Figure shows frequency registers.
SUBCARRIER FREQUENCY SUBCARRIER FREQUENCY SUBCARRIER FREQUENCY SUBCARRIER FREQUENCY
FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
These bits control timing mode ADV7175/ADV7176 These modes described Timing Control section data sheet.
BLANK Control (TR03)
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
This controls whether BLANK input used when part slave mode.
Luma Delay Control (TR05-TR04)
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10
FSC9
FSC8
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
These bits control addition luminance delay. Each represents delay
Pixel Port Select (TR06)
Figure Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER (FP7-FP0): (Address (SR4-SR0) 06H)
This used pixel port accept 8-bit 16-bit data. 8-bit input selected data will Pins P7-P0.
Timing Register Reset (TR07)
This 8-bit wide register used subcarrier phase. Each represents 1.41°.
Toggling TR07 from high again resets internal timing counters. This should toggled after setting timing mode.
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
TIMING REGISTER RESET TR07
BLACK INPUT CONTROL TR03 ENABLE DISABLE TIMING MODE SELECTION TR02 TR01 MODE MODE MODE MODE
MASTER/SLAVE CONTROL TR00 SLAVE TIMING MASTER TIMING
PIXEL PORT CONTROL TR06 8-BIT 16-BIT
LUMA DELAY TR05 TR04 DELAY 74ns DELAY 148ns DELAY 222ns DELAY
Figure Timing Register
REV.
-19-
ADV7175/ADV7176
CLOSED CAPTIONING EXTENDED DATA REGISTERS (CED15-CED00) (Address (SR4-SR0) 09-08H)
HSYNC VSYNC/FIELD Delay Control (TR13-TR12) These bits adjust position HSYNC output relative FIELD/VSYNC output. HSYNC FIELD Delay Control (TR15-TR14) When ADV7175/ADV7176 Timing Mode these bits adjust position HSYNC output relative FIELD output rising edge. VSYNC Width (TR15-TR14) When ADV7175/ADV7176 Timing Mode these bits adjust VSYNC pulse width. HSYNC Pixel Data Adjust (TR17-TR16) This enables HSYNC adjusted with respect pixel data. This allows components swapped. This adjustment available both master slave timing modes.
MODE REGISTER (MR27-MR20) (Address (SR4-SR0) 0DH)
These 8-bit wide registers used closed captioning extended data bytes. Figure shows high bytes registers.
BYTE
CED15 CED14 CED13 CED12 CED11 CED10 CED7 CED6 CED5 CED4 CED3 CED2
CED9
CED8
BYTE
CED1
CED0
Figure Closed Captioning Extended Data Register
CLOSED CAPTIONING DATA REGISTERS (CCD15-CCD00) (Subaddress (SR4-SR0) 0B-0AH)
These 8-bit wide registers used closed captioning data bytes. Figure shows high bytes registers.
BYTE
Mode Register 8-bit wide register.
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD8
Figure shows various operations under control Mode Register This register read from well written
MODE REGISTER (MR27-MR20) DESCRIPTION Square Pixel Mode Control (MR20)
BYTE
CCD0
Figure Closed Captioning Data Register
TIMING REGISTER (TR17-TR10) (Address (SR4-SR0) 0CH)
This used setup square pixel mode. This available slave mode only. NTSC, 24.54 clock must supplied. PAL, 29.5 clock must supplied.
Genlock Control (MR22-MR21)
Timing Register 8-bit wide register. Figure shows various operations under control Timing Register This register read from well written This register used adjust width position master mode timing signals.
TIMING REGISTER (TR17-TR10) DESCRIPTION HSYNC Width (TR11-TR10)
These bits adjust HSYNC pulse width.
These bits control genlock feature ADV7175/ ADV7176 Setting MR21 Logic configures SCRESET/RTC input. Setting MR22 logic level configures SCRESET/RTC subcarrier reset input. Therefore, subcarrier will reset Field following high transition SCRESET/RTC pin. Setting MR22 Logic Level configures SCRESET/RTC real time control input.
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC PIXEL DATA ADJUSTMENT TR17 TR16 TPCLK TPCLK TPCLK TPCLK
HSYNC FIELD RISING EDGE DELAY (MODE ONLY) TR15 TR14 32µs
HSYNC FIELD/VSYNC DELAY TR13 TR12 TPCLK TPCLK TPCLK TPCLK
HSYNC WIDTH TR11 TR10 TPCLK TPCLK TPCLK TPCLK
VSYNC WIDTH (MODE ONLY) TR15 TR14 TPCLK TPCLK TPCLK TPCLK
TIMING MODE (MASTER/PAL)
LINE HSYNC FIELD/VSYNC LINE LINE
Figure Timing Register
-20-
REV.
ADV7175/ADV7176
MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 RGB/YUV CONTROL MR26 OUTPUT OUTPUT CHROMINANCE CONTROL MR24 ENABLE COLOR DISABLE COLOR
GENLOCK SELECTION MR22 MR21 DISABLE GENLOCK ENABLE SUBCARRIER RESET ENABLE SQUARE PIXEL CONTROL MR20 CCIR624 OUTPUT CCIR601 OUTPUT DISABLE ENABLE
LOWER POWER MODE MR27 DISABLE ENABLE MR25
BURST CONTROL ENABLE BURST DISABLE BURST
CCIR624/CCIR601 CONTROL MR23
Figure Mode Register
CCIR624/CCIR601 Control (MR23)
LINE LINE LINE LINE LINE LINE LINE LINE FIELD
This switches video output between CCIR624 CCIR601 video standard.
Chrominance Control (MR24)
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
LINE LINE LINE LINE LINE LINE LINE LINE FIELD
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10
PCO9
PCO8
This enables color information switched video output.
Burst Control (MR25)
FIELD
LINE LINE LINE LINE LINE LINE LINE LINE
PCE7
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
PCE0
This enables burst information switched video output.
RGB/YUV Control (MR26)
LINE LINE LINE LINE LINE LINE LINE LINE FIELD
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
PCE8
This enables output from DACs output video standard. MR06 Mode Register must Logic Level before MR26 set.
Lower Power Control (MR27)
Figure Pedestal Control Registers
MODE REGISTER (MR37-30) (Address (SR4-SR0) 12H)
This enables lower power mode ADV7175/ ADV7176.
NTSC PEDESTAL CONTROL REGISTERS (PCE15-0, PCO15-0) (Subaddress (SR4-SR0) 11-0EH)
Mode Register 8-bit wide register. Figure shows various operations under control Mode Register Bits MR36-MR30 reserved Logic should written them.
MODE REGISTER (MR37-MR30) DESCRIPTION Switching Control (MR37)
These 8-bit wide registers used NTSC pedestal line line basis vertical blanking interval both even fields. Figure shows four control registers. Logic bits these registers effect turning pedestal equivalent line.
This used switch luminance signal onto composite DAC. Figure illustrates outputs they switch when Logic "1".
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR36-MR30 (RESERVED) ZERO SHOULD WRITTEN THESE BITS
OUTPUT SWITCHING MR37 COMPOSITE BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE
Figure Mode Register
REV.
-21-
ADV7175/ADV7176
APPENDIX BOARD DESIGN LAYOUT CONSIDERATIONS
ADV7175/ADV7176 highly integrated circuit containing both precision analog high speed digital circuitry. been designed minimize interference effects integrity analog circuitry high speed digital circuitry. imperative that these same design layout techniques applied system level design such that high speed, accurate performance achieved. "Recommended Analog Circuit Layout" shows analog interface between device monitor. layout should optimized lowest noise ADV7175/ADV7176 power ground lines shielding digital inputs providing good decoupling. lead length between groups pins should minimized minimize inductive ringing.
Ground Planes
operation, reduce lead inductance. Best performance obtained with ceramic capacitor decoupling. Each group pins ADV7175/ADV7176 must have least decoupling capacitor GND. These capacitors should placed close possible device. important note that while ADV7175/ADV7176 contains circuitry reject power supply noise, this rejection decreases with frequency. high frequency switching power supply used, designer should close attention reducing power supply noise consider using three terminal voltage regulator supplying power analog power plane.
Digital Signal Interconnect
ground plane should encompass ADV7175/ADV7176 ground pins, voltage reference circuitry, power supply bypass circuitry ADV7175/ADV7176, analog output traces, digital signal traces leading ADV7175/ ADV7176. ground plane board's common ground plane.
Power Planes
digital inputs ADV7175/ADV7176 should isolated much possible from analog outputs other analog circuitry. Also, these input signals should overlay analog power plane. high clock rates involved, long clock lines ADV7175/ADV7176 should avoided reduce noise pickup. active termination resistors digital inputs should connected regular power plane (VCC), analog power plane.
Analog Signal Interconnect
ADV7175/ADV7176 associated analog circuitry should have power plane, referred analog power plane (VAA). This power plane should connected regular power plane (VCC) single point through ferrite bead. This bead should located within three inches ADV7175/ADV7176. power plane should provide power digital logic board, analog power plane should provide power ADV7175/ADV7176 power pins voltage reference circuitry. Plane-to-plane noise coupling reduced ensuring that portions regular power ground planes overlay portions analog power plane, unless they arranged such that plane-to-plane noise common mode.
Supply Decoupling
ADV7175/ADV7176 should located close possible output connectors minimize noise pickup reflections impedance mismatch. video output signals should overlay ground plane, analog power plane, maximize high frequency power supply rejection. Digital inputs, especially pixel data inputs clocking signals should never overlay analog signal circuitry should kept away possible. best performance, outputs should each have load resistor connected GND. These resistors should placed close possible ADV7175/ADV7176 minimize reflections. ADV7175/ADV7176 should have inputs left floating. inputs that required should tied ground.
optimum performance, bypass capacitors should installed using shortest leads possible, consistent with reliable
-22-
REV.
ADV7175/ADV7176
POWER SUPPLY DECOUPLING EACH POWER SUPPLY GROUP 0.1µF 0.01µF (VAA) (VAA) 0.1µF (VAA) 0.1µF COMP VREF 38-42, 2-9, 12-14 P15-P0 GREEN/ LUMA/ 10µF 33µF (FERRITE BEAD) (VCC)
ADV7175 ADV7176
RED/ CHROMA/ BLUE/ COMPOSITE/
VIDEO
"UNUSED INPUTS SHOULD GROUNDED"
SCRESET/RTC HSYNC FIELD/VSYNC BLANK
COMPOSITE
(VCC)
(VCC)
RESET 27MHz CLOCK (SAME CLOCK USED MPEG2 DECODER) CLOCK (VAA) ALSB
SCLOCK SDATA RSET
Figure Recommended Analog Circuit Layout
circuit below used generate 13.5 waveform using clock HSYNC pulse. This waveform guaranteed produce 13.5 clock synchronization with clock. This 13.5 clock used 13.5 clock required MPEG decoder. This will guarantee that pixel information input ADV7175/ADV7176 correct sequence.
CLOCK
13.5MHz
HSYNC
Figure Circuit Generate 13.5
REV.
-23-
ADV7175/ADV7176
APPENDIX CLOSED CAPTIONING
ADV7175/ADV7176 supports closed captioning conforming standard television synchronizing waveform color transmission. Closed captioning transmitted during blanked active line time line fields. Closed captioning consists 7-cycle sinusoidal burst that frequency phase locked caption data. After clock signal, blanking level held data bits followed Logic Level start bit. Sixteen bits data follow start bit. These consist 8-bit bytes. data these bytes stored closed captioning data registers ADV7175/ADV7176 also supports extended closed captioning operation which active during even fields encoded scan line 284. data this operation stored closed captioning extended data registers clock run-in signals timing support closed captioning lines generated automatically ADV7175/ ADV7176. pixels inputs ignored during lines 282. Code Federal Regulations (CFR) section 15.119 EIA208 describe closed captioning information lines 284.
13.407µs
D6-D0
D6-D0
REFERENCE COLOR BURST CYCLES) FREQUENCY 3.579545MHz AMPLITUDE 10.003µs 17.379µs 33.764µs
Figure Closed Captioning Waveform (NTSC)
-24-
REV.
ADV7175/ADV7176
APPENDIX NTSC WAVEFORMS (With Pedestal)
130.8 PEAK COMPOSITE 1268.1mV
WHITE
1048.4mV
714.2mV BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV
Figure NTSC Composite Video Levels
WHITE
1048.4mV
714.2mV BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV
Figure NTSC Luma Video Levels
1067.7mV 835mV (pk-pk)
PEAK CHROMA
286mV (pk-pk) 650mV
BLANK/BLACK LEVEL
232.2mV
PEAK CHROMA
Figure NTSC Chroma Video Levels
WHITE
1052.2mV
720.8mV
BLACK LEVEL BLANK LEVEL SYNC LEVEL
387.5mV 331.4mV 45.9mV
Figure NTSC Video Levels
REV.
-25-
ADV7175/ADV7176
NTSC WAVEFORMS (Without Pedestal)
130.8 PEAK COMPOSITE 1289.8mV
WHITE
1052.2mV
714.2mV BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV
Figure NTSC Composite Video Levels
WHITE
1052.2mV
714.2mV
BLANK /BLACK LEVEL SYNC LEVEL
338mV 52.1mV
Figure NTSC Luma Video Levels
1101.6mV 903.2mV (pk-pk)
PEAK CHROMA
307mV (pk-pk) 650mV
BLANK/BLACK LEVEL
198.4mV
PEAK CHROMA
Figure NTSC Chroma Video Levels
WHITE
1052.2mV
715.7mV
BLANK/BLACK LEVEL SYNC LEVEL
336.5mV 51mV
Figure NTSC Video Levels
-26-
REV.
ADV7175/ADV7176
WAVEFORMS
1284.2mV PEAK COMPOSITE
1047.1mV
WHITE
696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL
Figure Composite Video Levels
1047mV
WHITE
696.4mV
350.7mV 50.8mV
BLANK/BLACK LEVEL SYNC LEVEL
Figure Luma Video Levels
1092.5mV 885mV (pk-pk)
PEAK CHROMA
300mV (pk-pk) 650mV
BLANK/BLACK LEVEL
207.5mV
PEAK CHROMA
Figure Chroma Video Levels
1050.2mV
WHITE
698.4mV
351.8mV 51mV
BLANK /BLACK LEVEL SYNC LEVEL
Figure Video Levels
REV.
-27-
ADV7175/ADV7176
APPENDIX REGISTER VALUES
ADV7175/ADV7176 registers depending user standard required. following examples give various register formats several video standards. each case output composite with DACs powered with BLANK input control disabled. Additionally, burst color information enabled output internal color generator switched off. examples shown timing mode Mode slave format. TR02-TR00 timing register control timing modes. detailed explanation each command registers, please turn register programming section data sheet. TR07 should toggled after setting timing mode. Timing Register provides additional control over position duration timing signals. examples this register programmed default mode.
NTSC
Mode Register Mode Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Phase Register Timing Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Timing Register Mode Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Mode Register
Mode Register Mode Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Phase Register Timing Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Timing Register Mode Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Mode Register
Mode Register Mode Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Phase Register Timing Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Timing Register Mode Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Mode Register
Mode Register Mode Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Frequency Register Subcarrier Phase Register Timing Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Closed Captioning Register Timing Register Mode Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Pedestal Control Register Mode Register
-28-
REV.
ADV7175/ADV7176
APPENDIX OUTPUT FILTER
output filter required composite output ADV7175/ADV7176. following filter used. Plots filter characteristics produced request.
470pF 330pF 56pF 2.7µH 0.7µH
Figure Output Filter
REV.
-29-
ADV7175/ADV7176
APPENDIX OUTPUT WAVEFORMS
Figure 100/75% Color Bars NTSC
Figure 100/75% Color Bars NTSC (Chrominance Only)
-30-
REV.
ADV7175/ADV7176
Figure 100/75% Color Bars NTSC (Luminance Only)
Figure 100/75% Color Bars
REV.
-31-
ADV7175/ADV7176
Figure Differential Phase Gain Measurements (PAL)
Figure Vectorscope Measurements (PAL)
-32-
REV.
ADV7175/ADV7176
Figure Modulated Ramp Measurements (PAL)
REV.
-33-
ADV7175/ADV7176
INDEX
Contents Page GENERAL DESCRIPTION ADV7175/ADV7176 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE DESCRIPTION/PIN CONFIGURATION DATA PATH DESCRIPTION INTERNAL FILTER RESPONSE COLOR GENERATION SQUARE PIXEL MODE COLOR SIGNAL CONTROL BURST SIGNAL CONTROL NTSC PEDESTAL CONTROL SUBCARRIER RESET REAL TIME CONTROL PIXEL TIMING DESCRIPTION VIDEO TIMING DESCRIPTION Timing Mode Timing Mode Timing Mode Timing Mode OUTPUT VIDEO TIMING POWER-ON RESET PORT DESCRIPTION
Contents Page REGISTER ACCESSES REGISTER PROGRAMMING Subaddress Register Mode Register Mode Register Subcarrier Frequency Registers Subcarrier Phase Register Timing Register Closed Captioning Extended Data Registers Closed Captioning Data Registers Timing Register Mode Register NTSC Pedestal Control Registers APPENDIX BOARD DESIGN LAYOUT CONSIDERATIONS APPENDIX CLOSED CAPTIONING APPENDIX VIDEO WAVEFORMS APPENDIX REGISTER VALUES APPENDIX OUTPUT FILTER APPENDIX OUTPUT WAVEFORMS OUTLINE DIMENSIONS
-34-
REV.
ADV7175/ADV7176
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic Quad Flatpack (S-44)
0.548 (13.925) 0.096 (2.44) 0.037 (0.94) 0.025 (0.64) SEATING PLANE VIEW
(PINS DOWN)
0.546 (13.875) 0.398 (10.11) 0.390 (9.91) 0.8°
0.040 (1.02) 0.032 (0.81)
0.040 (1.02) 0.032 (0.81)
0.033 (0.84) 0.029 (0.74)
0.016 (0.41) 0.012 (0.30)
0.083 (2.11) 0.077 (1.96)
REV.
-35-
-36-
C213a-4-
PRINTED U.S.A.
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