Fully Compatible Altera® FLEX® 10KE Family Prototype Your System With

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Fully Compatible Altera® FLEX® 10KE Family Prototype Your System With

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CL10K30E
Fully Compatible Altera® FLEX® 10KE Family Prototype Your System With Altera FPGAs Seamlessly Migrate Production Clear Logic ASIC Engineering, NRE, Test Vector Development Very Fast, Dense Signal Routing Using Vertical Link Interconnect "Gate Array" Option Eliminates Configuration EPROMs
LIBERATOR
CL10KE Product Family Overview
Parameter
Typical Gates (Logic RAM) Maximum System Gates Logic Elements Embedded Array Blocks Total Bits User pins Speed Grades
CL10K30E
30,000 119,000 1,728 24,576 144-pin TQFP 208-pin PQFP 256-pin FBGA 484-pin FBGA
Fabricated Using 0.25 Micron CMOS Process Very Power Consumption (Active Standby) High Density 30,000 Usable Gates 1,728 Logic Elements 24,576 Bits Maximum User Pins
CL10K50E CL10K50S
50,000 199,000 2,880 40,960 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin SBGA 484-pin FBGA
CL10K100E
100,000 257,000 4,992 49,152 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin SBGA 484-pin FBGA
CL10K200E CL10K200S
200,000 513,000 9,984 98,304 240-pin PQFP 356-pin SBGA 484-pin FBGA 600-pin SBGA 672-pin FBGA
10KE
Packages
June 2001
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LIBERATOR CL10K30E (PRELIMINARY)
Description
LIBERATOR CL10KE family offers time-tomarket benefits designing with programmable logic. Simply Altera FLEX 10KE FPGAs prototype verify design. Then, take five minutes submit bitstream using Clear Logic's site! Within eight weeks, your system volume production using compatible Clear Logic devices. LIBERATOR technology frees completely design, prototype, verify your custom logic using Altera FLEX 10KE products. Clear Logic's innovative technology eliminates costs, test vector development, ordering minimums, long lead times. re-simulation re-layout required, because Clear Logic offers architecture that exactly compatible functionality FPGA prototype. Clear Logic's NoFault® test technology ensures complete test coverage through special scan test registers. LIBERATOR family based upon array logic elements. Each logic element contains configurable look-up table combinatorial functions register sequential operations. Eight logic elements group form block. Logic functions signal routing defined Clear Logic's proprietary vertical metal links. Laser-based configuration allows quick-turn prototyping eliminates costs photomasks. Inherent CL10KE family performance benefits include extremely consistent propagation delays, reduced power consumption, improved immunity noise upset events.
Configuration
"Gate Array" configuration mode eliminates need external EPROMs software configuration. LIBERATOR device already factory-configured when shipped. When using device "Gate Array" mode, powers fully configured. this mode, customer selects INIT_DONE option, this will always high.
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LIBERATOR CL10K30E (PRELIMINARY)
Additional Information
further information designing with LIBERATOR family, please refer these documents: AN-01: Requesting First Article. This document provides instructions request first articles submitting bitstream file Clear Logic's site. AN-02: Clear Logic Packaging Guide. This document provides specifications drawings packages used CL10K family other Clear Logic devices. AN-13: LIBERATOR Design. This document describes most efficient path custom logic designs 200K gates using FPGA design techniques going production with Clear Logic. AN-14: CL10K Technology White Paper. This document outlines technologies employed LIBERATOR family. AN-15: LIBERATOR System Configuration. This document contains detailed discussion aspects configuring CL10K-based systems. AN-16: Introduction Clear Logic Verilog Model Generator. Clear Logic Verilog models your FPGA converted design. Learn what help you. AN-17: Clear Logic LIBERATOR Design Models. This document outlines capabilities freedom available Clear Logic Verilog VHDL design models. AN-18: Debugging Designs Using Clear Logic Models. This document shows enhanced troubleshooting capabilities that Clear Logic LIBERATOR Verilog/VHDL design models bring system debugging process.
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LIBERATOR CL10K30E (PRELIMINARY)
Block Diagram
Embedded Array Block (EAB) Element (IOE)
Column Interconnect
Logic Array Logic Building Block (LBB) Logic Element (LE)
Interconnect Logic Array
Local Interconnect
10KE
Logical Memory Array (LMA)
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LIBERATOR CL10K30E (PRELIMINARY)
Configuration
Name
MSEL0 MSEL1 nSTATUS nCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBSY CLKUSR DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
144-Pin TQFP
208-Pin PQFP
256-Pin FBGA
10K30E
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LIBERATOR CL10K30E (PRELIMINARY)
Configuration
Name
TRST Dedicated Inputs Dedicated Clock Pins GCLK1 LOCK DEV_CLRn DEV_OE 124,
144-Pin TQFP
208-Pin PQFP
182,
256-Pin FBGA
VCCINT
E11, F12, 106, 109, H10, J10, J11, 117, 137, 145, L12, M11,
VCCIO
115,
110, 118, 138, 146, 165, 178,
D12, F10, G11, H11, K11, L10,
VCC_CKLK
GNDINT
E12, F11, 123, 124, 129, 130, G10, K10, 103, 104, 127, 129, 151, 152, 171, 185, 188, L11,
GND_CKLK Connect
E16, H16, K14, K16, M14, M16,
Total user Pins
10K30E
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications
Absolute Maximum Ratings
Symbol
IOUT TSTG TAMB Supply Voltage Input Voltage Output Current, Storage Temperature Ambient Temperature Junction Temperature Bias Under Bias Under Bias
Parameter
Conditions
-0.5 -2.0
5.75
Unit
10KE
Recommended Operating Conditions
Symbol
VCCINT
Parameter
Supply Voltage, Internal Logic Input Buffers Commercial Grade Devices Industrial Grade Devices Input Voltage 3.3V Operation Commercial Grade Devices Industrial Grade Devices Input Voltage 2.5V Operation Commercial Grade Devices Industrial Grade Devices Input Voltage Output Voltage Operating Temperature Commercial Temperature Range Industrial Temperature Range Input Signal Rise Time Input Signal Fall Time
Conditions
2.375 2.375
2.625 2.625
Unit
VCCIO
3.00 3.00
3.60 3.60
VCCIO
2.375 2.375 -0.5
2.625 2.625 5.75 VCCIO
10KE
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications cont.
Electrical Characteristics (over operating range)
Symbol
Parameter
Input HIGH Voltage Input Voltage 3.3-V High-Level Output Voltage 3.3-V High-Level CMOS Output Voltage 3.3-V High-Level Output Voltage
Conditions
Lower VCCINT -0.5
Typ[3]
5.75 VCCIO
Unit
VCCIO 3.00 -0.1 VCCIO 3.00 -0.5 VCCIO 3.60 -0.1 VCCIO 2.30
VCCIO-0.2 VCCIO 0.45 VCCIO
10KE
2.5-V High-Level Output Voltage
VCCIO 2.30 VCCIO 2.30
3.3-V Low-Level Output Voltage 3.3-V Low-Level CMOS Output Voltage 3.3-V Low-Level Output Voltage
VCCIO 3.00 VCCIO 3.00 VCCIO 3.60 VCCIO 2.30
2.5-V Low-Level Output Voltage
VCCIO 2.30 VCCIO 2.30
ICC0
Input Leakage Current Output Leakage Current Standby Current
5.3V -0.3V 5.3V -0.3V GND, Load
Capacitance[4]
Symbol
COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VOUT
Unit
10KE
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications
Element Timing Parameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1
Speed:
Speed:
Speed:
Parameter
Register Data Delay Register Control Signal Delay Register Clock Output Delay Combinatorial Delay Register Setup Time Before Clock Register Hold Time After Clock Register Clear Delay Output Buffer Delay Slow Slew Rate off, VCCIO VCCINT Output Buffer Delay Slow Slew Rate off, VCCIO Voltage Output Buffer Delay Slow Slew Rate Output Buffer Disable Delay[6] Output Buffer Disable Delay Slow Slew Rate off, VCCIO VCCINT[6] Output Buffer Disable Delay Slow Slew Rate off, VCCIO Voltage
Unit
tZX2
tZX3 tINREG tIOFD tINCOMB
Output Buffer Disable Delay Slow Slew Rate Input Buffer Register Delay Register Feedback Delay Input Buffer Interconnect Delay
10KE
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications cont.
External Timing Parameters[4]
Symbol
tDRR Speed: Speed: Speed:
Parameter
Register Register Delay Four LEs, Three Interconnects, Four Local Interconnects Setup Time with Global Clock Register Hold time with Global Clock Register Output Data Hold Time After Clock
10.0
13.5
Unit
tINSU tINH tOUTCO
10KE
Logic Element Timing Parameters[5]
Speed: Speed: Speed:
Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
Parameter
Look-up Table Delay Data-in Look-up Table Delay Carry-in Look-up Table Delay Register Feedback Data-in Packed Register Delay Register Enable Delay Carry-in Carry-out Delay Data-in Carry-out Delay Register Feedback Carry-out Delay Cascade Chain Routing Ddelay Register Control Signal Delay Register Clock-to-output Delay Combinatorial Delay Register Setup Time Before Clock Register Hold Time After Clock Register Preset Delay Register Clear Delay Clock High Time Clock Time
Unit
10KE
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications cont.
Interconnect Timing Parameters[5]
Speed: Speed: Speed:
Symbol
tDIN2IOE tDIN2LE tDIN2DATA
Parameter
Delay from Dedicated Input Control Input Delay from Dedicated Input Control Input Delay from Dedicated Input Clock Data
Unit
tDCLK2IOE Delay from Dedicated Clock Clock tDCLK2LE tSAMELAB Delay from Dedicated Clock Clock Delay from Same Delay Driving IOE, IOE, Same Delay from Same Column Delay Driving Column IOE, Different Delay Driving Different Delay from Control Signal Peripheral Dontol Delay from Carry-out Signal Carry-in Signal Different Delay from Cascade-out Signal Cascade-in Signal Different
tSAMEROW
tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY
tLABCASC
10KE
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications cont.
Timing Parameters[5]
Speed: Speed: Speed:
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO
Parameter
Delay from Data Address Combinatorial Input Delay from Data Address Registered Input Delay Combinatorial Input Delay Registered Input Register Clock Delay Register Clock-to-output Delay
Unit
tEABBYPASS Bypass Register Delay tEABSU tEABH tWDSU tWDH tWASU tWAH tEABOUT tEABCH tEABCL Register Setup Time Register Hold Time Address Access Delay Write Pulse Width Data Setup Time Before Falling Edge Write Pulse Data Hold Time After Falling Edge Write Pulse Address Setup Time Before Rising Edge Write Pulse Address Hold After Falling Edge Write Pulse Write Enable Date Output Delay Data-in Date-out Delay Data-out Delay Clock High Time Clock Time
10KE
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications cont.
Timing Parameters[5]
Speed: Speed: Speed:
Symbol
tEABAA
Parameter
Address Access Delay
10.2 10.6
10.2
Unit
tEABRCCOMB Asynchronous Read Cycle Time tEABRCREG Synchronous Read Cycle Time tEABWP Write Pulse Width
tEABWCCOMB Asynchronous Write Cycle Time tEABWCREG Synchronous Write Cycle Time tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWESH Data-in Data-out Delay Clock-to-output Delay Using Output Registers Data/Address Setup Time Using Input Register Data/Address Hold Time Using Input Register Setup When Using Input Register Hold Time When Using Input Register Data Setup Time Falling Edge Write Pulse When Using Input Registers Data Hold Time After Falling Edge Write Pulse When Using Input Registers Address Setup Time Rising Edge Write Pulse When Using Input Registers Address Hold Time After Falling Edge Write Pulse When Using Input Registers Data Output Delay
tEABWDSU
tEABWDH
tEABWASU
tEABWAH tEABWO
10KE
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LIBERATOR CL10K30E (PRELIMINARY)
Electrical Specifications cont.
External Bidirectional Timing Parameters[5]
Speed: Speed: Speed:
Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR
Parameter
Setup Bi-directional Pins with Global Clock Adjacent Registers Hold Time Bi-directional Pins with Global Glock Adjacent Registers Clock-to-output Delay Bi-directional Pins with Global Clock Register Synchronous Output Buffer Disable Delay Synchronous Output Buffer Disable Delay, Slow Slew Rate
Unit
10KE
Test Conditions
VCCIO OUTPUT Includes capacitance
VCCIO OUTPUT Includes capacitance
Input Pulses
3.0V
10KE
Test fixture set-up general testing. Test fixture set-up high testing (tZX#).
Notes Tables
During transitions, inputs undershoot -2.0V overshoot 5.75V periods shorter than 20ns. Otherwise, minimum input voltage -0.5V. Device inputs driven before VCCINT VCCIO powered. Typical values volts ambient temperature Guaranteed tested. Characterized initially, after design changes which affect these parameters. Internal timing delays based characterization, cannot explicitly tested. Internal timing parameters should used performance estimation only. Test Conditions set-up these parameters.
Revision History
Dec. 2000: 2001:
Created document Corrected VCCINT table
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LIBERATOR CL10K30E (PRELIMINARY)
Ordering Information
Part Number
CL10K30ETC144-3 CL10K30ETC144-2 CL10K30ETC144-2X* CL10K30ETC144-1 CL10K30ETC144-1X* CL10K30EQC208-3 CL10K30EQC208-2 CL10K30EQC208-2X* CL10K30EQC208-1 CL10K30EQC208-1X* CL10K30EQI208-2 CL10K30EFC256-3 CL10K30EFC256-2 CL10K30EFC256-2X* CL10K30EFC256-1 CL10K30EFC256-1X* CL10K30EFI256-2 CL10K50EFC484-3 CL10K50EFC484-2 CL10K50EFC484-2X* CL10K50EFC484-1 CL10K50EFC484-1X*
Temperature Range
Commercial
Package Type
144-pin TQFP
Speed
Altera Equivalent
EPF10K30ETC144-3 EPF10K30ETC144-2 EPF10K30ETC144-2X EPF10K30ETC144-1 EPF10K30ETC144-1X EPF10K30EQC208-3 EPF10K30EQC208-2 EPF10K30EQC208-2X EPF10K30EQC208-1 EPF10K30EQC208-1X EPF10K30EQI208-2 EPF10K30EFC256-3 EPF10K30EFC256-2 EPF10K30EFC256-2X EPF10K30EFC256-1 EPF10K30EFC256-1X EPF10K30EFI256-2 EPF10K30EFC484-3 EPF10K30EFC484-2 EPF10K30EFC484-2X EPF10K30EFC484-1 EPF10K30EFC484-1X
10K30E
Commercial
208-pin Plastic
Industrial Commercial 256-pin FBGA
Industrial Commercial 484-pin SBGA CL10K50EFC484
484-pin FBGA offered CL10K30E. CL10K50E. This done locking I/Os MAX+PLUS® recompiling CL10K50E. Test part your board with Altera FLEX® EPF10K50E then submit bitstream Clear Logic production product. Contact your local Clear Logic Representative availability.
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LIBERATOR CL10K30E (PRELIMINARY)
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Fully Compatible Altera® FLEX® 10KE Family Prototype Your System With

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