CB-C8 3-VOLT, 0.5-MICRON CELL-BASED CMOS ASIC July 1994 Figu

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CB-C8 3-VOLT, 0.5-MICRON CELL-BASED CMOS ASIC July 1994 Figu

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NEC's 3-volt CB-C8 cell-based ASIC series ultra-high performance sub-micron CMOS products built within OpenCAD Design Systemof NEC. family allows designing complex logic functions, 600,000 gates user-defined logic, megafunction blocks compiled memory, using ring step sizes normal pitch. Fine pitch step sizes available, enabling higher gate count ratio. CB-C8 technology drawn silicon-gate CMOS. CB-C8 cell-based products fully supported OpenCAD Design SystemTM, front-end back-end unified design environment. This merges best today's most powerful ASIC software design tools into single environment. design methodology incorporates megafunction blocks that commensurate with latest technology advances. Also, memory compilation, floorplanning hardware acceleration available ease design CB-C8 cell-based ASIC series. CB-C8 library includes basic macrocells well NEC's V30MX (16-bit microprocessors), 710XX series support peripherals, RambusASIC Cell (RAC). Compilable ASIC memory blocks also offered library well over macrocells buffer choices CMOS levels.
CB-C8 3-VOLT, 0.5-MICRON CELL-BASED CMOS ASIC
July 1994
Figure Typical CB-C8 Series Cell-Based ASIC
Sample Megafunctions Library
Compatible Device 8086 8237A 8251A 8254 8255A 8259A 4991A Code V30MX 70008A 71037 71051 71054 71055 71059 72065B 4991A Description 16-bit Microprocessor 8-bit Microprocessor Programmable Controller USART Interval Timer Peripheral Interface Interrupt Controller Floppy Disk Controller Real Time Clock
Features
Advanced sub-micron drawn gate length CMOS technology with three-layer metalization Extensive macro library includes soft hard megafunction blocks Internal gate delay 0.22 (F/O power gate) Compiled pads power dissipation 1.25 µW/gate/MHz Library characterized 3.3V±0.3V 3V±10% I/Os interface direstly logic Wide package selection: CPGA, QFP, PLCC
Publications
This data sheet contains preliminary specifications, package information, operational data CB-C8 cell-based CMOS ASIC. Additional design information available NEC's CB-C8 Block Library CB-C8 Design Manual. Contact your local Design Center Literature Center availability further ASIC design information; back this data sheet locations phone numbers.
70181-1
CB-C8
Step Sizes Usable Gate Count
Step Size Std.I/O
Total Grids 54514 78051 105781 137730 174314 214706 259320 281698 333600 388691 439059 500594 565492 635786 708675 759062 838390 920776 1053685 1143833 1239796 1440973
Usable Grids Two-Layer Three-Layer 27257 39025 52890 68865 87157 107353 129660 140849 166800 194345 219529 250297 282746 317893 354337 379531 419195 460388 526842 571916 619898 720486 38159 54636 74046 96411 122020 150294 181524 197189 233520 272083 307341 350415 395844 445050 496073 531343 586873 644543 737579 800683 867857 1008681
Usable Gates2 Two-Layer Three-Layer 9085 13008 17630 22955 29052 35784 43220 46949 55600 64781 73176 83432 94248 105964 118112 126510 139731 153462 175614 190638 206632 240162 12719 18212 24682 32137 40673 50098 60508 65729 77840 90694 102447 116805 131948 148350 165357 177114 195624 214847 245859 266894 289285 336227
Notes: pads configured VDD/VSS, subject number drive output buffers. Usable gates, equivalent 2-input NAND gate (L302 type macrocell, which three grids area) will vary depending specific design. Gate/grid ratio 2.7, based actual conversion from CMOS gate array families.
Part Numbering System
CB-C8 part numbering system follows: Part Number µPD936XX µPD946XX µPD956XX Description Contains logic only logic plus and/or
Typical CB-C8 Package Marking
JAPAN
Contains same µPD936XX with code change Same µPD936XX contains megafunction blocks, such 710XXX V20H/V30HL Same µPD956XX with code change
D93000 D93600
9115K1 9315K1 NEC: Company Mark JAPAN: Origin D93000: Part Number Package Code 9115K1: Number Number Index
83NR-7687A
µPD966XX
CB-C8
On-Chip Compiled Memory
blocks custom compiled CB-C8 design environment. Kbits highspeed, synchronous single port RAMs (including built-in circuits reliable production testing) compiled. Kbits compiled. synchronous RAM, access time nanoseconds. NEC's RAMGEN ROMGEN software allows ASIC designers generate memory blocks specific size performance suit their exact system requirements quickly. table below summarizes features compiled memory blocks. compiled, high-speed RAM, minimum word depth minimum width (1). word depth increase words increments width increase maximum bits. other configurations determined same fashion.
Table Compilable Available CB-C8
Compiled Memory (High-Speed RAM)
Single port, synchronous operation Operating voltage: 3.6V Test used Address Data facilitate BIST (Built-in Self Test) external test Battery back-up mode Built-in power ring Compilable range increment) word (16w increment) Access time (512w max.
Compiled Memory (ROM)
Single port, asynchronous operation Operating voltage: 3.6V Test used with Address facilitate BIST external test Metal-1 programmable Built-in power ring Compilable range increment) word (128w increment) Access time: 25ns max. (2kw 16b)
RambusASIC Cell
Rambus ASIC Cell (RAC) specially designed high-speed Rambus channel Rambus, Inc. Rambus channel configured Rambus DRAM (RDRAMTM) that acheive 500M byte/sec data transmission. acts interface, bridge between system's microprocessor RDRAMs. Depending system architecture, designers integrate four RAC's into CB-C8 design. interface ASIC requires only pins. Rambus high-bandwidth solution used high-end graphics, multimedia systems, Aswitching systems PDAs.
Figure Rambus ASIC Cell
Graphics
Local
CB-C8 User Logic
Rambus Protocol (62.5 MHz)
Features: Highest memory bandwidth: 500M byte/sec/channel Minimum count: pins channel Reduced numbers RDRAMs Fully integrated CB-C8 design flow Built-in test capability
ClkFm ClkTo BCtrl
(250 MHz)
BData
RAMBUS Channel (500 MB/S)
CB-C8
Absolute Maximum Ratings
Power supply voltage, Input/output voltage, Output current, 3.0-mA drive 6.0-mA drive 9.0-mA drive 12.0-mA drive 18.0-mA drive 24.0-mA drive Operating temperature, TOPT Storage temperature, TSTG +85°C +150°C -0.5 +4.6 -0.5
Input/Output Capacitance
Terminal Input Output Symbol COUT CI/O Unit
Note: Values include package capacitance.
Power Consumption
Description Internal cell Input block Output block Limits (max) 1.25 Unit µW/MHz µW/MHz mW/MHz Test Conditions
Caution: Exposure absolute maximum ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. device should operated outside recommended operating conditions.
Recommended Operating Conditions
Parameter Power supply voltage Ambient temperature Low-level Input voltage Interface Block) Low-level Input voltage Interface Block) High-level input voltage Interface Block) High-level input voltage Interface Block) Input rise fall time Input rise fall time, Schmitt Positive Schmitt-trigger voltage Negative Schmitt-trigger voltage Hysteresis voltage Symbol 0.3VDD Unit
Note: rise/fall time given Schmitt trigger input buffer varies depending operating environment. Simultaneous switching output buffers should analyzed before deciding Schmitt trigger input buffer.
Characteristics
0.3V; +85°C Parameter Toggle frequency Delay time, internal gate Delay time, power gate Delay time, buffer Input Output Output rise time (FO01) Output fall time (FO01) 0.36 1.46 1.88 1.32 Symbol fTOG 0.13 0.22 Unit Conditions -F/F;
CB-C8
Characteristics
0.3V; +85°C Parameter Static Current Consumption (Note Symbol IDDS 10-5 -660 Off-State Output Current Input Clamp Voltage (Note Output Short Circuit Current (Note Input Leakage Current Normal Input pull-up pull-up pull-down Low-Level Output Current Normal Output BUFF High-Level Output Current Normal Output BUFF Low-Level Output Voltage Interface Block Interface Block High-Level Output Voltage Interface Block Interface Block VDD-0.1 VDD-0.2 -3.0 -3.0 -3.0 -3.0 -6.0 -9.0 -12.0 -18.0 -24.0 VOL= 12.0 18.0 24.0 VOL= VOL= Unit Conditions (Note (Note
Notes: When using interface blocks with pull-up/pull-down resistors oscillation circuits, static current consumption increases. Step size. Input clamp voltage means voltage clamped when input signal negative. case under-shooting ringing input signal, input signal clamped this voltage. Output short-circuit current should within second, LSI.
CB-C8 Package Options
Type Pitch (mm) 160* 184* (FP) 176* 208* 240* 256* 272* 304* 160* 160* (HS) 176* 208* 304* TQFP 100* 120* 144* PLCC Available 0.65 0.65 0.65 0.65 0.65 0.65 0.65 Body (mm) 10x10 14x14 14x20 14x20 14x20 28x28 28x28 28x28 28x28 32x32 40x40 14x14 20x20 20x20 24x24 24x24 24x24 28x28 28x28 32x32 28x28 36x36 40x40 28x28 24x24 24x24 28x28 40x40 10x10 12x12 14x14 14x14 20x20 .95"x.95" 1.05"x1.05"
Planned
leadframe
Note: Check with Design Center availability.
CB-C8
NEC's ASIC Design System
CB-C8 products fully supported OpenCAD Design Systemof NEC, which merges best today's most powerful hardware software design tools into single unified ASIC design environment. This expanding design system integrates industry-leading tools tools complete front-end back-end ASIC design. tools perform schematic capture, logic synthesis, floorplanning, logic timing simulation, layout, design circuit rule check memory compilation. offering these tightly coupled integrated tools with well developed design methodology, time expense usually associated with development semicustom devices considerably reduced. design flow CB-C8 standard cell shown below with software tools needed major portions design process. tools integrated under DEC's PowerFrameTM. Schematic capture provided ViewLogic's ViewDrawTM. Also, high level behavioral language offered Synopsys' Design Compiler. Back-end place route performed Cell3 Ensemble. benefits OpenCAD Design Systemis that post simulation signoff accomplished customer's site because offers designers three popular simulators, each with "golden simulator" status, namely Verilog System HILO®, V-SimTM. Simulation Verilog gate level models provided each megafunction block, including V20HL, V30HL core simulation purposes. alternative Verilog models hardware modeler simulation capability, where actual stand-alone megafunction block, such V20HL, provides event-driven simulation variety popular third-party environments. Testing During CB-C8 production test process, each megafunction used within specfic customer design, tested with NEC's production test vectors well test vectors provided customer. Each megafunction block must have test input/output each input/ output control megacell. These pins must accessible during production test. Compiled same testing methodology.
Figure CB-C8 Design Flow
Platform
Software Tools
System Framework (Digital PowerFrame)
Behavioral Interface Compiler (Synopsys) Verilog (Cadence)
Schematic Capture Viewdraw (Viewlogic)
Behavioral Specification Language
Schematic Capture
Logic Synthesis
Design Compiler (Synopsys)
Cell Compiler
LCore Module (Mentor Graphics) Generator (NEC)
Synthesis Compilation
EDIF
Simulation
Verilog-XL Veritime (Cadence) System Hilo (GenRad) V-SIM (NEC)
Simulation (Pre-route) Fault Simulation
XP-200 (Zycad) NEXPlus Systems Science
Estimated Wire Length Extraction
Power Simulation
PowerSim Systems Science
Place Route Megafunction Location Simulation (Post-route) ace_floorplan ace_io router
Floorplanning
ace_floorplan (NEC)
Place Route
Cell3 Ensemble (Cadence)
Mask Data (GDS
ICLOVE (NEC) DRACULA (Cadence)
Mask Production
CB-C8
Cell Library List
following preliminary list types elements planned CB-C8 standard cell library. Many elements development many more planned. names functions these blocks designed compatible with those CB-C7 CMOS-8/8L/ 8LCX families. Please contact your local ASIC Design Center latest information availability elements CB-C8 standard cell library.
Types Primitive Cells
Function Gate Complex Gate Parity Adder Decoder Shift Register Multiplexer Latch Flip-Flop Counter Comparator High Speed Power High Density
Buffers
Interface Voltage Input 5V-Protected 5V-Protected 5V-Protected State Input Type CMOS, CMOS-S CMOS, CMOS-S CMOS, CMOS-S CMOS, CMOS-S Output Type CMOS, CMOS-3S, Open-Drain CMOS, CMOS-3S, Open-Drain CMOS, CMOS-3S CMOS, CMOS-3S Output Drive (mA) Pull-Up/Pull-Down
Output
Schmitt
Trademarks
TMOpenCAD Design System trademark Electronics Inc. TMViewDraw trademark ViewLogic Corporation TMPowerFrame trademark Digital Equipment Corporation ®Verilog registered trademark Cadence Design System, Inc. ®System HILO registered trademark GenRad Corporation TMV-Sim trademark Corporation TMDRACULA trademark Cadence Design System Inc. TMNECPlus trademark Systems Science, Inc. TMPowerSim trademark Systems Science, Inc. TMICLOVE trademark Electronics, Inc. TMXP-200 trademark Zycad Corporation TMHDL Compiler Design Compiler trademarks Synopsys Inc. TMRambus RDRAM trademarks Rambus, Inc.
CB-C8
Notes:
CB-C8
ASIC DESIGN CENTERS
WEST
3033 Scott Boulevard Santa Clara, 95054 408-588-5008 408-588-5017 Embassy Centre 9020 S.W. Washington Square Road, Suite Tigard, 97223 503-671-0177 503-643-5911
SOUTH CENTRAL/SOUTHEAST
16475 Dallas Parkway, Suite Dallas, 75248 972-250-4522 972-931-8680
NORTH CENTRAL/NORTHEAST
Meadows, Floor Worcester Road Framingham, 01701 508-935-2200 508-935-2234 Greenspoint Tower 2800 Higgins Road, Suite Hoffman Estates, 60195 708-519-3945 708-882-7564
Research Triangle Park 2000 Regency Parkway, Suite Cary, 27511 919-460-1890 919-469-5926
THIRD-PARTY DESIGN CENTERS
SOUTH CENTRAL/SOUTHEAST
Koos Technical Services, Inc. Commerce Way, Suite Longwood, 32750 407-260-8727 407-260-6227 Integrated Silicon Systems Inc. 2222 Chapel Hill Nelson Highway Durham, 27713 919-361-5814 919-361-2019 Applied Systems, Inc. 1761 Hillsboro Blvd., Suite Deerfield Beach, 33442 305-428-0534 305-428-5906
literature, call toll-free a.m. p.m. Pacific time: 1-800-366-9782 your request 1-800-729-9288
CORPORATE HEADQUARTERS
2880 Scott Boulevard P.O. 58062 Santa Clara, 95052 408-588-6000
part this document copied reproduced form means without prior written consent Electronics Inc. (NECEL). information this document subject change without notice. DEVICES SOLD NECEL COVERED PROVISIONS APPEARING NECEL TERMS CONDITIONS SALES ONLY. INCLUDING LIMITATION LIABILITY, WARRANTY, PATENT PROVISIONS. NECEL makes warranty, express, statutory, implied description, regarding information forth herein regarding freedom described devices from patent infringement. NECEL assumes responsibility errors that appear this document. NECEL makes commitments update keep current information contained this document. devices listed this document suitable applications such limited aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems life support systems. "Standard" quality grade devices recommended computers, office equipment, communication equipment, test measurement equipment, machine tools, industrial robots, audio visual equipment, other consumer products. automotive transportation equipment, traffic control systems, anti-disaster anti-crime systems, recommended that customer contact responsible NECEL salesperson determine reliabilty requirements such application cost adder. NECEL does recommend approve products life support devices systems application where failure could result injury death. customers wish NECEL devices applications intended NECEL, customer must contact responsible NECEL sales people determine NECEL's willingness support given application.
©1996 Electronics Inc./Printed U.S.A.
Document 70181-1

CB-C8 3-VOLT, 0.5-MICRON CELL-BASED CMOS ASIC July 1994 Figu

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