HCMOS6 STANDARD CELLS 0.35 micron layer metal HCMOS6 process, ret
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CB45000 SERIES
HCMOS6 STANDARD CELLS
0.35 micron layer metal HCMOS6 process, retrograde well technology, resistance salicided active areas polysilicide gates. optimized transistor with interface capability input NAND delay (typ) with fanout Broad functionality including Voltage CMOS, Voltage LVDS. Driving capability ISA, EISA, PCI, MCA, SCSI interface levels High drive I/O; capability sinking with slew rate control, current spike suppression impedance matching. Generators support Single Port RAM, Dual Port RAM, with BIST options. DRAM integration ASIC methodology Extensive embedded function library including micro cores, third party micros Synopsys synthetic libraries. Fully independent power ground configurations inputs, core outputs. ring capability 1000 pads. Latchup trigger current protection 4000 volts typical value
Oscillators wide frequency spectrum. Broad range 500+ cells Design Test features including IEEE 1149.1 JTAG Boundary Scan architecture. Cadence, Mentor Synopsys based design systems with interfaces from multiple workstations. Broad ceramic plastic package range.
CB45000 Super-Integration Cost Effective Product Architecture Partitioning Trouble free integration Application Specific
DPRAM
ST20
Your Product Unique User specified cell integration Design Confidentiality fully re-usable
March 1998
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CB45000 SERIES
GENERAL DESCRIPTION CB45000 standard cell series uses high performance, voltage, level metal, HCMOS6 0.35 micron process achieve subnanosecond internal speeds while offering very power dissipation high noise immunity. With average routed logic density 14000 gates/mm2, CB45000 family allows design highly complex devices. potential available gate count ranges above Million equivalent gates. Devices operate over voltage range volts. count this array family ranges over signals 1000 pins based upon package technology utilized. flexible approach been developed provide Figure Process Overview optimum solution today's complex system problems drive levels specialized interface standards. product offers variable bonding approach supporting spacings from upwards supports staggered rows address today's bonding technologies. Additional flexibility support spacing will available near future. configured circuits ranging from voltage CMOS swing differential circuits (LVDS) 1Gigabit second high speed link. Standards like SCSI, Volt other Volt interfaces currently being addressed.
Metal Al-Cu
Metal Al-Cu
Metal Al-Cu
Metal Al-Cu
Metal
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CB45000 SERIES
TECHNOLOGY OVERVIEW major feature HCMOS6 process salicided active areas. This results source drain areas that order ohms resistance opposed hundreds thousands ohms source drain resistance non-salicided technologies. This very resistance reason that very transistor widths could utilized cell design since drive lost source drain resistance. This width transistors results lower capacitance loading gates smaller areas utilized. resistance, capacitance, small gates results power usage inverters compared previous technologies. reduction power consumption allows usage salicided active stripes distribute power internally simple cell, replacing, some cases, usage first metal layer. This saves silicon area allowing greater density, permeability routability cells resulting greater overall circuit density. other major feature HCMOS6 process five metal layer interconnect using (Chemical Mechanical Polishing) planarization. improved planarity between metal layers allows additional interconnect layers without yield degradation, improving density whilst retaining costs. power distribution methodology provides separate internal distributions improve product noise margin reduce power loss. three supplies are: Internal Serves core cells prebuffer sections External Serves output transistors only Receiver Serves first stages receiver cells. Optional distributions 5.0V interface other standards utilized necessary.
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CB45000 SERIES
LIBRARY CB45000 Series library organized into four categories: cell library Cell library Macrofunctions Module generators CELL LIBRARY OVERVIEW design CB45000 family been optimized allow extremely high density, high speed power designs. these reasons wide range cells with different ranges driving capability available library. library cells have been optimized term functional electrical parameters order have: Good balancing Maximum speed Optimum Threshold voltage Symmetric Vdd/Vss Noise margin Minimum Power-Speed figure geometrical aspect cells configured allow extremely dense design, fully exploiting features Place Route tool terms horizontal vertical routing grids. Place Route, five levels metal utilized. Intracell wiring limited possible first metal, with second, third fourth metal levels dedicated interconnect wiring power distribution. fifth metal used power clock bussing.
CORE LOGIC propagation delays shown CB45000 data book given nominal processing, 3.3V operation, temperature conditions. However there additional factors that affect delay characteristics macrocells. These include loading fanout interconnect routing, voltage supply, junction temperature device, processing tolerance input signal transition time. Prior physical layout, design system estimate delays associated with critical path. impact placement routing accurately back annotated from layout final simulations critical timing. effects junction temperature, (KT) voltage supply (KV) delay numbers summarized Table Table third factor, associated with process variation. This multiplier minimum maximum 1.2. Table Junction Temperature Multipliers Temperature 0.77 0.83 1.00 1.13 1.17 1.27
Figure Core Cell
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CB45000 SERIES
Table Voltage Multipliers 1.20 1.11 1.00 0.94 transistor subcells. These subcells quickly configured using metallization layers conform variety specifications whilst maintaining optimal protection levels latch-up prevention characteristics. circuitry also includes subcells specialized transistors that used form slew rate control sections each line. Current spike suppression logic ensures that conducting transistors turned before opposing turned bond itself variable terms pitch size even supports staggered bonding methodologies. This becoming more
BUFFER LIBRARY CB45000 does traditional cell design; SGS-THOMSON pioneers emerging "Flexible I/O" approach CB45000 features variable bonding flexible output transistor scheme based predefined Figure Flexible Buffer Technology
EDGE GUARDRING
Programmable locations allows cell library used both staggered linear bonding.
EDGE GUARDRING
CLAMP STRUCTURES
CLAMP STRUCTURES
CLAMP STRUCTURES
CLAMP STRUCTURES
CLAMP STRUCTURES
CLAMP STRUCTURES
OUTPUT DRIVE TRANSISTORS
OUTPUT DRIVE TRANSISTORS
OUTPUT DRIVE TRANSISTORS
OUTPUT DRIVE TRANSISTORS
OUTPUT DRIVE TRANSISTORS
OUTPUT DRIVE TRANSISTORS
DIODES LOGIC CIRCUITS TEST INTERFACE SLEW CONTROL
DIODES LOGIC CIRCUITS TEST INTERFACE SLEW CONTROL
DIODES LOGIC CIRCUITS TEST INTERFACE SLEW CONTROL
DIODES LOGIC CIRCUITS TEST INTERFACE SLEW CONTROL
DIODES LOGIC CIRCUITS TEST INTERFACE SLEW CONTROL
DIODES LOGIC CIRCUITS TEST INTERFACE SLEW CONTROL
CORE
CORE
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CB45000 SERIES
important packaging options become ever broader. size pitch determined until customers choice packaging, signal interface standards count considered. Wire bond spacings down centres will released near future support large signal counts without area loss. pads except sixteen corner pads configured power pads. configured power pads known placeable pads have associated current handling capability. Their placement dependent types output buffers used design. rules governing placement pads, please contact your local SGS-THOMSON design centre. TEST INTERFACE cells have dedicated test interface facilitate parametric Iddq testing devices. This test interface connects standard core signals dedicated test signals cells allowing Output Buffers driven high, into tristate regardless state internal logic. This greatly simplifies parametric testing part also assisting customers wish this feature during board testing. Note that output buffers tristated this function including buffers that normally tristate. This test function also turns pull down devices shuts down differential receivers converts them into standard CMOS receivers. This allows Iddq test methodologies employed very efficient way, avoiding unneeded circuit overhead. Inside cell section specialized transistors used create receiver functions. full standard receivers with pull pull down devices present library. technologies supported match output buffer capabilities include, LVCMOS, LVTTL, GTL, CTL, Differential, etc. five volt interface capability.
Table
Drive Capacity LVCMOS LVTTL Slew Rate Buffers Maximum Capacitance (pF)
Current Drive (mA) 12.0 16.0
MACROCELLS MACROFUNCTIONS CB45000 series internal macrocells that robust variety performance. cell selection been driven need Synthesis based design techniques. This offering rich buffers, complex combinatorial cells multi power drive cells, which allow Synthesis tool create netlist compatible with requirements Place Route tools. Macrofunctions series soft-macros facilitating quick capture large functional blocks available such functions counters, shift register adders. Macrofunctions implemented layout utilizing macrocells interconnecting create logic function.
Table
Drive Capacity LVCMOS LVTTL Slew Rate Buffers Maximum Capacitance (pF)
Current Drive (mA) 12.0 16.0
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CB45000 SERIES
Table Module Generator Library Description 256K bits word Zero static current, Tristate outputs 256K bits word Zero static current, Tristate outputs bits word Diffusion programmable, Tristate outputs
Cell SPRAM
DPRAM
MODULE GENERATORS series module generators using compiled cell generation techniques, available support range megacells. These modules enable designer choose individual parameters order create compiled cell, which meets specific application requirements. These include single port RAM, dual port ROM. compiled cell generators construct custom cells, which implemented using special leaf cell technique, ensuring predictable layout accurate module characteristics. choosing megacells designer consider tradeoffs between speed area generate fully customized cell which meets their specific device requirements. MEGACELLS These megacell generators complemented group application specific embedded megacells. These allow access technologies that have been hitherto domain standard products. Examples include mixed mode cells graphics, DAC/ADC's (4-9 bit), applications, Digital Signal Processor functions cellular comms, high-speed modems, which initially consist Triple 8-bit DAC, Graphics RAM, Clock Multiplier Frequency Synthesis PLL. Mbps serial transputer links coupled with large fast memory used pipelining, caching synchro circuits modern RISC computing architectures. Viterbi Reed Solomon cores HDTV satellite transmission markets. support telecom needs CCITT standard applications, ADPCM cells supporting protocol have been developed. DESIGN TESTABILITY time cost ASIC testing increases exponentially complexity size ASIC grows. Using design testability methodology allows large, more complex ASICs efficiently economically tested. CB45000 supports JTAG boundary Scan both edge level sensitive scan design techniques providing necessary macrocells. Scan testing aids device testability permitting access internal nodes without requiring separate external connection each node accessed. Testability assured device level with close coupling LSSD latch elements, Automatic Test Pattern Generation (ATPG) high pattern depth tester architecture. BIST options memory generators also available. system level, SGS-THOMSON fully supports IEEE 1149.1, structure utilized this family completely compatible. Several types core scan cells provided CB45000 Series library. Examples include FDxS/FJKxS cells which edge sensitive LSxx cells
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CB45000 SERIES
which true LSSD cells. Non-overlapping clock generator macros also available. parametric Iddq testing, cells contain dedicated test interface described previously (See "I/O TEST INTERFACE" page EVALUATION DEVICE evaluation device used demonstrate performance CB45000 series well verify effectiveness design system. device path delays, latches macrocells memory functions which were used verify simulated characteristics that supplied data book. Characterization path delays including interconnect shows typical delays input NAND with receivers/drivers operating frequencies MHz. evaluation device available plastic quad flat pack.
Figure Evaluation Device Cross Section
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CB45000 SERIES
PACKAGE AVAILABILITY CB45000 Series designed compatible with QFP, package types, addition more traditional types found. options include Plastic Leaded Chip Carriers (PLCC) pins, while Metric Quad Flat Pack (xQFP) offering ranges pins. Both high performance high power variants available well TQFP thin types. Ball Grid Array (BGA) packages available from pins with further developments planned near future. types allow count reach area 1000 pins. diversity count package style gives designer opportunity find best compromise system size, cost performance requirements.
Figure Packaging Capability NUMBER LEADS (Pins) Packages Production Packages Development
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PQFP
TQFP
PACKAGE NAME PLCC
POWER PQFP Slug/Spreader
CB45000 SERIES
DESIGN ENVIRONMENT Several interface levels possible between SGS-THOMSON customer undertaking ASIC design. four levels interface shown Figure Level characterized SGS-THOMSON receiving system specification taking design through validation fabrication. level interface designer supplies complete logic design implemented standard generic logic family. SGS-THOMSON then takes design through layout, validation fabrication. Level most common preferred interface level. Logic capture pre-layout simulation performed designer using SGS-THOMSON supported design kit. design then taken through layout, validation fabrication SGS-THOMSON. SGS-THOMSON design system validates designs before fabrication. Design kits provided that allow schematic capture entry Mentor Graphics Cadence products. Simulation supported Cadence Mentor Graphics. Full support also provided Cadence Verilog, Synopsys System Hilo simulators. Figure shows SGSTHOMSON Design Flow. Test vector development uses TSSI software from Summit Currentest from CrossCheck.
Figure Customer SGS-THOMSON Interface Levels
SYSTEM
SYSTEM SPECIFICATION
LOGIC DESIGN
SCHEMATIC CAPTURE
DESIGN VERIFICATION
PRE-LAYOUT SIMULATION
LAYOUT
POST-LAYOUT MANUFACTURE SIMULATION TEST
CUSTOMER
SGS-THOMSON
INTERFACE LEVELS
LEVEL
CUSTOMER LEVEL
SGS-THOMSON
CUSTOMER LEVEL
SGS-THOMSON
CUSTOMER
SGS-THOMSON
CUSTOMER LEVEL
SGS-THOMSON
ECR1
ECR2
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CB45000 SERIES
Figure SGS-THOMSON Layout Driven Design Flow
HARDWARE DESCRIPTION LANGUAGE VHDL VERILOG
FUNCTIONAL SIMULATION VHDL VERILOG
GATE LEVEL SIMULATION VERILOG MENTOR TIMING ANALYSIS FORMAL PROOF
FLOORPLANNING
LOGIC SYNTHESIS SCAN INSERTION
SCHEMATIC CAPTURE CADENCE MENTOR
DELAY EVALUATION BACK-ANNOTATION
ACCELERATION EMULATION
POWER ESTIMATION POWER ANALYSIS
FAULT ANALYSIS TSSI IDDQ
CLOCK TREE SYNTHESIS
LAYOUT
SILICON
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CB45000 SERIES
Table Absolute Maximum Ratings (note1)
-0.5 -0.5 (Vdd 0.5V) -0.5 +6.0 -24mA source, +24mA sink degrees Centigrade degrees Centigrade
Supply Voltage, Input Output Voltage Volt Tolerant Input Output Voltage Forward Bias Current, Input Output Storage Temperature Ceramic Storage Temperature Plastic
Note
Referenced Vss. Stresses above those listed under "absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. dedicated extra power supply needed case buffer usage order clip incoming signal pads Volt tolerant specified Absolute Maximum Rating value)R.
Table
Recommended Operating Conditions
(3.0 0.3V/-0.6V (2.7V 3.6V)
Normal Operating Supply Voltage (note Extended Operating Supply Voltage (notes 1,2) Operating Ambient Temperature Commercial (note Industrial (note Military (note
Note Note Note Note
degrees Centigrade degrees Centigrade +125 degrees Centigrade
Commercial, Industrial, Military Conditions Voltage Circuits functional specifications below Volts circuits will operate full specifications with 3.0V 3.6V junction temperature +125 degrees centigrade. These junction temperatures compatible with Commercial Industrial Temperature Ranges. circuits will functional from +150 degrees centigrade junction temperature (military Ambient Temperature Range) will necessary operate published specifications. Only circuits specified operational extended temperature range used when operating Military temperature conditions.
Table
Symbol Iklu Vesd
Note Note Note Note Note
General Interface Electrical Characteristics (Note
Parameter Level Input Current High Level Input Current Tri-State Output Leakage Input Capacitance Output Capacitance Bidi, Capacitance Latch Current Electrostatic Protection Conditions =Vss Vo=0V Freq=1MHz Freq=1MHz Freq=1MHz V<Vss, V>Vdd 2000 +/-10 +/-10 +/-10 Unit Notes
These extended voltage temperature specifications from Temperature Ambient from degrees Centigrade Adherence rules Power Specifications Required Excluding Package Volts Human Body Model
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CB45000 SERIES
Table
Symbol
LVTTL Interface Electrical Characteristics (Note
Parameter Level Input Voltage High Level Input Voltage Level Output Voltage High Level Output Voltage Rated Buffer Current Rated Buffer Current Conditions Unit Volts Volts Volts Volts Notes 2,3,4 2,3,4
Note
Schmitt Trigger Threshold Schmitt Trigger Threshold
Volts Volts
Note Note Note
These normal Voltage extended temperature specifications from Temperature Ambient from degrees Centigrade Adherence rules Power Specifications Required Refer CB45000 Standard Cell Specification full Testing Levels Conditions Buffers offered options (12, available request)
Table LVCMOS Interface Electrical Characteristics (Note
Symbol Parameter Level Input Voltage High Level Input Voltage Level Output Voltage Rated Buffer Current Rated Buffer Current 0.85 Conditions 0.2xVdd Unit Volts Volts Volts Notes 2,3,4 2,3,4 2,3,4,5,6
High Level Output Voltage
Volts
2,3,4,5,6
Schmitt Trigger Threshold Schmitt Trigger Threshold
Volts Volts
Note
Note Note Note Note
Note
These extended voltage temperature specifications from Temperature Ambient from degrees Centigrade Adherence rules Power Specifications Required Refer CB45000 Standard Cell Specification full Testing Levels Conditions Buffers offered CMOS options Note only CMOS buffer sink source current when parametric measurements taken reason that power supply specifications CMOS product written support current. more than buffer active voltage drops supply cause false failure readings. buffers sinking sourcing current internal pull pull down resistors bidi buffers have been disabled having Test positive (max) 0.05 Volts (min)=Vdd-0.05 Volts
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CB45000 SERIES
Table Five Volt Tolerant Interface Electrical Characteristics (Note 1,2)
Symbol Parameter Level Input Voltage High Level Input Voltage Level Output Voltage High Level Output Voltage Rated Buffer Current Rated Buffer Current Note
Conditions
Unit Volts Volts
Notes 3,4,5 3,4,5
Volts Volts
Schmitt Trigger Threshold Schmitt Trigger Threshold
Volts Volts
Note
Note Note
Five Volt Tolerant Inputs: receivers allowed receive signal while being supplied 3.3V Five Volt Tolerant Output: drivers allowed drive external loads between 3.3V while being supplied 3.3V having ability sustain signals when tristated. These normal Voltage extended temperature specifications specification only; from Temperature Ambient from degrees Centigrade Adherence rules Power Specifications Required Refer CB45000 Standard Cell Specification full Testing Levels Conditions
Note Buffers offered options
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CB45000 SERIES
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DESIGN CENTRES
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Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics rights reserved SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan United Kingdom U.S.A.
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