HCMOS STANDARD CELLS FEATURES micron triple layer metal HCMO

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HCMOS STANDARD CELLS FEATURES micron triple layer metal HCMO

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CB35000 SERIES
HCMOS STANDARD CELLS
FEATURES
micron triple layer metal HCMOS5S process featuring retrograde well technology, resistance salicided active areas, polysilicide gates thin metal oxide. optimized transistor with interface capability input NAND delay (typ) with fanout Broad functionality including LVCMOS, LVTTL, GTL, PECL, LVDS. High drive I/O; capability sinking with slew rate control, current spike suppression impedance matching. Generators support SPRAM, DPRAM, MULT with BIST options. Extensive embedded function library including micros, popular third party micros Synopsys synthetic libraries.
Fully independent power ground configurations inputs, core outputs. ring capability pads. Output buffers capable driving ISA, EISA, PCI, MCA, SCSI interface levels. Active pull pull down devices. Buskeeper functions. Oscillators wide frequency spectrum. Broad range cells. Power Drive library subset. Design Test includes IEEE 1149.1 JTAG Boundary Scan architecture built Cadence Mentor based design system with interfaces from multiple workstations. Broad ceramic plastic package range. Latchup trigger current protection 4000 volts.
Table
Module Generator Library Description 256K bits word Zero static current Tristate outputs 128K bits word Zero static current Tristate outputs bits word Diffusion programmable Tristate outputs Parallel asynchronous operation complement product bits both inputs Ripple Carry Fast Carry Look Ahead
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Cell SPRAM
DPRAM
MULT
July 1995
CB35000 SERIES
GENERAL DISCRIPTION CB35000 standard cell series uses high performance, voltage, triple level metal, HCMOS5S micron process achieve subnanosecond internal speeds while offering very power dissipation high noise immunity. With average gate density 5500 gates/mm2, CB35000 family allows design highly complex devices. potential available gate count ranges above Million equivalent gates. Devices operate over voltage range volts. count this array family ranges over signals pins dependent upon package technology utilized. approach been followed give solution Figure Advantages stacked contacts vias today's problems drive levels specialized interface standards. technology does utilize bond spacing allows spacings from microns upwards. fully compatible with that ISB35000 Structured Array family. configured circuits ranging from voltage CMOS plus swing differential circuits. Standards like GTL, SCSI-2, Volt PCI, CTI, limited Volt interfaces currently being addressed. specialized impedance matched transmission line driver LVTTL type circuits also available with output impedance. These buffers sacrifice direct current capabilities matching positive negative voltage current waveforms.
CONVENTIONAL LAYOUT
STACKED LAYOUT
METAL
METAL CONTACT METAL GATE DIELECTRIC DIELECTRIC CONTACT PLUGS
DIELECTRIC
ISOLATION
SUBSTRATE
AREA SAVINGS RANDOM LOGIC SIMPLIFIED ROUTING DESIGN RULE CHECKING
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CB35000 SERIES
LIBRARY OVERVIEW design CB35000 family been optimized allow extremely high density, high speed power designs. these reasons wide range cells with different ranges driving capability available library. library cells have been optimized term functional electrical parameters order have: Good balancing Maximum speed Optimum Threshold voltage Symmetric Vdd/Vss Noise margin Minimum Power-Speed figure Surrounding core configurational specialized transistors forming giving high degree flexibility system designer. geometrical aspect cells configured allow extremely dense design, fully exploiting features Place Route tool terms horizontal vertical routing grids. Place Route, three levels metal utilized. Intracell intercell wiring limited first metal, with second third metal levels dedicated interconnect wiring power distribution. Each cell gives possibility horizontal wiring channels using third metal. With horizontal grid unit being same Metal minimum contacted pitch, vertical wiring done every grid point, without limitation. TECHNOLOGY OVERVIEW major feature HCMOS5S process salicided active areas. This results source drain areas that ohms resistance opposed hundreds thousands ohms source drain resistance previous technologies. This very resistance reason that very transistor widths could utilized cell design since drive lost source drain resistance. This width transistors results lower capacitance loading gates smaller areas utilized. resistance, capacitance, small gates results power usage inverters compared previous technologies. reduction power consumption allows usage salicided active stripes distribute power internally simple cell, replacing, some cases, usage first metal layer. This saves silicon area allowing greater density, permeability routability cells resulting greater overall circuit density. standard power distributions Internal Vss, serving internal cells prebuffer sections I/O, External serving output transistors only, Receiver serving first stages receiver cells. Optional distributions 5.0V interface, GTL, CTL, other standards utilized necessary.
Figure Core Cell
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CB35000 SERIES
LIBRARY following section details elements which make CB35000 Series library. elements organized into three categories: Macrocell library with Input, Output, Bidirectional Buffers including JTAG macrocells Core cells. Macrofunctions Module generators. BUFFERS CB35000 technology does utilize standard type cell leader emerging approach handling chip interface problem. This approach starts bond area where size pitch determined until customers choice packaging, signal interface standards count considered. Wire bond spacings micron centres available where large signal counts most important. spacing increased incrementally. expected that most designs will micron spacings above. also possible different spacings different width output sections when needed within same device. Along with variable bond spacing output transistor section does have fixed width. Previous technologies utilized design approach where desired full function buffer designed maximum current taking location with usual current range twenty four milliamps. approach followed CB35000 have identical twenty five micron wide output transistor slices stepped around die. Each slice contains protection diodes external power rails eight eight transistors. transistors specifically laid selectively salicided protection latch prevention. These slices paralleled meet current needs user, example, construct 24mA sink 12mA source LVTTL buffer, number slices would used. next group devices that makes circuits again
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wide slice specialized transistors that utilized form slew rate control sections I/O. Each these slices circuits control switching sections output transistors. These sections course created from output transistor slice above slew rate section connected desired designer. Many configurations circuits created supply desired results with slew rate slices paralleled with multiple output sections. further function circuits current spike suppression during switching transistors. logic utilized causes conducting transistors turn before opposing transistors turn Figure Buffer Technology
EDGE
GUARDRING
PROGRAMMABLE PITCH BOND PADS
Selected SEGMENTED OUTPUT
RIVER DRIVE TRANSISTORS
INPUT CONTROL SLEW RATE
TRISTATE BUSKEEPER LEVEL SHIFTER
CORE
CB35000 SERIES MPUL LPUL
Volts Typical Current from supplies LPUL MPDL receiver MPDL LPDL
Trip Level
Figure D.C. Specifications LVCMOS Input Receivers
Volts
MPUL LPUL
Volts Volts Typical Current from supplies LPUL MPDL receiver MPDL LPDL
Trip Level Volts (nominal) Volts Volts
Figure D.C. Specifications LVTTL Input Receivers
Table
Drive Capacity LVCMOS LVTTL Slew Rate Buffers Maximum Capacitance (pF)
Table
Drive Capacity LVCMOS LVTTL Slew Rate Buffers Maximum Capacitance (pF)
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Current Drive (mA) 12.0 16.0 24.0
Current Drive (mA) 12.0 16.0 24.0
CB35000 SERIES
Table Temperature (Junction) Voltage Multipliers 0.77 0.83 1.00 1.13 1.17 1.27 1.20 1.11 1.00 0.94 down devices present library. technologies supported match output buffer capabilities include, LVCMOS, LVTTL, GTL, CTL, Differential, etc. five volt interface capability. pads except sixteen corner pads configured power pads. configured power pads known placeable pads have associated current handling capability. Their placement dependent types output buffers used design. rules governing placement pads, please contact your local SGS-THOMSON design centre. CORE LOGIC propagation delays shown CB35000 data book given nominal processing, 3.3V operation, temperature conditions. However there additional factors that affect delay characteristics macrocells. These include loading fanout interconnect routing, voltage supply, junction temperature device, processing tolerance input signal transition time. Prior physical layout, design system estimate delays associated with critical path. impact placement routing accurately back annotated from layout final simulations critical timing. effects junction temperature, (KT) voltage supply (KV) delay numbers summarized Table third factor, associated with process variation. This multiplier minimum maximum 1.2. MACROCELLS MACROFUNCTIONS CB35000 series internal macrocells that robust variety performance. cell selection been driven need Synthesis based design techniques. This offering rich buffers, complex combinatorial cells multi power drive cells, which allow Synthesis tool create netlist compatible with requirements Place Route tools. Macrofunctions series soft-macros facilitating quick capture large functional blocks available such functions counters,
Temperature
Inside slew rate sections next slices specialized designed components step micron wide pattern. first these micron wide sections utilized predriver circuits; these include specialized built test functions I/O. predriver course interfaces core signals controlling tristate switching functions with slew rate output transistor sections also allows Output Buffers driven high, into tristate regardless state internal logic greatly simplifying parametric testing part also assisting customers wish this feature during board testing. Note that output buffers tristated this function including buffers that normally tristate. This test function also turns pull down devices shuts down differential receivers converts them into standard CMOS receivers. Inside predriver section specialized transistors used create receiver functions. This section includes specialized salicide protection resistor diodes further protect gates receiver devices from latch Also present this section devices that utilized form various parameteriseable pull pull down buskeeper functions. full standard receivers with pull pull
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CB35000 SERIES
Table Module Generator Library Description 256K bits word Zero static current, Tristate outputs 128K bits word Zero static current, Tristate outputs bits word Diffusion programmable, Tristate outputs Parallel asynchronous operation complement product bits both inputs Ripple Carry Fast Carry Look Ahead Mbps serial transputer links coupled with large fast memory used pipelining, caching synchro circuits modern RISC computing architectures. Viterbi Reed Solomon cores HDTV satellite transmission markets. support telecom needs CCITT standard applications, ADPCM cells supporting protocol have been developed. DESIGN TESTABILITY time cost ASIC testing increases exponentially complexity size ASIC grows. Using design testability methodology allows large, more complex ASICs efficiently economically tested. CB35000 supports JTAG boundary Scan both edge level sensitive scan design techniques providing necessary macrocells. Scan testing aids device testability permitting access internal nodes without requiring separate external connection each node accessed. Testability assured device level with close coupling LSSD latch elements, Automatic Test Pattern Generation (ATPG) high pattern depth tester architecture. BIST options memory generators also available. system level, SGS-THOMSON fully supports IEEE 1149.1, structure utilized this family completely compatible. Several types
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Cell SPRAM
DPRAM
MULT
shift register adders. Macrofunctions implemented layout utilizing macrocells interconnecting create logic function. MODULE GENERATORS series module generators using compiled cell generation techniques, available support range megacells. These modules enable designer choose individual parameters order create compiled cell, which meets specific application requirements. These include single port RAM, dual port RAM, MULT. compiled cell generators construct custom cells, which implemented using special leaf cell technique, ensuring predictable layout accurate module characteristics. choosing megacells designer consider trade-offs between speed area generate fully customized cell which meets their specific device requirements. These megacell generators complemented group application specific embedded megacells. These allow access technologies that have been hitherto domain standard products. Examples include mixed mode cells graphics, DAC/ADC's (4-9 bit), applications, Digital Signal Processor functions cellular comms, high-speed modem.which initially consist Triple 8-bit DAC, Graphics RAM, Clock Multiplier Frequency Synthesis PLL.
CB35000 SERIES
core scan cells provided CB35000 Series library. Examples include FDxS/FJKxS cells which edge sensitive LSxx cells which true LSSD cells. Non-overlapping clock generator macros also available. EVALUATION DEVICE evaluation device used demonstrate performance CB35000 series well verify effectiveness design system. device path delays, latches, host macrocells memory functions which were used verify simulated characteristics that supplied data book. Characterization path delays including interconnect shows typical delays input NAND with receivers/drivers operating frequencies MHz. evaluation device available plastic quad flat pack.
Figure Evaluation Device
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CB35000 SERIES
PACKAGE AVAILABILITY CB35000 Series designed compatible with QFP, package types, addition more traditional types found. options include Plastic Leaded Chip Carriers (PLCC) from pins, while Metric Quad Flat Pack (xQFP) offering ranges pins. Both high performance high power variants available well TQFP thin types. Ball Grid Array (BGA) packages available from pins types allow count reach area 1000 pins. counts through board mounting (PGA) range 480. diversity count package style gives designer opportunity find best compromise system size, cost performance requirements. packages military market hermetically sealed meet MIL-STD-883 Method. Prototypes developed ceramic packages fast turnaround evaluation.
Figure Packaging Capability NUMBER LEADS (Pins) Packages Production Packages Development
PQFP
TQFP
PACKAGE NAME PLCC
CPGA
POWER PQFP Slug/Spreader
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CB35000 SERIES
DESIGN ENVIRONMENT Several interface levels possible between SGS-THOMSON customer undertaking ASIC design. four levels interface shown Figure Level characterized SGS-THOMSON receiving system specification taking design through validation fabrication. level interface designer supplies complete logic design implemented standard generic logic family. SGS-THOMSON then takes design through layout, validation fabrication. Level most common preferred interface level. Logic capture pre-layout simulation performed designer using SGS-THOMSON supported design kit. design then taken through layout, validation fabrication SGS-THOMSON. SGS-THOMSON design system validates designs before fabrication. Design kits provided that allow schematic capture entry Mentor Graphics Cadence products. Simulation supported Cadence Mentor Graphics. Full support also provided Cadence Verilog, Synopsys System Hilo simulators. Figure shows SGSTHOMSON Design Flow. Test vector development uses TSSI software from Summit Currentest from CrossCheck.
Figure Customer/SGS-THOMSON Interface Levels
SYSTEM
SYSTEM SPECIFICATION
LOGIC DESIGN
SCHEMATIC CAPTURE
DESIGN VERIFICATION
PRE-LAYOUT SIMULATION
LAYOUT
POST-LAYOUT MANUFACTURE SIMULATION TEST
CUSTOMER
SGS-THOMSON
INTERFACE LEVELS
LEVEL
CUSTOMER LEVEL
SGS-THOMSON
CUSTOMER LEVEL
SGS-THOMSON
CUSTOMER LEVEL
SGS-THOMSON
ECR1
ECR2
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CB35000 SERIES
Figure SGS-THOMSON Design Flow
HARDWARE DESCRIPTION LANGUAGE VHDL
FUNCTIONAL SIMULATION VHDL
LOGIC SYNTHESIS SYNOPSYS
SCHEMATIC CAPTURE CADENCE MENTOR
GATE LEVEL SIMULATION VERILOG-XL MENTOR SYSTEM HILO
FLOORPLANNING
DELAY EVALUATION BACK ANNOTATION TSSI CURRENTEST CLOCK TREE SYNTHESIS
SIGN SIMULATION SGS-THOMSON
LAYOUT
SILICON
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CB35000 SERIES
Table Absolute Maximum Ratings (note1)
-0.5 +6.0 -0.5 (Vdd 0.5V) -24mA source, +24mA sink degrees Centigrade degrees Centigrade
Supply Voltage, Input Output Voltage Forward Bias Current, Input Output Storage Temperature Ceramic Storage Temperature Plastic
Note
Referenced Vss. Stresses above those listed under "absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Table
Recommended Operating Conditions
(3.0 0.3V/-0.6V (2.7V 3.6V)
Normal Operating Supply Voltage (note Extended Operating Supply Voltage (notes 1,2) Operating Ambient Temperature Commercial (note Industrial (note Military (note
Note Note Note Note
degrees Centigrade degrees Centigrade +125 degrees Centigrade
Commercial, Industrial, Military Conditions Voltage Circuits functional specifications below Volts circuits will operate full specifications with 3.0V 3.6V junction temperature +125 degrees centigrade. These junction temperatures compatible with Commercial Industrial Temperature Ranges. circuits will functional from +150 degrees centigrade junction temperature (military Ambient Temperature Range) will necessary operate published specifications. Only circuits specified operational extended temperature range used when operating Military temperature conditions.
Table
Special Voltages (Vcc) Operating Conditions
5.0V (4.5 1.2V (1.14 1.26 1.5V (1.35 1.65
(Five Volt Interface) Supply Voltage (notes 1,2) (Gunning Transistor Logic) Supply Voltage (notes (Center Terminated) Supply Voltage (notes 1,4)
Note Note Note Note
Commercial, Industrial Only degrees Centigrade Circuits Only takes Special External Power Distribution mixed with circuits side die. Only very limited buffer available. Circuits Only takes Special External Power Distribution mixed with circuits side die. Only very limited buffer available. Circuits Only takes Special External Power Distribution mixed with circuits side die. Only very limited buffer available.
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CB35000 SERIES
Table
Symbol
LVTTL Interface Electrical Characteristics (Note
Parameter Level Input Voltage High Level Input Voltage Level Output Voltage High Level Output Voltage Rated Buffer Current Rated Buffer Current Conditions Unit Volts Volts Volts Volts Notes 2,3,4 2,3,4
Note
Schmitt Trigger Threshold Schmitt Trigger Threshold
Volts Volts
Note Note Note
These normal Voltage extended temperature specifications from Temperature Ambient from degrees Centigrade Adherence rules Power Specifications Required Refer CB35000 Standard Cell Specification full Testing Levels Conditions Buffers offered options
Table LVCMOS Interface Electrical Characteristics (Note
Symbol Parameter Level Input Voltage High Level Input Voltage Level Output Voltage Rated Buffer Current Rated Buffer Current 0.85 Conditions 0.2xVdd Unit Volts Volts Volts Notes 2,3,4 2,3,4 2,3,4,5,6
High Level Output Voltage
Volts
2,3,4,5,6
Schmitt Trigger Threshold Schmitt Trigger Threshold
Volts Volts
Note
Note Note Note Note
Note
These extended voltage temperature specifications from Temperature Ambient from degrees Centigrade Adherence rules Power Specifications Required Refer CB35000 Standard Cell Specification full Testing Levels Conditions Buffers offered CMOS options Note only CMOS buffer sink source current when parametric measurements taken reason that power supply specifications CMOS product written support current. more than buffer active voltage drops supply cause false failure readings. buffers sinking sourcing current internal pull pull down resistors bidi buffers have been disabled having Test positive (max) 0.05 Volts (min)=Vdd-0.05 Volts
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CB35000 SERIES
Table General Interface Electrical Characteristics (Note
Symbol Iklu Vesd
Note
Parameter Level Input Current High Level Input Current Tri-State Output Leakage Input Capacitance Output Capacitance Bidi, Capacitance Latch Current Electrostatic Protection
Conditions =Vss Vo=0V Freq=1MHz Freq=1MHz Freq=1MHz V<Vss, V>Vdd
+/-10 +/-10 +/-10
Unit
Notes
2000 4000
Note Note Note Note
These extended voltage temperature specifications from Temperature Ambient from degrees Centigrade Adherence rules Power Specifications Required Excluding Package Volts Human Body Model
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CB35000 SERIES
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DESIGN CENTRES
Carrollton, 75006-5039 1310 Electronics Drive 2337 Tel.: 214/466-8844 Lincoln, 01773 Bedford Tel.: 617/258-0300 Jose, 95110 2055 Gateway Place Suite Tel.: 408/452-8585
EUROPE FRANCE 94253 Gentilly Cedex avenue Gallieni Tel.: (33-1) 47407575 GERMANY 8011 Grasbrunn Bretonischer Ring Neukeferloh Technopark Tel.: (49-89) 460060 ITALY 20090 Assago (MI) Viale Milanofiori Strade Palazzo A/4/A Tel.: (39-2) 89213215 40033 Casalecchio Reno (BO) Fucini, Tel.: (39-51) 591914 SWEDEN S-16421 Kista Borgarfjordsgatan, 1094 Tel.: (46-8) 7939220 UNITED KINGDOM EIRE Marlow, Bucks Planar House, Parkway Globe Park Tel.: (44-1628) 890800
ASIA/PACIFIC HONG KONG Wanchai 22nd Floor Hopewell Centre Queen's Road East Tel.: (852-5) 8615788 KOREA Seoul floor Shinwon Building 823-14, Kuksman-Dong Kang-Nam-Gu Tel.: (82-2) 553-0399 SINGAPORE Singapore 2056 Industrial Park Tel.: (65) 482-1411 TAIWAN Taipei 11th Floor Section South Road Tel.: (886-2) 755-4111
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics rights reserved SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan United Kingdom U.S.A.

HCMOS STANDARD CELLS FEATURES micron triple layer metal HCMO

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