Triple-level Metal Embedded Memory 3.3V Operation with 5.0V Tolerant I
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Drawn Gate Length (0.45 Leff) Sea-of-Gates Architecture with
Triple-level Metal Embedded Memory 3.3V Operation with 5.0V Tolerant Input Output Buffers High-speed, Gate Delay, 2-input NAND, Nominal Million Used Gates pins System Level Integration Technology Cores: ARM7TDMIand AVR® (8-bit RISC) Microcontrollers, Cores, 10T/100 Ethernet Memory: SRAM, FIFO; Gate Level Embedded Interfaces: CMOS, LVTTL, LVDS, PCI, Tolerant
Embedded Arrays ATL50/E2 Series
Description
ATL50/E2 Series Embedded Array from Atmel offers capability incorporate memory System Level Integration ASIC designs. ATL50/E2 fabricated (drawn) process which combines logic nonvolatile memory without significant penalties memory speed logic density. blocks identical blocks Atmel's AT28 Series standard products. addition nonvolatile memory blocks, ATL50/E also offers system building blocks such microcontrollers, function, cores large number other cores (UART, USART, SCC, etc.). Customers specify their unique embedded array, combining nonvolatile memory, logic, system blocks, cores, SRAM ROM, resulting true system chip.
ATL50/E2 Embedded Array (example)
ASIC
Rev. 1173D-11/99
Absolute Maximum Ratings*
Operating Ambient Temperature.-55°C +125°C Storage Temperature .-65°C +150°C Maximum Input Voltage: Inputs 0.5V tolerant/compliant .VDD5 0.5V Maximum Operating Voltage (VDD) .3.6V Maximum Operating Voltage (VDD5 .5.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Volt Characteristics
Applicable over recommended operating temperature voltage range unless otherwise noted.
Symbol Parameter
Operating Temp Supply Voltage High-level Input Current CMOS Low-level Input Current High-impedance State Output Current Output Short-circuit Current Buffer CMOS, LVTTL High-level Input Voltage CMOS/TTL-level Schmitt CMOS Low-level Input Voltage CMOS/TTL-level Schmitt VHYS Hysteresis TTL-level Schmitt P011 High-level Output Voltage PO11V P011 Low-level Output Voltage PO11V (min) -500 -500 (min) 0.7VDD 0.9VDD 0.7VDD 0.1VDD Buffer VSS, (max), pull VOUT VDD, (max) VOUT VSS, (max) 0.475VDD 0.325VDD VSS, (max), Pull 620K
Buffer
CMOS
Test Condition
Units
VDD, (max)
ATL50/E2 Series
ATL50/E2 Series
Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bidirectional Test Condition 3.3V 3.3V 3.3V Units
Buffers
Programmable output drive 2,000 volt protection Programmable slew rate control Programmable Pullup/Pulldown/Keeper
fault coverage. This method requires only added pins Test Enable Test Mode. This easiest least expensive method designing testability into gate array design. means increasing testability gate array also available. Partitioning, memory array isolation, test point insertion encouraged supported ATL50/E2 Series embedded arrays. Atmel also encourages inclusion Built Self-Test (BIST) techniques whenever possible. Each these methods discussed detail Atmel CMOS Gate Array Design Manual. addition above, ATL50/E Series embedded arrays also support Joint Test Action Group (JTAG) boundary scan architecture Test Access Port (TAP) requirements. required soft hard macros implement IEEE 1149.1 compliant architecture available Atmel's cell library. JTAG architecture requires additional pins test mode, data clock signals.
Design Testability
Atmel supports wide range Design Testability techniques improve percentage design that fully tested. achieving high degree testability, designer reduce design prototype debug time, minimize production test time, improve board system level test diagnostic capability. Synopsys Test Compiler software fully supported Atmel. this system during design, computer will create scan chains design, test vectors will generated provide greater than
Design
Design Systems Supported
Atmel supports several major software systems design with complete cell libraries, well utilities netlist following design systems supported:
System Version 4.4.3 2.1.p2 4.1-s051 3.4B 5.2e Later 98.08, 98.05 Synopsys5.0.1A Exemplar Syntest
verification, test vector verification accurate delay simulations.
Tools Opus- Schematic Layout Verilog- Verilog Simulator Pearl- Static Path Verilog-XL- Verilog Simulator Logic Design Planner- Floorplanner BuildGates- Synthesis (Ambit) Modelsim Verilog VHDL (VITAL) Simulator QuickVHDLVSS- VHDL Simulator Design Compiler- Synthesis Test Compiler- Scan Insertion ATPG Primetime- Static Path VCS- Verilog Simulator Leonardo Spectrum- Synthesis TurboCheck Gate TurboScan TurboFault
Cadence®
Mentor/Model Tech
1998.2f V2.2 V2.2 V1.6
Design Flow
Atmel's Gate Array/Embedded Array design flow structured allow designer consolidate greatest number system components onto same silicon chip, using widely available third party design tools. Atmel's cell library reflects silicon performance over extremes temperature, voltage process, includes effects metal loading, inter-level capacitance edge rise fall times. design flow includes clock tree synthesis customer-specified skew latency goals. extraction performed final design database incorporated into timing analysis. Gate Array/Embedded Array Design Flow, shown following page, provides pictorial description typical interaction between Atmel's design staff customer. Atmel will deliver design kits support customer's synthesis, verification, floorplanning scan insertion activities. Tools such SynopsysTM, Cadence®, Verilog-HDL CTgen Exemplar PathMILL TimeMILL used, many others available. Should design include embedded memory (SRAM, CAM) embedded core, Atmel will conduct design review with customer understand partition Gate Array/Embedded Array define location memory blocks and/or cores that underlayer layout model created. Following Database Acceptance, automated test pattern generation (ATPG) performed, required, scan paths using Synopsysor Sunrisetools, design routed, post-route data extracted. After post-route verification Final Design Review, design taped fabrication.
Definition Requirements
corner pads reserved Power Ground only. other pads fully programmable Input, Output, Bidirectional, Power Ground. When implementing design with compliant buffers, buffer site must reserved VDD5 pin, which used distribute power compliant buffers.
ATL50/E2 Series
ATL50/E2 Series
Gate Array/Embedded Array Design Flow
Deliver Design
Kickoff Meeting
Embedded Array
Define Underlayer
Synthesis/ Translation/ Conversion
Scan/JTAG
Simulation/ Static Path
Floorplan
Embedded Array
Create Underlayer
Database Handoff
Tape Underlayer
Database Acceptance
Fabricate Underlayer
Place Route/ Clock Tree
Verification/ Resimulation
Final Design Review
Tape Personality Layers
Fabricate Personality
Legend
Customer Atmel Joint
Assembly Test
Design Options
Logic Synthesis
Atmel accept netlists VHDL (MIL-STD-454, IEEE 1076) Verilog-HDL format. Atmel fully supports Synopsys VHDL simulation well synthesis. VHDL Verilog-HDL Atmel's preferred database format Gate Array/Embedded Array design.
FPGA Conversions
Atmel successfully translated existing FPGA/PLD designs from most major vendors (Xilinx®, Actel®, Altera®, Atmel) into Atmel ASICs. There four primary reasons convert from FPGA/PLD ASIC. Conversion high volume devices single combined design cost effective. Performance often optimized speed power consumption. Several FPGA/PLDs combined onto single chip minimize cost while reducing on-board space requirements. Finally, situations where FPGA/PLD used fast cycle time prototyping, ASIC provide lower cost answer long-term volume production.
ASIC Design Translation
Atmel successfully translated existing designs from most major ASIC vendors (LSI Logic®, Motorola®, SMOSTM, Oki®, NEC®, Fujitsu®, AMI® others) into Atmel ASICs. These designs have been optimized speed gate count modified logic memory, replicated pin-for-pin compatible, drop-in replacement.
ATL50/E2 Series
ATL50/E2 Series
Macro Cores
(8-bit RISC) Microcontroller (8515)
RISC Microcontroller true 8-bit RISC architecture, ideally suited embedded control applications. offered gate level, soft macro ATL50/E2 family. supports powerful instructions. pre-fetches instruction during prior instruction execution, enabling execution instruction clock cycle. Fast Access RISC register file consists general purpose working registers. These registers eliminate data transfer delay traditional program code intensive accumulator architectures. will interface with program memory data memory. Included, several optional peripherals: UART, 8-bit timer/counter, 16-bit timer/counter, external internal interrupts programmable watchdog timer.
(8-bit RISC) ASIC Core
16-bit
ARM7TDMI Embedded Microcontroller Core
ARM7TDMI (Advanced RISC Machines) powerful 32-bit processor offered embedded core ATL50/E2 series embedded arrays. ARM7TDMI member Advanced RISC Machines ARM) family gener purpose microprocessors, which offer high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers (CISC). This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective chip. Pipelining employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory.
8-bit Data
memory interface been designed allow performance potential realized without incurring high costs memory system. Speed critical control signals pipelined allow system control functions implemented standard low-power logic, these control signals facilitate exploitation fast local
access modes offered industry standard dynamic SRAMs. ARM7TDMI core includes several optional peripheral macros. options offered Real Time Clock, Controller, USART, External Interface, Interrupt, Timer Advanced Power Management Controller.
ARM7TDMI Embedded Microcontroller Core
ATL50/E2 Series
ATL50/E2 Series
Cell Index
Signal Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI22H AOI222 AOI222H AOI2223 AOI2223H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF4T BUF8 BUF12 BUF16 CLA7X DEC4 DEC4N DEC8N DFFBCPX DFFBSRX DFFC DFFR DFFS Description 1-bit Full Adder with Buffered Outputs 2-input 2-input High-drive 3-input 3-input High-drive 4-input 4-input High-drive 5-input 2-input into 2-input 2-input into 2-input High-drive Two, 2-input ANDs into 2-input Two, 2-input ANDs into 2-input High-drive Three, 2-input ANDs into 3-input Three, 2-input ANDs into 3-input High-drive 2-input into 3-input Buffer Buffer Tri-state Driver with Active-high Enable Tri-state Driver with Active-low Enable Buffer Buffer Tri-state Driver with Active-high Enable Buffer Buffer Buffer 7-input Carry Lookahead Decoder Decoder with Active-low Enable Decoder with Active-low Enable Flip-flop Flip-flop with Asynchronous Clear Preset with Complementary Outputs Flip-flop with Asynchronous Reset with Complementary Outputs Flip-flop with Asynchronous Clear Flip-flop with Asynchronous Reset Flip-flop with Asynchronous Site Count(1)
Cell Index (Continued)
Signal Name DFFSR DLY1500 DLY2000 DLY3000 DLY6000 DSSBCPY DSSBR DSSBS DSSR DSSS DSSSR HLD1 INV1 INV1D INV1Q INV1TQ INV2 INV2T INV3 INV4 INV8 INV10 JKFBCPX JKFC LATBG LATBH LATR LATS LATSR MUX2 MUX2H MUX2I Description Flip-flop with Asynchronous Reset Delay Buffer Delay Buffer Delay Buffer Delay Buffer Scan Flip-flop Scan Flip-flop with Clear Preset Scan Flip-flop with Reset Scan Flip-flop with Scan Flip-flop with Reset Scan Flip-flop with Scan Flip-flop with Reset Hold Cell Inverter Dual Inverters Quad Inverters Quad Tri-state Inverter Inverter Tri-state Inverter with Active-high Enable Inverter Inverter Inverter Inverter Flip-flop Clear Preset Flip-flop with Asynchronous Clear Preset Complementary Outputs Flip-flop with Asynchronous Clear LATCH LATCH with Complementary Outputs Inverted Gate Signal LATCH with High-drive Complementary Outputs LATCH with Reset LATCH with LATCH with Reset High-drive with Inverted Output Site Count(1)
ATL50/E2 Series
ATL50/E2 Series
Cell Index (Continued)
Signal Name MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAND5S NAN6 NAN6H NAN8 NAN8H NOR2 NOR2D NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR5S Description with Inverted Output High-drive with Active-low Enable Quad with Active-low Enable Quad with Inverted Output with Inverted Output High-drive with Transmission Gate Data Inputs with Transmission Gate Data Inputs High-drive High-drive with Active-low Enable with Transmission Gate Data Inputs High-drive 2-input NAND Dual 2-input NAND 2-input NAND High-drive 3-input NAND 3-input NAND High-drive 4-input NAND 4-input NAND High-drive 5-input NAND 5-input NAND High-drive 5-input NAND Single Stage 6-input NAND 6-input NAND High-drive 8-input NAND 8-input NAND High-drive 2-input Dual 2-input 2-input High-drive 3-input 3-input High-drive 4-input 4-input High-drive 5-input 5-input Single Stage Site Count(1)
Cell Index (Continued)
Signal Name NOR8 OAI22 OAI22H OAI222 OAI222H OAI22224 OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Note: Description 8-input 2-input into 2-input NAND 2-input into 3-input NAND High-drive Two, 2-input into 2-input NAND Two, 2-input into 2-input NAND High-drive Four, 2-input into 4-input NAND 2-input into 3-input NAND 2-input 2-input High-drive 3-input 3-input High-drive 4-input 4-input High-drive 5-input 2-input Exclusive 2-input Exclusive High-drive 2-input Exclusive 2-input Exclusive High-drive
Site Count(1)
single ATL50/E routing site contains four transistors, N-channels P-channels, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated DoubleCheckTM, Atmel's netlist checker.
ATL50/E2 Series
ATL50/E2 Series
Volt Buffer Cell Index
Cell Name PFIPCI PFPECLL PFPECLR PICH PICI PICS PICSI PO11 PO11F PO11S PO22 PO22F PO22I PO22S PO33 PO33F PO33S PO44 PO44F PO44S PO55 PO55F PO55S Description Input Positive Output Positive Output CMOS Input CMOS Input High-drive CMOS Inverting Input CMOS Input with Schmitt Trigger CMOS Inverting Input with Schmitt Trigger Differential Input Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Inverting Tri-state Output Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow)
Volt Buffer Cell Index
Cell Name PO66 PO66F PO66S PO77 PO77F PO77S PO88 PO88F PO88S PO99 PO99F PO99S POAA POAAF POAAS POBB POBBF POBBS POCC POCCF POCCS PX1L PX2L PX3L PX4L Description Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) XTAL Oscillator XTAL Oscillator XTAL Oscillator XTAL Oscillator
Volt Tolerant(1)
Cell Name PFIPCI PFIPCIV PICH PICI PICS PICSI PICSV PICV PO11 PO11F PO11S PO11V PO11VF PO11VS PO22 PO22F PO22I PO22S PO22V PO22VF PO22VS PO33 PO33F PO33S PO33V PO33VF PO33VS PO44 PO44F PO44S PO44V PO44VF PO44VS PO55 PO55F Description Input Tolerant Input CMOS Input CMOS Input High-drive CMOS Inverting Input CMOS Input with Schmitt Trigger CMOS Inverting Input with Schmitt Trigger Tolerant CMOS Input with Schmitt Trigger Tolerant CMOS Input Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Inverting Tri-state Output Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast)
Volt Tolerant(1)
Cell Name PO55S PO55V PO55VF PO55VS PO66 PO66F PO66S PO66V PO66VF PO66VS PO77 PO77F PO77S PO77V PO77VF PO77VS PO88 PO88F PO88S PO88V PO88VF PO88VS PO99 PO99F PO99S PO99V PO99VF PO99VS POAA POAAF POAAS POAAV POAAVF POAAVS POBB POBBF Description Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast)
ATL50/E2 Series
ATL50/E2 Series
Volt Tolerant(1)
Cell Name POBBS POBBV POBBVF POBBVS POCC POCCF POCCS PX1L PX2L PX3L PX4L Description Tri-state Output (slow) Tolerant Tri-state Output Tolerant Tri-state Output (fast) Tolerant Tri-state Output (slow) Tri-state Output Tri-state Output (fast) Tri-state Output (slow) XTAL Oscillator XTAL Oscillator XTAL Oscillator XTAL Oscillator
Volt Compliant(2)
Cell Name PICV5 PO22V5 PO44V5 Notes: Description Compliant Compliant Tri-state Output Compliant Tri-state Output
Tolerant: accept volt input uses volt power supply. Compliant: accept volt input output. Requires volt power supply.
Embedded Memory
Description
ATL50/E2 Series Embedded Array Memory blocks accessed like static read write cycle without need external components. device contains 64-byte page register allow writing bytes simultaneously. During write cycle, addresses bytes data internally latched. Following initiation write cycle, device will automatically write latched data using internal control timer. write cycle detected polling BUSY. Once write cycle been detected, access read write begin.
Normal Operation Pins
Description During LOAD operation: Rising edge latches address input data LOAD high. CLOCK high, then address input data latched LOAD rises. During READ operation: Rising edge latches address data. Read access time will based rising edge CLOCK valid data out. address bits read from used loading data when write mode. bits input data. bits output data. Activates read mode. Active-high. When high enables data byte mode only. When enables data 16-bit mode. This valid both read write. While active, data loaded. falling edge write operation begins. When LOAD falls address that present address register latched will represent page address data will written address changes CLOCK pulses) should take place while BUSY high. Indicates write progress. This goes high after LOAD falls stays active throughout write cycle time. When high will allow loading data preventing write initiated unwanted control signal edges. External, active-low, reset which initializes clears BUSY low. Power reset. High power afterwards. confused with system power reset. This signal most generally will used. External clock control write cycle timing. This generated from 13.56 carrier frequency when contactless mode. specific timing requirements other than fixed frequency kHz. contactless mode this signal will high, enabling external clock (OSC_128 kHz) contacted mode this signal will internal oscillator will control write cycle timing.
CLOCK
AIN<12:0> DIN<15:0> DOUT<15:0> READ BYTEMD
LOAD BUSY WRTLOCK RESETB OSC_128 EXT_CLK
ATL50/E2 Series
ATL50/E2 Series
Test Mode Pins
BLKMD BLKDAT BLKE BLKO TSTMD CLEAR INCR MARGIN VMARGIN Description When high, block write will performed. Data written when block mode. BLKMD, then make BLKDAT. Enables BLKDAT data written even pages. Active-high. Enables BLKDAT data written pages. Active-high. Converts address register address counter TSTMD. Clears address register when high. rising edge, increments address when TSTMD high. Used read mode read cell with bias condition. READ MARGIN high, read margin mode. Bias condition used when MARGIN high.
Embedded Memory Normal Operations
BYTE MODE SIGNAL BYTEMD: BYTEMD controls will read/write byte word time. BYTEMD high, then only byte read written BYTEMD low, then 2-byte word will read written BYTEMD (word mode) byte addressed, then byte will active well. same applies bytes READ: Reads byte words bits) according BYTEMD signal. When LOAD READ high, rising edge CLOCK latches address data data stored memory location determined address pins asserted DOUT[15:0] pins. Read mode deactivated when LOAD BUSY high. BYTE WRITE: When WRTLOCK LOAD high, rising edge CLOCK latches address input data. Write cycle starts when LOAD falls. signal CLOCK free running clock. that case, LOAD should change synchronously with CLOCK falling preclude inadvertent cases CLOCK LOAD momentarily high together. CLOCK static high, then byte write could also accomplished using LOAD signal alone. that case, address data acquired LOAD rising. PAGE WRITE: page write operation allows bytes data written into device during single internal programming period. page write operation initiated same manner byte write. first byte written then followed additional bytes clock CLOCK while holding LOAD high. Data loaded into data latches order within page boundary bytes.
address register converted into address counter rising edge INCR increments address. CLEAR presets address counter 7FFh. CLOCK longer latches address. first INCR rising edge places address counter 000h. READ: While READ TSTMD high, clear address counter pulsing CLEAR high. High pulse INCR increment address counter data stored memory location determined address counter asserted DOUT[15:0] pins. WRITE: Write Operation test mode similar normal write except address changed INCR signal. With LOAD low, clear address counter with high pulse CLEAR. Next, assert LOAD pulse INCR increment address. Then rising edge CLOCK latches DIN[15:0]. Subsequent bytes written changing DIN, pulsing INCR then latching data with CLOCK. Write cycle starts when LOAD falls. continue writing following pages, activate CLEAR. BLOCK WRITE: Block write could used (1's) clear (0's) whole While BLKMD high BLKDAT valid, assert LOAD. BLKDAT then acquired rising edge CLOCK. Write operation begins after LOAD falls. BLKDAT must stable while LOAD CLOCK high. CLOCK left high always block writing accomplished using only LOAD signal. EVEN/ODD BLOCK PAGE WRITES: While BLKE/BLKO high, assert LOAD. While valid, pulse CLOCK latch data continue whole page. Write operation begins after LOAD falls.
Embedded Memory Test Modes Operations
test mode (TSTMD
Waveforms
Byte Write
Low: TSTMD BLKMD BLKE BLKO MARGIN High: RESETB READ CLEAR INCR BLKDAT VMARGIN
WRTLOCK
LOAD
CLOCK
BUSY
AIN<0-X>
DIN<0-X>
Write Page/Partial Page
Low: TSTMD BLKMD BLKE BLKO MARGIN High: RESETB READ CLEAR INCR BLKDAT VMARGIN
WRTLOCK
LOAD
BUSY
CLOCK
(<=61)
AIN<0-X>
DIN<0-X>
ATL50/E2 Series
ATL50/E2 Series
Read
Low: TSTMD BLKMD BLKE BLKO MARGIN WRTLOCK CLEAR INCR BLKDAT VMARGIN LOAD
READ
CLOCK
AIN<0-X>
DOUT<0-X>
Writing with Address Counter test mode)
Low: BLKMD BLKE BLKO MARGIN READ BLKDAT VMARGIN
WRTLOCK
TSTMD
CLEAR
LOAD INCR
CLOCK
BUSY
Reading with Address Counter test mode)
Low: LOAD TSTMD BLKMD BLKE BLKO MARGIN WRTLOCK INCR BLKDAT VMARGIN
READ
TSTMD
CLEAR
INCR
CLOCK
DOUT
Block Writing test mode)
Low: WRTLOCK TSTMD BLKE BLKO MARGIN CLEAR READ INCR VMARGIN
BLKDAT
BLKMD
LOAD
CLOCK
BUSY
ATL50/E2 Series
ATL50/E2 Series
Even/Odd Block Page Writes
Low: TSTMD BLKMD MARGIN WRTLOCK CLEAR INCR BLKDAT VMARGIN
BLKx
LOAD
CLOCK
BUSY
10ms
Notes:
Page loading will written even pages BLKE active pages BLKO active. Page loading also accomplished address counter write operation.
Read with Floating Gate Margin
Low: LOAD TSTMD BLKMD BLKE BLKO WRTLOCK CLOCK CLEAR INCR BLKDAT
READ
MARGIN analog level
VMARGIN
DOUT
data change examined
address
Note:
Address also generated address counter read operation.
Timing
Supply Range 2.2V Vsupply 3.9V Read Access Time Erase/Write Time
Standard Test Interface (STI)
Description
generic serial test circuit used insure clean usable test interface embedded EEPROM. This interface currently provides ability block, page byte read/write EEPROM core well perform margin testing EEPROM cells. Access test circuit through four-wire interface which multiplexed into customer logic kept stand alone interface with minimum restrictions customer. interface also includes provisions allow additional user test modes added needed. Access EEPROM through internal address counter.
Block Diagram
load clock
sti_din sti_load sti_clock sti_read sti_bytemdb sti_resetb sti_wrtlock sti_ext_osc sti_osc_128kHz blkmd blkdat blke blko tstmd incr clear margin
dout busy
User
read bytemdb resetb wrtlock ext_osc osc_128kHz
EEPROM
RB_W TEST
supervolt
rb_w test test_hv
ATL50/E2 Series
ATL50/E2 Series
Programming with Interface
Note that numbers expressed from left right. data loaded starting with read from MSB.
Pins Rb/W TEST Type Bidirectional Input Input Input Function Mode) Serial data input/output test modes. While internal write taking place, this will output busy signal (low logic level) ready (high logic level) when finished. Read not/write. This functions active-low read, active-high write controls data direction pin. Test mode signal, used initialize change test modes. Margin voltage supplied device through this during EEPROM margin testing. Clock, used clock serial data test mode information.
Test Mode Codes
Number Binary Number 00000000b 00000011b 00000100b 00000101b 00000110b 00000111b 00100001b Name Retest Test Block Write Even Page Block Write Page Block Write Address Preset Margin Read bytemd read/write
Device Operation
STR: Serial Test Register. INITIALIZATION: device will power with test mode disabled. When allowed, test mode entered raising voltage TEST volts. this time, test mode pins which multiplexed with customer pins must become enabled test purposes. Also this time, customer logic pins must become "don't cares" test control interface since these pins guaranteed driven during test mode. test mode will remain effect until either another code entered into device powered off. WRITING TEST MODE: With TEST pull high, shift each test code (LSB MSB) into STR. Rb/W "don't care" held high consistent with core write. Doing this will cause write core. valid test modes will become effective when TEST returns remains effect until changed. waveforms.
Test Mode Code Load (address present example)
TEST
addr Test mode applied
Test interface enabled
TEST MODE RESET: Writing (MSB 00000000b LSB) will cause device terminate test mode. will contain power indicate normal device operation. ADDRESS PRESET: Writing (00000110b) will cause EEPROM address counter preset maximum address. BYTE OPERATIONS: Writing (00000001b) will enable normal read/write operations EEPROM core. following operations supported:
READ: With Rb/W low, data from core will output starting with addressed byte pointed address counter. Data guaranteed valid until first pulse takes place. address counter will increment needed with produce continuous data stream without regard physical nature core (bit byte wide). address counter will wrap from address address.
Normal Core Read
TEST Rb/W
addr
addr
BYTE WRITE: With Rb/W high, shift data starting with byte into using CLK. When Rb/W falls, write cycle will initiated. ready/busy signal will present I/O. byte write after address preset will
write byte address After byte write finished, next sequential byte written same fashion device clocked (apply with Rb/W low) higher address next write sequence.
ATL50/E2 Series
ATL50/E2 Series
Core Byte Write
TEST Rb/W BUSY busy ready bits_addr write cycle
PAGE WRITE: This operation allows wordline (512 bytes) written same time. Perform same sequence byte write operation times, holding Rb/W high throughout. address counter will increment needed accomplish this. When Rb/W falls, write cycle will initiated. ready/busy signal will present
BUSY. page write performed after address preset opcode will write page EEPROM (the page starting address waiting page write finish then writing another page, multiple sequential pages written.
Core Page Write (two byte example)
TEST Rb/W busy BUSY addr write cycle ready
addr bits
BLOCK MODE: Block modes performed entering (00000011b) into STR, which enables wordlines bitlines core. block write (zeros) occurs taking Rb/W high, pulling low, pulsing clock bytes
allowing Rb/W fall. block clear (ones) takes place high. write cycle will initiated when Rb/W falls. read/busy signal will present I/O.
Block Write (two bytes clear)
TEST Rb/W ready bits busy
CORE MARGIN MODE: This mode entered with (00000111b) code. This mode allows cell margins tested placing test voltage TEST prior reading
core. practical voltage range this test voltage -0.7 volts -0.7 volts because circuit constraints margin path.
Core Margin Read
margin voltage
TEST Rb/W
addr
addr
EVEN PAGE BLOCK MODE: code (00000100b) causes even wordlines selected. normal page write should then executed (see Page Write) load data into each even page within core. This mode, conjunction with page block mode, allows certain test patterns written quickly.
PAGE BLOCK MODE: code (00000101b) causes wordlines selected. normal page write should then executed (see Page Write) lead data into each page within core. This mode, conjunction with even page block mode, allows certain test patterns written quickly.
ATL50/E2 Series
ATL50/E2 Series
Advanced Packaging
ATL50/E Series Embedded Arrays offered wide variety standard packages, including plastic ceramic quad flatpacks, thin quad flatpacks, ceramic grid arrays, ball grid arrays. High volume onshore offshore contractors provide assembly test commercial product, with prototype capability Colorado Springs. Custom package designs also available required meet customer's specific needs, supported through Atmel's package design center. When standard package cannot meet customer's need, package designed precisely application maintain performance obtained silicon. Atmel delivered custom-designed packages wide variety configurations.
Packaging Options
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super Low-profile Chip-scale BGA(1) Notes: Partial List Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 144, 160, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169, 208, 217, 225, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 168, 204, 240, 256, 304, 352, 432, 560, 132, 144, 160, 180, 100,
Atmel Headquarters
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Atmel Operations
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Asia
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Japan
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Atmel Corporation 1999. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life suppor devices systems. Actel Altera Motorola®, Epson Electronics America Inc®, NEC®, Fujitsu®, Synopsys VHDL Compiler Compiler Xilinx trademarks their respective owners. other marks bearing
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