LTC1325 provides core flexible, cost-effective solution integrated bat

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LTC1325 provides core flexible, cost-effective solution integrated bat

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LTC1325 Microprocessor-Controlled Battery Management System
LTC1325 provides core flexible, cost-effective solution integrated battery management system. monolithic CMOS chip controls fast charging nickel-cadmium, nickel-metal-hydride, lead-acid lithium batteries under microprocessor control. device features programmable 111kHz constant current source controller with built-in driver, 10-bit ADC, internal voltage regulator, discharge-before-charge controller, programmable battery voltage attenuator easy-to-use serial interface. chip operate five modes: power shutdown, idle, discharge, charge gauge. power shutdown supply current drops 30µA idle mode, reading made without switching noise affecting accuracy measurement. discharge mode, battery discharged external transistor while battery being monitored LTC1325 fault conditions. charge mode terminated while monitoring combination battery voltage temperature, ambient temperature charge time. LTC1325 also monitors battery fault conditions before during charging. gauge mode LTC1325 allows total charge leaving battery calculated.
registered trademarks Linear Technology Corporation.
Fast Charge Nickel-Cadmium, Nickel-Metal-Hydride, Lithium Lead-Acid Batteries under Control Flexible Current Regulation: Programmable 111kHz Current Regulator with Built-In PFET Driver PFET Current Gating with External Current Regulator Current Limited Transformer Discharge Mode Measures Battery Voltage, Battery Temperature Ambient Temperature with Internal 10-Bit Battery Voltage, Temperature Charge Time Fault Protection Built-In Voltage Regulator Programmable Battery Attenuator Easy-to-Use 4-Wire Serial Interface Accurate Gauge Function Wide Supply Range: 4.5V Charge Batteries with Voltages Greater Than Charge Batteries from Charging Supplies Greater Than Digital Input Pins High Impedance Shutdown Mode
APPLICATIONS
System Integrated Battery Charger
TYPICAL APPLICATION
Battery Charger NiCd NiMH Cells
10µF IRF9730 1N6818
LTC1325 (e.g. 8051) p1.4 p1.3 p1.2
CREG 4.7µF
DOUT
PGATE VBAT TBAT TAMB SENSE FILTER
0.1µF CREG 22µF THERM
THERM
4.5V
62µH
RTRK
RDIS IRFZ34
RSENSE
LTC1325 TA01
LTC1325
ABSOLUTE MAXIMUM RATINGS
(Notes
PACKAGE/ORDER INFORMATION
VIEW DOUT PACKAGE 18-LEAD PDIP PGATE VBAT TBAT TAMB SENSE FILTER PACKAGE 18-LEAD PLASTIC WIDE
Other Pins 0.3V 0.3V Operating Temperature Range 70°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1325CN LTC1325CSW
TJMAX 125°C, 75°C/ TJMAX 125°C, 100°C/ (SW)
Consult factory Industrial Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL VREG LDREG LIREG TCREG VDAC PARAMETER Supply Voltage Supply Current Supply Current Regulator Output Voltage Regulator Load Regulation Regulator Line Regulation Regulator Output Tempco Output Voltage CONDITIONS
±5%, 25°C, unless otherwise noted.
1200 3.072
VHYST VBATR VBATP VEDV VLTF, VMCV VHTF VOS(GG) TOLBATD
Fault Comparator Hysteresis Fault Comparator Offset VBAT BATR VBAT BATP Internal Voltage LTF, Voltage Range Voltage Range Gauge Gain Gauge Offset Internal Filter Resistor Battery Divider Tolerance Input Voltage Input High Voltage Level Input Current High Level Input Current
Inputs Load Power-Down Mode, Inputs Load Sourcing Only, IREG Load, 4.5V Load, 70°C 100% Duty Ratio, ICHRG (Note 100% Duty Ratio, ICHRG 100% Duty Ratio, ICHRG 100% Duty Ratio, ICHRG I/10 VHTF VEDV 0.9V, VBATR 100mV VMCV VLTF VHTF VEDV 0.9V, VBATR 100mV VMCV VLTF
3.047
2000 3.097
UNITS mV/mA µV/V ppm/°C
0.4V VSENSE 0.4V VSENSE (Note Division Ratios CLK, CLK, VCLK, VDIN VCLK, VDIN
1000
LTC1325
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Output Voltage Output High Voltage Hi-Z Output Leakage VOHFET PGATE Output High VOLFET PGATE Output tdDO Delay Time, DOUT Valid tdis Delay Time, DOUT Hi-Z Delay Time, DOUT Enabled thDO Time DOUT Remains Valid After trDOUT DOUT Rise Time tfDOUT DOUT Fall Time fCLK Serial Clock Frequency trPGATE PGATE Rise Time tfPGATE PGATE Fall Time fOSC Internal Oscillator Frequency Converter Offset Error Linearity Error Full-Scale Error On-Channel Leakage Off-Channel Leakage
±5%, 25°C, unless otherwise noted.
CONDITIONS DOUT, IOUT 1.6mA DOUT, IOUT 1.6mA 4.5V 4.5V Test Circuits Test Circuits Test Circuits Test Circuits Test Circuits Test Circuits CLOAD 1500pF CLOAD 1500pF Charge Mode, Fail-Safes Disabled Channel (Note Channel (Notes Channel (Note Channel Only (Notes Channel (Notes
0.05 0.05 ±0.5
UNITS
RECO
SYMBOL thDI tdsuCS tdsuDI tWHCLK tWLCLK tWHCS tWLCS
denotes specifications which apply over full operating temperature range. Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect pin. Note VREG within specified limits, (Pin 500kHz, unless otherwise stated. clock serial CLK.
CHARACTERISTICS
CONDITIONS UNITS Cycles Cycles
PARAMETER Hold Time, After Setup Time, Before First Setup Time, Stable Before First High Time Time High Time Between Data Transfers Time During Data Transfer
MSBF MSBF
Note Linearity error specified between actual points transfer curve. Note Channel leakage measured after channel selection. Note gauge offset excludes offset error. Note VDAC(Duty Ratio)/RSENSE, where VDAC output voltage with control bits duty ratio RSENSE determined user.
LTC1325 TYPICAL PERFORMANCE CHARACTERISTICS
Regulator Output Voltage Load Current
3.077 27°C
REGULATOR OUTPUT VOLTAGE
3.076 3.075 3.074
4.5V
3.079 3.078 3.077 3.076 3.075 3.074 3.073 3.072
SUPPLY CURRENT (µA)
REGULATOR OUTPUT VOLTAGE
3.073 3.072 3.071 3.070 LOAD CURRENT (mA)
Charge Current Battery Voltage
OUTPUT VOLTAGE (mV)
CHARGE CURRENT (mA)
12V, RSENSE 100µH, IRF9531
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
BATTERY VOLTAGE
1325
Fault Comparator Threshold Temperature
FAULT COMPARATOR THRESHOLD
FAULT COMPARATOR THRESHOLD
VCELL HIGH
VBAT BATP HIGH,
GAUGE GAIN OFFSET (COUNTS)
VTBAT HIGH, VHTF 0.4V
VCELL BATR HIGH
TEMPERATURE (°C)
1325
Regulator Output Voltage Temperature
3.082 3.081 3.080 IREG 1000 TEMPERATURE (°C)
Supply Current Temperature
4.5V
4.5V
TEMPERATURE (°C)
1325
1325
1325
Output Voltage Temperature
Shutdown Current Temperature
4.5V TEMPERATURE (°C)
1325
1325
Fault Comparator Threshold Temperature
Gauge Gain Offset Temperature
-1.0 -1.5 -2.0 -2.5 -3.0 GAUGE GAIN -4.0 -4.5 TEMPERATURE (°C) GAUGE OFFSET VSENSE -0.2V 0.4V INCLUDES CHANGES VREG WITH TEMPERATURE
VCELL HIGH, VMCV 2.8V VTBAT HIGH, VLTF 2.8V VCELL HIGH, VMCV 1.6V VTBAT HIGH, VLTF 1.6V VTBAT HIGH, VHTF 1.35V
TEMPERATURE (°C)
1325
1325
LTC1325 TYPICAL PERFORMANCE CHARACTERISTICS
PGATE Rise Time Load Capacitance
1200 1000 1000
DIFFERENTIAL NONLINEARITY (LSB)
PGATE RISE TIME (ns)
27°C 70°C
PGATE FALL TIME (ns)
LOAD CAPACITANCE (nF)
1325
Discharge Rise Fall Time Load Capacitance
DISCHARGE RISE FALL TIME (µs)
MINIMUM CHARGE VOLTAGE
RISE TIME
FALL TIME LOAD CAPACITANCE (nF)
1325
1325
INTEGRAL NONLINEARITY (LSB)
70°C 27°C
Oscillator Frequency Temperature
DOUT ENABLE DELAY TIME (ns)
DOUT VALID DELAY TIME (ns)
OSCILLATOR FREQUENCY (kHz)
TEMPERATURE (°C)
1325
PGATE Fall Time Load Capacitance
Differential Nonlinearity
fCLK 500kHz
LOAD CAPACITANCE (nF)
LTC1325
27°C
70°C
-0.5
-1.0
1024 CODE
1325
Minimum Charging Supply Number Cells
RSENSE 0.15, 1,VR0 10µH 100µH IRF9Z30PFET, 1N5819 DIODE
Integral Nonlinearity
fCLK 500kHz
RSENSE 25µH 100µH IRF9Z30PFET, 1N5819 DIODE 27°C, NiCd BATTERIES VCELL 1.4V NOMINAL
-0.5
-1.0
NUMBER CELLS
1024 CODE
1325
DOUT Enable Delay Time Temperature
TEMPERATURE (°C)
DOUT Valid Delay Time Temperature
DOUT GOING HIGH DOUT GOING
TEMPERATURE (°C)
1325
1325
LTC1325
FUNCTIONS
(Pin Internal Regulator Output. regulator provides steady 3.072V internal analog circuitry provides temperature stable reference voltage generating MCV, HTF, thermistor bias voltages with external resistors. Requires 4.7µF greater bypass capacitor ground. DOUT (Pin Data Output Signal Serial Interface. DOUT tied together form 3-wire interface, remain separated form 4-wire interface. Data transmitted falling edge (Pin (Pin Data Input Signal Serial Interface. data latched into chip rising edge (Pin (Pin Chip Select Signal Serial Interface. (Pin Clock Serial Interface. (Pin Minimum Allowable Battery Temperature Analog Input. generated resistive divider between (Pin ground. (Pin Maximum Allowable Cell Voltage Analog Input. generated resistive divider between (Pin ground. (Pin Maximum Allowable Battery Temperature Analog Input. generated resistive divider between (Pin ground. (Pin Ground. FILTER (Pin 10): external filter capacitor connected this pin. filter capacitor connected output internal resistive divider across battery reduce switching noise while charging. gauge mode, along with internal form lowpass filter average voltage across sense resistor. SENSE (Pin 11): Sense controls switching 111kHz constant current source charging mode. Sense connected external sense resistor RSENSE negative side battery. charging loop forces average voltage Sense equal programmable internal reference voltage VDAC. battery charging current equal VDAC/RSENSE. gauge mode voltage across Sense filtered network CF), amplified inverting gain four, then multiplexed average discharge current through battery measured total charge leaving battery calculated. (Pin 12): General Purpose Input. TAMB (Pin 13): Ambient Temperature Input. Connect external thermistor network. used. used another general purpose input. TBAT (Pin 14): Battery Temperature Input. Connect external thermistor network. used. VBAT (Pin 15): Battery Input. internal voltage divider connected between VBAT Sense pins normalize battery measurements cell voltage. divider programmable following ratios: 1/1, 1/2, 1/15, 1/16. shutdown gauge modes divider disconnected. (Pin 16): Active High Discharge Control Pin. Used turn external transistor which discharges battery. PGATE (Pin 17): Driver Output. Swings from VDD. (Pin 18): Positive Supply Voltage. 4.5V 16V.
LTC1325
BLOCK DIAGRAM
DIGITAL REGULATOR DIGITAL INPUT CIRCUITS 3.072V ANALOG REGULATOR
DOUT
SERIAL
10-BIT CONVERTER
DIVIDER TOUT TIMEOUT LOGIC
TEST CIRCUITS
Load Circuit tdDO,
1.4V
DOUT 100pF
LTC1325 TC01
ANALOG DIGITAL REFERENCE BATP, BATR, FMCV, FEDV, FHTF, FLTF, CONTROL LOGIC MOD0 MOD1, FAULT DETECT CIRCUITRY MSBF SGL/DIFF DIV0 DIV3 TAMB TBAT VBAT GAUGE MOD0 MOD1, VR1, CHARGE 111kHz OSCILLATOR CHARGE LOOP GAUGE SENSE FILTER PGATE DUTY RATIO GENERATOR
LTC1325
Load Circuit tdis
TEST POINT
DOUT 100pF
tdis WAVEFORM tdis WAVEFORM
LTC1325 TC02
LTC1325
TEST CIRCUITS
Voltage Waveforms DOUT Delay Time, tdDO Voltage Waveforms DOUT Rise Fall Times,
2.4V
0.8V tdDO 2.4V
LTC1325 TC04
0.4V
DOUT 0.4V
LTC1325 TC03
Channel Leakage
3.072V
Voltage Waveforms tdis
IOFF
CHANNEL
DOUT WAVEFORM (SEE NOTE tdis DOUT WAVEFORM (SEE NOTE
CHANNELS
NOTE: EXTERNAL CHANNELS ONLY-- TBAT, TAMB
LTC1325 TC05
NOTE WAVEFORM OUTPUT WITH INTERNAL CONDITIONS SUCH THAT OUTPUT HIGH UNLESS DISABLED NOTE WAVEFORM OUTPUT WITH INTERNAL CONDITIONS LTC1325 TC06 SUCH THAT OUTPUT UNLESS DISABLED
Voltage Waveforms
START
0.4V
DOUT
THREE-STATE
NULL 0.4V
LTC1325 TC07
LTC1325 DIAGRA
MSB-FIRST DATA (MSBF START DOUT HI-Z COMMAND WORD NULL DATA BATP STATUS WORD HI-Z MSBF
MSB-FIRST DATA (MSBF START DOUT HI-Z COMMAND WORD NOTE: TIMING DIAGRAM SHOWS POSSIBLE COMMAND WORDS. REFER FUNCTIONAL DESCRIPTION INFORMATION CONSTRUCT COMMAND WORD NULL DATA BATP STATUS WORD HI-Z
LTC1325
FUNCTIONAL DESCRIPTIO
GENERAL
During normal operation, command word shifted into chip serial interface, then measurement made 10-bit reading chip status word shifted out. command word configures LTC1325 forces into five modes: power shutdown, idle, discharge, charge gauge mode. power shutdown mode, analog section turned supply current drops 30µA. voltage regulator, which provides power internal analog circuitry external bias networks, shut down. voltage divider across battery disconnected only voltage regulator serial interface logic left During idle mode, chip fully powered discharge, charge, gauge circuits off. chip placed idle mode momentarily while charging battery, allowing measurement made without switching noise from current source affecting accuracy reading. mode command bits picked they appear DIN, allowing charging loop turn settle while remainder command word being shifted
During discharge mode, battery discharged external transistor series resistor. battery monitored fault conditions. charge mode, monitors battery's voltage, temperature ambient temperature 10-bit ADC. Termination methods such -VBAT, VBAT/Time, TBAT, TBAT/Time, (TBAT TA), maximum temperature, maximum voltage maximum charge time accurately implemented software. LTC1325 also monitors battery fault conditions. gauge mode, average voltage across sense resistor measured determine average battery load current. sense voltage filtered circuit, multiplied inverting gain four, then converted ADC. then accumulate measurements time average determine total charge leaving battery. circuit consists internal resistor external capacitor connected Filter pin.
LTC1325
FUNCTIONAL DESCRIPTIO
COMMAND WORD command word bits long contains information needed configure control chip. power-up bits cleared logical "0."
SGL/ DIFF DIV3 MSBF
LTC1325
START MOD0 MOD1 DIV0 FSCLR DIV1 DIV2
Figure Command Word
Start (Start) first "logical one" clocked into input after goes start bit. start initiates data transfer leading zeros which precede this logical will ignored. After start received, remaining bits command word will clocked Bits Mode Select (MOD0 MOD1) mode bits determine which four modes chip will idle, discharge, charge gauge.
MOD1 MOD0 DESCRIPTION Idle Discharge Charge Gauge
Single-Ended Differential Conversion (SGL/DIFF) SGL/DIFF determines whether makes singleended measurement with respect ground differential measurement with respect Sense pin.
SGL/DIFF DESCRIPTION Single-Ended Conversion Differential Conversion (with respect Sense)
MSB-First/LSB-First (MSBF) data programmed MSB-first LSB-first sequence using MSBF bit. Serial description details.
MSBF DESCRIPTION LSB-First Data Follows MSB-First Data MSB-First Data Only
Bits Data Input Select (DS0 DS2) DS2, select which circuit connected input. unlisted combinations.
DESCRIPTION Gauge Output Battery Temperature Pin, TBAT Ambient Temperature Pin, TAMB Battery Divider Output Voltage, VCELL
Bits Battery Divider Ratio Select (DIV0 DIV3) DIV3, DIV2, DIV1 DIV0 select division ratio voltage divider across battery.
DIV3 DIV2 DIV1 DIV0 DESCRIPTION (VBAT VSENSE)/1 (VBAT VSENSE)/2 (VBAT VSENSE)/3 (VBAT VSENSE)/4 (VBAT VSENSE)/5 (VBAT VSENSE)/6 (VBAT VSENSE)/7 (VBAT VSENSE)/8 (VBAT VSENSE)/9 (VBAT VSENSE)/10 (VBAT VSENSE)/11 (VBAT VSENSE)/12 (VBAT VSENSE)/13 (VBAT VSENSE)/14 (VBAT VSENSE)/15 (VBAT VSENSE)/16
LTC1325
FUNCTIONAL DESCRIPTIO
Power Shutdown (PS) selects between normal operating mode, shutdown mode.
DESCRIPTION Normal Operation Shutdown Circuits Except Digital Inputs
Bits Duty Ratio Select (DR0 DR2) DR2, select duty cycle charging loop operation (not 111kHz duty cycle). last three selections place chip into test mode should used.
DESCRIPTION 1/16 Test Mode Test Mode Test Mode
Fail-Safe Latch Clear (FSCLR) When FSCLR one, internal fail-safe timer reset fail-safe latches reset. FSCLR automatically reset when goes high.
FSCLR DESCRIPTION Action Reset Fail-Safe Timer Latches
Bits Timeout Period Select (TO0 TO2) TO2, select desired fail-safe timeout period,tOUT. power-up, default timeout minutes.
TIMEOUT (MINUTES) Indefinite Timeout)
Bits Charging Loop Reference Voltage Select (VR0 VR1) select desired reference voltage VCHRG charging loop. charging loop will force average voltage Sense equal VDAC. average charging current VDAC/RSENSE (see Figure
VDAC (mV)
STATUS WORD status word bits long contains status internal fail-safe circuits.
BATP BATR FMCV FEDV FHTF FLTF
LTC1325
Figure Status Word
Battery Present (BATP) BATP indicates presence battery. when voltage VBAT falls below (VDD 1.8V). BATP when battery removed VBAT pulled high RTRK (see Figure
BATP CONDITIONS (VDD 1.8) VBAT VBAT (VDD 1.8)
Battery Reversed (BATR) Shorted BATR indicates when battery connected backwards shorted. when battery cell voltage output battery divider VCELL below 100mV.
BATR CONDITIONS VCELL 100mV VCELL 100mV
LTC1325
FUNCTIONAL DESCRIPTIO
Maximum Cell Voltage (FMCV) indicates when battery cell voltage exceeded preset limit. when VCELL greater than voltage pin.
FMCV CONDITIONS VCELL VMCV VCELL VMCV
Discharge Voltage (FEDV) indicates when battery cell voltage dropped below internally preset limit. when battery cell voltage output voltage divider VCELL less than 900mV.
FEDV CONDITIONS VCELL 900mV VCELL 900mV
High Temperature Fault (FHTF) indicates when battery temperature high. Using negative thermistor, when voltage TBAT less than voltage pin.
FHTF CONDITIONS TBAT VHTF TBAT VHTF
Temperature Fault (FLTF) indicates when battery temperature low. Using negative thermistor, when voltage TBAT greater than voltage pin.
FLTF CONDITIONS TBAT VLTF TBAT VLTF
Timeout (tOUT) indicates that battery charging time exceeded preset limit. when internal timer exceeds limit command bits TO0, TO2.
TOUT CONDITIONS Timeout Occurred Timeout Occurred
Fail-Safe Occurred (FS) indicates that fault detection circuits halted discharging charging cycle. when EDV, LTF, HTF, fault occurs during discharge. During charging, when MCV, LTF, HTF, fault occurs. reset command word FSCLR.
CONDITIONS Fail-Safe Occurred Fail-Safe Occurred
DETAILED DESCRIPTION Fault Conditions LTC1325 monitors battery fault conditions before during discharge charge (see Figure They include: battery removed/present (BATP), battery reversed/shorted (BATR), maximum cell voltage exceeded
1.8V BATP RTRK
3.072V LINEAR REGULATOR
PROGRAMMABLE BATTERY DIVIDER
VBAT
FMCV
SENSE
FEDV BATR FHTF FLTF
900mV 100mV
TBAT
LTC1325
Figure Fail-Safe Fault Detection Circuitry
LTC1325
FUNCTIONAL DESCRIPTIO
(MCV), minimum cell voltage exceeded (EDV), high temperature limit exceeded (HTF), temperature limit exceeded (LTF) time limit exceeded (tOUT). When fault condition occurs, discharge charge loops disabled prevented from turning fail-safe (FS) set. chip reset shifting command word with fail-safe clear FSCLR set. 8-bit status word contains state each fault condition. Power Shutdown Mode Command: MOD1 MOD0 Status: BATP BATR FMCV FEDV FHTF FLTF tOUT
power shutdown mode, analog section turned supply current drops 30µA. voltage regulator, which provides power internal analog circuitry external bias networks, shut down. voltage divider across battery disconnected only circuit left voltage regulator serial interface logic. Idle Mode Command: MOD1 MOD0 Status: BATP BATR FMCV FEDV FHTF FLTF tOUT
chip enters idle mode when proper mode command bits power shutdown command cleared. During idle mode, chip fully powered, discharge, charge gauge circuits off. chip placed idle mode momentarily while charging battery, allowing measurement made without switching noise from current source affecting accuracy reading. mode command bits picked they appear DIN, that while rest command word being shifted charging loop time settle before measurement made. Discharge Mode Command: MOD1 MOD0 Status: BATP BATR FMCV FEDV FHTF FLTF tOUT
chip enters discharge mode when proper mode command bits power shutdown command clear. fault condition does exist, then pulled internal driver. voltage used turn external transistor which discharges battery through external series resistor RDIS. Discharging will continue until command word input change mode fault condition occurs. Charge Mode Command: MOD1 MOD0 Status: BATP BATR FMCV FEDV FHTF FLTF tOUT chip enters charge mode when proper mode command bits power shutdown command clear. fault condition does exist then charging begin. Charging will continue until command word input change mode fault condition occurs. charge current regulated programmable 111kHz buck current regulator, using PFET gate external current regulator current limited transformer. 111kHz Controller block diagram charging loop connected buck current regulator shown Figure operate either continuous discontinuous mode. loop forces average voltage across sense resistor equal voltage output DAC, that charging current becomes VDAC/RSENSE. With switch others off, amplifier along with configured integrator with 16kHz bandwidth. output integrator average difference between voltage across sense resistor output voltage. rising edge oscillator waveform triggers shot which sets flip-flop output high. This turns external PFET pulling gate driver. With current through inductor starts
LTC1325
FUNCTIONAL DESCRIPTIO
CHARGE
DUTY RATIO GENERATOR
111kHz OSCILLATOR SHOT 16pF 500k 125k
VOLTAGE 18mV 34mV 55mV 160mV
Figure Charging Loop Block Diagram
rise does voltage across sense resistor. When voltage across sense resistor greater than output integrator, comparator changes state. This resets flip-flop turned off. Catch diode clamps drain diode drop below ground when inductor flies back current through inductor starts drop. voltage across sense resistor also drops reach zero stay there until next clock cycle begins. average charging current output (VDAC) duty ratio generator. VDAC programmed four values with following ratios: 1/3, 1/10. duty ratio 1/16, 1/8, 1/4, When duty ratio duty ratio generator output always charge loop operates continuously (see Figure other duty ratio settings, duty generator output square wave with period seconds. time which generator output varies with duty ratio setting.
4.5V PGATE IRF9Z30 1N5818 RDIS BATTERY SENSE FILTER RSENSE IRFZ34 RTRK DISCHARGE 3.072V VDAC VR0, CHIP (GAS GAUGE) BOUNDARY
LTC1325
ample, duty ratio programmed, generator output only 42/2 seconds. Since loop operates only every seconds, average charging current halved. general, average charging current ICHRG VDAC(Duty Ratio)/RSENSE Gated PFET Controller When using external current regulator current limited wall pack, simply remove inductor catch diode control bits select desired duty ratio. insuring that voltage Sense never greater than 140mV, output integrator will saturate high comparator will never trip turn loop off. This achieved removing sense resistor grounding Sense gauge used, selecting RSENSE that RSENSE /ICHRG 140mV.
LTC1325
FUNCTIONAL DESCRIPTIO
Gauge Mode Command: MOD1 MOD0 Status: BATP BATR FMCV FEDV FHTF FLTF
gauge mode, average voltage across sense resistor measured determine average battery load current. output ground switches closed. configured inverting amplifier with setting gain voltage across sense resistor filtered circuit (RF, amplified then converted ADC. microprocessor then accumulate measurements time average determine total charge leaving battery. Sense voltage should more negative than 450mV ensure linearity. RFCF circuit consists internal resistor external capacitor connected Filter pin. RFCF should longer than measurement interval. With serial clock running 100kHz, take 380µs shift command word shift measurement status word. Trickle Resistor external trickle resistor several functions. First, provides continuous trickle charge current topping battery countering effects self-discharge. Second, used condition deeply discharged battery charging. LTC1325 will charge battery unless cell voltage above 100mV (BATR). Finally, resistor required battery detect circuit pull VBAT high when battery removed. SERIAL INTERFACE LTC1325 communicates with microprocessors other external circuitry synchronous, half duplex, 4-wire serial interface. clock synchronizes data transfer with each being transmitted falling edge captured rising edge both transmitting receiving systems. LTC1325 first receives input data then transmits back conversion result status word (half duplex). Because half
duplex operation, DOUT tied together allowing transmission over just three wires: DATA (DIN/DOUT). Data transfer initiated falling chip select signal. After falls, LTC1325 looks start DIN. start first "logical one" clocked into input after goes low. LTC1325 will ignore leading zeros which precede this logical one. After start received, other control bits shifted into configure LTC1325 start conversion. After last command bit, DOUT remains three-state clock period before taken null bit. Following null bit, conversion results status bits shifted DOUT pin. data exchange, should brought high. MSB-First/LSB-First (MSBF Control Bit) output data LTC1325 programmed MSBfirst LSB-first sequence using MSFB control bit. When MSBF data will appear DOUT MSB-first format. This followed status bits. Logical zeros will filled indefinitely following last data accommodate longer word lengths required some microprocessors. When MSBF LSB-first data will follow MSB-first data. Regardless state MSBF, status bits always shifted same order (see Figure Accommodating Microprocessors with Different Word Lengths LTC1325 will fill zeros indefinitely after transmitted data until brought high. that time DOUT disabled (three-stated). This makes easy interfacing serial ports with different transfer increments including bits (e.g., COP400) bits (e.g., MICROWIRE/PLUSTM). word length accommodated correct positioning start input word. Operation with DOUT Tied Together LTC1325 operated with DOUT tied together. This eliminates lines required
MICROWIRE/PLUS trademark National Semiconductor Corp.
LTC1325
FUNCTIONAL DESCRIPTIO
communicate with microprocessor. Data transmitted both directions single wire. processor connected this data line should configurable either input output. LTC1325 will take control data line drive after 23rd falling edge after start received. Therefore processor port must switched input before this happens avoid conflict. Power-Up After Shutdown When control word with written LTC1325, enters shutdown mode which supply current reduced 30µA. this mode onchip regulator circuits powered shut down. only circuits that remain alive DIN, input buffers. take LTC1325 from shutdown mode, high edge must applied pin. Either must when prevent false control word from being transmitted LTC1325. output decays with time constant 300ms with CREG 4.7µF. microprocessor should wait three seconds before applying wake-up edge ensure proper power-up. TEMPERATURE SENSING (Negative Temperature Coefficient) Thermistors simplest method sense temperature (battery ambient) with thermistor voltage divider powered pin. This divider consists load resistor series with thermistor shown Figure given thermistor, there value which makes VDIV linear over narrow adequate temperature range. easiest method (Inflection Point Method) calculate second temperature derivative divider output equations relevant this method are:
VDIV VREG
dVDIV VDIV
where, VDIV output divider, VREG voltage (3.072V nominal), thermistor resistance some temperature thermistor resistance some reference temperature constant dependent thermistor material, temperature coefficient %/°C) temperatures (i.e., 273) There assumptions derivation above equations. assumed constant temperature coefficient small compared that thermistor. Most thermistor data sheets specify RTO, RT/RTO ratios temperatures, tolerances RTO. Given RTO, easy calculate from equation
LTC1325
APPLICATIONS INFORMATION
(3). Alternatively, calculated from RT/RTO ratio using equation from using equation (6). numerical example, consider Panasonic ERT-D2FHL103S thermistor which following characteristics: (25°C) 4.6%/°C 25°C Ratio R25/R50 Using equation R25/R50 2.9, (323 298)In (2.9)/(298 323) 4099k. Alternatively, using equation 4.6%/°C, 0.046)(298)2 4085k. Both values close each other. Substituting 4085k into equation gives [4085 298)]/[4085 298)] 7.45k. nearest resistor value 7.5k. Figure shows plot VDIV(T) measured various temperatures this thermistor with 7.5k
DIVIDER OUTPUT VOLTAGE
IDEAL ACTUAL
TEMPERATURE (°C)
LTC1325
Figure ERT-D2FHL103S Divider
There methods calculating battery ambient temperature from readings TBAT TAMB channels. first method store VDIV(T) curve lookup table. second method straight line approximation. equation this line calculated from slope dVDIV/dT [see equation (7)] assuming that line passes through point [TO, VDIV(TO)] curve. ERT-D2FHL103S, slope minus 34mV/°C equation line
[2.605 VDIV(T)]/0.034. straight line approximation accurate within over temperature range 45°C, assuming tolerances. (Positive Temperature Coefficient) Thermistors Positive Temperature Coefficient (PTC) thermistors used battery chargers that require accurate temperature measurements. resistance temperature characteristics exhibits sharp increase selectable switch temperature This sharp change exploited chargers which (Temperature Cutoff) (Difference between battery ambient temperature). With termination, voltage divider consisting temperature coefficient load resistor connected between with REG. mounted battery sense temperature. divider output tied TBAT. When switch temperature reached, resistance increases sharply causing TBAT fall below HTF. This causes fault charging terminated. implement termination, load resistor can, principle, replaced matching divider responds differences between battery ambient temperature. With both terminations, position battery temperature swapped with load resistor ambient temperature PTC. both cases, fault terminates charge when trip point reached. Note that practice, matched PTCs readily available termination, thermistors recommended. HARDWARE DESIGN PROCEDURE This section discusses considerations selecting each component simple battery charger (see Figures Further applications assistance provided Application Note using LTC1325 Battery Management RSENSE: There three factors selecting RSENSE: LTC1325 VREF Duty Ratio Settings Sense Resistor Dissipation ILOAD (RSENSE) 450mV Gauge Linearity
LTC1325
APPLICATIONS INFORMATION
LTC1325 five duty ratio four VDAC settings giving possible charge rates (for given value RSENSE) shown following table. combination VDAC duty ratio, average charging current given ICHRG VDAC (Duty Ratio)/RSENSE
NORMALIZED VDAC 1(VR1 1/3(VR1 1/5(VR1 1/10(VR1 1/10 DUTY RATIO 1/12 1/24 1/10 l/20 1/40 1/20 1/40 1/80 1/16 1/16 1/48 1/80 1/160
Note that table entries give relative charge rates assuming that duty ratio entry equivalent charge rate. Therefore, charge rate C-units) other VR1, VR0, duty ratio settings read directly from table. general, duty ratio entry equivalent charge rate, times Then entries table should multiplied general, VDAC duty ratio settings changed microprocessor charge batteries different capacities alter charge rates when charging same battery several stages. best accuracy, should where possible. power dissipation sense resistor varies between charge, discharge gauge modes should calculated three modes. Typically, dissipation higher discharge gauge modes since batteries deliver higher currents than they charged with. gauge mode, load current supplied battery should exceed 450mV/RSENSE gauge remain linear response. RSENSE should enough ensure that ILOAD (RSENSE) does fall below ground more than diode drop. Supply: should least 1.8V above maximum battery voltage prevent BATP error when LTC1325 charge discharge mode. this requirement cannot specific application, external battery divider should connected
between VBAT Sense pins internal divider should divide-by-1. minimum supply must greater than end-of-charge voltage times number cells battery plus drops across on-resistance PFET, inductor (VL), battery internal resistance RINT sense resistor RSENSE. Minimum should greater voltage results from these equations: ICHRG [RDS(ON)(P1) RSENSE n(RINT)] n(VEC) n(VEC) 1.8V Assuming 1.6V, LTC1325 will charge cells with supply. higher number cells, external level shifter regulator needed. some applications, there other circuits attached charging supply. When charging supply (VDC) powered down removed, battery supply current these circuits through PFET body diode. prevent this, blocking diode added series with shown circuit Typical Application section. Inductor minimize losses, inductor should have winding resistance. should able handle expected peak charging currents without saturation. inductor saturates, charging current limited only total PFET RDS(ON), inductor winding resistance, RSENSE source resistance. This fault current high enough damage battery cause maximum power ratings PFET, inductor RSENSE exceeded. Catch Diode catch diode should have forward drop fast reverse recovery time minimize power dissipation. Total power loss given PdD1 (IF) (VR)(f)(tRR)(IF)
LTC1325
APPLICATIONS INFORMATION
where, forward diode current, forward diode current just prior turn off, forward drop, reverse diode voltage (approximately equal VDD), frequency (111kHz), reverse recovery time power maximum reverse voltage ratings diode should greater than PdD1 respectively. catch diode should also have fast turn-on times reduce voltage glitch cathode when turning Schottky diodes have fast switching times forward drops recommended Trickle Resistor RTRK: RTRK sets desired trickle current battery compensate self-discharge which order capacity NiCd NiMH batteries respectively. Trickle charge rates typically C/30 C/50 range, where battery capacity. ITRK (VDD VBAT)/RTRK where VBAT voltage full charged battery. Note that ITRK varies battery being charged. Thermistor Load total resistance thermistor network should greater than high temperature extreme minimize effects load regulation (see loading). Fault Setting Resistors voltage levels LTF, pins tapped from resistor divider powered pin. voltage levels selected taking into account: Manufacturer Recommended Temperature Voltage limits, Loading 2mA) Input Voltage Ranges LTF, Comparators: 1.6V VLTF, VMCV 2.8V 0.5V VHTF 1.3V Thermistor Divider Temperature Curve Typical temperature limits both NiCd NiMH batteries shown below.
BATTERY TYPE Standard Quick Fast Rapid Trickle DISCHARGE TEMP RANGE (°C) CHARGE TEMP RANGE (°C)
Note that discharge limits wider than charge limits. prolong battery life, manufacturers generally recommend discharge temperatures that similar charge limits. this reason, LTC1325 recognizes same limits both charge discharge modes. should just above charging voltage cell given battery specifications. voltage pins should correspond narrowest temperature range. These typically 15°C 45°C. corresponding voltages read from thermistor divider temperature curve such that shown Figure this thermistor, works about 2.12V 1.13V HTF. conveniently tied since typically desired, external analog switches under microprocessor control used vary LTF, voltages between modes different charge rates. values Figure calculated from following equations: VHTF (RE/VREG) VMCV VLTF (RE) where chosen minimize loading pin. minimum value recommended. Note that VLTF assumed greater than VMCV. this case, VLTF VMCV above equations should swapped. pins shorted same point, should
LTC1325
APPLICATIONS INFORMATION
Loading: 3.072V regulator load regulation specification 5mV/mA. Since uses same regulator reference, desirable reduce loading effects especially over temperature. Thermistors with values least 25°C recommended. 50°C, thermistor resistance could drop factor from value 25°C. chosen explained section Temperature Sensing. temperature coefficient critical since thermistor tempco dominates sensing circuit. RDIS: RDIS selected limit discharge current value within battery discharge specifications must have power rating above IDIS2 (RDIS) where: IDIS VBAT/[RDIS RDS(ON)(N1)] PFET(P1) NFET(N1): operation charge discharge loops, since PGATE pins swing between VDD. minimize power dissipation. power ratings should above ICHRG2[RDS(ON)(P1)] IDIS2 [RDS(ON)(N1)] respectively. VDS(MAX) should above VDD. Charging from Supplies Above many applications, charging supply greater than maximum rating LTC1325. LTC1325 easily adapted charge batteries from charging supply that above adding three external sub-circuits: regulator drop down within supply range LTC1325. level shifter between PGATE gate PFET, ensure that completely turned when PGATE rises VDD. voltage clamp VBAT prevent RTRK from pulling VBAT above VDD. Wide Voltage Battery Charger circuit Typical Application section shows cost implementations three sub-circuits. generate LTC1325. form level shifter. zener chosen clamp source gate voltage PFET within maximum gate source voltage rating latter. Finally, clamps VBAT 15V. Charging Batteries with Voltages Above charge battery with maximum (fully charged) voltage above 16V, charging supply must above 16V. Thus charger will need regulator, level shifter clamp mentioned previous section. addition, external battery divider must added limit voltage VBAT less than VDD. This shown typical application circuit, Wide Voltage Battery Charger. resistors selected divide battery voltage number cells battery battery divider internal LTC1325 divide-by-1. external divider prevents VBAT from ever rising this causes BATP (Battery Present Flag) high regardless whether battery physically present not. This does affect other operations LTC1325. SOFTWARE DESIGN general charging algorithm consists following stages: Discharge Before Charge Fast Charge Charge Trickle Charge Under some operating storage conditions, NiCd NiMH batteries provide full capacity. particular, repeated shallow charge discharge cycles cause "memory effect" NiCd batteries. order restore full capacity (battery conditioning), these batteries have subjected several deep discharge/charge cycles which will provided repetitions above algorithm. Figure shows simplified flowchart charging algorithm. practice, this flowchart augmented take into account occurrence fail-safes point algorithm. example, battery temperature could rise above during discharging charging. General programming notes follows: start always high. SGL/DIFF generally that makes conversions with respect ground.
LTC1325
APPLICATIONS INFORMATION
MSBF depending whether microprocessor clocks serial data with MSB- LSB-first. bits anything except when entering idle mode when requesting readings. these cases, select desired reading: TBAT, VCELL TAMB. should always that LTC1325 does into shutdown mode. should select test modes. assume different settings between Fast charge charge order alter charging current. FSCLR should clear faults reset timer when starting Discharge, Fast charge Off. status bits that LTC1325 returns
START
CONDITIONING? START DISCHARGE START CHARGE
WAIT
READ STATUS RESUME CHARGE START FAST CHARGE WAIT
RESUME FAST CHARGE
IDLE MODE WAIT
READ STATUS
TERMINATE?
Figure Simple Charging Algorithm
during same operation (that FSCLR should checked determine faults were indeed cleared, i.e., discharging charging begun. This shown simplified flowchart Figure commands other than START commands, FSCLR should reset timer. bits should discharge mode ensure discharge does prematurely timeout fault. During Fast charge charge, these bits value suitable charge rate used. example, charge rate timeout period should minutes. charge mode, capacitor filters VCELL node sees small ripple ripple Sense pin. Prior taking reading, LTC1325
WAIT
IDLE MODE
READ STATUS
TERMINATE? IDLE MODE WAIT
MORE CONDITIONING?
LTC1325
LTC1325
APPLICATIONS INFORMATION
idle mode minimize noise. microprocessor should either disregard readings wait second before taking reading. This allow VCELL decay correct cell voltage. worst case time constant 150k(CF Prior first START command, battery divider setting incorrect that charge voltage that causes EDV, BATR faults. worst case time constant (9). microprocessor should check faults during transmission START command resend START command again when been given enough time charge correct value. MICROPROCESSOR INTERFACES LTC1325 interface directly either synchronous, serial parallel ports most popular microprocessors. With parallel port, lines programmed form serial link LTC1325. Motorola (68HC11) 68HC11 dedicated synchronous serial interface called Serial Peripheral Interface (SPI) which transfers data with MSB-first 8-bit increments. communicate with this microprocessor, LTC1325 MSBF control should four lines: Master Slave (MISO), Master Slave (MOSI), Serial Clock (SCK) Slave Select (SS). 68HC11 configured Master tying line high. control byte written Serial Peripheral Control Register (SPCR) select master mode, baud rate clock timing relationship. Another byte written Port Direction Register (DDRD) MOSI, LTC1325) outputs. 68HC11 clocks data from LTC1325 simultaneously under control SCK. microprocessor transmits LTC1325 command word bytes. This followed more dummy bytes (with bits low) order clock remaining LTC1325 status bits. This software example allows verify communications with LTC1325. command word configures LTC1325 perform conversion general purpose input. tied wiper potentiometer between these two. Table illustrates complete 6-byte exchange. Note that first byte padded with zeroes align data status with byte boundaries. SPCR (SPIE DWOM MSTR CPOL CPHA SPR1 SPR0 DDRD (BIT7 BIT6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
Table 6-Byte Exchange Communication with LTC1325
68HC11 MOSI PORTD.0 MISO LTC1325 DOUT
START MOD0
BYTE
BYTE
MOD1
SGL/ DIFF
MSBF
DIV0
DIV1
BYTE
BYTE
DIV2
DIV3
FSCLR
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BATP
BATR
FMCV
FEVD
FHTF
FLTF
t0UT
BYTE
DON'T CARE
LTC1325 AI01
LTC1325
APPLICATIONS INFORMATION
LABEL MNEMONIC OPERAND
LDAA STAA LDAA STAA BCLR LDAA STAA LDAA STAA LDAA STAA LDAA STAA #$51 $1028 #$39 $1009 #$1000 $08,X,#$01 #$02 $102A $1029 LOOP1 #$24 $102A $1029 LOOP2 #$03 $102A $1029 LOOP3 #$C0 $102A
COMMENTS
Write control byte SPCR Setup Port DDRD Port Load port base ADDR Take Send Byte (MSB) with START Check transfer complete Send Byte Check transfer complete Send Byte Check transfer complete Send Byte
CSLOW
LOOP1
LOOP2
LOOP3
TYPICAL APPLICATION
Wide Voltage Battery Charger
MBR320 NOTE 1N4740A 100k IRF9Z30 0.1µF 62µH
NOTE NOTE
1/2W
1N4744A
(e.g. 8051) p1.4 p1.3 p1.2
DOUT
PGATE VBAT TBAT TAMB SENSE FILTER NOTE THERM THERM 500pF 0.1µF NOTE NOTE NOTE IRF830 1N4744A RSENSE RDIS
CREG 4.7µF
LTC1325
NOTE NEEDED WHEN MAXIMUM BATTERY VOLTAGE, VBAT 16V. NOTE REGULATOR. OMIT THIS BLOCK SHORT WHEN 16V. NOTE LEVEL SHIFTER. OMIT THIS BLOCK SHORT PGATE GATE WHEN 16V.
NOTE ZENER CLAMP VBAT BELOW VDD. OMIT WHEN 16V. NOTE EXTERNAL BATTERY DIVIDER. NEEDED WHEN MAXIMUM BATTERY VOLTAGE, VBAT 16V. NOTE UNCOMMITTED CHANNEL.
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LABEL MNEMONIC OPERAND
LOOP4 LDAA ANDA STAA LDAA STAA LOOP5 LDAA STAA LDAA STAA LOOP6 LDAA STAA BSET $1029 LOOP4 $102A #$03 HIDATA #$00 $102A $1029 LOOP5 $102A LODATA #$00 $102A $1029 LOOP6 $102A STATUS $08,X,#$01 CSLOW
COMMENTS
Check transfer complete high byte Mask unwanted bits Store user memory Send dummy Byte Check transfer complete byte Store user memory Send dummy Byte Check transfer complete STATUS byte Store user memory Raise high Loop continuous readings
NOTE NOTE
1N5818 RTRK
22µF VBAT
NOTE OPTIONAL DIODE PREVENT BATTERY DRAIN WHEN CHARGING SUPPLY POWERED DOWN (SEE SECTION HARDWARE DESIGN PROCEDURE).
1325 TA02
LTC1325
PACKAGE DESCRIPTION
Dimension inches (millimeters) unless otherwise noted. Package 18-Lead Plastic
0.300 0.325 (7.620 8.255) 0.130 0.005 (3.302 0.127) 0.015 (0.381) 0.045 0.065 (1.143 1.651) 0.900* (22.860)
0.009 0.015 (0.229 0.381)
0.065 0.255 0.015* (1.651) (6.477 0.381) 0.125 (3.175) 0.018 0.003 (0.457 0.076)
0.005 (0.127) 0.100 0.010 (2.540 0.254) *THESE DIMENSIONS INCLUDE MOLD FLASH PROTRUSIONS. MOLD FLASH PROTRUSIONS SHALL EXCEED 0.010 INCH (0.254mm)
+0.025 0.325 -0.015 +0.635 8.255 -0.381
0695
Package 18-Lead Plastic
0.447 0.463* (11.354 11.760) 0.291 0.299** (7.391 7.595)
0.010 0.029 (0.254 0.737)
0.093 0.104 (2.362 2.642)
0.037 0.045 (0.940 1.143)
NOTE
0.394 0.419 (10.007 10.643)
0.009 0.013 (0.229 0.330)
NOTE
0.050 (1.270)
0.004 0.012 (0.102 0.305)
SW18 0695
0.016 0.050 (0.406 1.270) NOTE: IDENT, NOTCH CAVITIES BOTTOM PACKAGES MANUFACTURING OPTIONS PART SUPPLIED WITH WITHOUT OPTIONS.
*DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
0.014 0.019 (0.356 0.482)
RELATED PARTS
PART NUMBER
1510 LT1512
Constant Voltage/Constant Current Battery Charger SEPIC Constant Current/Constant Voltage Battery Charger
COMMENTS
1.3A, Li-Ion, NiCd, NiMH, Pb-Acid Charger 0.75A, Greater Less Than VBAT
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7487
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LT/GP 0895 PRINTED
LINEAR TECHNOLOGY CORPORATION 1994

LTC1325 provides core flexible, cost-effective solution integrated bat

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