Programmable Logic Device Family November 1999, ver. 4.02 Fe

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Programmable Logic Device Family November 1999, ver. 4.02 Fe

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FLEX 6000
Programmable Logic Device Family
November 1999, ver. 4.02
Features.
Provides ideal low-cost, programmable alternative highvolume gate array applications allows fast design changes during prototyping design testing Product features Register-rich, look-up table- (LUT-) based architecture OptiFLEXarchitecture that increases device area efficiency Typical gates ranging from 5,000 24,000 gates (see Table Built-in low-skew clock distribution tree 100% functional testing devices; test vectors scan chains required Advanced 2.96-mil (75-µm) bond pitch 3.3-V devices reduced size System-level features In-circuit reconfigurability (ICR) external configuration device intelligent controller 5.0-V devices fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic MultiVoltI/O interface operation, allowing device bridge between systems operating different voltages power consumption (typical specification less than standby mode) 3.3-V devices support hot-socketing
Table FLEX 6000 Device Features
Feature
Typical gates Logic elements (LEs) Maximum pins Supply voltage (VCCINT) Note:
embedded IEEE Std. 1149.1 JTAG circuitry adds 14,000 gates addition listed typical gates.
EPF6010A
10,000
EPF6016
16,000 1,320
EPF6016A
16,000 1,320
EPF6024A
24,000 1,960
Altera Corporation
A-DS-F6000-04.02
FLEX 6000 Programmable Logic Device Family
.and More Features
Powerful pins Individual tri-state output enable control each Programmable output slew-rate control reduce switching noise Fast path from register fast clock-to-output time Flexible interconnect FastTrack® Interconnect continuous routing structure fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such fast adders, counters, comparators (automatically used software tools megafunctions) Dedicated cascade chain that implements high-speed, high-fanin logic functions (automatically used software tools megafunctions) Tri-state emulation that implements internal tri-state networks Four low-skew global paths clock, clear, preset, logic signals Software design support automatic place-and-route provided Altera's MAX+PLUS® development system Windows-based SPARCstation, 9000 Series 700/800, RISC System/6000 workstations, Quartusdevelopment system Windows-based SPARCstation 9000 Series workstations Flexible package options Available variety packages with pins, including innovative FineLine BGApackages (see Table SameFramepin-compatibility (with other FLEX® 6000 devices) across device densities counts Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA) packages (see Table Footprint- pin-compatibility with other FLEX 6000 devices same package Additional design entry simulation support provided EDIF netlist files, library parameterized modules (LPM), Verilog HDL, VHDL, DesignWare components, other interfaces popular tools from manufacturers such Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, Viewlogic
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 Package Options Count
Device
EPF6010A EPF6016 EPF6016A EPF6024A
100-Pin TQFP
100-pin FineLine
144-Pin TQFP
208-Pin PQFP
240-Pin PQFP
256-Pin
256-pin FineLine
General Description
Altera® FLEX 6000 programmable logic device (PLD) family provides low-cost alternative high-volume gate arrays designs. FLEX 6000 devices based OptiFLEX architecture, which minimizes size while maintaining high performance routability. devices have reconfigurable SRAM elements, which give designers flexibility quickly change their designs during prototyping design testing. Designers also change functionality during operation in-circuit reconfiguration. FLEX 6000 devices reprogrammable, they 100% tested prior shipment. result, designers required generate test vectors fault coverage purposes, allowing them focus simulation design verification. addition, designer does need manage inventories different gate array designs. FLEX 6000 devices configured board specific functionality required. Table shows FLEX 6000 performance some common designs. performance values shown were obtained using Synopsys DesignWare functions. Special design techniques required implement applications; designer simply infers instantiates function Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), schematic design file.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 Device Performance Common Designs
Application Used Performance Speed Grade
16-bit loadable counter 16-bit accumulator 24-bit accumulator 16-to-1 multiplexer (pin-to-pin) multiplier with 4-stage pipeline Note:
This performance value measured pin-to-pin delay.
Units
13.4
16.6
12.1
Table shows FLEX 6000 performance more complex designs.
Table FLEX 6000 Device Performance Complex Designs
Application Used
Note
Performance Speed Grade Units
8-bit, 16-tap parallel finite impulse response (FIR) filter 8-bit, 512-point fast Fourier transform (FFT) function a16450 universal asynchronous receiver/transmitter (UART) target with zero wait states Note:
MSPS
1,182
applications this table were created using Altera MegaCorefunctions.
FLEX 6000 devices supported Quartus MAX+PLUS development systems; single, integrated package that offers schematic, text (including AHDL), waveform design entry, compilation logic synthesis, full simulation worst-case timing analysis, device configuration. Quartus MAX+PLUS software provides EDIF LPM, VHDL, Verilog HDL, other interfaces additional design entry simulation support from other industrystandard UNIX workstation-based tools.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Quartus MAX+PLUS software works easily with common gate array tools synthesis simulation. example, MAX+PLUS software generate Verilog files simulation with tools such Cadence Verilog-XL. Additionally, Quartus MAX+PLUS software contains libraries that device-specific features such carry chains which used fast counter arithmetic functions. instance, Synopsys Design Compiler library supplied with Quartus MAX+PLUS development systems include DesignWare functions that optimized FLEX 6000 architecture. MAX+PLUS development system runs Windows-based SPARCstation, 9000 Series 700/800, RISC System/6000 workstations, Quartus development system runs Windowsbased SPARCstation 9000 Series workstations.
Functional Description
MAX+PLUS Programmable Logic Development System Software Data Sheet more information. FLEX 6000 OptiFLEX architecture consists logic elements (LEs). Each includes 4-input look-up table (LUT), which implement 4-input function, register, dedicated paths carry cascade chain functions. Because each contains register, design easily pipelined without consuming more LEs. specified gate count FLEX 6000 devices includes LUTs registers. combined into groups called logic array blocks (LABs); each contains LEs. MAX+PLUS software automatically places related into same LAB, minimizing number required interconnects. Each implement medium-sized block logic, such counter multiplexer. Signal interconnections within FLEX 6000 devices-and from device pins-are provided routing structure FastTrack Interconnect. routing structure series fast, continuous column channels that entire length width device. feed other FastTrack Interconnect. "FastTrack Interconnect" page this data sheet more information.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Each element (IOE) located each column FastTrack Interconnect. Each contains bidirectional buffer. Each placed next LAB, where driven local interconnect that LAB. This feature allows fast clock-to-output times less than when driven adjacent LAB. Also, drive column interconnect. pins drive registers column interconnect, providing setup times hold times IOEs provide variety features, such JTAG support, slew-rate control, tri-state buffers. Figure shows block diagram FLEX 6000 OptiFLEX architecture. Each group combined into LAB, LABs arranged into rows columns. LABs interconnected FastTrack Interconnect. IOEs located each FastTrack Interconnect column.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure OptiFLEX Architecture Block Diagram
IOEs
FastTrack Interconnect
FastTrack Interconnect
IOEs
Column FastTrack Interconnect
Column FastTrack Interconnect Local Interconnect (Each accesses local interconnect areas.) Logic Elements
FLEX 6000 devices provide four dedicated, global inputs that drive control inputs flipflops ensure efficient distribution highspeed, low-skew control signals. These inputs dedicated routing channels that provide shorter delays lower skews than FastTrack Interconnect. These inputs also driven internal logic, providing ideal solution clock divider internally generated asynchronous clear signal that clears many registers device. dedicated global routing structure built into device, eliminating need create clock tree.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Logic Array Block
consists LEs, their associated carry cascade chains, control signals, local interconnect. provides coarse-grained structure FLEX 6000 architecture, facilitates efficient routing with optimum device utilization high performance. interleaved structure-an innovative feature FLEX 6000 architecture-allows each drive local interconnects. This feature minimizes FastTrack Interconnect, providing higher performance. drive adjacent LABs local interconnect, which maximizes fitting flexibility while minimizing size. Figure
Figure Logic Array Block
interconnect bidirectionally connected local interconnect. directly drive column interconnect.
Interconnect
To/From Adjacent IOEs
To/From Adjacent IOEs
Local Interconnect
driven local interconnect areas. drive local interconnect areas.
Column Interconnect
most designs, registers only global clock clear signals. However, some cases, other clock asynchronous clear signals needed. addition, counters also have synchronous clear load signals. design that uses non-global clock clear signals, inputs from first re-routed drive control signals that LAB. Figure
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Control Signals
dedicated input signals drive clock asynchronous clear signals.
Dedicated Inputs
Input signals first (i.e., rerouted drive control signals within LAB.
LABCTRL1/ SYNCLR LABCTRL2
CLK1/SYNLOAD
CLK2
LAB-wide control signals (SYNCLR SYNLOAD signals used counter mode).
Logic Element
smallest unit logic FLEX 6000 architecture, compact size that provides efficient logic usage. Each contains fourinput LUT, which function generator that quickly implement function four variables. contains programmable flipflop, carry cascade chains. Additionally, each drives both local FastTrack Interconnect. Figure
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Logic Element
Carry-In Cascade-In
Register Bypass
Programmable Register
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
LE-Out
CLRN
labctrl1 labctrl2 Chip-Wide Reset
Clear/ Preset Logic Clock Select
labctrl3 labctrl4
Carry-Out Cascade-Out
programmable flipflop configured operation. clock clear control signals flipflop driven global signals, general-purpose pins, internal logic. combinatorial functions, flipflop bypassed output drives outputs output drive both local interconnect FastTrack Interconnect. FLEX 6000 architecture provides types dedicated high-speed data paths that connect adjacent without using local interconnect paths: carry chains cascade chains. carry chain supports high-speed arithmetic functions such counters adders, while cascade chain implements wide-input functions such equivalent comparators with minimum delay. Carry cascade chains connect through LABs same half row. Because extensive carry cascade chains reduce routing flexibility, these chains should limited speed-critical portions design.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Carry Chain
carry chain provides very fast (0.1 carry-forward function between LEs. carry-in signal from lower-order drives forward into higher-order carry chain, feeds into both next portion carry chain. This feature allows FLEX 6000 architecture implement high-speed counters, adders, comparators arbitrary width. Carry chain logic created automatically MAX+PLUS Quartus Compiler during design processing, manually designer during design entry. Parameterized functions such DesignWare functions automatically take advantage carry chains appropriate functions. Because first each generate control signals that LAB, first each included carry chains. addition, inputs first each used generate synchronous clear load enable signals counters implemented with carry chains. Carry chains longer than nine implemented automatically linking LABs together. enhanced fitting, long carry chain skips alternate LABs row. carry chain longer than skips either from even-numbered another even-numbered LAB, from odd-numbered another odd-numbered LAB. example, last first carries second third row. addition, carry chain does cross middle row. instance, EPF6016 device, carry chain stops 11th carry chain begins 12th LAB. Figure shows n-bit full adder implemented with carry chain. portion generates bits using input signals carry-in signal; routed output Although register bypassed simple adders, used accumulator function. Another portion carry chain logic generates carry-out signal, which routed directly carry-in signal next-higher-order bit. final carry-out signal routed where driven onto FastTrack Interconnect.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Carry Chain Operation
Carry-In
Register
Carry Chain
Register
Carry Chain
Register
Carry Chain
Register
Carry-Out
Carry Chain
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Cascade Chain
cascade chain enables FLEX 6000 architecture implement very wide fan-in functions. Adjacent LUTs used implement portions function parallel; cascade chain serially connects intermediate values. cascade chain logical logical gate (via Morgan's inversion) connect outputs adjacent LEs. Each additional provides four more inputs effective width function, with delay Cascade chain logic created automatically MAX+PLUS Quartus Compiler during design processing, manually designer during design entry. Parameterized functions such DesignWare functions automatically take advantage cascade chains appropriate functions. cascade chain implementing gate register last cascade chain implementing gate cannot this register because inversion required implement gate. Because first generate control signals that LAB, first each included cascade chains. Moreover, cascade chains longer than nine bits automatically implemented linking several LABs together. easier routing, long cascade chain skips every other row. cascade chain longer than skips either from even-numbered another even-numbered LAB, from odd-numbered another odd-numbered LAB. example, last first cascades second third LAB. cascade chain does cross center row. example, EPF6016 device, cascade chain stops 11th cascade chain begins 12th LAB. Figure shows cascade function connect adjacent form functions with wide fan-in. this example, functions variables implemented with LEs. With cascade chain, needed decode 16-bit address.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Cascade Chain Operation
Cascade Chain
Cascade Chain
d[3.0]
d[3.0]
d[7.4]
d[7.4]
d[(4n-1).4(n-1)]
d[(4n-1).4(n-1)]
Operating Modes
FLEX 6000 operate following three modes:
Normal mode Arithmetic mode Counter mode
Each these modes uses resources differently. each mode, seven available inputs LE-the four data inputs from local interconnect, feedback from programmable register, carry-in cascade-in from previous LE-are directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, synchronous clear, synchronous load control register. MAX+PLUS Quartus software, conjunction with parameterized functions such DesignWare functions, automatically chooses appropriate mode common functions such counters, adders, multipliers. required, designer also create special-purpose functions operating mode optimal performance.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure shows operating modes.
Figure Operating Modes
Normal Mode
Carry-In data1 data2 data3 data4 4-Input Cascade-In LE-Out
CLRN
Cascade-Out
Arithmetic Mode
Carry-In Cascade-In LE-Out data1 data2
3-Input
3-Input Cascade-Out Carry-Out
CLRN
Counter Mode
Carry-In Cascade-In
LAB-Wide Synchronous Load
LAB-Wide Synchronous Clear
data1 data2 data3 (data) 3-Input Carry-Out Cascade-Out CLRN
3-Input
LE-Out
Notes:
Register feedback multiplexer available each LAB. data1 data2 input signals supply clock enable, down control, register feedback signals other than second LAB. LAB-wide synchronous clear LAB-wide synchronous load affect registers LAB.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Normal Mode normal mode suitable general logic applications, combinatorial functions, wide decoding functions that take advantage cascade chain. normal mode, four data inputs from local interconnect carry-in inputs 4-input LUT. MAX+PLUS Quartus Compiler automatically selects carry-in DATA3 signal inputs LUT. output combined with cascade-in signal form cascade chain through cascade-out signal. Arithmetic Mode arithmetic mode ideal implementing adders, accumulators, comparators. arithmetic mode uses 3-input LUTs. computes 3-input function; other generates carry output. shown Figure first uses carry-in signal data inputs from local interconnect generate combinatorial registered output. example, when implementing adder, this output three signals: DATA1, DATA2, carry-in. second uses same three signals generate carry-out signal, thereby creating carry chain. arithmetic mode also supports simultaneous cascade chain. MAX+PLUS Quartus software implements logic functions arithmetic mode automatically where appropriate; designer does have decide carry chain will used. Counter Mode counter mode offers counter enable, synchronous up/down control, synchronous clear, synchronous load options. counter enable synchronous up/down control signals generated from data inputs local interconnect. synchronous clear synchronous load options LAB-wide signals that affect registers LAB. Consequently, counter mode, other that must used part same counter used combinatorial function. addition, MAX+PLUS Quartus Compiler automatically places registers that counter into other LABs. counter mode uses 3-input LUTs: generates counter data other generates fast carry bit. 2-to-1 multiplexer provides synchronous loading, another gate provides synchronous clearing. cascade function used counter mode, synchronous clear load will override signal carried cascade chain. synchronous clear overrides synchronous load.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Either counter enable up/down control used given counter. Moreover, synchronous load used count enable routing register output into data input automatically when requested designer. second each special function counter mode; carry-in driven fast feedback path from register. This function gives faster counter speed counter carry chains starting second LAB. MAX+PLUS Quartus software implements functions counter mode automatically where appropriate. designer does have decide carry chain will used.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without limitations physical tri-state bus. physical tri-state bus, tri-state buffers' output enable (OE) signals select which signal drives bus. However, multiple signals active, contending signals driven onto bus. Conversely, signals active, will float. Internal tri-state emulation resolves contending tri-state buffers value floating buses high value, thereby eliminating these problems. MAX+PLUS Quartus software automatically implements tri-state functionality with multiplexer.
Clear Preset Logic Control
Logic programmable register's clear preset functions controlled LAB-wide signals LABCTRL1 LABCTRL2. register asynchronous clear that implement asynchronous preset. Either LABCTRL1 LABCTRL2 control asynchronous clear preset. Because clear preset functions active-low, MAX+PLUS Quartus Compiler automatically assigns logic high unused clear preset signal. clear preset logic implemented either asynchronous clear asynchronous preset mode, which chosen during design entry (see Figure
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Clear Preset Modes
Asynchronous Clear Asynchronous Preset
labctrl1 labctrl2 Chip-Wide Reset
CLRN labctrl1 labctrl2 Chip-Wide Reset
Asynchronous Clear flipflop cleared either LABCTRL1 LABCTRL2. Asynchronous Preset asynchronous preset implemented with asynchronous clear. MAX+PLUS Quartus software provides preset control using clear inverting input output register. Inversion control available inputs both IOEs. Therefore, this technique used when register drives logic drives pin. addition clear preset modes, FLEX 6000 devices provide chip-wide reset (DEV_CLRn) that reset registers device. option this MAX+PLUS Quartus software before compilation. chip-wide reset overrides other control signals. register with asynchronous preset will preset when chip-wide reset asserted because inversion technique used implement asynchronous preset. MAX+PLUS Quartus software programmable NOT-gate push-back technique emulate simultaneous preset clear asynchronous load. However, this technique uses additional three register.
FastTrack Interconnect
FLEX 6000 OptiFLEX architecture, connections between device pins provided FastTrack Interconnect, series continuous horizontal vertical routing channels that traverse device. This global routing structure provides predictable performance, even complex designs. contrast, segmented routing FPGAs requires switch matrices connect variable number routing paths, increasing delays between logic resources reducing performance.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
FastTrack Interconnect consists column interconnect channels that span entire device. Each LABs served dedicated interconnect, which routes signals between LABs same row, also routes signals from pins LABs. Additionally, local interconnect routes signals between same adjacent LABs. column interconnect routes signals between rows routes signals from pins rows. through drive local interconnect right, while through drive local interconnect left. DATA1 DATA3 inputs each driven local interconnect left; DATA2 DATA4 driven local interconnect right. local interconnect also routes signals from pins. Figure shows overview FLEX 6000 interconnect architecture. first last columns have drivers both sides that drive pins local interconnect.
Figure FastTrack Interconnect Architecture
Interconnect Channels)
through through
through through
To/From Adjacent
To/From Adjacent
Local Interconnect Channels)
Column Interconnect Channels)
Note:
EPF6010A, EPF6016, EPF6016A devices, channels channels; EPF6024A devices, channels channels.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
channel driven column channels. These three signals feed 3-to-1 multiplexer that connects specific channels. channels drive into local interconnect multiplexers. Each column LABs served dedicated column interconnect. drive column interconnect. LAB, column IOE, interconnect drive column interconnect. column interconnect then drive another row's interconnect route signals other LABs device. signal from column interconnect must routed interconnect before enter LAB. Each FastTrack Interconnect output local output. FastTrack interconnect output drive column lines directly; local output drives local interconnect. Each local interconnect channel driven drive four column channels. This feature provides additional flexibility, because each drive lines four column lines. addition, drive global control signals. This feature useful distributing internally generated clock, asynchronous clear, asynchronous preset signals. pin-driven global signal also drive data signals, which useful high-fan-out data signals. Each drives groups local interconnects, which allows drive LABs, LEs, local interconnect. row-to-local multiplexers used more efficiently, because multiplexers drive LABs. Figure shows connects column interconnects.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Connections Column Interconnects
Each FastTrack Interconnect output drive channels. Each local channel driven drive column channels.
Each output signal driving FastTrack Interconnect drive column channels.
each intersection, four channels drive column channels. Each local channel driven drive four channels.
Interconnect
interconnect drives local interconnect.
From Adjacent Local Interconnect
Local Interconnect
Column Interconnect column channel drive channels.
driven signal from local interconnect areas.
improved routability, interconnect consists full-length half-length channels. full-length channels connect LABs row; half-length channels connect LABs half row. addition providing predictable, row-wide interconnect, this architecture provides increased routing resources. neighboring LABs connected using half-length channel, which saves other half channel other half row. One-third channels half-length channels.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table summarizes FastTrack Interconnect resources available each FLEX 6000 device.
Table FLEX 6000 FastTrack Interconnect Resources
Device
EPF6010A EPF6016 EPF6016A EPF6024A
Rows
Channels
Columns
Channels Column
addition general-purpose pins, FLEX 6000 devices have four dedicated input pins that provide low-skew signal distribution across device. These four inputs used global clock asynchronous clear control signals. These signals available control signals device. dedicated inputs also used generalpurpose data inputs because they feed local interconnect each device. Using dedicated inputs route data signals provides fast path high fan-out signals. local interconnect from LABs located either rows drive global control signal. instance, EPF6016 device, LABs C22, drive global control signals. When drives global control signal, dedicated input that drives that signal cannot used. device drive global control signal driving FastTrack Interconnect into appropriate LAB. minimize delay, however, MAX+PLUS Quartus software places driving appropriate LAB. LE-driving-global signal feature optimized speed control signals; regular data signals better routed FastTrack Interconnect receive advantage from being routed global signals. This LE-driving-global control signal feature controlled designer used automatically MAX+PLUS Quartus software. Figure
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Global Clock Clear Distribution
Note
(Repeated Across Device)
Dedicated Inputs
Dedicated Inputs
Notes:
global clock clear distribution signals shown EPF6016 EPF6016A devices. EPF6010A devices, LABs rows drive global signals. EPF6024A devices, LABs rows drive global signals. local interconnect from LABs drive global control signals left side. Global signals drive into every clock, asynchronous clear, preset, data signals. local interconnect from LABs drive global control signals right side.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Elements
contains bidirectional buffer tri-state buffer. IOEs used input, output, bidirectional pins. receives data signals from adjacent local interconnect, which driven column interconnect (allowing device drive IOE) adjacent (allowing fast clock-to-output delays). FastFLEXI/O column output that receives data signals from adjacent local interconnect driven adjacent receives output enable signal through same path, allowing individual output enables every permitting emulation open-drain buffers. MAX+PLUS Quartus Compiler uses programmable inversion invert data output enable signals automatically where appropriate. Open-drain emulation provided driving data input toggling each IOE. This emulation possible because there pin. chip-wide output enable feature allows designer disable pins device asserting (DEV_OE). This feature useful during board debugging testing. Figure shows block diagram.
Figure Block Diagram
Column Interconnect Delay
Chip-Wide Output Enable From Local Interconnect
From Local Interconnect Slew-Rate Control
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Each drives column interconnect when used input bidirectional pin. drive lines; column drive column lines. input path from FastTrack Interconnect programmable delay element that used guarantee zero hold time. Depending placement relative what driving, designer choose turn programmable delay ensure zero hold time. Figure shows connects interconnect, Figure shows connects column interconnect.
Figure Connection Interconnect
Interconnect
drive through local interconnect.
IOEs either side row. Each drive channels, each data signal driven local interconnect.
FastFLEX I/O: drive through local interconnect faster clock-to-output times.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure Connection Column Interconnect
Each drive column interconnect channels. Each data signal driven local interconnect.
FastFLEX I/O: drive through local interconnect faster clock-to-output times.
drive through local interconnect.
Column Interconnect
Interconnect
SameFrame Pin-Outs
3.3-V FLEX 6000 devices support SameFrame pin-out feature FineLine packages. SameFrame pin-out feature arrangement balls FineLine packages such that lower-ballcount packages form subset higher-ball-count packages. SameFrame pin-outs provide flexibility migrate only from device device within same package, also from package another. given printed circuit board (PCB) layout support multiple device density/package combinations. example, single board layout support EPF6016A device 100-pin FineLine package EPF6024A device 256-pin FineLine package. MAX+PLUS Quartus software packages provide support design PCBs with SameFrame pin-out devices. Devices defined present future use. MAX+PLUS Quartus software packages generate pin-outs describing board take advantage this migration (see Figure 15).
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure SameFrame Pin-Out Example
Printed Circuit Board Designed 256-Pin FineLine Package
100-Pin FineLine
256-Pin FineLine
100-Pin FineLine Package (Reduced Count Logic Requirements)
256-Pin FineLine Package (Increased Count Logic Requirements)
Table lists 3.3-V FLEX 6000 devices with SameFrame pin-out feature.
Table 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs
Device
EPF6016A EPF6024A
100-Pin FineLine
256-Pin FineLine
Output Configuration
This section discusses slew-rate control, MultiVolt interface, power sequencing, hot-socketing FLEX 6000 devices.
Slew-Rate Control
output buffer each adjustable output slew rate that configured low-noise high-speed performance. slower slew rate reduces system noise adds maximum delay fast slew rate should used speed-critical outputs systems that adequately protected against noise. Designers specify slew rate pin-by-pin basis during design entry assign default slew rate pins device-wide basis. slew rate setting affects only falling edge output.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
MultiVolt Interface
FLEX 6000 device architecture supports MultiVolt interface feature, which allows FLEX 6000 devices interface with systems differing supply voltages. EPF6016 device 3.3-V 5.0-V operation. This device pins internal operation input buffers (VCCINT), another output drivers (VCCIO). VCCINT pins 5.0-V FLEX 6000 devices must always connected 5.0-V power supply. With 5.0-V VCCINT level, input voltages levels therefore compatible with 3.3-V 5.0-V inputs. VCCIO pins 5.0-V FLEX 6000 devices connected either 3.3-V 5.0-V power supply, depending output requirements. When VCCIO pins connected 5.0-V power supply, output levels compatible with 5.0-V systems. When VCCIO pins connected 3.3-V power supply, output high therefore compatible with 3.3-V 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 incur nominally greater timing delay tOD2 instead tOD1. 3.3-V FLEX 6000 devices, VCCINT pins must connected 3.3-V power supply. Additionally, 3.3-V FLEX 6000A devices interface with 2.5-V, 3.3-V, 5.0-V systems when VCCIO pins tied output drive 2.5-V systems, inputs driven 2.5-V, 3.3-V, 5.0-V systems. When VCCIO pins tied output drive 3.3-V 5.0-V systems. MultiVolt I/Os supported 100-pin TQFP FineLine packages. Table describes FLEX 6000 MultiVolt support.
Table FLEX 6000 MultiVolt Support
VCCINT
Note:
When VCCIO FLEX 6000 device drive 2.5-V device that 3.3-V tolerant inputs.
VCCIO
Input Signal
Output Signal
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Open-drain output pins 5.0-V 3.3-V FLEX 6000 devices (with pullup resistor 5.0-V supply) drive 5.0-V CMOS input pins that require When open-drain active, will drive low. When inactive, trace will pulled resistor. open-drain will only drive tri-state; will never drive high. rise time dependent value pull-up resistor load impedance. current specification should considered when selecting pull-up resistor. Output pins 5.0-V FLEX 6000 devices with VCCIO (with pull-up resistor 5.0-V supply) also drive 5.0-V CMOS input pins. this case, pull-up transistor will turn when voltage exceeds Therefore, does have open-drain.
Power Sequencing Hot-Socketing
Because FLEX 6000 family devices used mixed-voltage environment, they have been designed specifically tolerate possible power-up sequence. VCCIO VCCINT power planes powered order. Signals driven into 3.3-V FLEX 6000 devices before during power without damaging device. Additionally, FLEX 6000 devices drive during power Once operating conditions reached, FLEX 6000 devices operate specified user.
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
FLEX 6000 devices provide JTAG circuitry that comply with IEEE Std. 1149.1-1990 specification. Table shows JTAG instructions FLEX 6000 devices. JTAG performed before after configuration, during configuration (except when disable JTAG support user mode). Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) more information JTAG circuitry.
Table FLEX 6000 JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. EXTEST BYPASS Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test result input pins. Places 1-bit bypass register between pins, which allows data pass synchronously through selected device adjacent devices during normal device operation.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
instruction register length FLEX 6000 devices three bits. Table shows boundary-scan register length FLEX 6000 devices.
Table FLEX 6000 Device Boundary-Scan Register Length
Device
EPF6010A EPF6016 EPF6016A EPF6024A
Boundary-Scan Register Length
FLEX 6000 devices include weak pull-up JTAG pins.
Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) more information. Figure shows timing requirements JTAG signals.
Figure JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table shows JTAG timing parameters values FLEX 6000 devices.
Table JTAG Timing Parameters Values
Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
Parameter
clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock-to-output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock-to-output Update register high impedance valid output Update register valid output high impedance
Unit
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Generic Testing
Each FLEX 6000 device functionally tested. Complete testing each configurable SRAM logic functionality ensures 100% configuration yield. test measurements FLEX 6000 devices made under conditions equivalent those shown Figure Multiple test patterns used configure devices during stages production flow.
Figure Test Conditions
Power supply transients affect measurements. Simultaneous transitions multiple outputs should avoided accurate measurement. Threshold tests must (703 performed under conditions. [521 Large-amplitude, fast-ground-current transients normally occur Device device outputs discharge load Output capacitances. When these transients flow through parasitic inductance between device ground test system ground, (8.06 significant reductions observable [481 noise immunity result. Numbers Device input without parentheses 5.0-V rise fall devices outputs. Numbers times parentheses 3.3-V devices outputs. Numbers brackets 2.5-V devices outputs.
Test System
(includes capacitance)
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FLEX 6000 Programmable Logic Device Family
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 5.0-V 3.3-V FLEX 6000 devices.
Table FLEX 6000 5.0-V Device Absolute Maximum Ratings
Symbol
Note
-2.0 -2.0
Parameter
Supply voltage input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias
Conditions
With respect ground
Unit
PQFP, TQFP, packages
Table FLEX 6000 5.0-V Device Recommended Operating Conditions
Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers
Conditions
(3),
4.75 (4.50) 4.75 (4.50) 3.00 (3.00) -0.5
5.25 (5.50) 5.25 (5.50) 3.60 (3.60) CCINT CCIO
Unit
Supply voltage output buffers, (3), 5.0-V operation Supply voltage output buffers, (3), 3.3-V operation
Input voltage Output voltage Operating temperature Input rise time Input fall time commercial industrial
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FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 5.0-V Device Operating Conditions
Symbol
Notes (5),
-0.5
Parameter
High-level input voltage Low-level input voltage 5.0-V high-level output voltage 3.3-V high-level output voltage 3.3-V high-level CMOS output voltage
Conditions
CCINT
Unit
CCIO 4.75 CCIO 3.00 -0.1 CCIO 3.00 CCIO 4.75 CCIO 3.00 CCIO 3.00 ground ground, load
CCIO 0.45 0.45
5.0-V low-level output voltage 3.3-V low-level output voltage 3.3-V low-level CMOS output voltage
Input leakage current supply current (standby)
Tri-stated leakage current ground
Table FLEX 6000 5.0-V Device Capacitance
Symbol
CINCLK
Note
Conditions
Parameter
Input capacitance
Unit
Input capacitance dedicated input Output capacitance
Notes tables:
Operating Requirements Altera Devices Data Sheet. Minimum input -0.3 During transitions, inputs undershoot -2.0 overshoot input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. Typical values These values specified under Table page parameter refers high-level CMOS output current. parameter refers low-level CMOS output current. This parameter applies open-drain pins well output pins. Capacitance sample-tested only.
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FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 3.3-V Device Absolute Maximum Ratings
Symbol
Note
-0.5 -2.0
Parameter
Supply voltage input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias
Conditions
With respect ground
5.75
Unit
PQFP, PLCC, packages
Table FLEX 6000 3.3-V Device Recommended Operating Conditions
Symbol
CCINT CCIO
Parameter
Supply voltage internal logic (3), input buffers Supply voltage output buffers, 3.3-V operation Supply voltage output buffers, 2.5-V operation
Conditions
3.00 (3.00) 3.00 (3.00) 2.30 (2.30) -0.5
3.60 (3.60) 3.60 (3.60) 2.70 (2.70) 5.75 CCIO
Unit
(3), (3),
Input voltage Output voltage Operating temperature Input rise time Input fall time commercial industrial
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 3.3-V Device Operating Conditions
Symbol
Notes (5),
-0.5
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level output voltage 3.3-V high-level CMOS output voltage 2.5-V high-level output voltage
Conditions
5.75
Unit
CCIO 3.00 -0.1 CCIO 3.00 -100 CCIO 2.30 CCIO 2.30 CCIO 2.30
CCIO 0.45
3.3-V low-level output voltage 3.3-V low-level CMOS output voltage 2.5-V low-level output voltage
CCIO 3.00 CCIO 3.00 CCIO 2.30 CCIO 2.30 CCIO 2.30
Input leakage current supply current (standby)
ground ground, load
Tri-stated leakage current ground
Table FLEX 6000 3.3-V Device Capacitance
Symbol
CINCLK
Note
Conditions
Parameter
Input capacitance
Unit
Input capacitance dedicated input Output capacitance
Notes tables:
Operating Requirements Altera Devices Data Sheet. minimum input voltage -0.5 During transitions, inputs undershoot -2.0 overshoot 5.75 input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. Typical values These values specified under Table page parameter refers high-level CMOS output current. parameter refers low-level CMOS output current. This parameter applies open-drain pins well output pins. Capacitance sample-tested only.
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FLEX 6000 Programmable Logic Device Family
Figure shows typical output drive characteristics 5.0-V 3.3-V FLEX 6000 devices with 5.0-V, 3.3-V, 2.5-V VCCIO. When VCCIO EPF6016 devices, output driver compliant with Local Specification, Revision 5.0-V operation. When VCCIO EPF6010A EPF6016A devices, output driver compliant with Local Specification, Revision 3.3-V operation.
Figure Output Drive Characteristics
EPF6010A EPF6016A
EPF6010A EPF6016A
VCCINT VCCIO Room Temperature
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
Typical Output Current (mA)
Output Voltage EPF6016
Output Voltage
EPF6016
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
Output Voltage
EPF6024A
Output Voltage
EPF6024A
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Output Voltage
Output Voltage
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FLEX 6000 Programmable Logic Device Family
Timing Model
continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance accurate simulation timing analysis. This predictable performance contrasts with that FPGAs, which segmented connection scheme therefore have unpredictable performance. Device performance estimated following signal path from source, through interconnect, destination. example, registered performance between same calculated adding following parameters:
register clock-to-output delay (tCO tREG_TO_OUT) Routing delay (tROW tLOCAL) delay (tDATA_TO_REG) register setup time (tSU)
routing delay depends placement source destination LEs. more complex registered path involve multiple combinatorial between source destination LEs. Timing simulation delay prediction available with MAX+PLUS Simulator Timing Analyzer, with industrystandard tools. MAX+PLUS Simulator offers both pre-synthesis functional simulation evaluate logic design accuracy post-synthesis timing simulation with 0.1-ns resolution. MAX+PLUS Timing Analyzer provides point-to-point timing delay information, setup hold time analysis, device-wide performance analysis. Figure shows overall timing model, which maps possible routing paths from various elements FLEX 6000 device.
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Figure FLEX 6000 Timing Model
tROW
Carry-In from Previous
Cascade-In from Previous
tLOCAL
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG
tCLR
tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT
tCOL tLD_CLR tLEGLOBAL tCARRY_TO_CARRY tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC
tDIN_D tDIN_C
tLABCARRY
Carry-out Carry-out Next Next Same Next
tLABCASC
Cascade-out Cascade-out Next Next Same Next
tIOE
tOD1 tOD2 tOD3 tZX1 tZX2 tZX3
tIN_DELAY
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FLEX 6000 Programmable Logic Device Family
Tables through describe FLEX 6000 internal timing microparameters, which expressed worst-case values. Using hand calculations, these parameters used estimate design performance. However, before committing designs silicon, actual worst-case performance should modeled using timing simulation timing analysis. Tables describe FLEX 6000 external timing parameters.
Table Timing Microparameters
Symbol
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT tCLR tLD_CLR tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC
Note
Parameter Conditions
delay register feedback carry chain Cascade-in register delay Carry-in register delay input register delay Cascade-in output delay Carry-in output delay input output delay Register output output delay register setup time before clock; register recovery time after asynchronous clear register hold time after clock register clock-to-output delay register clear delay register control signal delay Synchronous load clear delay counter mode
tCARRY_TO_CARRY Carry-in carry-out delay
Register output carry-out delay input carry-out delay Carry-in cascade-out delay Cascade-in cascade-out delay Register-out cascade-out delay input cascade-out delay register clock high time register clock time
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FLEX 6000 Programmable Logic Device Family
Table Timing Microparameters
Symbol
tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tIOE tIN_DELAY
Note
Parameter Conditions
Output buffer delay, slow slew rate off, VCCIO VCCINT Output buffer delay, slow slew rate off, VCCIO voltage Output buffer delay, slow slew rate Output buffer disable delay Output buffer enable delay, slow slew rate off, VCCIO VCCINT Output buffer enable delay, slow slew rate off, VCCIO voltage output buffer enable delay, slow slew rate Output enable control delay Input buffer FastTrack Interconnect delay Input buffer FastTrack Interconnect delay with additional delay turned
Table Interconnect Timing Microparameters
Symbol
tLOCAL tROW tCOL tDIN_D tDIN_C tLEGLOBAL tLABCARRY tLABCASC
local interconnect delay interconnect routing delay Column interconnect routing delay Dedicated input data delay Dedicated input control delay
Note
Conditions
Parameter
output control internally-generated global signal delay Routing delay carry-out driving carry-in signal different different Routing delay cascade-out signal driving cascade-in signal different different
Table External Reference Timing Parameters
Symbol
tDRR Register-to-register test pattern Register-to-register delay LEs, interconnects, local interconnects
Parameter
Conditions
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table External Timing Parameters
Symbol
tINSU tINH tOUTCO Notes tables:
Microparameters timing delays contributed individual architectural elements cannot measured explicitly. Operating conditions: VCCIO commercial 5.0-V FLEX 6000 devices. VCCIO industrial 5.0-V FLEX 6000 devices. VCCIO commercial industrial 3.3-V FLEX 6000 devices. Operating conditions: VCCIO commercial industrial 5.0-V FLEX 6000 devices. VCCIO commercial industrial 3.3-V FLEX 6000 devices. Operating conditions: VCCIO These parameters worst-case values typical applications. Post-compilation timing simulation timing analysis required determine actual worst-case performance. This timing parameter shows delay register-to-register test pattern used determine speed grades. There LEs, including source destination registers. column interconnects between registers vary length. This timing parameter shown reference specified characterization. This timing parameter specified characterization.
Parameter
Setup time with global clock register Hold time with global clock register Clock-to-output delay with global clock with register using FastFLEX
Conditions
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FLEX 6000 Programmable Logic Device Family
Tables through show timing information EPF6010A EPF6016A devices.
Table Timing Microparameters EPF6010A EPF6016A Devices
Parameter
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT tCLR tLD_CLR tCARRY_TO_CARRY tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC
Speed Grade
Unit
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FLEX 6000 Programmable Logic Device Family
Table Timing Microparameters EPF6010A EPF6016A Devices
Parameter
tOD1 tOD2 tOD3 tXZ1 tXZ2 tXZ3 tIOE tIN_DELAY
Speed Grade
Unit
Table Interconnect Timing Microparameters EPF6010A EPF6016A Devices
Parameter
tLOCAL tROW tCOL tDIN_D tDIN_C tLEGLOBAL tLABCARRY tLABCASC
Speed Grade
Unit
Table External Reference Timing Parameters EPF6010A EPF6016A Devices
Parameter Device
EPF6010A EPF6016A
Speed Grade
37.6 38.0
Unit
43.6 44.0
53.7 54.1
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table External Timing Parameters EPF6010A EPF6016A Devices
Parameter
tINSU tINH tOUTCO Notes:
Setup times longer when Increase Input Delay option turned setup time values shown with Increase Input Delay option turned off. Hold time zero when Increase Input Delay option turned
Speed Grade
Unit
10.1
Tables through show timing information EPF6016 devices.
Table Timing Microparameters EPF6016 Devices (Part
Parameter
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT tCLR tLD_CLR tCARRY_TO_CARRY tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC
Speed Grade
Unit
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table Timing Microparameters EPF6016 Devices (Part
Parameter
tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC
Speed Grade
Unit
Table Timing Microparameters EPF6016 Devices
Parameter
tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tIOE tIN_DELAY
Speed Grade
Unit
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table Interconnect Timing Microparameters EPF6016 Devices
Parameter
tLOCAL tROW tCOL tDIN_D tDIN_C tLEGLOBAL tLABCARRY tLABCASC
Speed Grade
Unit
Table External Reference Timing Parameters EPF6016 Devices
Parameter
tDRR
Speed Grade
53.0 16.0
Unit
65.0 20.0
Table External Timing Parameters EPF6016 Devices
Parameter
tINSU tINH tOUTCO
Speed Grade
Unit
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Tables through show timing information EPF6024A devices.
Table Timing Microparameters EPF6024A Devices
Parameter
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT tCLR tLD_CLR tCARRY_TO_CARRY tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC
Speed Grade
Unit
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table Timing Microparameters EPF6024A Devices
Parameter
tOD1 tOD2 tOD3 tXZ1 tXZ2 tXZ3 tIOE tIN_DELAY
Speed Grade
Unit
10.5
12.6
Table Interconnect Timing Microparameters EPF6024A Devices
Parameter
tLOCAL tROW tCOL tDIN_D tDIN_C tLEGLOBAL tLABCARRY tLABCASC
Speed Grade
Unit
Table External Reference Timing Parameters EPF6024A Devices
Parameter
Speed Grade
45.0
Unit
50.0
60.0
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table External Timing Parameters EPF6024A Devices
Parameter
tINSU tINH tOUTCO Notes:
Setup times longer when Increase Input Delay option turned setup time values shown with Increase Input Delay option turned off. Hold time zero when Increase Input Delay option turned
Speed Grade
Unit
Power Consumption
supply power FLEX 6000 devices calculated with following equations: PINT (ICCSTANDBY ICCACTIVE) Typical ICCSTANDBY values shown ICC0 "FLEX 6000 Device Operating Conditions" table pages this data sheet. ICCACTIVE value depends switching frequency application logic. This value based amount current that each typically consumes. value, which depends device output load characteristics switching frequency, calculated using guidelines given Application Note (Evaluating Power Altera Devices). ICCACTIVE value calculated with following equation: ICCACTIVE fMAX togLC -MHz Where: fMAX togLC Maximum operating frequency Total number used FLEX 6000 device Average percentage toggling each clock (typically 12.5%) Constant, shown Table
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FLEX 6000 Programmable Logic Device Family
Table Constant Values
Device
EPF6010A EPF6016 EPF6016A EPF6024A
Value
This calculation provides estimate based typical conditions with output load. actual should verified during operation because this measurement sensitive actual pattern device environmental operating conditions. better reflect actual designs, power model (and constant power calculation equations shown above) continuous interconnect FLEX devices assumes that drive FastTrack Interconnect channels. contrast, power model segmented FPGAs assumes that drive only short interconnect segment. This assumption lead inaccurate results, compared measured power consumption actual design segmented interconnect FPGA. Figure shows relationship between current operating frequency EPF6010A, EPF6016, EPF6016A, EPF6024A devices.
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FLEX 6000 Programmable Logic Device Family
Figure ICCACTIVE Operating Frequency
EPF6010A EPF6016
1000
Supply Current (mA)
Supply Current (mA)
Frequency (MHz) EPF6016A
Frequency (MHz) EPF6024A
Supply Current (mA)
Supply Current (mA)
Frequency (MHz)
Frequency (MHz)
Device Configuration Operation
FLEX 6000 architecture supports several configuration schemes load design into device(s) circuit board. This section summarizes device operating modes available device configuration schemes. Application Note (Configuring FLEX 6000 Devices) detailed information configuring FLEX 6000 devices, including sample schematics, timing diagrams, configuration options, pins names, timing parameters.
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FLEX 6000 Programmable Logic Device Family
Operating Modes
FLEX 6000 architecture uses SRAM configuration elements that require configuration data loaded every time circuit powers This process physically loading SRAM data into FLEX 6000 device known configuration. During initialization-a process that occurs immediately after configuration-the device resets registers, enables pins, begins operate logic device. pins tristated during power-up, before during configuration. configuration initialization processes device referred command mode; normal device operation called user mode. SRAM configuration elements allow FLEX 6000 devices reconfigured in-circuit loading configuration data into device. Real-time reconfiguration performed forcing device into command mode with device pin, loading different configuration data, reinitializing device, resuming user-mode operation. entire reconfiguration process requires less than used dynamically reconfigure entire system. Also, in-field system upgrades performed distributing configuration files.
Configuration Schemes
configuration data FLEX 6000 device loaded with three configuration schemes, which chosen basis target application. EPC2, EPC1, EPC1441 configuration device intelligent controller used control configuration FLEX 6000 device, allowing automatic configuration system powerup. Multiple FLEX 6000 devices configured three configuration schemes connecting configuration enable input (nCE) configuration enable output (nCEO) pins each device.
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FLEX 6000 Programmable Logic Device Family
Table shows data sources each configuration scheme.
Table Configuration Schemes
Configuration Scheme
Configuration device Passive serial (PS)
Data Source
EPC2, EPC1, EPC1441 configuration device BitBlasterTM, ByteBlasterTM, ByteBlasterMVTM, MasterBlasterdownload cables, serial data source
Passive serial asynchronous BitBlaster, ByteBlaster, ByteBlasterMVTM, (PSA) MasterBlasterdownload cables, serial data source Note:
ByteBlaster cable obsolete replaced ByteBlasterMV cable, which program configure 2.5-V, 3.3-V, 5.0-V devices.
Device PinOuts
Tables show names numbers FLEX 6000 device packages.
Table FLEX 6000 Device Pin-Outs (Part
Name 100-Pin TQFP EPF6010A
Notes (1),
100-Pin FineLine EPF6010A EPF6016A
100-Pin TQFP EPF6016A
144-Pin TQFP EPF6010A
144-Pin TQFP EPF6016 EPF6016A EPF6024A
MSEL nSTATUS nCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBUSY CLKUSR DATA (3),
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FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 Device Pin-Outs (Part
Name 100-Pin TQFP EPF6010A
Notes (1),
100-Pin FineLine EPF6010A EPF6016A
100-Pin TQFP EPF6016A
144-Pin TQFP EPF6010A
144-Pin TQFP EPF6016 EPF6016A EPF6024A
(7),
Dedicated Inputs DEV_CLRn DEV_OE VCCINT VCCIO connect (N.C.)
(7),
104, 104,
102, 102, (10)
Total user pins (11)
Table FLEX 6000 Device Pin-Outs (Part
Name 208-Pin PQFP EPF6016 EPF6016A EPF6024A
Notes (1),
256-Pin 256-Pin EPF6016 EPF6024A 256-Pin FineLine EPF6016A
240-Pin PQFP EPF6016 EPF6024A
256-Pin FineLine EPF6024A
MSEL nSTATUS nCONFIG DCLK CONF_DONE INIT_DONE nCEO
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 Device Pin-Outs (Part
Name 208-Pin PQFP EPF6016 EPF6016A EPF6024A
128, 111, 130, 112, 131, 149, 166, 183, 110, 129, 147, 165, 182,
Notes (1),
256-Pin 256-Pin EPF6016 EPF6024A 256-Pin FineLine EPF6016A
240-Pin PQFP EPF6016 EPF6024A
148, 130, 150, 110, 131, 151, 171, 192, 211, 109, 120, 129, 149, 169, 181, 191, 210, 229,
256-Pin FineLine EPF6024A
RDYnBSY CLKUSR DATA (3), (7), Dedicated Inputs DEV_CLRn DEV_OE VCCINT
K19, D20, K20, T20, D11, D15, F17, L17, R17, U10, D13, D17, H17, N17, U13,
K19, D20, K20, T20, D11, D15, F17, L17, R17, U10, D13, D17, H17, N17, U13,
J12, J12,
G10, G10, J10, J10, C13, C16, J16, N16, P12, A16, B15, K10, H10, R15, C13, C16, J16, N16, P12, A16, B15, H10, K10, R15,
VCCIO
Altera Corporation
FLEX 6000 Programmable Logic Device Family
Table FLEX 6000 Device Pin-Outs (Part
Name 208-Pin PQFP EPF6016 EPF6016A EPF6024A
Notes (1),
256-Pin 256-Pin EPF6016 EPF6024A 256-Pin FineLine EPF6016A
A10, A13, A14, B11, B16, D15, D16, E14, G15, G16, H16, L16, M15, N15, P11, P15, R11, R16, T10, T11, T12,
240-Pin PQFP EPF6016 EPF6024A
256-Pin FineLine EPF6024A
connect (N.C.)
A11, A16, D12, E20, J20, U12, V14, Y17, (12)
Total user pins (11) Notes tables:
pins listed user pins. Pin-out information FLEX 6000A devices, 256-pin FineLine packages preliminary. This dedicated configuration JTAG pin; therefore, available user pin. This used user used chip-wide configuration function. This used user after configuration. This tri-stated user mode. device configured JTAG circuitry, this available user pin. JTAG circuitry device option used, JTAG testing still performed before configuration. this used input user mode, ensure that does toggle before during configuration. maintain compatibility when migrating from EPF6016AT100 device EPF6010AT100 device, these user pins. (10) maintain compatibility when migrating EPF6010AT144 from larger device, these pins user pins. (11) user count includes dedicated input pins. (12) maintain compatibility when migrating from EPF6024AB256 device EPF6016B256 device, these pins user pins.
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FLEX 6000 Programmable Logic Device Family
Revision History
information contained FLEX 6000 Programmable Logic Device Family Data Sheet version 4.02 supersedes information published previous versions.
Version 4.02
following changes were made FLEX 6000 Programmable Logic Device Family Data Sheet version 4.02:
Text about JTAG added "IEEE Std. 1149.1 (JTAG) Boundary-Scan Support" section. EPF6024A boundary-scan register length corrected Table page
Version 4.01
following changes were made FLEX 6000 Programmable Logic Device Family Data Sheet version 4.01:
Quartus software added throughout document. EPF6010A EPF6016A devices 100-pin FineLine package were added Table page EPF6010A, EPF6016A, EPF6024A devices 256-pin FineLine package were added Table page Stylistic textual changes were made throughout document.
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Programmable Logic Device Family November 1999, ver. 4.02 Fe

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