Series 32-BIT RISC EMBEDDED PROCESSOR ADVANCE INFORMATION FEATURE

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Series 32-BIT RISC EMBEDDED PROCESSOR ADVANCE INFORMATION FEATURE

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MB86933H
Series 32-BIT RISC EMBEDDED PROCESSOR
ADVANCE INFORMATION FEATURES GENERAL DESCRIPTION MB86933H targeted toward applications which require high-performance, low-cost processor with high integration. based SPARC architecture, code compatible with previous implementations, compatible with MB86933. MHz, processor executes MIPs peak 22.5 MIPs sustained performance. Included maximize performance system large register file, 1KByte instruction cache, data write buffer, instruction prefetch buffer. Included minimize external glue logic chip-select outputs, programmable wait-state generators, interrupt controller, complete DRAM controller. Also included ability program each chip select region different external data widths (8/16/32-bit). MB86933H block diagram page These features combine allow MB86933H offer high performance SPARC compatibility cost make right choice wide range cost-sensitive, performance-oriented embedded designs. SEPTEMBER 1996
(40ns/cycle) operating frequency SPARC® high-performance RISC architecture KByte, direct mapped instruction cache Flexible locking mechanism instruction cache window, word register file Fast interrupt response time address spaces, MByte each User supervisor modes Data write buffer instruction prefetch buffer On-chip programmable chip selects wait-state generators Support 16-, 32-bit wide external memory On-chip DRAM controller glue-less connection DRAM
CONFIGURATION
On-chip interrupt controller On-chip clock generator circuit JTAG test interface Single vector trapping micron gate, 3-level metal CMOS technology 160-pin MB86933-compatible pinout
160-PIN
INDEX
VIEW
MB86933H
ASSIGNMENT 160-PIN
NAME -CAS0 -CAS1 -CAS2 -CAS3 TYPE NAME N.C. N.C. N.C. -RAS0 TYPE NAME -MEXC -READY -BREQ -RD/WR -LOCK -BGRNT -DWE -ERROR -SAME_PAGE XTAL2 CLK_ECB XTAL1 CLKOUT1 CLKOUT2 -TIMER_OVF TYPE NAME N.C. -RAS1 -TRST -RESET -BMODE8 -BMODE16 N.C. TYPE
ORDERING CODE
Clock Frequency (MHz)
Note:
Ordering Code MB86933H-25PF-G-B
Package Type Plastic
ordering code production level product. Early shipments this device marked with "ES" indicate that part full production status. Contact your local Fujitsu representative additional information "ES" level products.
MB86933H
BLOCK DIAGRAM
XTAL1/CLKIN CLOCK GENERATOR CLK_OUT INTEGER UNIT DATA INTERFACE UNIT DRAM CONTROLLER CHIP_SEL PAGE_DET TIMER_OVF ADDRESS DECODER INTERRUPT CONTROLLER 16-BIT TIMER D_ADDR I_ADDR D_DATA INSTRUCTION CACHE I_DATA
SCAN
DIVIDE STEP
ADDRESS
CONTROL
MB86933H
SIGNAL DESCRIPTIONS
SYMBOL -RESET TYPE DESCRIPTION SYSTEM RESET: Asserting reset least processor cycles after clock stabilized, causes MB86933 initialized. EXTERNAL OSCILLATOR: crystal inputs determine execution rate timing MB86933H processor. Connecting crystal these pins forms complete crystal oscillator circuit. crystal oscillator frequency same processor operating frequency. When driving processor with external clock, XTAL2 should left floating. CLOCK OUTPUT This output signal against which MB86933H transactions referenced. CLKOUT1 frequency same frequency applied XTAL1 same processor operating frequency. CLKOUT1 phase with CLK_IN. CLOCK OUTPUT This output signal against which MB86933H transactions referenced. CLKOUT2 frequency same frequency applied XTAL1 same processor operating frequency. CLKOUT2 phase with CLK_IN. LOCK: This control signal asserted processor indicate system that current transaction requires more than transfer bus. Atomic Load Store instruction example requires contiguous transactions which cause assertion lock signal. granted another owner long -LOCK active. -LOCK asserted with assertion remains active until -READY asserted locked transaction. REQUEST: Asserted another device indicate that wants ownership bus. request must answered with grant (-BGRNT) from MB86933H before device proceed driving bus. Once been granted, device ownership until de-asserts -BREQ. user should ensure that devices cannot monopolize exclusion CPU. Inputs -BREQ while -RESET active valid cause Grant asserted. GRANT: Asserted response request from device wanting ownership bus. grants other devices only after transfers current transaction completed. drivers three-stated with assertion grant signal. ERROR SIGNAL: Asserted indicate that halted error state result encountering synchronous trap while traps disabled. this situation saves registers, sets value TBR, enters into error state asserts -ERROR signal. system monitor -ERROR initiate reset under error condition. This high reset. MEMORY EXCEPTION: Asserted memory system indicate memory error either data instruction access. Assertion this signal initiates either data instruction access exception trap current access invalidated asserting -MEXC same cycle -READY signal. Assertion other cycle give indeterminate results. ignores contents data cycles where -MEXC asserted. INTERRUPT REQUEST BUS: Based mode selected on-chip interrupt controller, these pins defined ways. mode (IRL) value these pins defines external interrupt vector >=1111 forces non-maskable interrupt. value 0000 indicates pending interrupts. other values indicate maskable interrupts enabled field processor status register (PSR). this mode, interrupts should latched prioritized external logic should held pending until acknowledged processor. other mode (IRQ), each represents decoded interrupt source. When active, values pins IRQ<15:12> will cause processor vector interrupts through respectively. trigger each high-level, low-level, rising edge, falling edge.
XTAL1, (CLK_IN) XTAL2 CLKOUT1
CLKOUT2
-LOCK
-BREQ
-BGRNT
-ERROR
-MEXC
IRL< IRQ<15:12>
following descriptions, signal names preceded minus sign indicate active state. Dual function pins have names separated slash (/).
MB86933H
SYMBOL -TIMER_OVF
TYPE
DESCRIPTION TIMER UNDERFLOW: Asserted processor indicate that internal 16-bit timer underflowed. This signal used initiate DRAM refresh cycle on-chip DRAM controller used generate periodic waveforms. timer overflow signal programmed active single cycle three cycles after each underflow. reset, timer turned -TIMER_OVF high. SAME-PAGE DETECT: -SAME_PAGE used take advantage fast consecutive accesses within Fast Page Mode DRAM page boundaries. This signal output also goes internally on-chip DRAM controller. asserted processor when current address within chip select region also within same page previous memory access -SAME_PAGE signal asserted with remains active processor cycle. -SAME_PAGE never asserted first transaction following transaction another device bus. page size specified writing SAME-PAGE MASK register. CHIP SELECTS: These outputs asserted when value address matches address range corresponding ADDRESS RANGE registers. signals used decode current address into address ranges. Address ranges should overlap. Each address range corresponding wait specifier which used automatically assert -READY signal after user defined number processor clock cycles. This allows variety memory devices with different access times connected MB86933H without need additional logic. MB86933H, chip select defined support on-chip DRAM controller. ADDRESS BUS: 26-bit ADDRESS (ADR27-ADR2) output which identifies data instruction address 32-bit word. Reads always word size while byte, half-word, word transaction sizes writes identified separate byte-enable signals (-BE0-3). address valid duration transaction. ADR27-ADR16 (MA<11:0>)are also used DRAM address. value these pins when RAS_ falls DRAM address. value these pins when CAS_ falls DRAM column address.
-SAME_PAGE
-CS0, -CS1, -CS2, -CS3, -CS4, -CS5
27:2
ADDRESS SPACE IDENTIFIERS: ADDRESS SPACE IDENTIFIERS outputs which indicate which available spaces current ADDRESS value corresponds. values defined follows: ADDRESS SPACE Control Registers Application Definable User Instruction Space Supervisor Instruction Space User Data Space Supervisor Data Space Application Definable
values specified "application definable" used supervisor mode instructions such Load Alternate Store Alternate. value available same cycle which corresponding address value asserted address bus. pins valid duration transaction.
MB86933H
SYMBOL -BE3-0
TYPE
DESCRIPTION BYTE ENABLES (O): These pins indicate whether current store transaction byte, half-word word transaction. -BE3-0 signals available same cycle which corresponding address value asserted address valid duration transaction. This should used only qualify store transactions. read transactions sub-word requests read (and replaced cache) words. loads appropriate byte half-word extracted integer unit. Possible values -BE3-0 follows:
Byte Byte Byte Byte
Byte Writes Half-Word Writes Word Writes
also used 16-bit accesses where they used lower address bits. these modes they defined follows:
Mode 8-bit Byte
16-bit
16-bit wide buses, BE<1:0> used byte enables during stores. BE<1> valid high order byte while BE<0> valid order byte.
31:0
DATA BUS: interface bidirectional data pins (D31-D0) transfer data thirty-two quantities. (31) corresponds most significant 32-bit word. double word aligned 8-byte boundary, word aligned 4-byte boundary, half-word aligned 2-byte boundary. load store these quantities properly aligned, Aligned Trap will occur processor. write cycles, point which data driven onto depends type preceding cycle. preceding cycle write, data driven cycle immediately following cycle which -READY asserted. preceding cycle read, data driven cycle after cycle which -READY asserted minimize contention between processor system. given chip select region, pins D[7:0] used when 8-bit wide used D[15:0] used when 16-bit wide used.
ADDRESS STROBE: control signal asserted MB86933H other master indicate start transaction. transaction begins with assertion ends with assertion -READY. remains asserted clock cycle. During cycles which neither processor another master driving idle, remains de-asserted. READ/BUS TRANSACTION: This signal specifies whether current transaction read write operation. When asserted RD/-WR low, then current transaction write. With asserted RD/-WR high, current transaction read. RD/-WR remains active duration transaction de-asserted with assertion -READY.
RD/-WR
MB86933H
SYMBOL -READY
TYPE
DESCRIPTION READY: This control signal asserted external memory system indicate that current transaction being completed that ready start with next transaction following cycle. case fetch from memory, processor will strobe value data rising edge CLK_IN following assertion -READY. case write, memory system will assert -READY when appropriate access time been met. most cases, additional logic required generate -READY signal. On-chip circuitry programmed assert -READY based address current transaction. external system override internal ready generator terminate current cycle early. address ranges each with different transaction times programmed. EXTERNAL CLOCK BYPASS: Tying this signal high causes CLK_IN signal bypass Phases Lock Loop (PLL). This signal used testing chip. 8-BIT BOOT MODE: This signal sampled during reset causes read accesses memory mapped -CS0 assume 8-bit memory. MB86933H generates four sequential fetches assemble complete instruction data word before continuing. Bytes fetched sequence (0,1,2,3) encoded -BE[2] -BE[3] (00, 03). left unconnected, weak pull-up this (and -BMODE16 pin) causes processor default 32-bit mode. 16-BIT BOOT MODE: This signal sampled during reset causes read accesses memory mapped -CS0 assume 16-bit memory. MB86933H generates sequential fetches assemble complete instruction data word before continuing. Half words fetched sequence (0,1) encoded -BE[2]. left unconnected, weak pull-up this (and -BMODE8 pin) causes processor default 32-bit mode. DRAM ADDRESS STROBES: MB86933H support banks DRAM. -RAS0 address strobe bank0. -RAS1 address strobe bank1. Note that address DRAM appears pins ADR[27:16]. DRAM COLUMN ADDRESS STROBES: MB86933H supports byte, half-word, word accesses DRAM. -CAS0 used accesses byte0, -CAS1 used accesses byte1, -CAS2 used accesses byte2, -CAS3 used accesses byte3. Note that column address DRAM appears pins ADR[27:16]. DRAM WRITE ENABLE: When this signal deasserted (high) access DRAM read. When asserted (low), access DRAM write. TEST CLOCK: JTAG compatible test clock input. TEST MODE: JTAG compatible test mode select pin. TEST DATA JTAG compatible test data input. TEST DATA OUT: JTAG compatible test data output. TEST RESET: Asynchronous reset JTAG logic. using JTAG, this signal must pulled low.
While granted another master (-BGRNT=asserted), driven driven floats valid output While between cycles being reset) granted another master, driven driven floats valid output
CLK_ECB -BMODE8
-BMODE16
-RAS0, -RAS1
-CAS0, -CAS1, -CAS2, -CAS3
-DWE -TRST
NOTE:
Input Only
Output Only Either Input Output Pins "must connected described Asynchronous: Inputs asynchronous CLKOUT1. Synchronous: Inputs must meet setup hold times relative CLK_IN Outputs Synchronous CLK_IN
MB86933H
OVERVIEW Fujitsu MB86933H high-performance, 32-bit RISC processor which executes MIPs peak 22.5 MIPs sustained performance with clock frequency. Like predecessors, MB86933H based SPARC architecture upward code compatible with previous implementations. More importantly, MB86933H been developed specifically with needs embedded applications mind offers high performance cost these applications. MB86933H instruction streamlined hardwired fast execution with most instructions executing single cycle. Integer Unit (IU) features 5-stage pipeline which been designed handle data interlocks, optimized branch handler efficient control transfers, interface handle single cycle accesses on-chip memory. FEATURES Fast Instruction Execution: Simple functions make bulk instructions most programs that execution speed greatly improved designing these instructions execute short time possible. majority instructions execute cycle with only more complex, such integer multiply, taking additional cycles. On-chip Instruction Cache: decouple speed processor from memory subsystem KByte direct mapped instruction cache included chip. possible individually lock lines cache ensure deterministic response higher performance critical frequently recurring routines. Large Register Set: large register (104 registers) reduces number required accesses data memory. registers organized into overlapping groups called register windows which allows registers reserved high priority tasks, such interrupts, recurring requirements such operating system working registers. overlapping windows also simplify parameter passing during procedure linkage reduce code most programs. Hardware Multiplier: MB86933H also includes hardware integer multiply. hardware support significantly improves performance these operations with 32-bit integer multiplies executing clock cycles, 16-bit integer multiplies cycles, 8-bit integer multiplies cycles, multiply zero complete single cycle. Interrupt Controller: on-chip interrupt controller provided MB86933H. Four interrupt pins
either programmed encoded external interrupt vector providing interrupts four individual interrupt lines. Interface: requirement glue logic between MB86933H system removed providing programmable chip selects programmable wait-state circuitry. Each chip select region programmed support either 8-bit, 16-bit, 32-bit wide memory. Multiple masters supported through simple handshake protocol. Instruction Prefetch Buffer: one-word prefetch buffer provided increase performance when instruction cache misses occur. Data Write Buffer: one-word write buffer provided decouple writes from internal instruction execution. Data posted write buffer execution from internal cache continue parallel while store completes external memory. DRAM Controller: Present MB86933H complete DRAM controller which provides glueless connection banks DRAM memory. Support either 16-bit 32-bit wide DRAM memory banks provided. Clock Generator: simplify clock design crystal connected directly on-chip oscillator external clock source used. built-in phase-locked loop minimizes skew between off-chip clocks. Enhanced Instruction Set: integer divide-step instruction cuts divide times factor over previous SPARC implementations. scan instruction supports single cycle search most significant word. Fully Static Circuit Design: Embedded applications that need means reduce power consumption take advantage MB86933H's fully static design. processor clock slowed stopped arbitrary periods time reduce operating current with loss internal state. Noise immunity improved well. (Note: stopping clock will result Phase-Locked Loop losing lock. Lock must re-established before normal operation resumed.) Test Debug Interface: MB86933H supports production test through industry standard JTAG boundary scan.
MB86933H
MB86933H core high-performance full-custom implementation SPARC architecture. core compact leave room peripheral integration designed allow major blocks customized varying application requirements. core made three functional units: Instruction block, Address block Execute block. (See Figure five-stage instruction pipeline responsible decoding instructions generating control signals other blocks. 5-stage pipeline consists Fetch (F), Decode (D), Execute (E), Memory Writeback (W). Instruction memory addressed returns instructions stage, register file addressed returns operands stage, computes results stage, external memory addressed stage, register file written back stage. ADDRESS SPACE MB86933H offers large addressing range allows separate user supervisor spaces defined. addition address lines, alternate address space identifiers (ASIs) distinguish between protected unprotected space. possible values, define accesses user data user instruction space while remaining values define supervisor space. Anytime reset, synchronous trap asynchronous trap occurs, processor placed into supervisor mode. this mode, processor executes instructions moves data supervisor space. While supervisor mode, processor also access remaining values. Except those mentioned those reserved control register space, remaining values used access other alternate data spaces defined application. distinction user versus supervisor space allows hardware protect against accidental un-authorized access system resources. real-time operating system (RTOS) development example, separate spaces provide mechanism effectively partitioning RTOS space from user space.
MB86933H
TABLE MB86933H Instruction LOGICAL
CONDITION CODES UNCHANGED
ARITHMETIC/SHIFT
CONDITION CODES UNCHANGED
DATA MOVEMENT
USER/SUPERVISOR SPACE SIGNED
XNOR
CONDITION CODES
SUBTRACT MULTIPLY (SIGNED/UNSIGNED) SCAN SETHI SHIFT LEFT LOGICAL SHIFT RIGHT LOGICAL SHIFT RIGHT ARITHMETIC
CONDITION CODES
LOAD BYTE LOAD HALF-WORD LOAD WORD LOAD DOUBLE WORD STORE BYTE STORE HALF-WORD STORE WORD STORE DOUBLE WORD
USER SPACE UNSIGNED
XNOR CONTROL TRANSFER CONDITIONAL BRANCH CONDITIONAL TRAP CALL RETURN SAVE RESTORE JUMP LINK
SUBTRACT MULTIPLY (SIGNED/UNSIGNED) MULTIPLY STEP DIVIDE STEP
EXTENDED CONDITION CODES UNCHANGED
LOAD BYTE LOAD HALF-WORD
ALTERNATE SPACE SIGNED
SUBTRACT
EXTENDED CONDITION CODES
LOAD BYTE LOAD HALF-WORD LOAD WORD LOAD DOUBLE WORD STORE BYTE STORE HALF-WORD STORE WORD STORE DOUBLEWORD
ALTERNATE SPACE UNSIGNED
TAGGED CONDITION CODES
(WITH WITHOUT TRAP OVERFLOW)
SUBTRACT SUBTRACT
LOAD BYTE LOAD HALF-WORD
ATOMIC OPERATION USER SPACE
SWAP WORD LOAD/STORE UNSIGNED BYTE
ATOMIC OPERATION ALTERNATE SPACE
READ/WRITE CONTROL REGISTER READ WRITE READ WRITE READ WRITE READ WRITE RDASR WRASR
SWAP WORD LOAD/STORE UNSIGNED BYTE
MB86933H
REGISTERS MB86933H register divided into those used general-purpose functions those used control status. general-purpose registers divided into global registers overlapping blocks "windows". Each window contains registers. these, local window, "out" registers overlap with next window "in" registers overlap with previous window. (See Figure This organization makes easy pass parameters subroutines. Parameters that passed along written "out" registers subsequent procedure call decrements window pointer make registers available. passed parameters available subroutine current window's "in" registers. Register windows improve performance embedded applications because they function local variable caches which retain either interrupt, subroutine, context operating system variables with additional
DATA ADDRESS
overhead. addition, code reduced exploiting efficient execution procedure linkage preventing in-lining compiler optimizations. registers that make register file each have three read-only write-only port. four-port register file allows even store instructions, which require that three operands read register file, proceed instruction cycle. control status registers include those defined SPARC architecture (see Table those mapped into alternate address space control peripheral functions (see Table INSTRUCTION MB86933H upward code compatible with other SPARC processors. Additional instructions, previously directly supported, have been added improve performance embedded applications. Integer multiply, integer divide step, scan first changed have been added already powerful SPARC instruction set. Table list supported instructions.
read
REGISTER FILE read read
write
adder e_ir m_ir w_ir d_pc PSR/TBR/WIM/Y e_pc m_pc INSTRUCTION BLOCK ADDRESS BLOCK EXECUTE BLOCK st_align id_align (+4)
ALU/SHIFTER
ADDRESS
DATA
Figure MB86933H Integer Unit Data Path
MB86933H
INTERRUPTS measure processor's suitability embedded application ability handle interrupts with minimum delay deterministic fashion. MB86933H implementation been tailored insure only average latency maximum latency well. Interrupt response time made times takes processor finish current task after recognizing interrupt, time takes begin executing interrupt service routine instructions. MB86933H implements numerous features minimize both factors. minimize time takes finish current task, MB86933H designed that tasks either interrupted completed minimum number cycles. Implementation details that accomplish this include integer divide operation that interruptible through divide step instruction fast multiply operation minimize non-interruptible instruction execution. minimize time required start executing interrupt service routine processor switches register window when interrupt detected. This feature allows service routine executed without first requiring that current registers saved. INTERRUPT CONTROLLER SPARC architecture, MB86933H particular, provides separate external interrupt sources. MB86933H four external
interrupt pins on-chip interrupt controller (IRC) which support modes operation. Mode (IRL mode): mode input four external pins interpreted encoded interrupt vector. This mode allows external logic generate possible interrupts ("0" represents interrupt request"). this mode operation assumed that external interrupt source maintains interrupt vector pins until explicitly cleared writing external memory mapped location. Note that this mode same that MB86930/932/933 compatible with MB86940 companion chip. Mode (IRQ mode): mode four pins considered four separate interrupt sources mapping interrupts through Note this mode same that MB86931 Figure shows block diagram mode Trigger Mode Control logic selects four trigger modes each four channels: high level, level, rising edge, falling edge. processor controls triggers writing Trigger Mode register. latch captures each four interrupt requests. system processor reads latch Request Sense register clears latch writing Request Clear register. example assembly language program below shows code sequence writing Request Clear register channel Mask logic allows selective masking interrupts. processor controls masking writing Mask register.
define Request Clear Register #define 0x20c define valid memory location #define rqs_loc 0x1000 define control register address space #define casi Request Clear; rqc, 0x1000, rqs_loc, !memory location defined main prog %g0, [%16] %17, [%10] casi !write Request Clear register
write Request Clear register must preceeded store valid memory location prevent previous high value bits data from unintentionally setting other bits Clear Request register.
MB86933H
Priority Encoder prioritizes interrupt requests encodes highest priority pending interrupt that masked. IRL3 maps interrupt IRL2 maps interrupt IRL1 maps interrupt IRL0 maps interrupt latch captures encoded interrupt level number that generated priority encoder.
CURRENT WINDOW
cache miss instruction prefetch buffer fetches next sequential anticipating that will needed fill then next instruction cache miss. cache used either normal mode lock modes. Global locking allows entire content instruction cache frozen. cache control register enables disables global locking. Local locking makes possible dynamically lock selected instructions line-by-line basis. This feature gives flexibility, example, assure deterministic response certain critical routines locking routine's code into cache while still allowing other locations used cache. Note, however, that because cache direct-mapped, code which would normally into locked cache locations will cached.
outs locals locals outs locals
outs locals outs locals locals outs
outs
INTERFACE Interface Unit (BIU) designed simplify interface between MB86933H rest system. Separate address data buses make de-multiplexing unnecessary. Simple control signals make easy build fast systems. includes features increase performance when accessing external memory instruction prefetch buffer support efficient instruction fetches write buffer support data writes. measure processor's suitability embedded application ability handle interrupts with minimum delay deterministic fashion. MB86933H implementation been tailored insure only average latency maximum latency well.
Priority Encoder Latch Mask
Figure General-Purpose Register Organization
INSTRUCTION CACHE MB86933H on-chip, 1KByte, direct- mapped, sectored instruction cache. line length cache bytes. Lines subdivided into four sub-blocks, each four bytes wide. cache miss, cache updated sub-block increments. Also,
Trigger Mode Control IRQ15 (IRL3) IRQ14 (IRL2) IRQ13 (IRL1) IRQ12 (IRL0) Latch Mask
Mask Control
Figure Block Diagram Mode
MB86933H
also includes circuitry enable design complex systems with minimum requirement external glue logic. interface unit supports regions memory each region with independently programmable wait-state generation, chip select generation, programmable widths. This allows support multiple width memories within single system. There also included complete DRAM controller glueless connection DRAM.
Series family member where minimum granularity on-chip data cache word.
DRAM Controller
MB86933H provides necessary logic directly connect fast page-mode DRAM without external glue logic with external buffers). Address multiplexing performed internally DRAM column addresses (MA<11:0>) output ADR<27:16> pins. -RAS lines allow access banks memory. Each -RAS signal controls bank memory. Each bank configurable both depth width. width programmed either 32-bit wide cost systems, 16-bit wide. Four -CAS signals allow byte, halfword, word stores memory. Each -CAS signal controls byte word. -CAS0 controls accesses byte etc. Internal "samepage" detect logic provided allow minimum 2-cycle samepage access DRAM. internal refresh timer used generate -CAS before -RAS refresh cycles automatically programmable intervals. -DWE (DRAM Write Enable) pins determines whether read write access being made DRAM. DRAM configurations supported MB86933H:
DRAM Size (RAS bits bits)
Prefetch Buffer
Associated with instruction cache one-word prefetch buffer. After instruction fetch which misses cache been satisfied, prefetch buffer will immediately initiate another instruction access next sequential address. Instructions prefetched only when does have another pending request transaction (eg. write memory).
Write Buffer
Also associated with one-word write buffer. stores this buffer effectively hides external memory latency. When store occurs data posted write buffer. then continue execute from internal cache while write buffer completes store external memory.
Chip Selects
other Series chips, there chip selects. Each chip select associated with region memory will determine characteristics that region. Associated with each chip select wait state generator which internally terminate external memory access after preprogrammed number cycles. Also associated with each chip select (except chip select control bits which determine external width. width each memory region 8-bit, 16-bit 32-bit. Chip select dedicated boot code. programmed 8-bit, 16-bit, 32-bit wide based external pins: BMODE8_ BMODE16_. When DRAM controller used, chip select dedicated DRAM controller support. should noted that while previous Series family members "samepage" circuitry could associated with chip select, MB86933H "samepage" specifically associated with chip select Byte, halfword, word operations supported widths (8-, 16-, 32-bit). should noted that loads (byte, halfword, word) return total bits (possibly with multiple accesses) regardless width bus. This done compatible with other
256Kxn 512Kxn 1Mxn 2Mxn 2Mxn 4Mxn 4Mxn 16Mxn where
(9x9) (10x9) (10x10) (11x10) (12x9) (11x11) (12x10) (12x12)
CLOCK GENERATOR on-chip clock generator provides means directly connect MB86933H either crystal oscillator external clock source. either case, external frequency same chip operating frequency. clock output signal provides system with reference which external timing synchronized when using external clock source. skew between internal clock external input clock source minimized inclusion on-chip phase lock loop circuit.
MB86933H
TABLE MB86933H Control Status Registers (All registers read/write)
Processor State Register
reserved
Conditions (Negative=1, Non-Negative=0) (Zero=1, Non-Zero=0) (Overflow=1, Overflow=0) (Carry=1, Carry=0) Processor Interrupt Level (Value 1-15, RST=Undefined) MODE (Supervisor=1, User=0, RST=Undefined) Prior Mode Enable Trap (Enable=1, Disable=0, RST=0) Current Window Pointer (Value=0-5, RST=Undefined)
Window Invalid Mask
reserved
Window Invalid Mask (Invalid=1, Valid=0, RST=Undefined)
Trap Base Register
Trap Base Address
(RST=Undefined)
Trap Type (RST=0)
NULL
Register
Ancillary State Register
reserved Reserved (Must Write RST=1) Reserved (Must Write RST=1) Single Vector Trapping (Enabled=1, Disabled=0, RST=0)
MB86933H
TABLE MB86933H Memory Mapped Control Registers (All registers read/write)
System Support Control ADDRESS 0000 0080
reserved DRAM Controller Enable 1,Off Same Page Enable (On=1, Off=0, RST=0) Chip Select Enable (On=1, Off=0, RST=0) Programmable Wait-State (On=1, Off=0, RST=1) Timer On/Off (On=1, Off=0, RST=0) RESERVED Address Mask
[Care=0, Don't Care=1, RST=0]
Same Page Mask ADDRESS 0000 0120
Mask
[Care=0, Don't Care=1, RST=0]
Address Range1 ADDRESS
0000 0124 0000 0128 0000 012C 0000 0130 0000 0134
(RST=Undefined)
31:10
(RST=Undefined)
NOTE:
hardwired ASI=0x9 31:10
Address Mask ADDRESS
0000 0140 0000 0144 0000 0148 0000 014C 0000 0150 0000 0154
Mask
31:10 Mask
(0=Care, 1=Don't Care, RST=Undefined)
NOTE:
14:10 31:15 reset
Wait State Specifier ADDRESS
CS1,CS0 0000 0160 CS3,CS2 0000 0164 CS5,CS4 0000 0168
Count1
Count2
Count1
Count2
reserved
(RST=Undefined)
(RST=Undefined)
(RST=Undefined)
(RST=Undefined)
Wait Enable (On=1, Off=0, RST=0) Single Cycle (On=1, Off=0, RST=0) Override (On=1, Off=0, RST=0) (CS0 RST=1)
Timer ADDRESS 0000 0174
reserved
Timer Value
(RST=Undefined)
Timer Pre-Load ADDRESS 0000 0178
reserved TIMEROVF CTRL cycle pulse) three cycle pulse) (RST UNDEFINED)
Timer Pre-Load Value
(RST=Undefined)
This register Write Only
MB86933H
TABLE MB86933H Memory Mapped Control Registers (All registers read/write) (Continued)
Width ADDRESS 0000 016C
reserved
RSVD
WIDTH DIFFERENT CHIP SELECTS. NOTE THAT PROGRAMMED USING PINS, BMODE16 BMODE8
WIDTH RESERVED 16-BIT 8-BIT BUS* 32-BIT
*Not applicable
(RST
Trigger Mode ADDRESS 0000 0200
reserved
reserved
MD15
MD14
MD13
MD12
Request Sense2 ADDRESS 0000 0208
reserved
reserved
Request Clear1 ADDRESS 0000 020C
reserved
reserved
clear)
Mask ADDRESS 0000 0210
reserved
reserved
mask)
MKIRL Mask Output)
(Interrupt Level)
Latch Clear ADDRESS 0000 0214
reserved
Clear Latch (1=Clear Latch)
DRAM Bank Configuration ADDRESS
bank 0000 07D0 bank 0000 07D4
reserved
reserved
Bank Starting Address (Bits 27:19 starting address bank)
DRAM TYPE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001-1111 DEPTH 256K 512K reserved reserved (11x10) (12x9) (11x11) (12x10) (12x12) (RAS BITS BITS) (9x9) (10x9) (10x10)
MB86933H
Load
OPERATION Interface Unit (BIU) logic which allows MB86933H interface with system. system interface made address data buses, interrupt request various control signals. either handling requests external memory operations, arbitrating access, idle. Operation case write external memory, makes write buffer which hold one-word write transaction. When receives request write transaction stores write data address write buffer allowing continue operating on-chip instruction cache. then proceeds complete write external memory. most cases write buffer will hide external memory latency from exceptions cases where write buffer still filled from previous transaction subsequent cycle results instruction cache miss. these cases, execution held until write buffer emptied. includes one-stage prefetch buffer instruction fetches. This buffer used fetch next sequential instructions after instruction cache miss. instruction prefetched only does have request transaction from external device requesting bus. prefetch buffer operation suspended buffer full. This occurs prefetched instruction instruction cache. buffer restarts after another instruction cache miss. exception occurs during instruction prefetch, exception sent unless instruction actually requested prefetch buffer operates only when instruction cache enabled. Exception Handling external memory system indicate exception during memory operation. signals appropriate data instruction exception which will trap accordingly. Cycles Timings through illustrate representative combinations cycles.
Regardless external size bits), instruction fetches loads (including load byte load half word) retrieve 32-bit quantity. This done compatibility with Series processors with data cache where smallest granularity cache word. sizes programmed based chip select regions wide.
Load (32-bit wide bus)
Whenever load from data memory requested instruction cache miss occurs, performs read from external memory (see Timing With 32-bit external data bus, read transaction begins with asserting -AS, indicate transaction. signal de-asserted after cycle. same time ADR< 27:2 ASI< bits driven with location read. drives RD/-WR signal high indicate read transaction. Since loads retrieve bits, -BE<0:3> used when 32-bit wide driven low. external memory system responds with read data pins 31:0 also asserts -READY signal when data ready. slow memory, -READY signal delayed until data valid. load double operation treated back-to-back reads.
Load (16-bit wide bus)
When programmed bits wide (defined chip select region) every load will retrieve 32-bits. Timing shows load (Byte, half word, word) operating with 16-bit bus. masks bits which required. 16-bit -BE<2> defined ADR<1> address bit. -BE<2> well BE<0:1> unused driven low.
Load (8-bit wide bus)
When programmed bits wide (defined chip select region) every load will retrieve 32-bits. Timing shows load (Byte, half word, word) operating with 8-bit bus. masks bits which required. 8-bit -BE<2:3> ADR<1:0> address bits. -BE<0:1> unused driven low.
MB86933H
Load with Exception Store with Exception
external memory system sees memory exception terminate current memory transaction asserting -MEXC -READY signals. data data ignored MB86933H.
Store
access exception occurs write, external memory system terminate current memory transaction asserting -MEXC -READY signals. external memory system expected ignore data data this situation.
Unlike loads, stores sized programmed size require only minimum number cycles complete store. example, only cycles required 8-bit bus.
Store (32-bit wide bus)
Atomic Load Store
write transaction begins with asserting -AS, indicate transaction. signal de-asserted after phase. same time 27:2 pins driven with location written while 31:0 pins have corresponding write data. -BE<0:3> high order byte enables, respectively indicate which bytes write given type store operation (byte, half-word word drives RD/-WR signal indicate write transaction. external memory system responds asserting -READY signal when stored data. internal wait state generator enabled, -READY generated internally MB86933H. store double operation treated back-to-back writes. (see Timing
Store (16-bit wide bus)
atomic load store executes load followed store with operation allowed between. -LOCK signal asserted indicate that being used more than external memory operation. There cycle between termination read beginning write provide time switching data drivers.
DRAM Timings
During DRAM access column address,are output ADR<27:16> pins. Timing diagram shows back-to-back DRAM reads which same page. Timing shows DRAM write followed DRAM read, again same page. Timing shows both samepage reads writes. Note that always inserts idle cycle between read write. Timing shows read followed refresh. on-chip timer used refresh counter.
Stores 16-bit memory sized bus. That 16-bit bus, store word requires cycles while store halfword store byte requires single cycle. Timing show timing different types stores. 16-bit bus, -BE<2> defined ADR<1>. -BE<3> unused driven low. -BE<1:0> defined high order byte enables, respectively.
Store (8-bit wide bus)
External Request Grant
Stores 8-bit memory sized bus. That 8-bit bus, store word requires four cycles, store halfword requires cycles, store byte requires single cycle. Timing 10., show timing different types stores. 8-bit bus, -BE<2:3> defined ADR<1:0>. -BE<1:0> unused driven low.
external device request ownership asserting -BREQ signal. asserts -BGRNT signal indicate that relinquishing control also three-states drivers. following cycle, external device complete transaction. completion transaction external device de-asserts -BREQ signal. responds de-asserting -BGRNT signal following cycle. MB86933H default owner bus.
MB86933H
LOAD CLK_IN
LOAD
27:2
RD/-WR
-READY
31:0
Timing Typical Back-to-Back Loads with 32-Bit Wide (Same Load Double)
ADR,ASI
RD/-WR
-READY
[0:3]
0000
0010
[15:0]
BE<2> ADR<1>, BE<3> BE<0:1> BE<3> WAIT STATE
Timing Load with 16-Bit Wide
MB86933H
ADR,ASI
RD/-WR
-READY
[0:3]
0000
0001
0010
0011
Byte0 [7:0]
Byte1
Byte2
Byte3
BE<2:3> ADR<0:1>, BE<0:1> WAIT STATE
Timing Load with 8-Bit Wide
LOAD CLK_IN
27:2
RD/-WR
-READY
-MEXC
31:0
INVALID
Timing Load with Exception 32-Bit Wide
MB86933H
STORE CLK_IN
STORE
27:2
RD/-WR
-READY
31:0
Timing Typical Back-to-Back Stores 32-Bit Wide (Same Store Double)
ADR,ASI
RD/-WR
-READY
[0:3]
0010
0000
[15:0]
BE<2> ADR<1>, BE<3> BYTE ENABLE, BE<0> BYTE ENABLE, WAIT STATE
Timing Store Word with 16-Bit
MB86933H
ADR,ASI
ADR1
RD/-WR
-READY
[0:3]
[15:0]
NOTES: BE<2> ADR<1>, BE<3> BYTE ENABLE, BE<0> BYTE ENABLE, WAIT STATE
Timing Store Half Word with 16-Bit
ADR,ASI
ADR1
RD/-WR
-READY
[0:3]
[15:0]
Byte0 NOTES: BE<2> ADR<1>, BE<3> BYTE ENABLE, BE<0> BYTE ENABLE, WAIT STATE
Timing Store Byte with 16-Bit
MB86933H
ADR,ASI
RD/-WR
-READY
[0:3]
0011
0010
0001
0000
Byte3 [7:0]
Byte2
Byte1
Byte0
NOTES: BE<2:3> ADR<1:0>, BE<0:1> WAIT STATE
Timing Store Word with 8-Bit
ADR,ASI
RD/-WR
-READY
[0:3]
00X1
00X0
[7:0]
Byte1
Byte0
NOTES: BE<2:3> ADR<1:0>, BE<0:1> WAIT STATE
Timing Store Half-Word with 8-Bit
MB86933H
ADR,ASI
ADR1
-READY
RD/-WR
[0:3]
00XX
[7:0]
Byte NOTES: BE<2:3> ADR<1:0>, BE<0:1> WAIT STATE
Timing Store Byte with 8-Bit
STORE CLK_IN
27:2
RD/-WR
-READY
-MEXC
31:0
Timing Store with Exception
MB86933H
LOAD CLK_IN
STORE
27:2
RD/-WR
-READY
-LOCK
31:0
Note:
load followed store requires intervening clock cycle while store followed load occur consecutive clock cycles.
Timing Atomic Operation
MB86933H
ADR<31:16> ADR1 ADR1 ADR2
ADR2
-RAS
-CAS
(HIGH) Timing DRAM Reads (Non-SAME PAGE) 32-Bit
D<31:0>
-DWE
MB86933H
ADR<31:16>
ADR1
COLADR1
ADR2
COLADR2
-RAS
-CAS
(WRITE) (READ) Timing DRAM Write Followed DRAM Read (Non-SAME PAGE) 32-Bit
D<31:0>
-DWE
MB86933H
ADR<31:16>
ADR1
ADR1
ADR2
IDLE
ADR3
ADR4
-RAS
-CAS
(READ) (READ) (WRITE) (WRITE) Timing DRAM SAME PAGE READS WRITES 32-Bit
D<31:0>
-DWE
MB86933H
ADR<27:16>
ADR1
ADR1
3fffffff
ADR2
-RAS
-CAS
REFRESH REQUEST (READ) REFRESH Timing DRAM READ Followed Refresh 32-Bit
D<31:0>
-DWE
TIMEROVF_
*Note: During refresh, address remains constant.
MB86933H
Processor Cycle Complete
Processor Cycle Start
CLK_IN
-BREQ
-BGRNT
DRIVERS THREE-STATE
Timing Request Grant Cycle
MB86933H
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS1
Symbol Supply voltage Input voltage Operating junction temperature Rating Conditions Min. -0.3 -0.3 Max. Units
Notes: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other condition above those indicated operation section this specification implied. Exposure Absolute Maximum Ratings conditions extended periods affect device reliability. Recommended Connections: Power ground connections must made multiple pins. Every MB86933H based circuit board should include power (VCC) ground (VSS) planes power distribution. Every must connected power plane, every must connected ground plane. Pins identified "N.C." must connected system. Liberal decoupling capacitance should placed near MB86933H. processor cause transient power surges when numerous output buffers transition, particularly when connected large capacitive loads. inductance capacitors interconnections recommended best high frequency electrical performance. Inductance reduced shortening board traces between processor decoupling capacitors much possible. Capacitors specifically designed packages will offer lowest possible inductance. reliable operation, alternate masters must drive pins that three-stated MB86933H when granted bus, particular -LOCK, 27:2 -BE0-3, 31:0 -AS, RD/-WR must driven alternate master. These pins normally driven processor during active idle states don't require external pullups. N.C. pins must always remain unconnected.
PACKAGE THERMAL CHARACTERISTICS2
Symbol Parameter Thermal resistance junction case Thermal resistance junction ambient Package Plastic Plastic Value °C/W Units °C/W
SPECIFICATIONS3
Symbol CPIN Parameter Input voltage Input high voltage (All pins except XTAL1) Input high voltage (Pin XTAL1) Output voltage Output high voltage Input leakage current 3-state output leakage current Operating power supply current capacitance (All pins except XTAL2) capacitance (Pin XTAL2) 3.2mA -0.4mA VOUT Conditions Freq. Min. Typ. Max. 0.45 Units
Note: (typ) values calculate maximum case ambient temperature allowed. Note that maximum junction temperature 125°C. example, Allowed ambient temp 125°C.- (ICC) (5.25V) Note: numbers package thermal characteristics assume multilayer PCB. multilayer board defined Board with least metal routing layers.
MB86933H
CHARACTERISTICS1,2,4,5
Symbol CLKIN period CLKIN high time CLKIN time CLKIN rise time CLKIN fall time CLKIN CLKOUT1 CLKIN CLKOUT2 delay CLKOUT1, CLKOUT2 high time CLKOUT1, CLKOUT2 time CLKOUT1, CLKOUT2 fall time CLKOUT1, CLKOUT2 rise time 31:0 27:2 27:2 [DRAMC] -BE0-3 -BE0-3 8/16-bit mode -SAME PAGE -SAME_PAGE RD/-WR -LOCK -TIMER_OVF -TIMER -BGRNT Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold 23.5
0.35xPeriod 0.4xPeriod
Parameter Description
Min. Max.
Units
23.5
MB86933H
CHARACTERISTICS1,2,4
Symbol ERROR -RAS -CAS -DWE -MEXC input setup time -MEXC input setup time [8/16-bit mode] -READY input setup time
Parameter Description Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold
Min. 32.5 Max.
Units
-READY input setup time [8/16-bit mode] 31:0 input setup time -BREQ input setup time input setup time input hold time -MEXC input hold time -READY input hold time 31:0 input hold time -BREQ input hold time
Parameters valid over specified temperature range supply voltage range unless otherwise noted. voltage measurements referenced ground. time measurements referenced input output levels 1.5V. testing, inputs swing between 0.4V 2.4V (Except XTAL1 which swings from 0.4V 3.0V). Input rise fall times less. more than output shorted time maximum duration second. Timing specifications apply frequency operation listed column. output timings based 50pF load. These specs will improved future. Data output driver control same RD/-WR timing similar.
MB86933H
CLK_IN Cycle Minimum RESET
Cycles ADDR CLK_IN must stable least 100µs before RESET de-asserted. When RESET hold time (3ns) met. 0x0000 0000
Timing Reset Timing
MB86933H
2.8v
0.8v 0.8v 2.8v 1.5v
CLK_IN
CLKOUT1
2.0v 1.5v
2.0v 0.8v
2.0v 0.8v
CLKOUT2
0.8v 0.8v 2.0v 1.5v
2.0v 0.8v
Note: CLKOUT1 CLKOUT2 derived from non-overlapping internal clocks, however, relative timing these signals tested.
Timing Clock Timing
MB86933H
CLK_IN
1.5v t12d t12h 1.5v t13d t13h 1.5v t14d t14h 1.5v t15d t15h 1.5v t16d t16h 1.5v t17d t17h 1.5v t18d t18h 1.5v t19d t19h 1.5v
31:0 ADDR 27:2 -BE0-3,
-CS0-5
-SAME_PAGE
RD/-WR
-LOCK
-TIMER_OVF
-BGRNT
t20d ERROR t21d -RAS t22d -CAS t23d -DWE Note: d=delay, h=hold 1.5v 1.5v 1.5v 1.5v
t20h
t21h
t22h
t23h
Timing Output Timing
MB86933H
CLK_IN
1.5v
-MEXC
1.5v
-READY
1.5v
31:0
1.5v
-BREQ
1.5v
NOTE:
d=delay, h=hold
Timing Output Timing
12ns NOTE: These specifications based sample characterization should considered typical values.
Timing JTAG Timing
MB86933H
Interrupt Signal, Interrupt Input Width
Symbol TIHW TILW
Description Min. input High level duration input level duration
Unit Max. tCLK+10 tCLK+10
HIGH Level RISING-EDGE trigger mode, this width satisfied, interrupt request FLIP-FLOP set. Level FALLING-EDGE trigger mode, this width satisfied, interrupt request FLIP-FLOP set.
tIHW
IRQx
tILW
Timing Interrupt Request Timing Diagram
MB86933H
Ordering Info.: MB86933H-25PF-G-B
MB86933H
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MB86933H
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EC-DS-20385-9/96 DOCUMENT CONTROL 05981-001

Series 32-BIT RISC EMBEDDED PROCESSOR ADVANCE INFORMATION FEATURE

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