0.25µm CMOS Technology 0.18µm Leff (0.24µm drawn) million gates 0

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0.25µm CMOS Technology 0.18µm Leff (0.24µm drawn) million gates 0

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CS71 Series Standard Cell
0.25µm CMOS Technology
0.18µm Leff (0.24µm drawn) million gates 0.05µW/gate/MHz power dissipation 2.5V, 3.3V, tolerant options Special high-performance I/Os-PCML, LVDS, PCI, SSTL, GTL+, AGP, Core power supply voltage: 2.5V, 1.8V, 1.5V Junction temperature: High-performance embedded SRAM DRAM Analog digital PLLs Powerful mixed-signal offering-A/D convertors Advanced packaging Proven design methodology tool support
2.5V Device T-LVTTL High-Speed Interface P-CML High-Speed Devices LVDS 3.3V CMOS 3.3V CS71 SSTL 3.3V Device CMOS Dual Power Supply GTL+ Analog (3.3V/2.5V) 5.0V Interface Device Tolerant ADC/DAC 2.5V CMOS 2.5V CMOS
Devices
T-LVTTL SDRAM
Description
Fujitsu's CS71, 0.25µm (0.18µm Leff) standard cell product, based Fujitsu's state-of-the-art CMOS process technology-a process designed high performance high integration. CS71 family offers million gates, using many five layers metal. CS71 standard cell library most aggressive enhanced libraries implementing today's deep submicron system-on-silicon designs. cell library optimized synthesis-based designs, designed power. core process operates 1.5V, 1.8V, 2.5V, with I/Os operating 2.5V, 3.3V, tolerant conditions. library supports most popular third-party tools data exchange file standards. Both standard staggered configurations available 44µm, 66µm 88µm pitches. Interface options include low-swing, high-speed I/Os high-speed interface I/Os. addition traditional packages, CS71 family available Ball Grid Array. CS71 offers rich ADCs DACs, digital analog PLLs, high-speed RAMs, ROMs, DRAMs, well variety other embedded functions. Design Methodology Fujitsu's design methodology ensures first-silicon success integrating proprietary point tools with most popular, sign-off quality, industry-standard tools. Fujitsu's clock-driven design methodology devised power skew. identifies best-suited clock distribution strategy given design predicts performance advance. Fujitsu supports co-simulation, emulation, high-level floorplanning ease power, timing, size estimation design. This enables designer make effective architectural-level decisions achieve optimal design solutions. Fujitsu's design methodology supports cycle-based simulators formal verification, well static timing analysis more conventional VHDL Verilog simulators. Fujitsu's design-for-test strategy includes boundary scan (JTAG), full partial scan, well built-in self-test memory. Applications CS71 offers high integration performance low-power consumption. High performance transmission switching applications, well power-sensitive applications, such mobile computing mobile communications, benefit from this technology.
CS71 Series Standard Cell
Mixed-Signal Macros Converters 10-bit: MS/s, MS/s, MS/s, MS/s, MS/s, MS/s 8-bit: KS/s, MS/s, MS/s Converters 12-bit: MS/s 10-bit: MS/s, MS/s, MS/s 8-bit: MS/s, MS/s, MS/s 6-bit: MS/s, MS/s Memory Macros SRAM Compiler: single dual port R/W, 1R), bits block, both Partial Write Compiler: 512K bits block High-density single-port 288K bits Register file (2R/W, 2R/2W), 4,608 bits Phase-Locked Loops Analog: (622 under development) I/Os 2.5V, 3.3V, tolerant Slew-rate controlled CMOS, TTL, PCML, T-LVTTL, LVDS, PCI, SSTL, GTL+, AGP, Cores 7TDMI Hard Macro 32-bit RISC 834/836 SPARClite Hard Macros Hard Macro 10/100 64/256 MPEG2 Decoder/Demultiplexer 8VSB Demodulator AC-3 Dolby Voice Decoder JPEG Encoder Decoder PCI-33/66 MHz, 32/64-bit cores Host Controller/Device (ATA3) Host Controller Smart Card IRDA Interface More being added
ASIC Design Support Verilog Logic Simulators from Cadence, Synopsys, Mentor VHDL/VITAL Logic Simulators from Synopsys, Cadence, Mentor Synthesis, power, DFT, tools from Synopsys Other tools Verilog-XL, NC-Verilog, VCS, Model-sim (Verilog) VSS, Model-sim (VHDL), V-System, Leapfrog Design Compiler, Design Power, Test Compiler, PrimeTime, MOTIVE, Sunrise TestGen Chrysalis Design Verifyer Sente Watt Watcher
PACKAGE AVAILABILITY Pins Frame Size
Thin Profile Packages (0.4, lead pitch)
Shrink Package (0.5 lead pitch)
Heatspreader Package (0.4, lead pitch)
Ball Grid Array (1.27 ball pitch)
Fine-Pitch Ball Grid Array (0.75, ball pitch)
Ball Grid Array (0.8, ball pitch)
FUJITSU MICROELECTRONICS, INC.
Corporate Headquarters 3545 North First Street, Jose, California 95134-1804 Tel: (800) 866-8608 Fax: (408) 922-9179 E-mail: fmicrc@fmi.fujitsu.com Site: http://www.fujitsumicro.com
1999 Fujitsu Microelectronics, Inc. company product names trademarks registered trademarks their respective owners. Printed U.S.A. ASIC-FS-20690-11/99

0.25µm CMOS Technology 0.18µm Leff (0.24µm drawn) million gates 0

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