FUJITSU MICROELECTRONICS, INC. REVISION Application Note INT

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FUJITSU MICROELECTRONICS, INC. REVISION Application Note INT

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MB86933H BASIC CONFIGURATION SYSTEM
FUJITSU MICROELECTRONICS, INC. REVISION
Application Note
INTRODUCTION
This application outlines design basic system using high performance, cost MB86933H SPARClite RISC embedded controller from Fujitsu Microelectronics, Inc. main objective demonstrate simplicity MB86933H interface various subsystems such EPROM, DRAM MB86940 companion chip. This system with other devices fitted applications limited space environment. MB86933H features full 32-bit data 26-bit address bus. separation data address buses facilitates system design. built-in DRAM Controller, programmable Chip Selects, Address Decoder 16-bit counter further reduce external hardware required interface memory subsystems. MB86933H maintains full software compatibility with rest Series family. MB86940 direct Table Bill Materials
Fujitsu Fujitsu Fujitsu National MAXIM MAXIM MB86933H MB86940, Interrupt DUARTs AM27C010-205DC, EPROM 1288K MB814260-70 DRAM 256Kx16, RXDT-2-20-MHZ, OSC, TTL, 74B2525, 74B2525, SOIC 702CSA MA208CAG 74F74 74F04 74F10 Description QTY.
coupled companion chip, which provides general functions including: USARTs 16-bit Timers 15-channel Interrupt Request Controller.
system uses industry standard memory devices such byte-wide EPROM similar AMD27C010-205DC 256Kx16 DRAM, MB814260-70. MB86940 companion chip used provide serial communications. Other common components used pull-ups, clock reset generation. schematic diagram shown Figure highlights EPROM, DRAM memory array, interrupt controller, inputs outputs. Table lists major parts this minimum system configuration.
MB86933H
Notes: unspecified resistors Ohms Rev. MB86933H Ohms Rev. MB86933H unspecified capacitors only required Rev. MB86933H These signals shown with `nc' user expansions. used they should properly terminated either `high' `low' Vccs Gnds omitted clarity IRL<3:0>
D<31:0> 27C020 MB86940 D<7:0> 74FCT244 A<17:2>
MEXC* READY* BREQ* BMODE16*
Application Note
A<27:2> BE2* BE3* CS0* A<17:2> D<7:0> 74F04 OUT1 OUT2 TRDY0 RRDY0 TRDY1 RRDY1 IRL<3:0> TIMER1 TIMER2 T0INT R0INT T1INT R1INT
CLK-ELB -TRST* BMODE8* 74F10 A<24:16> A<8:0> D<31:16> DQ<15:0> LCAS DSR0 DTR0* CTS0* RTS0* MB814260
DWE* RAS0* CAS0* CAS1*
74F04 A<8:0> D<15:0> D<31:16> A<6:2> DQ<15:0> 74F04 LCAS 74F10
A<24:16>
MB814260
R0INT T0INT TIMER1 R1INT T1INT TIMER2 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 0.1uF MAX208CAG OUT3 TCLK0* TCLK1* RCLK0 RCLK1 D<15:0> RS<4:0>
MAX702 74F74 RESET* RESET*
CS4*
8PCONN TRNDT0 DTR1* RTS1* TRNDT1 RCVDT0 DSR1* RCVDT1 CTS1* RD/WR* CS1* RESET* CLOCK TXD0 DTR1 RTS1 TXD1 RXD0 DSR1 RXD1 CTS1 VC1C20.1uF RSTXD0 RSDTR1 RSRTS1 RSTXD1 RSRXD0 RSDSR1 RSRXD1 RSCTS1
CAS2* CAS3*
RD/WR* CS1* RESET* CLK_IN
B2525
0.1uF
0.1uF
READY2* READY1* SYBRK0 TEMP0 TEMP1 SYBRK1 PRSCK1 6PCONN
CLKIN
ACK1 CLK1 CLK2 CLK0 ACLK0 PRSCK OUT0
Figure
Schematics
Application Note
System Clock Generation Reset
MB86933H operates clock frequency MHz. easiest obtain clean, symmetrical clock signal oscillator. This design also uses skew clock distribution chip 74B2525 dispense master clock signal individual clock inputs. reset circuitry consists power supply monitor MAX702 that controls RESET. MAX702 insures that MB86933H will stay RESET until supply Table Peripheral Memory
Register Trigger Mode Register Trigger Mode Register Sense Register Clear Register Mask Register Latch/IRL Clear SDTR Data Register SDTR Cntrl Status SDTR Data Register SDTR Cntrl Status Prescaler Register TCR0 Reload Value Register Count Value Register Prescaler Register TCR1 Reload Value Register Count Value Register TCR2 Reload Value Register Count Value Register TCR3 Reload Value Register Count Value Register DRAM, EPROM, 256K 0x8, 0xA, 0x8, 0xA, Address 0x10000000 0x10000004 0x10000008 0x1000000C 0x10000010 0x10000014 0x10000020 0x10000024 0x10000030 0x10000034 0x10000040 0x10000044 0x10000048 0x1000004C 0x10000050 0x10000054 0x10000058 0x1000005C 0x10000064 0x10000068 0x1000006C 0x10000074 0x10000078 0x1000007C 0x400000000x401fffff 0x000000000x0001ffff Data Size <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <16:31> <0:31> <0:7>
greater than 4.65V. After surpassed 4.65V, RESET continues being asserted minimum milliseconds. pair 74F74 flip flops synchronize monitor output produce synchronous RESET signal.
Peripheral System Memory
following table shows basic peripheral memory map.
Device MB86940
Application Note
EPROM
MB86933H elegant feature, which ability interface 8-bit, 16-bit 32-bit memory during boot-up. There pins, -BMODE8 -BMODE16 MB86933H dedicated select this feature. This design sets -BMODE8 `low' -BMODE16 `high' enable 8-bit access during boot-up. Hence, single 32-bit instruction fetch requires four times long would 32-bit design. This design includes Kbyte 8-bit EPROM, which mapped peripheral chip select, CS0. 74FCT244 buffers EPROM prevent data contention between EPROM other devices slow EPROM output disable time. EPROM output enable buffer enable signals directly derived from RD/-WR signals MB86933H. Each Chip Select MB86933H, except CS0, features internal registers program functionality. These registers respectively Address Range Specifier Register (ARSR), Address Mask Register (AMR) Wait-State Specifier Register (WSSR). There ARSR associated with CS0. EPROM start address hardwired ASI=0x09, 0x000 0000. Address Mask Register, AMR[0] used expanding range accommodate various sizes EPROM boot-ROM. EPROM access uses MB86933H internally generated READY logic, which programmable WSSR (ASI=0x01, 0x0000 0160). Upon reset number wait states defaulted After reset, boot firmware easily number wait states speed execution. common page-mode DRAM with before refresh. column addresses MA<11:0> multiplexed internally output ADR<27:16>. signals, -RAS<1:0>, provided easy access banks memory configuration. Four signals, -CAS<3:0>, used controlling byte, half-word word write access memory. Internal same-page-detect logic supports minimum 2-cycle memory access. internal timer used generating -CAS before -RAS refresh cycle interval, which programmable. This design showcases simplicity interface built-in DRAM Controller memory. this design, memory array consists bank 256Kx16 DRAMs, such MB814260-70. total capacity array Mbytes. Since outputs MB86933H capable driving capacitive load, signals directly wired memory array without buffering. This reduces external hardware components required enhances performance significantly. -RAS0 signal used enable bank select DRAM array. multiplexed addresses, ADR<24:16>, data bus, D<31:0>, connected without buffering directly A<8:0> DQ<15:0> pins, respectively, DRAM devices. -CAS<3:0> signals used control byte, half-word word write access DRAM devices connecting appropriate UCAS LCAS pins. RD/-WR, -RAS0 signals gated together enable DRAM devices. -DWE pins used indicate whether access read write cycle. MB86933H dedicates registers configure activate DRAM controllers. details setting these registers given Programming Chip Selects section.
DRAM memory
MB86933H built-in programmable DRAM controller, which provides logic directly interface MBytes DRAM. DRAM controller supports Table DRAM Controller Related Internal Registers
Address 0x00000130, 0x01 0x00000150, 0x01 0x000007D0, 0x01 0x000007D4, 0x01 0x00000174, 0x01 0x00000178, 0x01 0x00000120, 0x01 0x0000016C, 0x01 0x00000080, 0x01 Timer Register
Registers Address Range Specifier Register Address Mask Register DRAM Bank Configuration Registers
Bank
Bank Bank
Timer Preload Register Same Page Mask Register Width Register System Support Control Register
Application Note
memory array this design mapped CS4, which normally designated DRAM chip select. memory array start address 0x4000 0000. DRAM controller programmed internal READY signal. MB86933H on-chip timer generate pulse DRAM refresh timing. DRAM access time deterministic refresh page miss cycles. However, using industrial standard DRAM, this controller supports: Table DRAM Memory Access Time
cycles cycles cycles
Access Type DRAM Non-page Access DRAM Page Access DRAM Worst Case
ADR<27:16>
ADR1
COLADR1
IDLE
ADR2
COLADR2
-RAS0
-CAS<3:0> D<31:0> -DWE (WRITE) (READ)
Timing
DRAM Write Followed DRAM Read (Non-SAME PAGE) 32-Bit
ADR<27:16>
ADR1
ADR1
ADR2
IDLE
ADR3
ADR4
-RAS0
-CAS<3:0>
D<31:0> -DWE
(READ)
(READ)
(WRITE)
(WRITE)
Timing
DRAM SAME-PAGE READS WRITES 32-bit
Application Note
MB86940 COMPANION CHIP
MB86940 companion chip dedicated interface MB86933H chip. MB86940 used provide system functions which include interrupt handling, timers serial ports. this design, MB86940 mapped Chip Select address space connected upper bits data bus, D<31:16> MB86933H chip. MB86933H uses internal READY access MB86940. Serial Port MB86940 provides RS232 compatible communication channels MB86933H through MAX208CAG quad transceiver. serial ports their baud rate from Timer3 output. Both serial ports interrupt driven. Counter /Timers There counter/timers MB86940. Timer connected. Timer used interrupts. Timer used generating serial port baud rate. Interrupt Request Controller Interrupt Priority Encoder take inputs from timers serial ports shown following table. IRQ15 highest priority, IRQ1 lowest. unconnected IRQs user configurable. Interrupt Request Controller abitrates 15-channel unmasked interrupt requests pending IRQ<15:1>, interrupts MB86933H driving encoded highest priority interrupt onto IRL<3:0> pins, which connected MB86933H directly. Table
Interrupt Priority Encoder
Interrupt Source Timer output UART Transmit Ready UART Receive Ready Timer output UART Transmit Ready UART Receive Ready
Application Note
PROGRAMMING CHIP SELECTS
following segment SPARC assembly code programs
#define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define SYSTEM_SUPPORT_CTL_REG SAME_PAGE_MASK_REG CS1_ADDRESS_RANGE_REG CS2_ADDRESS_RANGE_REG CS3_ADDRESS_RANGE_REG CS4_ADDRESS_RANGE_REG CS5_ADDRESS_RANGE_REG CS0_ADDRESS_MASK_REG CS1_ADDRESS_MASK_REG CS2_ADDRESS_MASK_REG CS3_ADDRESS_MASK_REG CS4_ADDRESS_MASK_REG CS5_ADDRESS_MASK_REG CS01_WAIT_STATE_REG CS23_WAIT_STATE_REG CS45_WAIT_STATE_REG BUS_WIDTH_REG DRAM_TIMER_PRELOAD_REG DRAM_CONFIG_REG0 DRAM_CONFIG_REG1 0x080 0x120 0x124 0x128 0x12C 0x130 0x134 0x140 0x144 0x148 0x14C 0x150 0x154 0x160 0x164 0x168 0x16C 0x178 0x7D0 0x7D4
MB86933H Chip Selects CS0=EPROM, CS1=the MB86940 peripheral chip, CS4=DRAM.
Number nanoseconds/cycle 25MHz part 40nsecs; 20MHz part 50nsecs #define NSECS_PER_CYCLE DRAM refresh every usec #cycles nsec/cycle define DRAM Same Page Address Mask (2**#column_bits #buswidth_bits/8 Smallest DRAMS 933H Eval Board 256kxN (2**8 32/4 #define DRAM_PAGE_MASK 0x3ff DRAM types #defineDRAM_256K_X_N #defineDRAM_512K_X_N #defineDRAM_1M_X_N #defineDRAM_2M_X_N #defineDRAM_4M_X_N
Wait State Registers Values Wait States (These values MHz) #define WS_EPROM (4-1) #define WS_MB86940 (3-1) #define WS_SRAM (2-1) System Support Register Enable Bits #define DRAMC 0x40 #define SAME_PAGE 0x20 #define CHIP_SELECT 0x10 #define WAIT_STATE 0x80 #define DRAM_TIMER 0x40 Width Codes #define WIDTH_8BIT #define WIDTH_16BIT #define WIDTH_32BIT
following code initializes programmable chip select other control Boot EPROM, MB86940 peripheral chip, DRAM memory EPROM ASI= 0x9, ADR=0x00000000-0x0003ffff
Address Range Register hardwired ASI=0x09 ADR=0x00000000 CS0_ADDRESS_MASK_REG, 0x2<<23, 0x0fffffff>>9, %l1, %l2, %l1, [%l0]0x1 Allow ASIs ADR<27:0> dont care
Width controlled BMODE8 BMODE16 pins MB86940 ASI=0x4 ADR=0x10000000-0x1fffffff CS1_ADDRESS_RANGE_REG, 0x4<<23, 0x10000000>>9, %l1, %l2,
Application Note
Wait %l1, [%l0]0x1 CS1_ADDRESS_MASK_REG, 0x00<<23, 0x0fffffff>>9, %l1, %l2, %l1, [%l0]0x1 BUS_WIDTH_REG, [%l0]0x1, %l1, 0xff3, %l1, WIDTH_16BIT<<2, %l1, [%l0]0x1 must ADR<27:0re
field Width <3:2>
State Register CS01_WAIT_STATE_REG, (WS_MB86940<<27 WS_MB86940<<22 0x4<<19), (WS_EPROM<<14 WS_EPROM<<9 0x4<<6), %l1, %l2, %l1, [%l0]0x1
DRAM ASI=0x8, 0x9, Bank ADR=0x40000000-0x403fffff Bank ADR=0x40400000-0x407fffff CS4_ADDRESS_RANGE_REG, 0x8<<23, 0x40000000>>9, %l1, %l2, %l1, [%l0]0x1 CS4_ADDRESS_MASK_REG, 0x3<<23, 0x007fffff>>9, %l1, %l2, %l1, [%l0]0x1 BUS_WIDTH_REG, [%l0]0x1, %l1, 0xcff, %l1, WIDTH_32BIT<<8, %l1, [%l0]0x1 Allows 0x8, 0x9, 0xA, ADR<22:0> dont care
field Width <9:8>
Wait State Register Disable Wait Generation DRAM Controller CS45_WAIT_STATE_REG, 0x0, %l1, [%l0]0x1 DRAM Same DRAM Bank Bank Timer Preload Register DRAM_TIMER_PRELOAD_REG, DRAM_REFRESH_CYCLES, %l1, [%l0]0x1 Page Mask Register SAME_PAGE_MASK_REG, 0xFF<<23, ASIs DRAM_PAGE_MASK>>9, %l1, %l2, %l1, [%l0]0x1 Configuration Registers 0x40000000 with 1Mxn DRAMs DRAM_CONFIG_REG0, 0x40000000, 0x0ff80000, %l1, %l2, %l1, %l1, DRAM_1M_X_N, %l1, [%l0]0x1 0x44000000 with 1Mxn DRAMs DRAM_CONFIG_REG1, 0x44000000, 0x0ff80000, %l1, %l2, %l1, %l1, DRAM_1M_X_N, %l1, [%l0]0x1
System Status Control Rgeister SYSTEM_SUPPORT_CTL_REG, (DRAMC SAME_PAGE CHIP_SELECT WAIT_STATE DRAM_TIMER), %l1, [%l0]0x1
Application Note
CONCLUSION
This design illustrates simplicity interfacing MB86933H various memory sub-systems with minimal glue logic. internal READY allows cost parts with minimal loss performance. Chip Select logic allows easy re-mapping DRAM memory different address space changing only corresponding Address Range register contents. This implies minimal hardware changes required. This basic configuration easily expanded accommodate 32-bit boot access adding more EPROMs. Additional banks DRAM memory easily configured. summary, this design basis many other applications which require performance Fujitsu's series 32-bit SPARCLite embedded controller.
Application Note
Rights Reserved. Circuit diagrams using fujitsu products included illustrate typical semiconductor applications. Information sufficient construction purpose shown. information contained this document been carefully checked believed reliable. However, Fujitsu Microelectronics, Inc. assumes responsibility inaccuracies. information conveyed this document does convey license under copyrights, patent rights trademarks claimed owned Fujitsu Limited, subsidiaries, Fujitsu Microelectronics, Inc. Fujitsu Microelectronics, Inc. reserves right change products specifications without notice. part publication copied reproduced form means, transferred third party without prior written consent Fujitsu Microelectronics, Inc.
Application Note
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FUJITSU MICROELECTRONICS, INC. REVISION Application Note INT

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