ML4824 Combo Controller Applications STAGE (Figure POWERING

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ML4824 Combo Controller Applications STAGE (Figure POWERING

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G.A. Hall J.H. Hwang
ML4824 Combo Controller Applications
STAGE (Figure
POWERING ML4824 ML4824 initialized once charged through R30. switching action boosts voltage 380V T1's primary inductance. then supplies well regulated ML4824 from secondary winding full wave rectifier consisting C11. primary secondary turns ratio (NPRI/NSEC) 25.5:1. proper circuit operation, high frequency bypassing with ceramic film capacitors VREF provided. Orderly operation upon start-up guaranteed when quick
GENERAL DESCRIPTION
This Application Note shows step-by-step process design high performance supply. equations shown this document also used different output voltages total power. complete power supply circuit shown Figure demonstrates ML4824's ability manage high output power while easily complying with international requirements regarding line quality. section provides 380VDC dual transistor current-mode forward converter. output converter delivers +12V amps. circuit operates from 264VAC with both power sections switching 100kHz.
INPUT 264V
ML4824
IEAO ISENSE VRMS RAMP1 RAMP2 VEAO ILIM
Figure Stage
REV. 10/25/2000
charges boost capacitor peak line voltage before boost switch turned This ensures boost inductor current zero before action begins. value regulated voltage must always greater than peak value maximum line voltage delivered supply. 2VRMS(MAX) (1.414)(264) 373V 380V Because ML4824 uses transconductance amplifiers loop compensation networks returned ground (see ML4824 data sheet error amplifier characteristics/ advantages). This eliminates interaction resistive divider network with loop compensation capacitors permitting wide choice divider values chosen only minimize amplifier offset voltages input bias currents. reliable operation must have voltage rating least volts. Calculate resistor divider ratio R7/R8. 2.50 SELECTING POWER COMPONENTS ML4824 section operates with continuous inductor current minimize peak currents maximize available power. inductance value required continuous current operation typical application found equation T1(PRI) 0.445VRMS(MAX)2 (fPFC )(POUT Where: tHLD hold-up time (sec) VC5(MIN) minimum voltage which stage still deliver full output power advantage using leading/trailing edge modulation that large portion inductor current "dumped" directly into load (PWM stage transformer) boost capacitor. This relaxes requirement boost capacitor. reference, equation should used starting point when choosing C5's maximum ripple current rating 120Hz). IRMS(C5) IOUT(C5) IAVG POUT 2VRMS(MIN)
IAVG (3.1416)(200) (2)(1.414)(80) IAVG 2.78A IAVG
IPEAK
IPEAK (3.1416)(2.78) IPEAK 4.37A
boost capacitor value chosen permit given output voltage hold-up time event line voltage suddenly removed. 2(POUT )(tHLD VC5(NOM)2 VC5(MIN)2
PEAK
IRMS(C5)
(7a)
SELECTING POWER SETTING COMPONENTS maximum average power delivered stage easily using following procedure: Find resistive divider ratio that results voltage VRMS being equal 1.20V lowest line voltage. voltage this must well filtered able respond well transient line voltage changes. 1.20 2VRMS(MIN)
T1(PRI) (0.445)(264) 105)(200)
T1(PRI) 1.55mH 1.5mH boost diode switch chosen with reverse voltage rating 500V safely withstand 380V boost potential. average peak currents respectively through these components are:
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resistor capacitor values typical example were found empirically offer lowest ripple voltage still respond well line voltage changes. Should ratio required which greatly different from that found equation adjust filter capacitor values according equations f1R2 Where (10) MULO multiplier output ation resis (3.5k) VOLTAGE LOOP COMPENSATION (Figure Maximum transient response section, without instability, obtained when open loop crossover frequency one-half line frequency. this application compensation components (pole/zero pair) chosen that closed loop response decreases 20dB/decade, crossing unity gain 30Hz, then immediately decreasing 40dB/decade. error amplifier pole placed 30Hz effective zero one-tenth this frequency 3Hz. First find crossover frequency (GPS power stage. reference, equation finds power stage pole, equation power stage gain.
VBOOST
MULO (VEAO 1.5)kM (R1)(POUT (13)
(3500)(6.8 1.5)(2099) )(200) 0.195 0.15
Where 15Hz, 23Hz
Find constant proportionality multiplier gain equation 11a. obtain "brown-out" action below lowest input voltage maximum gain multiplier must used when finding maximum gain (0.328) occurs when VRMS input multiplier 1.20V. Equation 11(ref) general expression multiplier gain versus line voltage. (ref VRMS2 (11)
kVRMS(MIN)2 (0.328)(80)2 2099 select value which permits greatest multiplier output current without saturating output. maximum output current multiplier 200µA. 2VRMS(MIN) (VEAO 1.5) 10-6 (11a)
VEAO
Figure Voltage Compensation PIN(AVG) VEAO(MAX) (2)(3.1416)(380)(5.3)(270 10-6 (14)
(0.328) (80)(6.8 1.5) 10-6 983k Selecting value current sense resistor completes calculations power setting components.
(12)
58.5Hz
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(3.1416)(722)(270 10-6 (15) amount error amplifier gain required bring open loop gain unity 30Hz negative power stage plus divider stage gain (attenuation): -(GPS(30) GRDIV -(5.8 (-43.6)) 37.8dB (77.6V value R11, which sets high frequency gain error amplifier, determined. GPS(DC) (16) 77.6 65.7 10-6 (20) (19)
1.63Hz Where POUT
GPS(DC) (1.414)(58.5) (1.63) GPS(DC) 35.9
1.18M Calculate which together with sets zero frequency 3Hz. )(3) (21)
gain power stage 30Hz calculated. GPS(30Hz) GPS(30Hz) (17)
58.5
48nF (use 47nF) Since pole frequency times zero frequency pole capacitor will one-tenth value (22)
GPS(30Hz) 1.95 (5.8dB) power stage gain will attenuated resistive divider R7/R8 according equation GRDIV GRDIV (2.37) (357 2.37) (18)
4.7nF
GRDIV 6.59 10-3 (-43.6dB)
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CURRENT LOOP COMPENSATION (Figure current loop compensated exactly like voltage loop with exception choice open loop crossover frequency. prevent interaction with voltage loop, current loop bandwidth should greater than times voltage loop crossover frequency more than one-sixth switching frequency 16.7kHz. power stage crossover frequency found equation pole frequency reference power stage gain found equation Find gain power stage 16.7kHz. GPS(16.7kHz) 16.7 (26)
GPS(16.7kHz) 2.42 16.7
GPS(16.7kHz) 1.45 10-1(-16.8dB) current loop contains attenuating resistors proceed find error amplifier gain equation -(-GPS(16.7kHz)
3.5K VEAO VREF IEAO
-(-16.8) 16.8dB (6.9V
(27)
determine value current error amplifier setting resistor R12. 10-6 (28)
3.5K ISENSE
38.1 Figure Current Compensation T1(PRI) VRAMP Calculate value form zero 1.6kHz. (23) (2)(3.1416)(36 103)(1.67 103) (29)
(0.15)(380) (2)(3.1416)(1.5 10-3)(2.5)
2.6nF (use 2.7nF) pole capacitor one-tenth value (30)
2.42kHz
(3.1416)(722)(270 10-6 (24)
1.63Hz same equation
270pF
GPS(DC)
(25)
GPS(DC) (1.414)(2.42 (1.63)
GPS(DC) 2099 (66.4dB)
REV. 10/25/2000
STAGE (Figure
SOFT-STARTING STAGE ML4824 features dedicated soft-start controlling rate rise output voltage preventing overshoot during power controller will initiate soft-start action until voltage reaches nominal value thereby preventing stalling output voltage excessive currents. Furthermore, action will terminated event that ML4824 loses power boost voltage should fall below 228VDC. soft-start capacitor value (C19) 25ms delay found equation
(tSS 1.25 (0.025) 1.25
SETTING OSCILLATOR FREQUENCY There versions ML4824. ML4824-1 where same frequency ML4824-2 where stage frequency. ML4824-1 general best choose small valued capacitor maximize oscillator duty cycle (minimize discharge time). small value capacitor increase oscillator's sensitivity phase modulation caused stray field voltage induction into this node. practical example 470pF capacitor first chosen Equation accurate with values greater than 10k. (31) 961CT 0.51fSW (961 10-12) 105)(470 10-12) (32)
41.2k
VOUT +12V,
ML4824
IEAO ISENSE VRMS RAMP1 RAMP2 VEAO ILIM
Figure Stage
REV. 10/25/2000
Note 0.51R ML4824-2 ML4824-2 allows user operate stage twice frequency, thereby reducing physical size stage magnetics filter components. frequency same external oscillator frequency. frequency formed comparing oscillator ramp voltage internal voltage references which ideally make duty cycle waveforms generated during each oscillator cycle identical. section duty cycle must balanced minimize phase jitter. This accomplished making oscillator dead-time discharge time) equal 2.5% total period. First choose value from equation 0.025 (33) RRAMP VOLTAGE MODE (FEED-FORWARD) Should voltage mode control used necessary know C5's peak voltage order choose correct ramp generating components. Equation finds worse case peak peak ripple voltage across find peak voltage divide ripple voltage regulated boost voltage. Remember that since ML4824 employs leading/trailing modulation actual peak peak ripple voltage will generally much less than calculated value. ESR(C VR(C5) IOUT(C5) Where line frequency Solve equation ramp resistor value. ramp capacitor value should range 470pF 10000pF. Choose resistor with adequate voltage rating withstand boost voltage. (MAX) VREF CRAMP 0.5VR
(36)
found from equation (34) which identical equation 961CT 0.51fsw (34) Where:
(37)
final test, in-circuit check adjacent cycles should examined duty cycle balance. more detail involving duty cycle balancing please refer Micro Linear's Application Note CURRENT LIMIT power stage operates current mode using generate voltage ramp duty cycle control. ML4824 limits maximum primary current internal comparator which when exceeded terminates drive external power MOSFETs. Maximum primary current IPRI(MAX) IPRI(MAX) IPRI(MAX) 2Amps (35)
(MAX) maximum duty cycle (0.45 ML4824-1) peak peak boost capacitor ripple voltage (equation POWER TRANSFORMER TURNS RATIO minimum output voltage secondary found equation VSEC(MIN) VOUT (MAX) (38)
VSEC(MIN) 0.45 VSEC(MIN) 27.7 Volts
secondary voltage chosen volts increase output voltage hold time. transformer turns ratio easily found from equation NPRI NSEC VSEC(MIN) NPRI NSEC NPRI NSEC
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(39)
maximum secondary current with output shorted limited equation ISEC(MAX) IPRI(MAX)NPRI NSEC (40) 3.3V OUTPUT DESIGN CHANGES (Figure latest microprocessors support circuitry require 3.3V supply proper operation. ML4824 ideal these applications including energy efficient, ecologically friendly "Green PC's". total output power required varies greatly from watts will necessary re-select certain components beginning with stage. T2's turn ratio must adjusted according equation another current secondary winding added using same turns ratio originally found volts. This second winding necessary power TL431/opto circuit 3.3V output adequate fully bias feedback circuitry. increased reduce output ripple voltage. figure below displays 3.3V output stage capable supplying amps.
µF4001
ISEC(MAX) (2)(38) ISEC(MAX) 25.3Amps output inductor rectifier were chosen with maximum current ratings larger than maximum secondary current. OUTPUT FILTER COMPONENT FILTER SELECTION
L1's value chosen efficiently minimize output ripple current thereby easing requirement filter capacitor. C21's value dominant contributor output ripple. maximum value required found equation ESR(C21) Where peak peak output ripple voltage OUTPUT VOLTAGE COMPENSATION TL431 shunt regulator opto-isolator perform output voltage setting regulation. opto crosses primary secondary safety boundary varying voltage keep output voltage constant against line load changes. Using current mode control simplifies loop compensation leaving only single pole zero output stage. pole created from output capacitor equivalent load resistance. zero formed from filter capacitor ESR. this example, action zero occurs well after closed loop response crossed unity, compensated with pole. output pole canceled increasing overall bandwidth addition which form zero with TL431. more information using TL431, including gain/phase versus frequency characteristics, please refer Texas Instruments Linear Data Handbook. VSEC(MAX) (41)
VOUT +3.3V,
10.2K
31.6K
Figure 3.3V Output Stage
NOTE: more information Application Note
REV. 10/25/2000
INPUT 264V
VOUT +12V,
ML4824
Figure Complete 200W Circuit
IEAO ISENSE VRMS RAMP1 RAMP2 VEAO ILIM
REV. 10/25/2000
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS HEREIN IMPROVE RELIABILITY, FUNCTION DESIGN. FAIRCHILD DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN; NEITHER DOES CONVEY LICENSE UNDER PATENT RIGHTS, RIGHTS OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. www.fairchildsemi.com
2000 Fairchild Semiconductor Corporation
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.

ML4824 Combo Controller Applications STAGE (Figure POWERING

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