Clock Tripled 3.45 Volt IMPROVED 486DX4 PERFORMANCE Clock tripled

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Clock Tripled 3.45 Volt IMPROVED 486DX4 PERFORMANCE Clock tripled

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ST486DX4V
Clock Tripled 3.45 Volt
IMPROVED 486DX4 PERFORMANCE Clock tripled core speeds Integrated faster than 80486DX4 speeds fast local systems, servers
ON-CHIP 8-KBYTE WRITE-BACK CACHE Industry-wide write-back chipset support Burst-mode write capability Configurable write-back write-through ADVANCED POWER MANAGEMENT Fast interrupt with separate memory space Fully static design permits dynamic clock control Software hardware initiated power suspend
INDUSTRY STANDARD COMPATIBILITY 486DX socket instruction compatible Runs DOS, Windows, OS/2, UNIX Standard 168-pin Ceramic Plastic 208-pin SGS-THOMSON ST486DX4 3.45 volt CPUs advanced 486DX/DX2/DX4 compatible processors. These CPUs incorporate on-chip 8KByte write-back cache integrated math coprocessor. on-chip write-back cache allows higher performance eliminating unnecessary external write cycles. traditional write-through CPUs, these external write cycles create bottlenecks affecting system wide performance. integrated floating point unit, improves performance over 80486DX4 equal internal frequency measured using Power Meter Whetstone test. BLOCK DIAGRAM
Decoder Control Sequencer Address Immediate Microcode Control Limit Unit Immediate 16-byte Instruction Queue
Automatic power-down mode These processors designed meet power management requirements newest generation low-power desktops notebooks. Power saved taking advantage advanced power management features such static circuitry, SMM, automatic power-down. Fast entry exit allows frequent feature without noticeable performance degradation. This family maintains compatibility with installed base software provides essential socket compatibility with 486DX/DX2/DX4
Core Clock Prefetch Data Clock
SMM, Suspend Mode Clock Control
SUSP# SUSPA# SMI# SMADS#
Branch Control
Execution Pipeline
Execution Unit 3-Input Multiplier Shift Register Adder File Unit Unit Unit Linear Address
Memory Data
Byte Muxes Regs
Write Buffers Data Buffers
D31-D0
Cache Memory Management
Memory Management Unit
Prefetch Unit
KByte Instr/Data Cache
Control
Control
Control
Instruction Address Data Address
Address Buffers
A31-A2 BE3#-BE0#
486DX Compatible Interface
1738600
October 1995
This preliminary information product undergoing evaluation. Details subject change without notice.
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ST486DX4V
PRODUCT OVERVIEW THOMSON ST486DX3.45 volt microprocessors advanced 486DX4 microprocessors. ST486DX4 operates three times external speed. CPUs ST486DX4 family high speed voltage CPUs attaining clock-tripled core speeds MHz. ST486DX4 8-KByte cache configured traditional write-through mode higher performance write-back mode. Write-back mode eliminates unnecessary external memory write cycles offering higher overall performance (100 MHz, Bench 9.0) than writethrough mode. ST486DX4 supports 32-bit data types operates real, virtual 8086 protected modes. access GBytes physical memory using 32-bit burst mode bus. Floating point instructions parallel processed using on-chip math coprocessor. ST486DX4 CPUs ideal design solutions low-powered "Green desktops well portable computers. These microprocessors typically draw only while input clock stopped suspend mode, their static design. System Management Mode (SMM) allows impleme nspa syst management software emulation peripheral devices. list ST486DX4 3.45 volt parts, including their operating frequency, package types listed page this document. Clock-Tripled Core clock-tripled ST486DX4 core operates three times frequency external clock input, while continuing operate interface external clock frequency. This configuration provides high frequency performance without requiring high speed interface external memory. ST486DX4 provides times performance 486DX same external clock frequency. This level performance achieved tripling frequency input clock using resulting signal drive core. further enhance this architecture, ST486DX4 reduces performance penalty slow external memory accesses through on-chip writeback cache eight write buffers. core consists five-stage pipeline optimized minimal instruction cycle times includes necessary hardware interlocks permit successive instruction execution overlap. execution stage pipeline executes simple frequently used instructions single clock cycle hardware multiplier executes 16-bit integer multiplications only three clocks.
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On-Chip Write-Back Cache ST486DX4 on-chip cache configured traditional write-through mode higher performance write-back mode. writeback cache mode specifically designed optimize performance core eliminating bottlenecks caused unnecessary external write cycles. This write-back architecture especially effective improving performance clock-tripled ST486DX4 CPU. Traditional write-through cache architectures require that writes cache also update external memory simultaneously. These unnecessary write cycles create bottlenecks which result stalls adversely impact performance. contrast, write-back architecture allows data written cache without updating external memory. With write-back cache, external write cycles only required when cache miss occurs, modified line replaced cache, when external master requires access data. ST486DX4 cache 8-KByte unified instruction data cache implemented using four-way associative architecture least recently used (LRU) replacement algorithm. cache designed optimum performance write-back mode, however, cache operated write-through mode. cache line size bytes lines only allocated during memory read cycles. Valid status maintained 16-byte cache line basis, modified "dirty" status write-back mode maintained 4-byte (double-word) basis. Therefore, only double-words that have been modified written back external memory when line replaced cache. core access cache single internal clock cycle both reads writes. Operations Since resident within CPU, overhead associated with external math coprocessor cycles eliminated. use, automatically powered down. This feature reduces overall power consumption. System Management Mode System Management Mode (SMM) provides additional interrupt separate address space that used system power management software transparent emulation peripherals. entered using System Management Interrupt (SMI#) SMINT instruction. While running isolated address space, interrupt routine execute without interfering with operating system application programs. After entering SMM, portions state automatically saved. Program execution begins base address space. location size memory pro- grammable within ST486DX4. Eight instructions have been
ST486DX4V
added instruction that permit software entry into SMM, well saving restoring total state when mode. Power Management ST486DX4 power management features allow dramatic improvement battery life over systems designed with non-static processors. During suspend mode typical current consumption less than percent full operation current. Suspend mode entered either hardware software initiated action. Using hardware method initiate suspend mode involves two-pin handshake between SUSP# SUSPA# signals. software initiate suspend mode through execution HALT instruction. Once suspend mode, ST486DX4 power consumption further reduced stopping external clock input. resulting current draw typically Since ST486DX4 static, internal data lost when clock stopped. Signal Summary ST486DX4 signal includes cache interface signals, coprocessor interface signals, power management signals, system management mode signals, power supply voltage control signal clock multiplier control signal. Figure 1-1. ST486 Input Output Signals.
A31-A2 A20M# AHOLD BOFF# BRDY# BS16#, BS8# EADS# FLUSH# IGNNE# INTR INVAL HOLD KEN# RDY# RESET SMI# SUSP# WM_RST CLKMUL Cache Interface Coprocessor Interface Power Management System Management Mode Reset Input Control Clock Multiplier ADS# BE3#-BE0# BLAST# BREQ
ST486DX4
D31-D0 D/C# DP3-DP0 FERR# HITM# HLDA LOCK# M/IO# PCHK# PLOCK# RPLSET(1-0) RPLVAL# SMADS# SUSPA# W/R# VOLDET
1738000
3/23
ST486DX4V
VOLDET Voldet output signal used system detect that voltage part socket. permanently logic level voltage part. CLKMUL CLKMUL input signal used select internal clock multiplication factor. internal clock multiplication factor when CLKMUL logic when CLKMUL logic CLKMUL internal pullup. left unconnected, will driven logic Programable Interface Following power-up RESET, ST486DX4 interface pins disabled. Once enabled, these pins either function defined DBST486DXST/1) (SMI# SMADS#) programmed function with protocol compatible SL-enhanced CPUs (SMI SMIACT#). 1.10 Mode Control Configuration register CCR3 (SMM_Mode) controls interface mode. 0=ST mode, Table 1.1. Definitions
MODE SMI#: Bidirectional System management Interrupt pin. Asserted system logic request interrupt. Sampled each rising clock edge. Causes trap occur sampled asserted least clocks prior RDY# sampled asserted cycle. Asserted during execution service routine response SMINT SMAC set. SMADS#: Address Strobe output used indicate that SMIACT#: Active output asserted during current cycle memory access. execution service routine. SL-COMPATIBLE MODE SMI#: System Management Interrupt input pin. Asserted system logic request interrupt. Sampled each rising clock edge. SMI# falling edge sensitive causes trap occur least rior RDY#/BRDY# sampled cycle.
1=SL-compatible mode, default state after reset SMI_Lock SMM_Mode modified. SMI_Lock set, SMM_Mode longer modified. Once SMI_lock set, must reset(RESET pin) order modify SMI_Lock SMM_Mode. 1.11 Definitions pins that change function SL-compatible mode SMI# SMADS#. Table lists definitions these pins. 1.12 Features Used with SL-Compatible Mode SMAC SMAC functions controlled Configuration Control Register (CCR1) disabled when SL-compatible mode. service routine accesses memory outside defined memory space, SMIACT# remains asserted. Also SMINT instruction should used SLcompatible mode.
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ST486DX4V
ELECTRICAL SPECIFICATIONS Electrical specifications this chapter valid clock-doubled ST486DX2, clock-tripled ST486DX4. ST486DX4 differs from ST486DX2 that ST486DX4 internal core operates three times frequency interface Electrical Connections 2.1.1 Power Ground Connections Decoupling high frequency operation ST486DX4, necessary install test this device using standard high frequency techniques. high clock frequencies used ST486DX4 output buffer circuits cause transient power surges when several output buffers switch output levels simultaneously. These effects minimized filtering power leads with low-inductance decoupling capacitors, using impedance wiring, utilizing pins. 2.1.2 Pull-Up/Pull-Down Resistors Table lists input pins which internally connected pull-up pull-down resistors. pull-up resistors connected pull-down resistors connected VSS. When unused, these inputs require connection external pull-up pull-down resistors. SUSP# unique that connected pull-up resistor only when SUSP# asserted. recommended that ADS#, LOCK# SMI# output pins connected pull-up resistors, indicated Table 2-2. external pull-ups guarantee that signals remain negated during hold acknowledge states. 2.1.3 Unused Input Pins inputs used system designer listed Table should connected either ground VCC. Connect active-high inputs ground through (±10%) pull-down resistor active-low inputs through (±10%) pull-up resistor prevent possible spurious operation. Table 2-3. Absolute Maximum Ratings
PARAMETER Case Temperature Storage Temperature Supply Voltage, Voltage Input Clamp Current, Output Clamp Current, ST486DX4V -65° +110° -65° +150° -0.5 -0.5 UNITS NOTES Power Applied Bias With Respect With Respect Power Applied Power Applied
Absolute Maximum Ratings following table lists absolute maximum ratings ST486DX4 microprocessors. Stresses beyond those listed under Table limits cause permanent damage device. These stress ratings only imply that operation under conditions other than those listed under "Recommended Operating Conditions" Table possible. Exposure conditions beyond Table reduce device reliability result premature failure even when there immediately apparent sign failure. Prolonged exposure conditions near absolute maximum ratings (Table 2-3) also result reduced useful life reliability. Table 2-1. Pins Connected Internal Pull-Up Pull-Down Resistors
SIGNAL A20M# AHOLD BOFF# BS16# BS8# BRDY# EADS# FLUSH# IGNNE# INVAL KEN# RDY# SUSP# WM_RST CLKMUL RESISTOR 20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-down 20-k pull-up
Table 2-2. Pins Requiring External Pull-Up Resistors
SIGNAL ADS# LOCK# EXTERNAL RESISTOR 20-k pull-up 20-k pull-up
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ST486DX4V
Recommended Operating Conditions Table presents recommended operating conditions ST486DX4V device. Table 2-4. Recommended Operating Conditions
PARAMETER Case Temperature Supply Voltage High Level Input Level Input Output Current (High) Output Current (Low)
ST486DX4V
-0.3 +85°
UNITS
NOTES
Power Applied With Respect
VOH=VOH(MIN) VOL=VOL(MAX)
Characteristics Table 2-5. Characteristics Recommended Operating Conditions)
PARAMETER Output Voltage Output High Voltage Input Leakage Current pins except those listed Table 2-1. Input Leakage Current pins with internal pull-downs. Input Leakage Current pins with internal pull-ups Active ICCSM Suspend Mode ICCSS Standby (Suspended/CLK Stopped) Input Capacitance COUT Output Capacitance CCLK Capacitance ST486DX4V 0.35 UNITS 0<VIN<VCC Table 2-1. 0.45 Table 2-1. NOTES
-400 Typical: Typical: 0.45
Note
Note
Note (Note (Note (Note
Notes: ratings refer internal clock frequency. 100% tested. inputs (CMOS levels). inputs held static except clock outputs unloaded (static IOUT mA). Specification also valid inputs (CMOS levels). inputs held static outputs unloaded (static IOUT mA).
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ST486DX4V
Characteristics Tables through list characteristics including output delays, input setup requirements, input hold requirements output float delays. These measurements based measurement points identified Figure Figure 2-2. rising clock edge reference level VREF, other reference levels shown Table below ST486DX4 Input output signals must Figure shows output delay input setup hold times Input setup hold times specified minimums, defining smallest acceptable sampling window synchronous input signal must stable correct operation.
Table 2-6. Drive Level Measurement Points Switching Characteristics
SYMBOL VREF VIHD VILD
Note: Refer Figure 2-1.
ST486DX4V
UNITS
7/23
ST486DX4V
Figure 2-1. Drive Level Measurement Points Switching Characteristics
CLK:
OUTPUTS:
Valid Output
Valid Output
INPUTS:
Maximum Output Delay Specification Minimum Output Delay Specification Minimum Input Setup Specification Minimum Input Hold Specification
Valid Input
LEGEND:
1709403
Figure 2-2. Timing Measurement Points
IH(MIN) IL(MAX)
1730400
8/23
ST486DX4V
Table 2-7. Characteristics ST486DX4V75 3.6V, Tcase=0° CL=50pF External (Max.)
SYMBOL T12a T13a T18a T20a T21a PARAMETERS Period High Time Time Fall Time Rise Time A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, HLDA, FERR#, LOCK#, M/IO#, PCD, PWT, W/R# Valid Delay SMADS#, SMI# Valid Delay A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Float Delay SMADS#, SMI# Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay HITM#, RPLSET(1-0), RPLVAL#, SUSPA# Valid Delay BLAST#, PLOCK# Float Delay RPLSET(1-0), RPLVAL# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS# Setup Time INVAL Setup Time EADS# Hold Time INVAL Hold Time BS16#, BS8#, KEN# Setup Time BS16#, BS8#, KEN# Hold Time BRDY#, RDY# Setup Time BRDY#, RDY# Hold Time AHOLD, HOLD Setup Time BOFF# Setup Time AHOLD, BOFF#, HOLD Hold Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Setup Time SMI#, SUSP#, WM_RST Setup Time A20M#, FLUSH#, INTR, IGNNE#, NMI, RESET Hold Time SMI#, SUSP#, WM_RST Hold Time A31-A4, D31-D0, DP3-DP0 Read Setup Time A31-A4, D31-D0, DP3-DP0 Read Hold Time (ns) (ns) FIGURE 2-3, 2-3,2-4 Note Note Note Note Note NOTES VIL(MAX) VIL(MAX) VIL(MAX)
Note 100% tested.
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ST486DX4V
Table Characteristics ST486DX4V10 3.6V, Tcase=0° CL=50pF External (Max.)
SYMBOL T12a T13a T18a T20a T21a PARAMETERS Period High Time Time Fall Time Rise Time A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, FERR#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Valid Delay SMADS#, SMI# Valid Delay A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Float Delay SMADS#, SMI# Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay HITM#, RPLSET(1-0), RPLVAL#, SUSPA# Valid Delay BLAST#, PLOCK# Float Delay RPLSET(1-0), RPLVAL# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS# Setup Time INVAL Setup Time EADS# Hold Time INVAL Hold Time BS16#, BS8#, KEN# Setup Time BS16#, BS8#, KEN# Hold Time BRDY#, RDY# Setup Time BRDY#, RDY# Hold Time AHOLD, HOLD Setup Time BOFF# Setup Time AHOLD, BOFF#, HOLD Hold Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Setup Time SMI#, SUSP#, WM_RST Setup Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Hold Time SMI#, SUSP#, WM_RST Hold Time A31-A4, D31-D0, DP3-DP0 Read Setup Time A31-A4, D31-D0, DP3-DP0 Read Hold Time (ns) (ns) FIGURE 2-3, 2-3, Note Note Note Note Note NOTES VIL(MAX) VIL(MAX) VIL(MAX)
Note 100% tested.
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ST486DX4V
Table 2-9. Characteristics ST486DX4V12 3.6V, Tcase=0° CL=50pF External (Max.)
SYMBOL T12a T13a T18a T20a T21a PARAMETERS Period High Time Time Fall Time Rise Time A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, FERR#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Valid Delay SMADS#, SMI# Valid Delay A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Float Delay SMADS#, SMI# Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay HITM#, RPLSET(1-0), RPLVAL#, SUSPA# Valid Delay BLAST#, PLOCK# Float Delay RPLSET(1-0), RPLVAL# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS# Setup Time INVAL Setup Time EADS# Hold Time INVAL Hold Time BS16#, BS8#, KEN# Setup Time BS16#, BS8#, KEN# Hold Time BRDY#, RDY# Setup Time BRDY#, RDY# Hold Time AHOLD, HOLD Setup Time BOFF# Setup Time AHOLD, BOFF#, HOLD Hold Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Setup Time SMI#, SUSP#, WM_RST Setup Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Hold Time SMI#, SUSP#, WM_RST Hold Time A31-A4, D31-D0, DP3-DP0 Read Setup Time A31-A4, D31-D0, DP3-DP0 Read Hold Time (ns) (ns) FIGURE 2-3,2-4 2-3,2-4 Note Note Note Note Note NOTES VIL(MAX) VIL(MAX) VIL(MAX)
Note 100% tested.
11/23
ST486DX4V
Figure Input Setup Hold Timing
EADS#
T12A INVAL
T13A
BS8#, BS16#, KEN# AHOLD, HOLD T18A BOFF# A20M#, FLUSH#, INTR, NMI, RESET T20A SMI#, SUSP#, WM_RST
T21A
A31-A4 (CACHE INQUIRY CYCLE)
1724401
12/23
ST486DX4V
Figure Input Setup Hold Timing
BRDY#, RDY# D31-D0, DP3-DP0 (READ)
1719303
Figure 2-5. PCHK# Valid Delay Timing
BRDY#, RDY#
DP3-DP0
PCHK#
D31-D0,
VALID VALID
1719403
13/23
ST486DX4V
Figure Output Valid Delay Timing.
A31-A2, ADS#, BE3-BE0#, BREQ, D/C#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# SMADS#, SMI#
VALID VALID VALID VALID
VALID
VALID
BLAST#, PLOCK#
VALID
HITM#, RPLSET(1-0), RPLVAL#, SUSPA# D31-D0, DP3-DP0 (WRITE)
VALID
VALID
1724500
VALID
Figure 2-7. Output Valid Delay Timing
A31-A2, ADS#, BE3-BE0#, BREQ, D/C#, PWT, PCD, HLDA, LOCK#, M/IO#, W/R#
VALID VALID
SMADS#, SMI#
BLAST#, PLOCK#
VALID
RPLSET(1-0), RPLVAL#
VALID
D31-D0, DP3-DP0 (WRITE)
VALID
1724600
14/23
ST486DX4V
MECHANICAL SPECIFICATIONS 168-Pin Ceramic Plastic Packages assignments ST486DX4V 168-pin packages shown Figure 3-1. pins listed signal name number Table 3-1.
Figure 168-Pin Plastic Ceramic Packages Assignments
BLAST# PLOCK# ADS# CLKMUL PCHK# M/IO# W/R# BE1# RDY# BE3# BS8# RESET INTR VOLDET
WM_RST SMI# INVAL HITM#
ST486 3.45Volt STANDARD PINOUT 168-Pin (Top View)
SMADS# RPLSET1
TEST RPLVAL# SUSPA# FERR# RPLSET0 BE0# BE2# BRDY# SUSP# KEN# HOLD A20M# FLUSH# IGNNE#
BREQ HLDA LOCK# D/C#
BOFF# BS16# EADS# AHOLD
1738301
15/23
ST486DX4V
Table ST486DX4 168-Pin Packages Signal Names Sorted Number
Signal Name INVAL HITM# SUSPA# IGNNE# INTR AHOLD SMI#
Signal Name RPLSET1 RPLVAL# RPLSET0 EADS# WM_RST SMADS# TEST FERR# FLUSH# RESET BS16# A20M# BS8#
Signal Name BOFF# HOLD KEN# RDY# BE3# SUSP# BRDY#
Signal Name BE2# BE1# BE0# D/C# LOCK# M/IO# W/R#
Signal Name HLDA BREQ
Signal Name BLAST# CLKMUL VOLDET ADS#
PLOCK# PCHK#
16/23
ST486DX4V
Figure Ceramic Plastic package
1.65 SEATING PLANE
ST486
2.29 1.52
(ALL PINS) DEG. CHAMFER INDEX CORNER SWAGGED PLACES SEATING PLANE
1718803
SWAGGED DETAIL
Table Packages Dimensions
SYMBOL MILLIMETERS 3.65 1.14 0.43 44.07 40.51 2.29 2.54 4.57 1.40 0.51 44.83 40.77 2.79 3.30 0.140 0.045 0.017 1.735 1.595 0.090 0.110 INCHES 0.180 0.055 0.020 1.765 1.605 0.110 0.120
17/23
ST486DX4V
Lead QFP(Quad Flat Package) assignments ST486DX4 lead package shown Figure 3-2. pins listed signal name number Table 3-2.
Figure 208-Lead Package Assignments
LOCK# PLOCK# BLAST# ADS#
WM_RST SMADS# HITM# RPLSET1 SMI# FERR# SUSPA# RPLVAL# INVAL IGNNE# SUSP# RPLSET0
PCHK# BRDY# BOFF# BS16# BS8# CLKMUL RDY# KEN# HOLD AHOLD HLDA W/R# BREQ BE0# BE1# BE2# BE3# M/IO# D/C# EADS# A20M# RESET FLUSH# INTR
ST486DX4 208-Lead PQFP (Top View)
TEST
1738400
18/23
ST486DX4V
Table ST486DX4 Lead Package Signal Names Sorted Number
Signal PCHK# BRDY# BOFF# BS16# BS8# CLKMUL RDY# KEN# HOLD AHOLD HLDA W/R# BREQ BE0# BE1# BE2# BE3# Signal M/IO# D/C# EADS# A20M# RESET FLUSH# INTR SMADS# HITM# SMI# FERR# SUSPA# RPLVAL# Signal INVAL IGNNE# SUSP# Signal TEST Signal Signal ADS# BLAST# PLOCK# LOCK#
WM_RST
RPLSET0
RPLSET1
19/23
ST486DX4V
Figure Lead Plastic Package
VIEW
ST486DX 208-Lead
1726400
VIEW
Table Lead Plastic Package Dimensions
SYMBOL MILLIMETERS 0.13 3.27 30.45 27.9 0.33 3.47 30.75 28.1 0.005 0.129 1.198 1.098 0.015 INCHES 0.013 0.137 1.21 1.106 0.023
20/23
ST486DX4V
Thermal Characteristics ST486DX4V designed operate when case temperature between 85°C. case temperature measured center package. maximum temperature MAX) maximum ambient temperature (TaMAX) calculated using following equations. (PMAX (PMAX where: Maximum average junction temperature (°C) Case temperature center package (°C) PMAX Maximum device power dissipation Junction-to-case thermal resistance (°C/W) Maximum ambient temperature (°C) Average junction temperature (°C) Junction-to-ambient thermal resistance (°C/W) Packages Table lists junction-to-ambient junction-to-case thermal resistances package. Table lists maximum ambient temperatures permitted various clock frequencies airflows Package equal 3.6volts. Package dimensions heatsink used thermal analysis shown Figure Table 3-7.
Table Ceramic Plastic Packages Thermal Resistance Airflow
AIRFLOW (m/sec) CERAMIC THERMAL RESISTANCE (C/W) WITH HEATSINK WITHOUT HEATSINK PLASTIC THERMAL RESISTANCE (C/W) WITH HEATSINK WITHOUT HEATSINK 11.5
Table 3-6. Ceramic Plastic Packages Maximum Ambient Temperature (TA) with
PACKAGE INTERNAL CLOCK FREQUENCY Ceramic Grid Array Plastic Grid Array HEATSINK (Yes/No) AIRFLOW (m/sec) 21/23
ST486DX4V
Figure Typical Heatsink Packages
1720703
Table Typical Heatsink Dimensions
SYMBOL MILLIMETERS 39.1 INCHES 0.24 0.05 0.19 1.54
Package Table lists junction-to-ambient junctionto-case thermal resistances package without heat sink. Table lists maximum ambient temperatures permitted various clock frequencies airflows Package equal volts. These package thermal characteristics assume that package soldered four-layer printed circuit board. Table
AIRFLOW THERMAL RESISTANCE (°C/W) m/sec m/sec
Table
INTERNAL CLOCK FREQUENCY AIRFLOW (m/sec) (m/sec)
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ST486DX4V
Ordering Information*.
SGS-THOMSON Prefix Device Name 486DX Clock ratio Clock Tripled Clock Doubled Voltage Dash volts 3.45 volts Speed (internal clock frequency) Package Type Package PQFP Package PPGA Package Temperature Range Commercial temperature range
486DX
1724301
Please contact your nearest SGS-THOMSON sales office confirm availability specific valid combinations check newly released combinations.
SGS-THOMSON registered trademark SGS-THOMSON Microelectronics. ST486DX, ST486DX2, ST486DX4 trademarks SGS-THOMSON Microelectronics. Product names used this publication identification purposes only trademarks their respective companies. Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics. rights reserved. SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil France Germany Hong Kong Italy Korea Malaysia Malta Marocco Netherlands Singapore Spain Sweden Switzerland Taiwan United Kingdom U.S.A.
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Clock Tripled 3.45 Volt IMPROVED 486DX4 PERFORMANCE Clock tripled

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